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5/5/06
DirectFET Power MOSFET
DirectFET ISOMETRIC
ST
Fig 1. Typical On-Resistance Vs. Gate Voltage
Typical values (unless otherwise specified)
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
SQ SX ST MQ MX MT
Description
The IRF6614PbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to
achieve the lowest on-state resistance in a package that has the footprint of a MICRO-8 and only 0.7 mm profile. The DirectFET
package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-
red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and pro-
cesses. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, improving previous best
thermal resistance by 80%.
The IRF6614PbF balances both low resistance and low charge along with ultra low package inductance to reduce both conduction
and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest
generation of processors operating at higher frequencies. The IRF6614PbF has been optimized for parameters that are critical in
synchronous buck operating from 12 volt bus converters including Rds(on) and gate charge to minimize losses in the control FET
socket.
2.0 4.0 6.0 8.0 10.0
VGS, Gate-to-Source Voltage (V)
4
8
12
16
20
Typical RDS(on) (
mΩ)
TJ = 25°C
TJ = 125°C
ID = 12.7A
0 1020304050
QG Total Gate Charge (nC)
0
2
4
6
8
10
12
VGS, Gate-to-Source Voltage (V)
VDS= 32V
VDS= 20V
ID= 10.2A
VDSS VGS RDS(on) RDS(on)
40V max ±20V max 5.9mΩ@ 10V 7.1mΩ@ 4.5V
Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage
Qg tot Qgd Qgs2 Qrr Qoss Vgs(th)
19nC 6.0nC 1.4nC 5.5nC 9.5nC 1.8V
Click on this section to link to the appropriate technical paper.
Click on this section to link to the DirectFET Website.
Surface mounted on 1 in. square Cu board, steady state.
TC measured with thermocouple mounted to top (Drain) of part.
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 0.43mH, RG = 25Ω, IAS = 10.2A.
Notes:
Absolute Maximum Ratin
g
s
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TA = 25°C Continuous Drain Current, VGS @ 10V
e
ID @ TA = 70°C Continuous Drain Current, VGS @ 10V
e
A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
f
IDM Pulsed Drain Current
g
EAS Single Pulse Avalanche Energy
h
mJ
IAR Avalanche Current
g
A
10.2
Max.
10.1
55
102
±20
40
12.7
22
PD -97090
IRF6614PbF
IRF6614TRPbF
l RoHS Compliant
l Lead-Free (Qualified up to 260°C Reflow)
l Application Specific MOSFETs
lIdeal for CPU Core DC-DC Converters
l Low Conduction Losses and Switching Losses
l Low Profile (<0.7mm)
l Dual Sided Cooling Compatible
l Compatible with existing Surface Mount Techniques
IRF6614PbF
2www.irf.com
Repetitive rating; pulse width limited by max. junction temperature.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Notes:
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BVDSS Drain-to-Source Breakdown Voltage 40 ––– ––– V
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 38 ––– mV/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 5.9 8.3 mΩ
––– 7.1 9.9
VGS(th) Gate Threshold Voltage 1.35 1.80 2.25 V
∆VGS(th)/∆TJGate Threshold Voltage Coefficient ––– -5.5 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA
––– ––– 150
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
gfs Forward Transconductance 71 ––– ––– S
QgTotal Gate Charge ––– 19 29
Qgs1 Pre-Vth Gate-to-Source Charge ––– 5.9 –––
Qgs2 Post-Vth Gate-to-Source Charge ––– 1.4 ––– nC
Qgd Gate-to-Drain Charge ––– 6.0 –––
Qgodr Gate Charge Overdrive ––– 5.7 ––– See Fig. 15
Qsw Switch Charge (Qgs2 + Qgd)––– 7.4 –––
Qoss Output Charge ––– 9.5 ––– nC
RGGate Resistance ––– 1.0 1.5 Ω
td(on) Turn-On Delay Time ––– 13 –––
trRise Time ––– 27 –––
td(off) Turn-Off Delay Time ––– 18 ––– ns
tfFall Time ––– 3.6 –––
Ciss Input Capacitance ––– 2560 –––
Coss Output Capacitance ––– 370 ––– pF
Crss Reverse Transfer Capacitance ––– 200 –––
Diode Characteristics
Parameter Min. Typ. Max. Units
ISContinuous Source Current ––– ––– 53
(Body Diode) A
ISM Pulsed Source Current ––– ––– 102
(Body Diode)g
VSD Diode Forward Voltage ––– ––– 1.0 V
trr Reverse Recovery Time ––– 15 23 ns
Qrr Reverse Recovery Charge ––– 5.5 8.3 nC
VDS = 32V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
VGS = 4.5V
ID = 10.2A
VGS = 0V
VDS = 20V
ID = 10.2A
TJ = 25°C, IF = 10.2A
di/dt = 100A/µs i
TJ = 25°C, IS = 10.2A, VGS = 0V i
showing the
integral reverse
p-n junction diode.
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 12.7A i
VGS = 4.5V, ID = 10.2A i
VDS = VGS, ID = 250µA
VDS = 32V, VGS = 0V
MOSFET symbol
Clamped Inductive Load
VDS = 10V, ID = 10.2A
Conditions
ƒ = 1.0MHz
VDS = 16V, VGS = 0V
VDD = 20V, VGS = 4.5Vi
VDS = 20V
IRF6614PbF
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Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
1E-006 1E-005 0.0001 0.001 0.01 0.1 110 100
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
100
Thermal Response ( Z
thJA )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
Ri (°C/W) τi (sec)
0.6676 0.000066
1.0462 0.000896
1.5611 0.004386
29.282 0.68618
25.455 32
τJ
τJ
τ1
τ1
τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
Ci= τi/Ri
Ci= τi/Ri
τ
τC
τ4
τ4
R4
R4
τ5
τ5
R5
R5
Surface mounted on 1 in. square Cu board, steady state.
TC measured with thermocouple incontact with top (Drain) of part.
Used double sided cooling, mounting pad with large heatsink.
Notes:
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
Rθ is measured at TJ of approximately 90°C.
Surface mounted on 1 in. square Cu
board (still air).
Mounted to a PCB with
small clip heatsink (still air)
Mounted on minimum
footprint full size board with
metalized back and with small
clip heatsink (still air)
Absolute Maximum Ratin
g
s
Parameter Units
PD @TA = 25°C Power Dissipation
e
W
PD @TA = 70°C Power Dissipation
e
PD @TC = 25°C Power Dissipation
f
TP Peak Soldering Temperature °C
TJ Operating Junction and
TSTG Storage Temperature Range
Thermal Resistance
Parameter Typ. Max. Units
RθJA Junction-to-Ambient
el
––– 58
RθJA Junction-to-Ambient
jl
12.5 –––
RθJA Junction-to-Ambient
kl
20 ––– °C/W
RθJC Junction-to-Case
fl
––– 3.0
RθJ-PCB Junction-to-PCB Mounted 1.0 –––
Linear Derating Factor
e
W/°C
0.017
270
-40 to + 150
Max.
42
2.1
1.4
IRF6614PbF
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Fig 5. Typical Output Characteristics
Fig 4. Typical Output Characteristics
Fig 6. Typical Transfer Characteristics Fig 7. Normalized On-Resistance vs. Temperature
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage Fig 9. Typical On-Resistance Vs.
Drain Current and Gate Voltage
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60µs PULSE WIDTH
Tj = 25°C
2.3V
VGS
TOP 10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
BOTTOM 2.3V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60µs PULSE WIDTH
Tj = 150°C
2.3V
VGS
TOP 10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
BOTTOM 2.3V
1.5 2.0 2.5 3.0 3.5 4.0
VGS, Gate-to-Source Voltage (V)
0.1
1.0
10.0
100.0
ID, Drain-to-Source Current
(Α)
VDS = 15V
≤ 60µs PULSE WIDTH
TJ = 150°C
TJ = 25°C
TJ = -40°C
-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
Typical RDS(on) (Normalized)
ID = 12.7A
VGS = 10V
110 100
VDS, Drain-to-Source Voltage (V)
0
1000
2000
3000
4000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
020 40 60 80
ID, Drain Current (A)
5
10
15
20
25
30
Typical RDS(on) (mΩ)
TA= 25°C
VGS = 3.0V
VGS = 3.5V
VGS = 4.0V
VGS = 4.5V
VGS = 5.0V
VGS = 10V
IRF6614PbF
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Fig 12. Maximum Drain Current vs. Case Temperature
Fig 10. Typical Source-Drain Diode Forward Voltage Fig11. Maximum Safe Operating Area
Fig 14. Maximum Avalanche Energy Vs. Drain Current
25 50 75 100 125 150
TJ , Junction Temperature (°C)
0
10
20
30
40
50
60
ID , Drain Current (A)
0.2 0.6 1.0 1.4 1.8 2.2
VSD, Source-to-Drain Voltage (V)
0.1
1.0
10.0
100.0
ISD, Reverse Drain Current (A)
VGS = 0V
TJ = 150°C
TJ = 25°C
TJ = -40°C
25 50 75 100 125 150
Starting TJ, Junction Temperature (°C)
0
20
40
60
80
100
EAS, Single Pulse Avalanche Energy (mJ)
I D
TOP 4.3A
6.4A
BOTTOM 10.2A
0.01 0.10 1.00 10.00 100.00
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
DC
-75 -50 -25 025 50 75 100 125 150
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
VGS(th) Gate threshold Voltage (V)
ID = 250µA
Fig 13. Typical Threshold Voltage vs. Junction
Temperature
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Fig 15a. Gate Charge Test Circuit Fig 15b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 16c. Unclamped Inductive Waveforms
tp
V
(BR)DSS
I
AS
Fig 16b. Unclamped Inductive Test Circuit
Fig 17b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)
trtf
Fig 17a. Switching Time Test Circuit
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
1K
VCC
DUT
0
L
IRF6614PbF
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DirectFET Substrate and PCB Layout, ST Outline
(Small Size Can, T-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
Fig 18. Diode Reverse Recovery Test Circuit for N-Channel
HEXFET® Power MOSFETs
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
Inductor Current
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
• di/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
+
-
+
+
+
-
-
-
RGVDD
D.U.T
G = GATE
D = DRAIN
S = SOURCE
D
D
D
D
G
S
S
IRF6614PbF
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DirectFET Outline Dimension, ST Outline
(Small Size Can, T-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
DirectFET Part Marking
CODE
A
B
C
D
E
F
G
H
J
K
L
M
R
P
IMPERIAL
MIN
4.75
3.70
2.75
0.35
0.58
0.58
0.75
0.53
0.26
0.88
2.18
0.616
0.020
0.08
MAX
4.85
3.95
2.85
0.45
0.62
0.62
0.79
0.57
0.30
0.98
2.28
0.676
0.080
0.17
MIN
0.187
0.146
0.108
0.014
0.023
0.023
0.030
0.021
0.010
0.035
0.086
0.0235
0.0008
0.003
METRIC
DIMENSIONS
MAX
0.191
0.156
0.112
0.018
0.024
0.024
0.031
0.022
0.012
0.039
0.090
0.0274
0.0031
0.007
IRF6614PbF
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DirectFET Tape & Reel Dimension (Showing component orientation).
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.05/06
CODE
A
B
C
D
E
F
G
H
MAX
0.319
0.161
0.484
0.219
0.165
0.205
N.C
0.063
MIN
0.311
0.154
0.469
0.215
0.158
0.197
0.059
0.059
MAX
8.10
4.10
12.30
5.55
4.20
5.20
N.C
1.60
DIMENSIONS
METRIC IMPERIAL
Loaded Tape Feed Direction
MIN
7.90
3.90
11.90
5.45
4.00
5.00
1.50
1.50
STANDARD OPTION (QTY 4800)
MIN
330.0
20.2
12.8
1.5
100.0
N.C
12.4
11.9
CODE
A
B
C
D
E
F
G
H
MAX
N.C
N.C
13.2
N.C
N.C
18.4
14.4
15.4
MIN
12.992
0.795
0.504
0.059
3.937
N.C
0.488
0.469
MAX
N.C
N.C
0.520
N.C
N.C
0.724
0.567
0.606
METRIC IMPERIAL
TR1 OPTION (QTY 1000)
IMPERIAL
MIN
6.9
0.75
0.53
0.059
2.31
N.C
0.47
0.47
MAX
N.C
N.C
12.8
N.C
N.C
13.50
12.01
12.01
MIN
177.77
19.06
13.5
1.5
58.72
N.C
11.9
11.9
METRIC
MAX
N.C
N.C
0.50
N.C
N.C
0.53
N.C
N.C
REEL DIMENSIONS
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6614TRPBF). For 1000 parts on 7"
reel, order IRF6614TR1PBF
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
