DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT259
8-bit addressable latch
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
FEATURES
•Combines demultiplexer and 8-bit latch
•Serial-to-parallel capability
•Output from each storage bit available
•Random (addressable) data entry
•Easily expandable
•Common reset input
•Useful as a 3-to-8 active HIGH decoder
•Output capability: standard
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT259 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT259 are high-speed 8-bit addressable
latches designed for general purpose storage applications
in digital systems. The “259” are multifunctional devices
capable of storing single-line data in eight addressable
latches, and also 3-to-8 decoder and demultiplexer, with
active HIGH outputs (Q0 to Q7), functions are available.
The “259” also incorporates an active LOW common reset
(MR) for resetting all latches, as well as, an active LOW
enable input (LE).
The “259” has four modes of operation as shown in the
mode select table. In the addressable latch mode, data on
the data line (D) is written into the addressed latch. The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous states.
In the memory mode, all latches remain in their previous
states and are unaffected by the data or address inputs.
In the 3-to-8 decoding or demultiplexing mode, the
addressed output follows the state of the D input with all
other outputs in the LOW state. In the reset mode all
outputs are LOW and unaffected by the address (A0 to A2)
and data (D) input. When operating the “259” as an
addressable latch, changing more than one bit of address
could impose a transient-wrong address. Therefore, this
should only be done while in the memory mode. The mode
select table summarizes the operations of the “259”.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD × VCC2× fi+ ∑ (CL× VCC2 × fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× VCC2× fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC − 1.5 V
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay CL= 15 pF; VCC =5 V
D to Qn18 20 ns
An, LE to Qn17 20 ns
tPHL MR to Qn15 20 ns
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per latch notes 1 and 2 19 19 pF
December 1990 3
Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 2, 3 A0 to A2address inputs
4, 5, 6, 7, 9 10, 11, 12 Q0 to Q7latch outputs
8 GND ground (0 V)
13 D data input
14 LE latch enable input (active LOW)
15 MR conditional reset input (active LOW)
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
MODE SELECT TABLE
LE MR MODE
L
H
L
H
H
H
L
L
addressable latch
memory
active HIGH 8-channel demultiplexer
reset
Fig.4 Functional diagram.
December 1990 5
Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition
q = lower case letters indicate the state of the referenced output established during the last cycle in which it was
addressed or cleared
OPERATING
MODES INPUTS OUTPUTS
MR LE D A0A1A2Q0Q1Q2Q3Q4Q5Q6Q7
master reset L H X X X X L L L L L L L L
demultiplex
(active HIGH)
decoder
(when D = H)
L
L
L
L
L
L
L
L
d
d
d
d
L
H
L
H
L
L
H
H
L
L
L
L
Q=d
L
L
L
L
Q=d
L
L
L
L
Q=d
L
L
L
L
Q=d
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
d
d
d
d
L
H
L
H
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Q=d
L
L
L
L
Q=d
L
L
L
L
Q=d
L
L
L
L
Q=d
store (do nothing) H H X X X X q0q1q2q3q4q5q6q7
addressable latch
H
H
H
H
L
L
L
L
d
d
d
d
L
H
L
H
L
L
H
H
L
L
L
L
Q=d
q0
q0
q0
q1
Q=d
q1
q1
q2
q2
Q=d
q2
q3
q3
q3
Q=d
q4
q4
q4
q4
q5
q5
q5
q5
q6
q6
q6
q6
q7
q7
q7
q7
H
H
H
H
L
L
L
L
d
d
d
d
L
H
L
H
L
L
H
H
H
H
H
H
q0
q0
q0
q0
q1
q1
q1
q1
q2
q2
q2
q2
q3
q3
q3
q3
Q=d
q4
q4
q4
q5
Q=d
q5
q5
q6
q6
Q=d
q6
q7
q7
q7
Q=d
December 1990 6
Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
Fig.5 Logic diagram.
December 1990 7
Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
D to Qn
58
21
17
185
37
31
230
46
39
280
56
48
ns 2.0
4.5
6.0
Fig.7
tPHL/ tPLH propagation delay
An to Qn
58
21
17
185
37
31
230
46
39
280
56
48
ns 2.0
4.5
6.0
Fig.8
tPHL/ tPLH propagation delay
LE to Qn
55
20
16
170
34
29
215
43
37
255
51
43
ns 2.0
4.5
6.0
Fig.6
tPHL propagation delay
MR to Qn
50
18
14
155
31
26
195
39
33
235
47
40
ns 2.0
4.5
6.0
Fig.9
tTHL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
119
22
19
ns 2.0
4.5
6.0
Figs 6 and 7
tWLE pulse width
HIGH or LOW 70
14
12
17
6
5
90
18
15
105
21
18
ns 2.0
4.5
6.0
Fig.6
tWMR pulse width
LOW 70
14
12
17
6
5
90
18
15
105
21
18
ns 2.0
4.5
6.0
Fig.9
tsu set-up time
D, An to LE 80
16
14
19
7
6
100
20
17
120
24
20
ns 2.0
4.5
6.0
Figs 10 and 11
thhold time
D to LE 0
0
0
−19
−6
−5
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.10
thhold time
An to LE 2
2
2
−11
−4
−3
2
2
2
2
2
2
ns 2.0
4.5
6.0
Fig.11
December 1990 8
Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
An
LE
D
MR
1.50
1.50
1.20
0.75
December 1990 9
Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS
+25 −40 TO +85 −40 TO +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
D to Qn
23 39 49 59 ns 4.5 Fig.7
tPHL/ tPLH propagation delay
An to Qn
25 41 51 62 ns 4.5 Fig.8
tPHL/ tPLH propagation delay
LE to Qn
22 38 48 57 ns 4.5 Fig.6
tPHL propagation delay
MR to Qn
23 39 49 59 ns 4.5 Fig.9
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 6 and 7
tWLE pulse width
LOW 19 11 24 29 ns 4.5 Fig.6
tWMR pulse width
LOW 18 10 23 27 ns 4.5 Fig.9
tsu set-up time
D to LE 17 10 21 26 ns 4.5 Fig.10
tsu set-up time
An to LE 17 10 21 26 ns 4.5 Fig.11
thhold time
D to LE 0−8 0 0 ns 4.5 Fig.10
thhold time
An to LE 0−4 0 0 ns 4.5 Fig.11
December 1990 10
Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
AC WAVEFORMS
Fig.6 Waveforms showing the enable input (LE) to output (Qn) propagation delays, the enable input pulse width
and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the data input (D) to output (Qn) propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the address inputs (An) to outputs (Qn) propagation delays and the output transition
times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
December 1990 11
Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.9 Waveforms showing the conditional reset input (MR) to output (Qn) propagation delays.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.10 Waveforms showing the data set-up and hold times for the D input to LE input.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.11 Waveforms showing the address set-up and hold times for An inputs to LE input.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
