W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
Preliminary – Revision C
1.8V 1G-BIT
SERIAL SLC NAND FLASH MEMORY WITH
DUAL/QUAD SPI
BUFFER READ & CONTINUOUS READ
W25N01GWxxIG/IT
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Table of Contents
1. GENERAL DESCRIPTIONS ............................................................................................................. 6
2. FEATURES ....................................................................................................................................... 6
3. PACKAGE TYPES AND PIN CONFIGURATIONS ........................................................................... 7
3.1 Pad Configuration WSON 8x6-mm ...................................................................................... 7
3.2 Pad Description WSON 8x6-mm .......................................................................................... 7
3.3 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8
3.4 Ball Description TFBGA 8x6-mm ......................................................................................... 8
4. PIN DESCRIPTIONS ........................................................................................................................ 9
4.1 Chip Select (/CS) .................................................................................................................. 9
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ..................................... 9
4.3 Write Protect (/WP) .............................................................................................................. 9
4.4 HOLD (/HOLD) ..................................................................................................................... 9
4.5 Serial Clock (CLK) ................................................................................................................ 9
5. BLOCK DIAGRAM .......................................................................................................................... 10
6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 11
6.1 Device Operation Flow ....................................................................................................... 11
6.1.1 Standard SPI Instructions ..................................................................................................... 11
6.1.2 Dual SPI Instructions ............................................................................................................ 12
6.1.3 Quad SPI Instructions ........................................................................................................... 12
6.1.4 Hold Function ....................................................................................................................... 12
6.2 Write Protection .................................................................................................................. 13
7. PROTECTION, CONFIGURATION AND STATUS REGISTERS .................................................. 14
7.1 Protection Register / Status Register-1 (Volatile Writable, OTP lockable) ......................... 14
7.1.1 Block Protect Bits (BP3, BP2, BP1, BP0, TB) – Volatile Writable, OTP lockable ................. 14
7.1.2 Write Protection Enable Bit (WP-E) – Volatile Writable, OTP lockable ................................ 15
7.1.3 Status Register Protect Bits (SRP1, SRP0) – Volatile Writable, OTP lockable .................... 15
7.2 Configuration Register / Status Register-2 (Volatile Writable) ........................................... 16
7.2.1 One Time Program Lock Bit (OTP-L) – OTP lockable .......................................................... 16
7.2.2 Enter OTP Access Mode Bit (OTP-E) – Volatile Writable ..................................................... 16
7.2.3 Status Register-1 Lock Bit (SR1-L) – OTP lockable ............................................................. 16
7.2.4 ECC Enable Bit (ECC-E) – Volatile Writable ........................................................................ 17
7.2.5 Buffer Read / Continuous Read Mode Bit (BUF) – Volatile Writable .................................... 17
7.3 Status Register-3 (Status Only) .......................................................................................... 18
7.3.1 Look-Up Table Full (LUT-F) – Status Only ........................................................................... 18
7.3.2 Cumulative ECC Status (ECC-1, ECC-0) – Status Only....................................................... 18
7.3.3 Program/Erase Failure (P-FAIL, E-FAIL) – Status Only ....................................................... 19
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 2 - Preliminary – Revision C
7.3.4 Write Enable Latch (WEL) – Status Only ............................................................................. 19
7.3.5 Erase/Program In Progress (BUSY) – Status Only .............................................................. 19
7.3.6 Reserved Bits – Non Functional ........................................................................................... 19
7.4 W25N01GW Status Register Memory Protection .............................................................. 20
8. INSTRUCTIONS ............................................................................................................................. 21
8.1 Device ID and Instruction Set Tables ................................................................................. 21
8.1.1 Manufacturer and Device Identification ................................................................................ 21
8.1.2 Instruction Set Table 1 (Continuous Read, BUF = 0, xxIT Default Power Up Mode)(11) ....... 22
8.1.3 Instruction Set Table 2 (Buffer Read, BUF = 1, xxIG Default Power Up Mode)(12) ............... 23
8.2 Instruction Descriptions ...................................................................................................... 25
8.2.1 Device Reset (FFh) .............................................................................................................. 25
8.2.2 Read JEDEC ID (9Fh) .......................................................................................................... 26
8.2.3 Read Status Register (0Fh / 05h) ......................................................................................... 27
8.2.4 Write Status Register (1Fh / 01h) ......................................................................................... 28
8.2.5 Write Enable (06h) ............................................................................................................... 29
8.2.6 Write Disable (04h) ............................................................................................................... 29
8.2.7 Bad Block Management (A1h) .............................................................................................. 30
8.2.8 Read BBM Look Up Table (A5h) .......................................................................................... 31
8.2.9 Last ECC Failure Page Address (A9h) ................................................................................. 32
8.2.10 128KB Block Erase (D8h) ................................................................................................... 33
8.2.11 Load Program Data (02h) / Random Load Program Data (84h) ......................................... 34
8.2.12 Quad Load Program Data (32h) / Quad Random Load Program Data (34h) ..................... 35
8.2.13 Program Execute (10h)....................................................................................................... 36
8.2.14 Page Data Read (13h) ........................................................................................................ 37
8.2.15 Read Data (03h) ................................................................................................................. 38
8.2.16 Fast Read (0Bh) ................................................................................................................. 39
8.2.17 Fast Read with 4-Byte Address (0Ch) ................................................................................ 40
8.2.18 Fast Read Dual Output (3Bh) ............................................................................................. 41
8.2.19 Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................ 42
8.2.20 Fast Read Quad Output (6Bh) ............................................................................................ 43
8.2.21 Fast Read Quad Output with 4-Byte Address (6Ch) ........................................................... 44
8.2.22 Fast Read Dual I/O (BBh) ................................................................................................... 45
8.2.23 Fast Read Dual I/O with 4-Byte Address (BCh) .................................................................. 46
8.2.24 Fast Read Quad I/O (EBh) ................................................................................................. 47
8.2.25 Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................ 49
8.2.26 Accessing Unique ID / Parameter / OTP Pages (OTP-E=1) ............................................... 51
8.2.27 Parameter Page Data Definitions ....................................................................................... 52
9. ELECTRICAL CHARACTERISTICS ............................................................................................... 53
9.1 Absolute Maximum Ratings (1) ............................................................................................ 53
9.2 Operating Ranges............................................................................................................... 53
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9.3 Power-up Power-down Timing Requirements .................................................................... 54
9.4 DC Electrical Characteristics .............................................................................................. 55
9.5 AC Measurement Conditions .............................................................................................. 56
9.6 AC Electrical Characteristics(3) ........................................................................................... 57
9.7 Serial Output Timing ........................................................................................................... 59
9.8 Serial Input Timing .............................................................................................................. 59
9.9 /HOLD Timing ..................................................................................................................... 59
9.10 /WP Timing ......................................................................................................................... 59
10. PACKAGE SPECIFICATIONS ........................................................................................................ 60
10.1 8-Pad WSON 8x6-mm (Package Code ZE) ....................................................................... 60
10.2 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 Ball Array) ......................................... 61
10.3 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 Ball Array) ............................................ 62
11. ORDERING INFORMATION .......................................................................................................... 63
11.1 Valid Part Numbers and Top Side Marking ........................................................................ 64
12. REVISION HISTORY ...................................................................................................................... 65
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 4 - Preliminary – Revision C
Table of Figures
Figure 1a. W25N01GW Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE) ............................. 7
Figure 1b. W25N01GW Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB & TC) .................. 8
Figure 2. W25N01GW Flash Memory Architecture and Addressing .......................................................... 10
Figure 3. W25N01GW Flash Memory Operation Diagram ......................................................................... 11
Figure 4a. Protection Register / Status Register-1 (Address Axh) .............................................................. 14
Figure 4b. Configuration Register / Status Register-2 (Address Bxh) ......................................................... 16
Figure 4c. Status Register-3 (Address Cxh) ............................................................................................... 18
Figure 5. Device Reset Instruction .............................................................................................................. 25
Figure 6. Read JEDEC ID Instruction.......................................................................................................... 26
Figure 7. Read Status Register Instruction ................................................................................................. 27
Figure 8. Write Status Register-1/2/3 Instruction ........................................................................................ 28
Figure 9. Write Enable Instruction ............................................................................................................... 29
Figure 10. Write Disable Instruction ............................................................................................................ 29
Figure 11. Bad Block Management Instruction ........................................................................................... 30
Figure 12. Read BBM Look Up Table Instruction ........................................................................................ 31
Figure 13. Last ECC Failure Page Address Instruction .............................................................................. 32
Figure 14. 128KB Block Erase Instruction .................................................................................................. 33
Figure 15. Load / Random Load Program Data Instruction ........................................................................ 34
Figure 16. Quad Load / Quad Random Load Program Data Instruction ..................................................... 35
Figure 17. Program Execute Instruction ...................................................................................................... 36
Figure 18. Page Data Read Instruction ....................................................................................................... 37
Figure 19a. Read Data Instruction (Buffer Read Mode, BUF=1) ................................................................ 38
Figure 19b. Read Data Instruction (Continuous Read Mode, BUF=0) ........................................................ 38
Figure 20a. Fast Read Instruction (Buffer Read Mode, BUF=1) ................................................................. 39
Figure 20b. Fast Read Instruction (Continuous Read Mode, BUF=0) ........................................................ 39
Figure 21a. Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ................................ 40
Figure 21b. Fast Read with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ....................... 40
Figure 22a. Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1) ............................................. 41
Figure 22b. Fast Read Dual Output Instruction (Continuous Read Mode, BUF=0) .................................... 41
Figure 23a. Fast Read Dual Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ............ 42
Figure 23b. Fast Read Dual Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ... 42
Figure 24a. Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1) ........................................... 43
Figure 24b. Fast Read Quad Output Instruction (Continuous Read Mode, BUF=0) ................................... 43
Figure 25a. Fast Read Quad Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) .......... 44
Figure 25b. Fast Read Quad Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) .. 44
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Figure 26a. Fast Read Dual I/O Instruction (Buffer Read Mode, BUF=1) ................................................... 45
Figure 26b. Fast Read Dual I/O Instruction (Continuous Read Mode, BUF=0) .......................................... 45
Figure 27a. Fast Read Dual I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) .................. 46
Figure 27b. Fast Read Dual I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ......... 46
Figure 28a. Fast Read Quad I/O Instruction (Buffer Read Mode, BUF=1) ................................................. 47
Figure 28b. Fast Read Quad I/O Instruction (Continuous Read Mode, BUF=0) ......................................... 48
Figure 29a. Fast Read Quad I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ................ 49
Figure 29b. Fast Read Quad I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ........ 50
Figure 30a. Power-up Timing and Voltage Levels ...................................................................................... 54
Figure 30b. Power-up, Power-Down Requirement ...................................................................................... 54
Figure 31. AC Measurement I/O Waveform................................................................................................ 56
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 6 - Preliminary – Revision C
1. GENERAL DESCRIPTIONS
The W25N01GW (1G-bit) Serial SLC NAND Flash Memory provides a storage solution for systems with
limited space, pins and power. The W25N SpiFlash family incorporates the popular SPI interface and the
traditional large NAND non-volatile memory space. They are ideal for code shadowing to RAM, executing
code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single
1.70V to 1.95V power supply with current consumption as low as 25mA active and 10µA for standby. All
W25N SpiFlash family devices are offered in space-saving packages which were impossible to use in the
past for the typical NAND flash memory.
The W25N01GW 1G-bit memory array is organized into 65,536 programmable pages of 2,048-bytes
each. The entire page can be programmed at one time using the data from the 2,048-Byte internal buffer.
Pages can be erased in groups of 64 (128KB block erase). The W25N01GW has 1,024 erasable blocks.
The W25N01GW supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial
Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies
of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and
416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions.
The W25N01GW provides a new Continuous Read Mode that allows for efficient access to the entire
memory array with a single Read command. This feature is ideal for code shadowing applications.
A Hold pin, Write Protect pin and programmable write protection, provide further control flexibility.
Additionally, the device supports JEDEC standard manufacturer and device ID, one 2,048-Byte Unique ID
page, one 2,048-Byte parameter page and ten 2,048-Byte OTP pages. To provide better NAND flash
memory manageability, user configurable internal ECC, bad block management are also available in
W25N01GW.
2. FEATURES
New W25N Family of SpiFlash Memories
– W25N01GW: 1G-bit / 128M-byte
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– Compatible SPI serial flash commands
Highest Performance Serial NAND Flash
– 104MHz Standard/Dual/Quad SPI clocks
– 208/416MHz equivalent Dual/Quad SPI
– 40MB/S continuous data transfer rate
– Fast Program/Erase performance
– More than 100,000 erase/program cycles
– More than 10-year data retention
Efficient “Continuous Read Mode”(1)
– Alternative method to the Buffer Read Mode
– No need to issue “Page Data Read” between
Read commands
– Allows direct read access to the entire array
Low Power, Wide Temperature Range
– Single 1.70V to 1.95V supply
– 25mA active, 10µA standby current
– -40°C to +85°C operating range
Flexible Architecture with 128KB blocks
– Uniform 128K-Byte Block Erase
– Flexible page data load methods
Advanced Features
– On chip 1-Bit ECC for memory array
– ECC status bits indicate ECC results
– bad block management and LUT(2) access
– Software and Hardware Write-Protect
– Power Supply Lock-Down and OTP protection
– 2KB Unique ID and 2KB parameter pages
– Ten 2KB OTP pages(3)
Space Efficient Packaging
– 8-pad WSON 8x6-mm
– 24-ball TFBGA 8x6-mm
– Contact Winbond for other package options
Notes:
1. Only the Read command structures are different between
the “Continuous Read Mode (BUF=0)” and the “Buffer
Read Mode (BUF=1)”, all other commands are identical.
W25N01GWxxIG: Default BUF=1 after power up
W25N01GWxxIT: Default BUF=0 after power up
2. LUT stands for Look-Up Table.
3. OTP pages can only be programmed.
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3. PACKAGE TYPES AND PIN CONFIGURATIONS
W25N01GW is offered in an 8-pad WSON 8x6-mm (package code ZE), and two 24-ball 8x6-mm TFBGA
(package code TB & TC) packages as shown in Figure 1a-b respectively. Package diagrams and
dimensions are illustrated at the end of this datasheet.
3.1 Pad Configuration WSON 8x6-mm
1
2
3
4
/CS
DO (IO1)
/WP (IO2)
GND
VCC
/HOLD (IO3)
DI (IO0)
CLK
Top View
8
7
6
5
Figure 1a. W25N01GW Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE)
3.2 Pad Description WSON 8x6-mm
PAD NO.
PAD NAME
I/O
FUNCTION
1
/CS
I
Chip Select Input
2
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
3
/WP (IO2)
I/O
Write Protect Input ( Data Input Output 2)(2)
4
GND
Ground
5
DI (IO0)
I/O
Data Input (Data Input Output 0)(1)
6
CLK
I
Serial Clock Input
7
/HOLD (IO3)
I/O
Hold Input (Data Input Output 3)(2)
8
VCC
Power Supply
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD functions are only available for Standard/Dual SPI.
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 8 - Preliminary – Revision C
3.3 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
Figure 1b. W25N01GW Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB & TC)
3.4 Ball Description TFBGA 8x6-mm
BALL NO.
PIN NAME
I/O
FUNCTION
B2
CLK
I
Serial Clock Input
B3
GND
Ground
B4
VCC
Power Supply
C2
/CS
I
Chip Select Input
C4
/WP (IO2)
I/O
Write Protect Input (Data Input Output 2)(2)
D2
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
D3
DI (IO0)
I/O
Data Input (Data Input Output 0)(1)
D4
/HOLD (IO3)
I/O
Hold Input (Data Input Output 3)(2)
Multiple
NC
No Connect
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD functions are only available for Standard/Dual SPI.
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4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure
30b). If needed, a pull-up resistor on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25N01GW supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge of
CLK.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect bits BP[3:0] and Status Register Protect SRP bits
SRP[1:0], a portion as small as 256K-Byte (2x128KB blocks) or up to the entire memory array can be
hardware protected. The WP-E bit in the Protection Register (SR-1) controls the functions of the /WP pin.
When WP-E=0, the device is in the Software Protection mode that only SR-1 can be protected. The /WP
pin functions as a data I/O pin for the Quad SPI operations, as well as an active low input pin for the Write
Protection function for SR-1. Refer to section 7.1.3 for detail information.
When WP-E=1, the device is in the Hardware Protection mode that /WP becomes a dedicated active low
input pin for the Write Protection of the entire device. If /WP is tied to GND, all “Write/Program/Erase”
functions are disabled. The entire device (including all registers, memory array, OTP pages) will become
read-only. Quad SPI read operations are also disabled when WP-E is set to 1.
4.4 HOLD (/HOLD)
During Standard and Dual SPI operations, the /HOLD pin allows the device to be paused while it is actively
selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals
on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can
resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The
/HOLD pin is active low.
When a Quad SPI Read/Buffer Load command is issued, /HOLD pin will become a data I/O pin for the
Quad operations and no HOLD function is available until the current Quad operation finishes.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 10 - Preliminary – Revision C
5. BLOCK DIAGRAM
Figure 2. W25N01GW Flash Memory Architecture and Addressing
Page
Structure
(2,112-Byte)
Sector 0
512-Byte
Sector 1
512-Byte
Sector 2
512-Byte
Sector 3
512-Byte
Spare 0
16-Byte
Spare 1
16-Byte
Spare 2
16-Byte
Spare 3
16-Byte
Column
Address
000h -- 1FFh
200h -- 3FFh
400h -- 5FFh
600h -- 7FFh
800h -- 80Fh
810h -- 81Fh
820h -- 82Fh
830h -- 83Fh
Byte
Definition
Bad Block
Marker
User Data
II
User Data
I
ECC for
Sector 0
ECC for
Spare
Byte
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Main Memory Array (2,048-Byte)
ECC Protected Spare Area (64-Byte)
No ECC
Protection ECC
Protected ECC for
Byte 4 to Byte D
Block (64 Pages, 64 X 2KB) 64 X
64B
Main Array
Data Buffer (2,048 Byte) 64
Byte
1,024 Blocks X 64 Pages
(65,536 Pages)
Page Address PA[15:0]
2,112 Bytes
Column Address CA[11:0]
Address Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SpiFlash (up to 128M-Bit) X X X X X X X X
SpiFlash (up to 32G-Bit) X X X X
X X X X Ext
Serial NAND (1G-Bit)
Page Address (PA) [15:0]
Column Address (CA) [11:0]
128KB Block Addr (1024 Blocks)
Page Addr (64 Pages)
Byte Address (0-2047 Byte)
64KB Block Addr (256 Blocks)
Page Address (256 Pages)
Byte Address (0-255 Byte)
64KB Block Address
Page Address (256 Pages)
Byte Address (0-255 Byte)
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6. FUNCTIONAL DESCRIPTIONS
6.1 Device Operation Flow
Power Up
(default BUF=1, ECC-E=1)
Initialization &
Default Page Load (00) ~500us
Load Page xx
tRD ~50us
Y
N
Start “Buffer Read” with column address
(Page 00 or Page xx)
Read
page 00?
Set BUF=0
Load Page yy
tRD ~50us
Start “Continuous Read” from column 0
(Page yy)
Power Up
(default BUF=0, ECC-E=1)
Initialization &
Default Page Load (00) ~500us
Load Page xx
tRD ~50us
Y
N
Start “Continuous Read” from column 0
(Page 00 or Page xx)
Read
page 00?
Set BUF=1
Load Page yy
tRD ~50us
Start “Buffer Read” with column address
(Page yy)
W25N01GWxxIG W25N01GWxxIT
Figure 3. W25N01GW Flash Memory Operation Diagram
6.1.1 Standard SPI Instructions
The W25N01GW is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is
not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and
rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 12 - Preliminary – Revision C
6.1.2 Dual SPI Instructions
The W25N01GW supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the
device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are
ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-
critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins
become bidirectional I/O pins: IO0 and IO1.
6.1.3 Quad SPI Instructions
The W25N01GW supports Quad SPI operation when using instructions such as “Fast Read Quad Output
(6Bh)”, “Fast Read Quad I/O (EBh)” and “Quad Program Data Load (32h/34h)”. These instructions allow
data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad
Read instructions offer a significant improvement in continuous and random access transfer rates allowing
fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI
instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become
IO2 and IO3 respectively.
6.1.4 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25N01GW operation to be
paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where
the SPI data and clock signals are shared with other devices. For example, consider if the page buffer
was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD
function can save the state of the instruction and the data in the buffer so programming can resume where
it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual
SPI operation, not during Quad SPI. When a Quad SPI command is issued, /HOLD pin will act as a
dedicated IO pin (IO3).
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on
the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the
rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD
condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data
Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip
Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid
resetting the internal logic state of the device.
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6.2 Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25N01GW
provides several means to protect the data from inadvertent writes.
Device resets when VCC is below threshold
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (/WP pin) write protection using Protection Register (SR-1)
Lock Down write protection for Protection Register (SR-1) until the next power-up
One Time Program (OTP) write protection for memory array using Protection Register (SR-1)
Hardware write protection using /WP pin when WP-E is set to 1
Upon power-up or at power-down, the W25N01GW will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 30a). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Program Execute, Block Erase and the Write Status Register instructions. Note
that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL
time delay is reached, and it must also track the VCC supply level at power-down to prevent adverse
command sequence. If needed a pull-up resister on /CS can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Program Execute or
Block Erase instruction will be accepted. After completing a program or erase instruction the Write Enable
Latch (WEL) is automatically cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP0, SRP1) and Block Protect (TB, BP[3:0]) bits. These settings allow a portion
or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP)
pin, changes to the Status Register can be enabled or disabled under hardware control. See Protection
Register section for further information.
The WP-E bit in Protection Register (SR-1) is used to enable the hardware protection. When WP-E is set
to 1, bringing /WP low in the system will block any Write/Program/Erase command to the W25N01GW,
the device will become read-only. The Quad SPI operations are also disabled when WP-E is set to 1.
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 14 - Preliminary – Revision C
7. PROTECTION, CONFIGURATION AND STATUS REGISTERS
Three Status Registers are provided for W25N01GW: Protection Register (SR-1), Configuration Register
(SR-2) & Status Register (SR-3). Each register is accessed by Read Status Register and Write Status
Register commands combined with 1-Byte Register Address respectively.
The Read Status Register instruction (05h / 0Fh) can be used to provide status on the availability of the
flash memory array, whether the device is write enabled or disabled, the state of write protection, Read
modes, Protection Register/OTP area lock status, Erase/Program results, ECC usage/status. The Write
Status Register instruction can be used to configure the device write protection features, Software/Hardware
write protection, Read modes, enable/disable ECC, Protection Register/OTP area lock. Write access to the
Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the
Write Enable instruction, and when WP-E is set to 1, the /WP pin.
7.1 Protection Register / Status Register-1 (Volatile Writable, OTP lockable)
S7 S6 S5 S4 S3 S2 S1 S0
SRP0 BP3 BP2 BP1 BP0 TB
Status Register Protect-0
(Volatile Writable, OTP Lock)
Top/Bottom Protect Bit
(Volatile Writable, OTP Lock)
Block Protect Bits
(Volatile Writable, OTP Lock)
SRP1WP-E
Status Register Protect-1
(Volatile Writable, OTP Lock)
/WP Enable Bit
(Volatile Writable, OTP Lock)
Figure 4a. Protection Register / Status Register-1 (Address Axh)
7.1.1 Block Protect Bits (BP3, BP2, BP1, BP0, TB) – Volatile Writable, OTP lockable
The Block Protect bits (BP3, BP2, BP1, BP0 & TB) are volatile read/write bits in the status register-1 (S6,
S5, S4, S3 & S2) that provide Write Protection control and status. Block Protect bits can be set using the
Write Status Register Instruction. All, none or a portion of the memory array can be protected from
Program and Erase instructions (see Status Register Memory Protection table). The default values for the
Block Protection bits are 1 after power up to protect the entire array. If the SR1-L bit in the Configuration
Register (SR-2) is set to 1, the default values will the values that are OTP locked.
W25N01GWxxIG/IT
- 15 -
7.1.2 Write Protection Enable Bit (WP-E) – Volatile Writable, OTP lockable
The Write Protection Enable bit (WP-E) is a volatile read/write bits in the status register-1 (S1). The WP-E
bit, in conjunction with SRP1 & SRP0, controls the method of write protection: software protection,
hardware protection, power supply lock-down or one time programmable (OTP) protection, /WP pin
functionality, and Quad SPI operation enable/disable. When WP-E = 0 (default value), the device is in
Software Protection mode, /WP & /HOLD pins are multiplexed as IO pins, and Quad program/read
functions are enabled all the time. When WP-E is set to 1, the device is in Hardware Protection mode, all
Quad functions are disabled and /WP & /HOLD pins become dedicated control input pins.
7.1.3 Status Register Protect Bits (SRP1, SRP0) – Volatile Writable, OTP lockable
The Status Register Protect bits (SRP1 and SRP0) are volatile read/write bits in the status register (S0
and S7). The SRP bits control the method of write protection: software protection, hardware protection,
power supply lock-down or one time programmable (OTP) protection.
Software Protection (Driven by Controller, Quad Program/Read is enabled)
SRP1
SRP0
WP-E
/WP / IO2
Descriptions
0
0
0
X
No /WP functionality
/WP pin will always function as IO2
0
1
0
0
SR-1 cannot be changed (/WP = 0 during Write Status)
/WP pin will function as IO2 for Quad operations
0
1
0
1
SR-1 can be changed (/WP = 1 during Write Status)
/WP pin will function as IO2 for Quad operations
1
0
0
X
Power Lock Down(1) SR-1
/WP pin will always function as IO2
1
1
0
X
Enter OTP mode to protect SR-1 (allow SR1-L=1)
/WP pin will always function as IO2
Hardware Protection (System Circuit / PCB layout, Quad Program/Read is disabled)
SRP1
SRP0
WP-E
/WP only
Descriptions
0
X
1
VCC
SR-1 can be changed
1
0
1
VCC
Power Lock-Down(1) SR-1
1
1
1
VCC
Enter OTP mode to protect SR-1 (allow SR1-L=1)
X
X
1
GND
All "Write/Program/Erase" commands are blocked
Entire device (SRs, Array, OTP area) is read-only
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 16 - Preliminary – Revision C
7.2 Configuration Register / Status Register-2 (Volatile Writable)
S7 S6 S5 S4 S3 S2 S1 S0
BUF
Reserved
Enter OTP Mode
(Volatile Writable)
Buffer Mode
(Volatile Writable)
OTP Data Pages Lock
(OTP Lock)
OTP-L OTP-E ECC-E
Enable ECC
(Volatile Writable)
(R) (R)SR1-L
Status Register-1 Lock
(OTP Lock)
(R)
Figure 4b. Configuration Register / Status Register-2 (Address Bxh)
7.2.1 One Time Program Lock Bit (OTP-L) – OTP lockable
In addition to the main memory array, W25N01GW also provides an OTP area for the system to store
critical data that cannot be changed once it’s locked. The OTP area consists of 10 pages of 2,112-Byte
each. The default data in the OTP area are FFh. Only Program command can be issued to the OTP area
to change the data from “1” to “0”, and data is not reversible (“0” to “1”) by the Erase command. Once the
correct data is programmed in and verified, the system developer can set OTP-L bit to 1, so that the entire
OTP area will be locked to prevent further alteration to the data.
7.2.2 Enter OTP Access Mode Bit (OTP-E) – Volatile Writable
The OTP-E bit must be set to 1 in order to use the standard Program/Read commands to access the OTP
area as well as to read the Unique ID / Parameter Page information. The default value after power up or a
RESET command is 0.
7.2.3 Status Register-1 Lock Bit (SR1-L) – OTP lockable
The SR1-L lock bit is used to OTP lock the values in the Protection Register (SR-1). Depending on the
settings in the SR-1, the device can be configured to have a portion of or up to the entire array to be write-
protected, and the setting can be OTP locked by setting SR1-L bit to 1. SR1-L bit can only be set to 1
permanently when SRP1 & SRP0 are set to (1,1), and OTP Access Mode must be entered (OTP-E=1) to
execute the programming. Please refer to 8.2.26 for detailed information.
W25N01GWxxIG/IT
- 17 -
7.2.4 ECC Enable Bit (ECC-E) – Volatile Writable
W25N01GW has a built-in ECC algorithm that can be used to preserve the data integrity. Internal ECC
calculation is done during page programming, and the result is stored in the extra 64-Byte area for each
page. During the data read operation, ECC engine will verify the data values according to the previously
stored ECC information and to make necessary corrections if needed. The verification and correction
status is indicated by the ECC Status Bits. ECC function is enabled by default when power on (ECC-E=1),
and it will not be reset to 0 by the Device Reset command.
7.2.5 Buffer Read / Continuous Read Mode Bit (BUF) – Volatile Writable
W25N01GW provides two different modes for read operations, Buffer Read Mode (BUF=1) and
Continuous Read Mode (BUF=0). Prior to any Read operation, a Page Data Read command is needed to
initiate the data transfer from a specified page in the memory array to the Data Buffer. By default, after
power up, the data in page 0 will be automatically loaded into the Data Buffer and the device is ready to
accept any read commands.
The Buffer Read Mode (BUF=1) requires a Column Address to start outputting the existing data inside the
Data Buffer, and once it reaches the end of the data buffer (Byte 2,111), DO (IO1) pin will become high-Z
state.
The Continuous Read Mode (BUF=0) doesn’t require the starting Column Address. The device will always
start output the data from the first column (Byte 0) of the Data buffer, and once the end of the data buffer
(Byte 2,048) is reached, the data output will continue through the next memory page. With Continuous
Read Mode, it is possible to read out the entire memory array using a single read command. Please refer
to respective command descriptions for the dummy cycle requirements for each read commands under
different read modes.
For W25N01GWxxIG part number, the default value of BUF bit after power up is 1. BUF bit can be written
to 0 in the Status Register-2 to perform the Continuous Read operation.
For W25N01GWxxIT part number, the default value of BUF bit after power up is 0. BUF bit can be written
to 1 in the Status Register-2 to perform the Buffer Read operation.
BUF
ECC-E
Read Mode
(Starting from Buffer)
ECC Status
Data Output Structure
1
0
Buffer Read
N/A
2,048 + 64
1
1
Buffer Read
Page based
2,048 + 64
0
0
Continuous Read
N/A
2,048
0
1
Continuous Read
Operation based
2,048
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 18 - Preliminary – Revision C
7.3 Status Register-3 (Status Only)
S7 S6 S5 S4 S3 S2 S1 S0
Write Enable Latch
(Status-Only)
(R) ECC-1 ECC-0 WEL BUSYP-FAIL E-FAIL
Reserved
ECC Status Bit[1:0]
(Status-Only)
Program Failure
(Status-Only)
Erase Failure
(Status-Only)
Operation In Progress
(Status-Only)
BBM LUT Full
(Status Only)
LUT-F
Figure 4c. Status Register-3 (Address Cxh)
7.3.1 Look-Up Table Full (LUT-F) – Status Only
To facilitate the NAND flash memory bad block management, the W25N01GW is equipped with an
internal Bad Block Management Look-Up-Table (BBM LUT). Up to 20 bad memory blocks may be
replaced by a good memory block respectively. The addresses of the blocks are stored in the internal
Look-Up Table as Logical Block Address (LBA, the bad block) & Physical Block Address (PBA, the good
block). The LUT-F bit indicates whether the 20 memory block links have been fully utilized or not. The
default value of LUT-F is 0, once all 20 links are used, LUT-F will become 1, and no more memory block
links may be established.
7.3.2 Cumulative ECC Status (ECC-1, ECC-0) – Status Only
ECC function is used in NAND flash memory to correct limited memory errors during read operations. The
ECC Status Bits (ECC-1, ECC-0) should be checked after the completion of a Read operation to verify the
data integrity. The ECC Status bits values are don’t care if ECC-E=0. These bits will be cleared to 0 after a
power cycle or a RESET command.
W25N01GWxxIG/IT
- 19 -
ECC Status
Descriptions
ECC-1
ECC-0
0
0
Entire data output is successful, without any ECC correction.
0
1
Entire data output is successful, with 1~4 bit/page ECC corrections in either a
single page or multiple pages.
1
0
Entire data output contains more than 4 bits errors only in a single page
which cannot be repaired by ECC.
In the Continuous Read Mode, an additional command can be used to read out
the Page Address (PA) which had the errors.
1
1
Entire data output contains more than 4 bits errors/page in multiple pages.
In the Continuous Read Mode, the additional command can only provide the
last Page Address (PA) that had failures, the user cannot obtain the PAs for
other failure pages. Data is not suitable to use.
Notes:
1. ECC-1,ECC-0 = (1,1) is only applicable during Continuous Read operation (BUF=0).
7.3.3 Program/Erase Failure (P-FAIL, E-FAIL) – Status Only
The Program/Erase Failure Bits are used to indicate whether the internally-controlled Program/Erase
operation was executed successfully or not. These bits will also be set respectively when the Program or
Erase command is issued to a locked or protected memory array or OTP area. Both bits will be cleared at
the beginning of the Program Execute or Block Erase instructions as well as the device RESET
instruction.
7.3.4 Write Enable Latch (WEL) – Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Program
Execute, Block Erase, Page Data Read and Program Execute for OTP pages.
7.3.5 Erase/Program In Progress (BUSY) – Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is powering up or
executing a Page Data Read, BBM Management, Program Execute, Block Erase, Program Execute for
OTP area, OTP Locking or after a Continuous Read instruction. During this time the device will ignore
further instructions except for the Read Status Register and Read JEDEC ID instructions. When the
program, erase or write status register instruction has completed, the BUSY bit will be cleared to a 0 state
indicating the device is ready for further instructions.
7.3.6 Reserved Bits – Non Functional
There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be
written as “0”, but there will not be any effects.
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 20 - Preliminary – Revision C
7.4 W25N01GW Status Register Memory Protection
STATUS REGISTER(1)
W25N01GW (1G-BIT / 128M-BYTE) MEMORY PROTECTION(2)
TB
BP3
BP2
BP1
BP0
PROTECTED
BLOCK(S)
PROTECTED
PAGE ADDRESS
PA[15:0]
PROTECTED
DENSITY
PROTECTED
PORTION
X
0
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
1022 & 1023
FF80h - FFFFh
256KB
Upper 1/512
0
0
0
1
0
1020 thru 1023
FF00h - FFFFh
512KB
Upper 1/256
0
0
0
1
1
1016 thru 1023
FE00h - FFFFh
1MB
Upper 1/128
0
0
1
0
0
1008 thru 1023
FC00h - FFFFh
2MB
Upper 1/64
0
0
1
0
1
992 thru 1023
F800h - FFFFh
4MB
Upper 1/32
0
0
1
1
0
960 thru 1023
F000h - FFFFh
8MB
Upper 1/16
0
0
1
1
1
896 thru 1023
E000h - FFFFh
16MB
Upper 1/8
0
1
0
0
0
768 thru 1023
C000h - FFFFh
32MB
Upper 1/4
0
1
0
0
1
512 thru 1023
8000h - FFFFh
64MB
Upper 1/2
1
0
0
0
1
0 & 1
0000h – 007Fh
256KB
Lower 1/512
1
0
0
1
0
0 thru 3
0000h - 00FFh
512KB
Lower 1/256
1
0
0
1
1
0 thru 7
0000h - 01FFh
1MB
Lower 1/128
1
0
1
0
0
0 thru 15
0000h - 03FFh
2MB
Lower 1/64
1
0
1
0
1
0 thru 31
0000h - 07FFh
4MB
Lower 1/32
1
0
1
1
0
0 thru 63
0000h - 0FFFh
8MB
Lower 1/16
1
0
1
1
1
0 thru 127
0000h - 1FFFh
16MB
Lower 1/8
1
1
0
0
0
0 thru 255
0000h - 3FFFh
32MB
Lower 1/4
1
1
0
0
1
0 thru 511
0000h - 7FFFh
64MB
Lower 1/2
X
1
0
1
X
0 thru 1023
0000h - FFFFh
128MB
ALL
X
1
1
X
X
0 thru 1023
0000h - FFFFh
128MB
ALL
Notes:
1. X = don’t care
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be
ignored.
W25N01GWxxIG/IT
- 21 -
8. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the W25N01GW consists of 27 basic instructions that are
fully controlled through the SPI bus (see Instruction Set Table1, 2). Instructions are initiated with the falling
edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code.
Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 5
through 29. All read instructions can be completed after any clocked bit. However, all instructions that
Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been
clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent
writes. Additionally, while the device is performing Program or Erase operation, BBM management, Page
Data Read or OTP locking operations, BUSY bit will be high, and all instructions except for Read Status
Register or Read JEDEC ID will be ignored until the current operation cycle has completed.
8.1 Device ID and Instruction Set Tables
8.1.1 Manufacturer and Device Identification
MANUFACTURER ID
(MF7 - MF0)
Winbond Serial Flash
EFh
Device ID
(ID15 - ID0)
W25N01GW
BA21h
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 22 - Preliminary – Revision C
8.1.2 Instruction Set Table 1 (Continuous Read, BUF = 0, xxIT Default Power Up Mode)(11)
Commands
OpCode
Byte2
Byte3
Byte4
Byte5
Byte6
Byte7
Byte8
Byte9
Device RESET
FFh
JEDEC ID
9Fh
Dummy
EFh
BAh
21h
Read Status Register
0Fh / 05h
SR Addr
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
Write Status Register
1Fh / 01h
SR Addr
S7-0
Write Enable
06h
Write Disable
04h
BB Management
(Swap Blocks)
A1h
LBA
LBA
PBA
PBA
Read BBM LUT
A5h
Dummy
LBA0
LBA0
PBA0
PBA0
LBA1
LBA1
PBA1
Last ECC failure
Page Address
A9h
Dummy
PA15-8
PA7-0
Block Erase
D8h
Dummy
PA15-8
PA7-0
Program Data Load
(Reset Buffer)
02h
CA15-8
CA7-0
Data-0
Data-1
Data-2
Data-3
Data-4
Data-5
Random Program
Data Load
84h
CA15-8
CA7-0
Data-0
Data-1
Data-2
Data-3
Data-4
Data-5
Quad Program
Data Load (Reset Buffer)
32h
CA15-8
CA7-0
Data-0 / 4
Data-1 / 4
Data-2 / 4
Data-3 / 4
Data-4 / 4
Data-5 / 4
Random Quad Program
Data Load
34h
CA15-8
CA7-0
Data-0 / 4
Data-1 / 4
Data-2 / 4
Data-3 / 4
Data-4 / 4
Data-5 / 4
Program Execute
10h
Dummy
PA15-8
PA7-0
Page Data Read
13h
Dummy
PA15-8
PA7-0
Read
03h
Dummy
Dummy
Dummy
D7-0
D7-0
D7-0
D7-0
D7-0
Fast Read
0Bh
Dummy
Dummy
Dummy
Dummy
D7-0
D7-0
D7-0
D7-0
Fast Read
with 4-Byte Address
0Ch
Dummy
Dummy
Dummy
Dummy
Dummy
D7-0
D7-0
D7-0
Fast Read Dual Output
3Bh
Dummy
Dummy
Dummy
Dummy
D7-0 / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Dual Output
with 4-Byte Address
3Ch
Dummy
Dummy
Dummy
Dummy
Dummy
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Quad Output
6Bh
Dummy
Dummy
Dummy
Dummy
D7-0 / 4
D7-0 / 4
D7-0 / 4
D7-0 / 4
Fast Read Quad Output
with 4-Byte Address
6Ch
Dummy
Dummy
Dummy
Dummy
Dummy
D7-0 / 4
D7-0 / 4
D7-0 / 4
Fast Read Dual I/O
BBh
Dummy / 2
Dummy / 2
Dummy / 2
Dummy / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Dual I/O
with 4-Byte Address
BCh
Dummy / 2
Dummy / 2
Dummy / 2
Dummy / 2
Dummy / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Quad I/O
EBh
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
D7-0 / 4
D7-0 / 4
Fast Read Quad I/O
with 4-Byte Address
ECh
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
D7-0 / 4
W25N01GWxxIG/IT
- 23 -
8.1.3 Instruction Set Table 2 (Buffer Read, BUF = 1, xxIG Default Power Up Mode)(12)
Commands
OpCode
Byte2
Byte3
Byte4
Byte5
Byte6
Byte7
Byte8
Byte9
Device RESET
FFh
JEDEC ID
9Fh
Dummy
EFh
BAh
21h
Read Status Register
0Fh / 05h
SR Addr
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
Write Status Register
1Fh / 01h
SR Addr
S7-0
Write Enable
06h
Write Disable
04h
BB Management
(Swap Blocks)
A1h
LBA
LBA
PBA
PBA
Read BBM LUT
A5h
Dummy
LBA0
LBA0
PBA0
PBA0
LBA1
LBA1
PBA1
Last ECC failure
Page Address
A9h
Dummy
PA15-8
PA7-0
Block Erase
D8h
Dummy
PA15-8
PA7-0
Program Data Load
(Reset Buffer)
02h
CA15-8
CA7-0
Data-0
Data-1
Data-2
Data-3
Data-4
Data-5
Random Program
Data Load
84h
CA15-8
CA7-0
Data-0
Data-1
Data-2
Data-3
Data-4
Data-5
Quad Program
Data Load (Reset Buffer)
32h
CA15-8
CA7-0
Data-0 / 4
Data-1 / 4
Data-2 / 4
Data-3 / 4
Data-4 / 4
Data-5 / 4
Random Quad Program
Data Load
34h
CA15-8
CA7-0
Data-0 / 4
Data-1 / 4
Data-2 / 4
Data-3 / 4
Data-4 / 4
Data-5 / 4
Program Execute
10h
Dummy
PA15-8
PA7-0
Page Data Read
13h
Dummy
PA15-8
PA7-0
Read
03h
CA15-8
CA7-0
Dummy
D7-0
D7-0
D7-0
D7-0
D7-0
Fast Read
0Bh
CA15-8
CA7-0
Dummy
D7-0
D7-0
D7-0
D7-0
D7-0
Fast Read
with 4-Byte Address
0Ch
CA15-8
CA7-0
Dummy
Dummy
Dummy
D7-0
D7-0
D7-0
Fast Read Dual Output
3Bh
CA15-8
CA7-0
Dummy
D7-0 / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Dual Output
with 4-Byte Address
3Ch
CA15-8
CA7-0
Dummy
Dummy
Dummy
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Quad Output
6Bh
CA15-8
CA7-0
Dummy
D7-0 / 4
D7-0 / 4
D7-0 / 4
D7-0 / 4
D7-0 / 4
Fast Read Quad Output
with 4-Byte Address
6Ch
CA15-8
CA7-0
Dummy
Dummy
Dummy
D7-0 / 4
D7-0 / 4
D7-0 / 4
Fast Read Dual I/O
BBh
CA15-8 / 2
CA7-0 / 2
Dummy / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Dual I/O
with 4-Byte Address
BCh
CA15-8 / 2
CA7-0 / 2
Dummy / 2
Dummy / 2
Dummy / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Quad I/O
EBh
CA15-8 / 4
CA7-0 / 4
Dummy / 4
Dummy / 4
D7-0 / 4
D7-0 / 4
D7-0 / 4
D7-0 / 4
Fast Read Quad I/O
with 4-Byte Address
ECh
CA15-8 / 4
CA7-0 / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
D7-0 / 4
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 24 - Preliminary – Revision C
Notes:
1. Output designates data output from the device.
2. Column Address (CA) only requires CA[11:0], CA[15:12] are considered as dummy bits.
3. Page Address (PA) requires 16 bits. PA[15:6] is the address for 128KB blocks (total 1,024 blocks), PA[5:0]
is the address for 2KB pages (total 64 pages for each block).
4. Logical and Physical Block Address (LBA & PBA) each consists of 16 bits. LBA[9:0] & PBA[9:0] are
effective Block Addresses. LBA[15:14] is used for additional information.
5. Status Register Addresses:
Status Register 1 / Protection Register: Addr = Axh
Status Register 2 / Configuration Register: Addr = Bxh
Status Register 3 / Status Register: Addr = Cxh
6. Dual SPI Address Input (CA15-8 / 2 and CA7-0 / 2) format:
IO0 = x, x, CA10, CA8, CA6, CA4, CA2, CA0
IO1 = x, x, CA11, CA9, CA7, CA5, CA3, CA1
7. Dual SPI Data Output (D7-0 / 2) format:
IO0 = D6, D4, D2, D0, ……
IO1 = D7, D5, D3, D1, ……
8. Quad SPI Address Input (CA15-8 / 4 and CA7-0 / 4) format:
IO0 = x, CA8, CA4, CA0
IO1 = x, CA9, CA5, CA1
IO2 = x, CA10, CA6, CA2
IO3 = x, CA11, CA7, CA3
9. Quad SPI Data Input/Output (D7-0 / 4) format:
IO0 = D4, D0, ……
IO1 = D5, D1, ……
IO2 = D6, D2, ……
IO3 = D7, D3, ……
10. All Quad Program/Read commands are disabled when WP-E bit is set to 1 in the Protection Register.
11. For all Read operations in the Continuous Read Mode, once the /CS signal is brought to high to terminate
the read operation, the device will still remain busy for ~5us (BUSY=1), and all the data inside the Data
buffer will be lost and un-reliable to use. A new Page Data Read instruction must be issued to reload the
correct page data into the Data Buffer.
12. For all Read operations in the Buffer Read Mode, as soon as /CS signal is brought to high to terminate the
read operation, the device will be ready to accept new instructions and all the data inside the Data Buffer
will remain unchanged from the previous Page Data Read instruction.
W25N01GWxxIG/IT
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8.2 Instruction Descriptions
8.2.1 Device Reset (FFh)
Because of the small package and the limitation on the number of pins, the W25N01GW provide a
software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any
on-going internal operations will be terminated and the device state bits will follow the below table. Once
the Reset command is accepted by the device, the device will take approximately tRST to reset,
depending on the current operation the device is performing, tRST can be 5us~500us. During this period,
no command will be accepted.
Data corruption may happen if there is an on-going internal Erase or Program operation when Reset
command sequence is accepted by the device. It is recommended to check the BUSY bit in Status
Register before issuing the Reset command.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 1 20 4 53 6 7
Mode 0
Mode 3
High Impedance
Instruction (FFh)
Figure 5. Device Reset Instruction
Default values of the Status Registers after power up and Device Reset
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 26 - Preliminary – Revision C
8.2.2 Read JEDEC ID (9Fh)
The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial
memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the
instruction code “9Fh” followed by 8 dummy clocks. The JEDEC assigned Manufacturer ID byte for
Winbond (EFh) and two Device ID bytes are then shifted out on the falling edge of CLK with most
significant bit (MSB) first as shown in Figure 6. For memory type and capacity values refer to
Manufacturer and Device Identification table.
7
High Impedance
8 15 16 24 38
8 Dummy
Clocks
Mode 0
Mode 3
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0
Instruction
9Fh
EFh BAh 21h
23 3231
*= MSB
** *
Mfr. ID Device ID
Figure 6. Read JEDEC ID Instruction
W25N01GWxxIG/IT
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8.2.3 Read Status Register (0Fh / 05h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code “0Fh or 05h” into the DI pin on the rising edge
of CLK followed by an 8-bit Status Register Address. The status register bits are then shifted out on the
DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7. Refer to
section 7.1-3 for Status Register descriptions.
The Read Status Register instruction may be used at any time, even while a Program or Erase cycle is in
progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if
the device can accept another instruction. The Status Register can be read continuously. The instruction
is completed by driving /CS high.
7
High Impedance
8 9 15 16 17
SR Address
SR Value[7:0]
Mode 0
Mode 3
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0
Instruction
0Fh / 05h
76543210
18 19 20 21 22 23
7 6 1 0
Figure 7. Read Status Register Instruction
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 28 - Preliminary – Revision C
8.2.4 Write Status Register (1Fh / 01h)
The Write Status Register instruction allows the Status Registers to be written. The writable Status
Register bits include: SRP[1:0], TB, BP[3:0] and WP-E bit in Status Register-1; OTP-L, OTP-E, SR1-L,
ECC-E and BUF bit in Status Register-2. All other Status Register bit locations are read-only and will not
be affected by the Write Status Register instruction.
To write the Status Register bits, the instruction is entered by driving /CS low, sending the instruction code
“1Fh or 01h”, followed by an 8-bit Status Register Address, and then writing the status register data byte
as illustrated in Figure 8.
Refer to section 7.1-3 for Status Register descriptions. After power up, factory default for BP[3:0], TB,
ECC-E bits are 1, while other bits are 0.
7
High Impedance
8 9 15 16 17
SR Address SR Value[7:0]
Mode 0
Mode 3
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0
Instruction
1Fh / 01h 76543210
18 19 20 21 22 23
7 6 1 0
Figure 8. Write Status Register-1/2/3 Instruction
W25N01GWxxIG/IT
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8.2.5 Write Enable (06h)
The Write Enable instruction (Figure 9) sets the Write Enable Latch (WEL) bit in the Status Register to a
1. The WEL bit must be set prior to every Page Program, Quad Page Program and Block Erase
instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code “06h”
into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 1 20 4 53 6 7
Mode 0
Mode 3
High Impedance
Instruction (06h)
Figure 9. Write Enable Instruction
8.2.6 Write Disable (04h)
The Write Disable instruction (Figure 10) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Page Program, Quad Page Program, Block Erase and Reset instructions.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 1 20 4 53 6 7
Mode 0
Mode 3
High Impedance
Instruction (04h)
Figure 10. Write Disable Instruction
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 30 - Preliminary – Revision C
8.2.7 Bad Block Management (A1h)
Due to large NAND memory density size and the technology limitation, NAND memory devices are
allowed to be shipped to the end customers with certain amount of “Bad Blocks” found in the factory
testing. Up to 2% of the memory blocks can be marked as “Bad Blocks” upon shipment, which is a
maximum of 20 blocks for W25N01GW. In order to identify these bad blocks, it is recommended to scan
the entire memory array for bad block markers set in the factory. A “Bad Block Marker” is a non-FFh data
byte stored at Byte 0 of Page 0 for each bad block. An additional marker is also stored in the first byte of
the 64-Byte spare area.
W25N01GW offers a convenient method to manage the bad blocks typically found in NAND flash memory
after extensive use. The “Bad Block Management” command is initiated by shifting the instruction code
“A1h” into the DI pin and followed by the 16-bit “Logical Block Address” and 16-bit “Physical Block
Address” as illustrated in Figure 11. The logical block address is the address for the “bad” block that will
be replaced by the “good” block indicated by the physical block address.
Once a Bad Block Management command is successfully executed, the specified LBA-PBA link will be
added to the internal Look Up Table (LUT). Up to 20 links can be established in the non-volatile LUT. If all
20 links have been written, the LUT-F bit in the Status Register will become a 1, and no more LBA-PBA
links can be established. Therefore, prior to issuing the Bad Block Management command, the LUT-F bit
value can be checked or a “Read BBM Look Up Table” command can be issued to confirm if spare links
are still available in the LUT.
7
High Impedance
8 15 23
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0
Instruction
A1h
31
[15:8] [7:0] [15:8] [7:0]
2416 32 39
PBALBA
Mode 0
Mode 3
Figure 11. Bad Block Management Instruction
W25N01GWxxIG/IT
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8.2.8 Read BBM Look Up Table (A5h)
The internal Look Up Table (LUT) consists of 20 Logical-Physical memory block links (from LBA0/PBA0 to
LBA19/PBA19). The “Read BBM Look Up Table” command can be used to check the existing address
links stored inside the LUT.
The “Read BBM Look Up Table” command is initiated by shifting the instruction code “A5h” into the DI pin
and followed by 8-bit dummy clocks, at the falling edge of the 16th clocks, the device will start to output the
16-bit “Logical Block Address” and the 16-bit “Physical Block Address” as illustrated in Figure 12. All block
address links will be output sequentially starting from the first link (LBA0 & PBA0) in the LUT. If there are
available links that are unused, the output will contain all “00h” data.
The MSB bits LBA[15:14] of each link are used to indicate the status of the link.
LBA[15]
(Enable)
LBA[14]
(Invalid)
Descriptions
0
0
This link is available to use.
1
0
This link is enabled and it is a valid link.
1
1
This link was enabled, but it is not valid any more.
0
1
Not applicable.
7
High Impedance
8 15 23
8 Dummy
Clocks
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0
Instruction
A5h
31
LBA0
*= MSB
** *
[15:8] [7:0] [15:8] [7:0] [15:8]
PBA0
2416 32 39 40 47 48
Figure 12. Read BBM Look Up Table Instruction
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 32 - Preliminary – Revision C
8.2.9 Last ECC Failure Page Address (A9h)
To better manage the data integrity, W25N01GW implements internal ECC correction for the entire
memory array. When the ECC-E bit in the Status/Configuration Register is set to 1 (also power up
default), the internal ECC algorithm is enabled for all Program and Read operations. During a “Program
Execute” command for a specific page, the ECC algorithm will calculate the ECC information based on the
data inside the 2K-Byte data buffer and write the ECC data into the extra 64-Byte ECC area in the same
physical memory page.
During the Read operations, ECC information will be used to verify the data read out from the physical
memory array and possible corrections can be made to limited amount of data bits that contain errors. The
ECC Status Bits (ECC-1 & ECC-0) will also be set indicating the result of ECC calculation.
For the “Continuous Read Mode (BUF=0)” operation, multiple pages of main array data can be read out
continuously by issuing a single read command. Upon finishing the read operation, the ECC status bits
should be check to verify if there’s any ECC correction or un-correctable errors existed in the read out
data. If ECC-1 & ECC-0 equal to (1, 0) or (1, 1), the previous read out data contain one or more pages
that contain ECC un-correctable errors. The failure page address (or the last page address if it’s multiple
pages) can be obtained by issuing the “Last ECC failure Page Address” command as illustrated in Figure
13. The 16-bit Page Address that contains un-correctable ECC errors will be presented on the DO pin
following the instruction code “A9h” and 8-bit dummy clocks on the DI pin.
7
High Impedance
8 9 15 16 17 29 30 31
15 14 13 2 1 0
8 Dummy
Clocks
Page Address[15:0]
Mode 0
Mode 3
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0
Instruction
A9h
Figure 13. Last ECC Failure Page Address Instruction
W25N01GWxxIG/IT
- 33 -
8.2.10 128KB Block Erase (D8h)
The 128KB Block Erase instruction sets all memory within a specified block (64-Pages, 128K-Bytes) to the
erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the
Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the
/CS pin low and shifting the instruction code “D8h” followed by 8-bit dummy clocks and the 16-bit page
address. The Block Erase instruction sequence is shown in Figure 14.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Block Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be
executed if the addressed block is protected by the Block Protect (TB, BP2, BP1, and BP0) bits.
7
High Impedance
8 9 15 16 17 29 30 31
15 14 13 2 1 0
8 Dummy
Clocks Page Address[15:0]
Mode 0
Mode 3
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0
Instruction
D8h
Figure 14. 128KB Block Erase Instruction
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 34 - Preliminary – Revision C
8.2.11 Load Program Data (02h) / Random Load Program Data (84h)
The Program operation allows from one byte to 2,112 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Program operation involves two steps: 1. Load the program
data into the Data Buffer. 2. Issue “Program Execute” command to transfer the data from Data Buffer to
the specified memory page.
A Write Enable instruction must be executed before the device will accept the Load Program Data
Instructions (Status Register bit WEL= 1). The “Load Program Data” or “Random Load Program Data”
instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” or “84h” followed by
a 16-bit column address (only CA[11:0] is effective) and at least one byte of data into the DI pin. The /CS
pin must be held low for the entire length of the instruction while data is being sent to the device. If the
number of data bytes sent to the device exceeds the number of data bytes in the Data Buffer, the extra
data will be ignored by the device. The Load Program Data instruction sequence is shown in Figure 15.
The “Load Program Data” instruction has to be issued prior to “Random Load Program Data” instruction
for random page program. The difference is that “Load Program Data” instruction will reset the unused the
data bytes in the Data Buffer to FFh value, while “Random Load Program Data” instruction adding will only
update the data bytes that are specified by the command input sequence, the rest of the Data Buffer will
remain unchanged.
If internal ECC algorithm is enabled, all 2,112 bytes of data will be accepted, but the bytes designated for
ECC parity bits in the extra 64 bytes section will be overwritten by the ECC calculation. If the ECC-E bit is
set to a 0 to disable the internal ECC, the extra 64 bytes section can be used for external ECC purpose or
other usage.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 21 22 23
15 14 13
02h / 84h 210
Column Address[15:0]
24
1 07 6 1 07 6 7
Data-0 Data-1
30 31 32 38 3924
/CS
CLK
DI
(IO0)
DO
(IO1)
7
0 1 07 6
40
High Impedance
Mode 0
Mode 3
Data-2111
Figure 15. Load / Random Load Program Data Instruction
W25N01GWxxIG/IT
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8.2.12 Quad Load Program Data (32h) / Quad Random Load Program Data (34h)
The “Quad Load Program Data” and “Quad Random Load Program Data” instructions are identical to the
“Load Program Data” and “Random Load Program Data” in terms of operation sequence and functionality.
The only difference is that “Quad Load” instructions will input the data bytes from all four IO pins instead of
the single DI pin. This method will significantly shorten the data input time when a large amount of data
needs to be loaded into the Data Buffer. The instruction sequence is illustrated in Figure 16.
The “Quad Load Program Data” instruction has to be issued prior to “Quad Random Load Program Data”
instruction for random page program. The difference is that “Quad Load Program Data” instruction will
reset the unused the data bytes in the Data Buffer to FFh value, while “Quad Random Load Program
Data” instruction adding will only update the data bytes that are specified by the command input sequence,
the rest of the Data Buffer will remain unchanged.
When WP-E bit in the Status Register is set to a 1, all Quad SPI instructions are disabled.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 23 24 25
15
32h / 34h 0
Data
0
26 27
4 0
5 1
IO2High Impedance 6 2
IO3High Impedance 7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
Data
1Data
2111
Column
Addr[15:0]
Mode 0
Mode 3
Figure 16. Quad Load / Quad Random Load Program Data Instruction
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 36 - Preliminary – Revision C
8.2.13 Program Execute (10h)
The Program Execute instruction is the second step of the Program operation. After the program data are
loaded into the 2,112-Byte Data Buffer (or 2,048 bytes when ECC is enabled), the Program Execute
instruction will program the Data Buffer content into the physical memory page that is specified in the
instruction. The instruction is initiated by driving the /CS pin low then shifting the instruction code “10h”
followed by 8-bit dummy clocks and the 16-bit Page Address into the DI pin as shown in Figure 17.
After /CS is driven high to complete the instruction cycle, the self-timed Program Execute instruction will
commence for a time duration of tpp (See AC Characteristics). While the Program Execute cycle is in
progress, the Read Status Register instruction may still be used for checking the status of the BUSY bit.
The BUSY bit is a 1 during the Program Execute cycle and becomes a 0 when the cycle is finished and
the device is ready to accept other instructions again. After the Program Execute cycle has finished, the
Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Program Execute instruction will
not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1, and BP0) bits.
7
High Impedance
8 9 15 16 17 29 30 31
15 14 13 2 1 0
8 Dummy
Clocks Page Address[15:0]
Mode 0
Mode 3
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0
Instruction
10h
Figure 17. Program Execute Instruction
W25N01GWxxIG/IT
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8.2.14 Page Data Read (13h)
The Page Data Read instruction will transfer the data of the specified memory page into the 2,112-Byte
Data Buffer. The instruction is initiated by driving the /CS pin low then shifting the instruction code “13h”
followed by 8-bit dummy clocks and the 16-bit Page Address into the DI pin as shown in Figure 18.
After /CS is driven high to complete the instruction cycle, the self-timed Read Page Data instruction will
commence for a time duration of tRD (See AC Characteristics). While the Read Page Data cycle is in
progress, the Read Status Register instruction may still be used for checking the status of the BUSY bit.
The BUSY bit is a 1 during the Read Page Data cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again.
After the 2,112 bytes of page data are loaded into the Data Buffer, several Read instructions can be
issued to access the Data Buffer and read out the data. Depending on the BUF bit setting in the Status
Register, either “Buffer Read Mode” or “Continuous Read Mode” may be used to accomplish the read
operations.
7
High Impedance
8 9 15 16 17 29 30 31
15 14 13 2 1 0
8 Dummy
Clocks Page Address[15:0]
Mode 0
Mode 3
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0
Instruction
13h
Figure 18. Page Data Read Instruction
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 38 - Preliminary – Revision C
8.2.15 Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the Data Buffer
after executing the Read Page Data instruction. The Read Data instruction is initiated by driving the /CS
pin low and then shifting the instruction code “03h” followed by the 16-bit Column Address and 8-bit
dummy clocks or a 24-bit dummy clocks into the DI pin. After the address is received, the data byte of the
addressed Data Buffer location will be shifted out on the DO pin at the falling edge of CLK with most
significant bit (MSB) first. The address is automatically incremented to the next higher address after each
byte of data is shifted out allowing for a continuous stream of data. The instruction is completed by driving
/CS high.
The Read Data instruction sequence is shown in Figure 19a & 19b. When BUF=1, the device is in the
Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by the 16-
bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output, the
output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 21 22 23
15 14 13
1 0
03h 210
Column Address[15:0] 8 Dummy
Clocks
7 6 1 07 6 7
Data Out 1 Data Out 2
* *
38 39 40 46 4731 32
Figure 19a. Read Data Instruction (Buffer Read Mode, BUF=1)
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 29 30
23 22 21
1 0
03h 210
24 Dummy Clocks
7 6 1 07 6 7
Data Out 1 Data Out 2
* *
38 39 40 46 4731 32
Figure 19b. Read Data Instruction (Continuous Read Mode, BUF=0)
W25N01GWxxIG/IT
- 39 -
8.2.16 Fast Read (0Bh)
The Fast Read instruction allows one or more data bytes to be sequentially read from the Data Buffer after
executing the Read Page Data instruction. The Fast Read instruction is initiated by driving the /CS pin low
and then shifting the instruction code “0Bh” followed by the 16-bit Column Address and 8-bit dummy
clocks or a 32-bit dummy clocks into the DI pin. After the address is received, the data byte of the
addressed Data Buffer location will be shifted out on the DO pin at the falling edge of CLK with most
significant bit (MSB) first. The address is automatically incremented to the next higher address after each
byte of data is shifted out allowing for a continuous stream of data. The instruction is completed by driving
/CS high.
The Fast Read instruction sequence is shown in Figure 20a & 20b. When BUF=1, the device is in the
Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by the 16-
bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output, the
output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 21 22 23
15 14 13
1 0
0Bh 210
Column Address[15:0] 8 Dummy
Clocks
7 6 1 07 6 7
Data Out 1 Data Out 2
* *
38 39 40 46 4731 32
Figure 20a. Fast Read Instruction (Buffer Read Mode, BUF=1)
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 21 22 23
31 30 29
1 0
0Bh 18 17 16
32 Dummy Clocks
7 6 1 07 6 7
Data Out 1 Data Out 2
* *
46 47 48 54 5539 40
0
Figure 20b. Fast Read Instruction (Continuous Read Mode, BUF=0)
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 40 - Preliminary – Revision C
8.2.17 Fast Read with 4-Byte Address (0Ch)
The Fast Read instruction allows one or more data bytes to be sequentially read from the Data Buffer after
executing the Read Page Data instruction. The Fast Read instruction is initiated by driving the /CS pin low
and then shifting the instruction code “0Ch” followed by the 16-bit Column Address and 24-bit dummy
clocks (when BUF=1) or a 40-bit dummy clocks (when BUF=0) into the DI pin. After the address is
received, the data byte of the addressed Data Buffer location will be shifted out on the DO pin at the falling
edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next
higher address after each byte of data is shifted out allowing for a continuous stream of data. The
instruction is completed by driving /CS high.
The Fast Read instruction sequence is shown in Figure 21a & 21b. When BUF=1, the device is in the
Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by the 16-
bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output, the
output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 21 22 23
15 14 13
1 0
0Ch 210
Column Address[15:0] 24 Dummy
Clocks
7 6 1 07 6 7
Data Out 1 Data Out 2
* *
54 55 56 62 6347 48
Figure 21a. Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 21 22 23
39 38 37
1 0
0Ch 26 25 24
40 Dummy Clocks
7 6 1 07 6 7
Data Out 1 Data Out 2
* *
54 55 56 62 6347 48
0
Figure 21b. Fast Read with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
W25N01GWxxIG/IT
- 41 -
8.2.18 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard
SPI devices.
The Fast Read Dual Output instruction sequence is shown in Figure 22a & 22b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 21 22 23
15 14 13
3Bh 210
Column Address[15:0] 8 Dummy
Clocks
7
Data Out 1
*
31 32
6420
3433
7531
Data Out 2
6420
7531
6
35 36 3837 39 40
*
Figure 22a. Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1)
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 21 22 23
31 30 29
3Bh 18 17 16
7
Data Out 1
*
39 40
6420
4241
7531
Data Out 2
6420
7531
6
43 44 4645 47 48
32 Dummy Clocks
0
*
Figure 22b. Fast Read Dual Output Instruction (Continuous Read Mode, BUF=0)
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 42 - Preliminary – Revision C
8.2.19 Fast Read Dual Output with 4-Byte Address (3Ch)
The Fast Read Dual Output (3Ch) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard
SPI devices.
The Fast Read Dual Output instruction sequence is shown in Figure 23a & 23b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 21 22 23
15 14 13
3Ch 210
Column Address[15:0] 24 Dummy
Clocks
7
Data Out 1
*
47 48
6420
5049
7531
Data Out 2
6420
7531
6
51 52 5453 55 56
*
Figure 23a. Fast Read Dual Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 29 30 31
39 38 37
3Ch 18 17 16
7
Data Out 1
*
47 48
6420
5049
7531
Data Out 2
6420
7531
6
51 52 5453 55 56
40 Dummy Clocks
0
*
Figure 23b. Fast Read Dual Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
W25N01GWxxIG/IT
- 43 -
8.2.20 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. The Fast Read Quad Output Instruction
allows data to be transferred at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction sequence is shown in Figure 24a & 24b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
*
= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 21 22 23
15 14 13
6Bh 210
Column Address[15:0] 8 Dummy
Clocks
5
Data
Out 1
31 32
4 0
3433
5 1
4
35 36 3837 39 40
IO2High Impedance 66 2
IO3High Impedance 77 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
*Data
Out 2 *Data
Out 3 *Data
Out 4 *Data
Out 5
Figure 24a. Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1)
*
= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 21 22 23
31 30 29
6Bh 18 17 16
5
Data
Out 1
4 0
5 1
4
48
IO2High Impedance 66 2
IO3High Impedance 77 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
*Data
Out 2 *Data
Out 3 *Data
Out 4 *Data
Out 5
32 Dummy Clocks
0
39 40 4241 43 44 4645 47
Figure 24b. Fast Read Quad Output Instruction (Continuous Read Mode, BUF=0)
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 44 - Preliminary – Revision C
8.2.21 Fast Read Quad Output with 4-Byte Address (6Ch)
The Fast Read Quad Output (6Ch) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. The Fast Read Quad Output Instruction
allows data to be transferred at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction sequence is shown in Figure 25a & 25b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
*
= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 21 22 23
15 14 13
6Ch 210
Column Address[15:0] 24 Dummy
Clocks
5
Data
Out 1
47 48
4 0
5049
5 1
4
51 52 5453 55 56
IO2High Impedance 66 2
IO3High Impedance 77 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
*Data
Out 2 *Data
Out 3 *Data
Out 4 *Data
Out 5
Figure 25a. Fast Read Quad Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
*
= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 29 30 31
39 38 37
6Ch 18 17 16
5
Data
Out 1
4 0
5 1
4
56
IO2High Impedance 66 2
IO3High Impedance 77 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
*Data
Out 2 *Data
Out 3 *Data
Out 4 *Data
Out 5
40 Dummy Clocks
0
47 48 5049 51 52 5453 55
Figure 25b. Fast Read Quad Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
W25N01GWxxIG/IT
- 45 -
8.2.22 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Column Address or the dummy clocks two bits per clock. This reduced instruction overhead may allow
for code execution (XIP) directly from the Dual SPI in some applications.
The Fast Read Quad Output instruction sequence is shown in Figure 26a & 26b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 13 14 15
14 12 10
BBh 420
Column Address[15:0] 4 Dummy
Clocks
7
Data Out 1
*
19 20
6420
2221
7531
Data Out 2
6420
7531
6
23 24 2625 27 28
*
15 13 11 5 3 1
Figure 26a. Fast Read Dual I/O Instruction (Buffer Read Mode, BUF=1)
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 15 16 17
30 28 26
BBh 16 14 12
7
Data Out 1
*
23 24
6420
2625
7531
Data Out 2
6420
7531
6
27 28 3029 31 32
16 Dummy Clocks
0
*
31 29 27 17 15 13 1
Figure 26b. Fast Read Dual I/O Instruction (Continuous Read Mode, BUF=0)
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 46 - Preliminary – Revision C
8.2.23 Fast Read Dual I/O with 4-Byte Address (BCh)
The Fast Read Dual I/O (BCh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Column Address or the dummy clocks two bits per clock. This reduced instruction overhead may allow
for code execution (XIP) directly from the Dual SPI in some applications.
The Fast Read Quad Output instruction sequence is shown in Figure 27a & 27b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 13 14 15
14 12 10
BCh 420
Column Address[15:0] 12 Dummy
Clocks
7
Data Out 1
*
27 28
6420
3029
7531
Data Out 2
6420
7531
6
31 32 3433 35 36
*
15 13 11 5 3 1
Figure 27a. Fast Read Dual I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
*= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 19 20 21
38 36 34
BCh 16 14 12
7
Data Out 1
*
27 28
6420
3029
7531
Data Out 2
6420
7531
6
31 32 3433 35 36
20 Dummy Clocks
0
*
39 37 35 17 15 13 1
Figure 27b. Fast Read Dual I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
W25N01GWxxIG/IT
- 47 -
8.2.24 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 prior to the data
output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code
execution (XIP) directly from the Quad SPI.
The Fast Read Quad Output instruction sequence is shown in Figure 28a & 28b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
Figure 28a. Fast Read Quad I/O Instruction (Buffer Read Mode, BUF=1)
*
= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9
EBh
Column
Address[15:0]
5
Data
Out 1
13 14 1615
4
17 18 2019 21 22
IO2High Impedance 6
IO3High Impedance 7
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
*Data
Out 2 *Data
Out 3 *Data
Out 4
12 8
13 9
14 10
15 11
4 0
5 1
6 2
7 3
X X
X X
X X
X X
10 11 12
4 Dummy
Clocks
X X
X X
X X
X X
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 48 - Preliminary – Revision C
Figure 28b. Fast Read Quad I/O Instruction (Continuous Read Mode, BUF=0)
*
= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 13 14 15
44 40 36
EBh 24 20 16
5
Data
Out 1
4 0
5 1
4
28
IO2High Impedance 66 2
IO3High Impedance 77 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
*Data
Out 2 *Data
Out 3 *Data
Out 4 *Data
Out 5
12 Dummy Clocks
0
19 20 2221 23 24 2625 27
45 41 37 25 21 17 1
46 42 38 26 22 18 2
47 43 39 27 23 19 3
W25N01GWxxIG/IT
- 49 -
8.2.25 Fast Read Quad I/O with 4-Byte Address (ECh)
The Fast Read Quad I/O (ECh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 prior to the data
output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code
execution (XIP) directly from the Quad SPI.
The Fast Read Quad Output instruction sequence is shown in Figure 29a & 29b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
Figure 29a. Fast Read Quad I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
*
= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9
ECh
Column
Address[15:0]
5
Data
Out 1
2221
4
23 24 2525 27 28
IO2High Impedance 6
IO3High Impedance 7
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
*Data
Out 2 *Data
Out 3 *Data
Out 4
12 8
13 9
14 10
15 11
4 0
5 1
6 2
7 3
X
X
X
X
10 11 12
10 Dummy
Clocks
X
X
X
X
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 50 - Preliminary – Revision C
Figure 29b. Fast Read Quad I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
*
= MSB
*
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 7
Instruction
High Impedance
8 9 15 16 17
52 48 44
ECh 24 20 16
5
Data
Out 1
4 0
5 1
4
30
IO2High Impedance 66 2
IO3High Impedance 77 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
*Data
Out 2 *Data
Out 3 *Data
Out 4 *Data
Out 5
14 Dummy Clocks
0
21 22 2423 25 26 2827 29
53 49 45 25 21 17 1
54 50 46 26 22 18 2
55 51 47 27 23 19 3
W25N01GWxxIG/IT
- 51 -
8.2.26 Accessing Unique ID / Parameter / OTP Pages (OTP-E=1)
In addition to the main memory array, the W25N01GW is also equipped with one Unique ID Page, one
Parameter Page, and ten OTP Pages.
Page Address
Page Name
Descriptions
Data Length
00h
Unique ID Page
Factory programmed, Read Only
32-Byte x 16
01h
Parameter Page
Factory programmed, Read Only
256-Byte x 3
02h
OTP Page [0]
Program Only, OTP lockable
2,112-Byte
…
OTP Pages [1:8]
Program Only, OTP lockable
2,112-Byte
0Bh
OTP Page [9]
Program Only, OTP lockable
2,112-Byte
To access these additional data pages, the OTP-E bit in Status Register-2 must be set to “1” first. Then,
Read operations can be performed on Unique ID and Parameter Pages, Read and Program operations
can be performed on the OTP pages if it’s not already locked. To return to the main memory array
operation, OTP-E bit needs to be to set to 0.
Read Operations
A “Page Data Read” command must be issued followed by a specific page address shown in the table
above to load the page data into the main Data Buffer. After the device finishes the data loading
(BUSY=0), all Read commands may be used to read the Data Buffer starting from any specified Column
Address. Please note all Read commands must now follow the “Buffer Read Mode” command structure
(CA[15:0], number of dummy clocks) regardless the previous BUF bit setting. ECC can also be enabled
for the OTP page read operations to ensure the data integrity.
Program and OTP Lock Operations
OTP pages provide the additional space (2K-Byte x 10) to store important data or security information that
can be locked to prevent further modification in the field. These OTP pages are in an erased state set in
the factory, and can only be programmed (change data from “1” to “0”) until being locked by OTP-L bit in
the Configuration/Status Register-2. OTP-E must be first set to “1” to enable the access to these OTP
pages, then the program data must be loaded into the main Data Buffer using any “Program Data Load”
commands. The “Program Execute” command followed by a specific OTP Page Address is used to initiate
the data transfer from the Data Buffer to the OTP page. When ECC is enabled, ECC calculation will be
performed during “Program Execute”, and the ECC information will be stored into the 64-Byte spare area.
Once the OTP pages are correctly programmed, OTP-L bit can be used to permanently lock these pages
so that no further modification is possible. While still in the “OTP Access Mode” (OTP-E=1), user needs to
set OTP-L bit in the Configuration/Status Register-2 to “1”, and issue a “Program Execute” command
without any Page Address. After the device finishes the OTP lock setting (BUSY=0), the user can set
OTP-E to “0” to return to the main memory array operation.
SR1-L OTP Lock Operation
The Protection/Status Register-1 contains protection bits that can be set to protect either a portion or the
entire memory array from being Programmed/Erased or set the device to either Software Write Protection
(WP-E=0) or Hardware Write Protection (WP-E=1). Once the BP[3:0], TB, WP-E bits are set correctly,
SRP1 and SRP0 should also be set to “1”s as well to allow SR1-L bit being set to “1” to permanently lock
the protection settings in the Status Register-1 (SR1). Similar to the OTP-L setting procedure above, in
order to set SR1-L lock bit, the device must enter the “OTP Access Mode” (OTP-E=1) first, and SR1-L bit
should be set to “1” prior to the “Program Execute” command without any Page Address. Once SR1-L is
set to “1” (BUSY=0), the user can set OTP-E to “0” to return to the main memory array operation.
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 52 - Preliminary – Revision C
8.2.27 Parameter Page Data Definitions
The Parameter Page contains 3 identical copies of the 256-Byte Parameter Data. The table below lists all
the key data byte locations. All other unspecified byte locations have 00h data as default.
Byte
Number
Descriptions
Values
0~3
Parameter page signature
4Fh, 4Eh, 46h, 49h
4~5
Revision number
00h, 00h
6~7
Feature supported
00h, 00h
8~9
Optional command supported
02h, 00h
10~31
Reserved
All 00h
32~43
Device manufacturer
57h, 49h, 4Eh, 42h, 4Fh, 4Eh, 44h, 20h, 20h, 20h, 20h, 20h
44~63
Device model
57h, 32h, 35h, 4Eh, 30h, 31h, 47h, 57h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h
64
JEDEC manufacturer ID
EFh
65~66
Date code
00h, 00h
67~79
Reserved
All 00h
80~83
Number of data bytes per page
00h, 08h, 00h, 00h
84~85
Number of spare bytes per page
40h, 00h
86~91
Reserved
All 00h
92~95
Number of pages per block
40h, 00h, 00h, 00h
96~99
Number of blocks per logical unit
00h, 04h, 00h, 00h
100
Number of logical units
01h
101
Number of address bytes
00h
102
Number of bits per cell
01h
103~104
Bad blocks maximum per unit
14h, 00h
105~106
Block endurance
01h, 05h
107
Guaranteed valid blocks at beginning of target
01h
108~109
Block endurance for guaranteed valid blocks
00h, 00h
110
Number of programs per page
04h
111
Reserved
00h
112
Number of ECC bits
00h
113
Number of plane address bits
00h
114
Multi-plane operation attributes
00h
115~127
Reserved
All 00h
128
I/O pin capacitance, maximum
08h
129~132
Reserved
All 00h
133~134
Maximum page program time (us)
BCh, 02h
135~136
Maximum block erase time (us)
10h, 27h
137~138
Maximum page read time (us)
32h, 00h
139~163
Reserved
All 00h
164~165
Vendor specific revision number
00h, 00h
166~253
Vendor specific
All 00h
254~255
Integrity CRC
Set at test
256~511
Value of bytes 0~255
512~767
Value of bytes 0~255
768+
Reserved
W25N01GWxxIG/IT
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9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings (1)
PARAMETERS
SYMBOL
CONDITIONS
RANGE
UNIT
Supply Voltage
VCC
–0.6 to +2.5
V
Voltage Applied to Any Pin
VIO
Relative to Ground
–0.6 to VCC+0.4
V
Transient Voltage on any Pin
VIOT
<20nS Transient
Relative to Ground
–2.0 to VCC+2.0
V
Storage Temperature
TSTG
–65 to +150
°C
Lead Temperature
TLEAD
See Note (2)
°C
Electrostatic Discharge Voltage
VESD
Human Body Model(3)
–2000 to +2000
V
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside
of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability.
Exposure beyond absolute maximum ratings may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the
European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Standard JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).
9.2 Operating Ranges
PARAMETER
SYMBOL
CONDITIONS
SPEC
UNIT
MIN
MAX
Supply Voltage
VCC
1.70
1.95
V
Ambient Temperature,
Operating
TA
Industrial
–40
+85
°C
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 54 - Preliminary – Revision C
9.3 Power-up Power-down Timing Requirements
PARAMETER
SYMBOL
SPEC
UNIT
MIN
MAX
VCC (min) to /CS Low
tVSL(1)
50
500
µs
Time Delay Before Write Instruction
tPUW(1)
5
ms
Write Inhibit Threshold Voltage
VWI(1)
1.0
1.4
V
Note:
1. These parameters are characterized only.
Figure 30a. Power-up Timing and Voltage Levels
VCC
Time
/CS must track VCC
during VCC Ramp Up/Down
/CS
Figure 30b. Power-up, Power-Down Requirement
W25N01GWxxIG/IT
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9.4 DC Electrical Characteristics
PARAMETER
SYMBOL
CONDITIONS
SPEC
UNIT
MIN
TYP
MAX
Input Capacitance
CIN(1)
VIN = 0V(1)
6
pF
Output Capacitance
Cout(1)
VOUT = 0V(1)
8
pF
Input Leakage
ILI
±2
µA
I/O Leakage
ILO
±2
µA
Standby Current
ICC1
/CS = VCC,
VIN = GND or VCC
10
50
µA
Read Current
ICC2
C = 0.1 VCC / 0.9 VCC
DO = Open
25
35
mA
Current Page Program
ICC3
/CS = VCC
25
35
mA
Current Block Erase
ICC4
/CS = VCC
25
35
mA
Input Low Voltage
VIL
VCC x 0.3
V
Input High Voltage
VIH
VCC x 0.7
V
Output Low Voltage
VOL
IOL = 100 µA
0.2
V
Output High Voltage
VOH
IOH = –100 µA
VCC – 0.2
V
Notes:
1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 1.8V.
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 56 - Preliminary – Revision C
9.5 AC Measurement Conditions
PARAMETER
SYMBOL
SPEC
UNIT
MIN
MAX
Load Capacitance
CL
30
pF
Input Rise and Fall Times
TR, TF
5
ns
Input Pulse Voltages
VIN
VCC*0.1 to VCC*0.9
V
Input Timing Reference Voltages
IN
VCC*0.3 to VCC*0.7
V
Output Timing Reference Voltages
OUT
VCC*0.5
V
Input and Output
Timing Reference Levels
Input Levels
VCC*0.9
VCC*0.1
VCC*0.5
Figure 31. AC Measurement I/O Waveform
W25N01GWxxIG/IT
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9.6 AC Electrical Characteristics(3)
DESCRIPTION
SYMBOL
ALT
SPEC
UNIT
MIN
TYP
MAX
Clock frequency for all instructions except
Continuous Read Mode
FR
fC1
D.C.
104
MHz
Clock frequency for Continuous Read Mode
FR
fC1
D.C.
83
MHz
Clock High, Low Time
for all instructions
tCLH,
tCLL(1)
4
ns
Clock Rise Time peak to peak
tCLCH(2)
0.1
V/ns
Clock Fall Time peak to peak
tCHCL(2)
0.1
V/ns
/CS Active Setup Time relative to CLK
tSLCH
tCSS
6
ns
/CS Not Active Hold Time relative to CLK
tCHSL
5
ns
Data In Setup Time
tDVCH
tDSU
3
ns
Data In Hold Time
tCHDX
tDH
4
ns
/CS Active Hold Time relative to CLK
tCHSH
3
ns
/CS Not Active Setup Time relative to CLK
tSHCH
3
ns
/CS Deselect Time (for Array Read Array Read)
tSHSL1
tCSH
10
ns
/CS Deselect Time (for Erase, Program or Read
Status Registers Read Status Registers)
tSHSL2
tCSH
50
ns
Output Disable Time
tSHQZ(2)
tDIS
15
ns
Clock Low to Output Valid
tCLQV
tV
8
ns
Output Hold Time
tCLQX
tHO
2
ns
/HOLD Active Setup Time relative to CLK
tHLCH
5
ns
/HOLD Active Hold Time relative to CLK
tCHHH
5
ns
Continued – next page
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 58 - Preliminary – Revision C
AC Electrical Characteristics (cont’d)
DESCRIPTION
SYMBOL
ALT
SPEC
UNIT
MIN
TYP
MAX
/HOLD Not Active Setup Time relative to CLK
tHHCH
5
ns
/HOLD Not Active Hold Time relative to CLK
tCHHL
5
ns
/HOLD to Output Low-Z
tHHQX(2)
tLZ
7
ns
/HOLD to Output High-Z
tHLQZ(2)
tHZ
12
ns
Write Protect Setup Time Before /CS Low
tWHSL
20
ns
Write Protect Hold Time After /CS High
tSHWL
100
ns
Status Register Write Time
tW
50
ns
/CS High to next Instruction after Reset during
Page Data Read / Program Execute / Block Erase
tRST(2)
5/10/500
µs
Read Page Data Time (ECC disabled)
tRD1
25
µs
Read Page Data Time (ECC enabled)
tRD2
60
µs
Page Program, OTP Lock, BBM Management Time
tPP
250
700
us
Block Erase Time
tBE
2
10
ms
Number of partial page programs
NoP
4
times
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 1.8V.
W25N01GWxxIG/IT
- 59 -
9.7 Serial Output Timing
/CS
CLK
IO
output
tCLQX tCLQV
tCLQX tCLQV tSHQZtCLL
LSB OUT
tCLH
MSB OUT
9.8 Serial Input Timing
/CS
CLK
IO
input
tCHSL
MSB IN
tSLCH
tDVCH tCHDX
tSHCHtCHSH
tCLCH tCHCL
LSB IN
tSHSL
9.9 /HOLD Timing
/CS
CLK
IO
output
/HOLD
tCHHL tHLCH
tCHHH
tHHCH
tHLQZ tHHQX
IO
input
9.10 /WP Timing
/CS
CLK
/WP
tWHSL tSHWL
IO
input
Write Status Register is allowed Write Status Register is not allowed
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 60 - Preliminary – Revision C
10. PACKAGE SPECIFICATIONS
10.1 8-Pad WSON 8x6-mm (Package Code ZE)
Symbol
Millimeters
Inches
Min
Nom
Max
Min
Nom
Max
A
0.70
0.75
0.80
0.028
0.030
0.031
A1
0.00
0.02
0.05
0.000
0.001
0.002
b
0.35
0.40
0.48
0.014
0.016
0.019
C
---
0.20 REF
---
---
0.008 REF
---
D
7.90
8.00
8.10
0.311
0.315
0.319
D2
3.35
3.40
3.45
0.132
0.134
0.136
E
5.90
6.00
6.10
0.232
0.236
0.240
E2
4.25
4.30
4.35
0.167
0.169
0.171
e
---
1.27
---
---
0.050
---
L
0.45
0.50
0.55
0.018
0.020
0.022
y
0.00
---
0.050
0.000
---
0.002
W25N01GWxxIG/IT
- 61 -
10.2 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 Ball Array)
Symbol
Millimeters
Inches
Min
Nom
Max
Min
Nom
Max
A
---
---
1.20
---
---
0.047
A1
0.25
0.30
0.35
0.010
0.012
0.014
A2
---
0.85
---
---
0.033
---
b
0.35
0.40
0.45
0.014
0.016
0.018
D
7.90
8.00
8.10
0.311
0.315
0.319
D1
4.00 BSC
0.157 BSC
E
5.90
6.00
6.10
0.232
0.236
0.240
E1
4.00 BSC
0.157 BSC
SE
1.00 TYP
0.039 TYP
SD
1.00 TYP
0.039 TYP
e
1.00 BSC
0.039 BSC
Note:
Ball land: 0.45mm. Ball Opening: 0.35mm
PCB ball land suggested <= 0.35mm
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 62 - Preliminary – Revision C
10.3 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 Ball Array)
Symbol
Millimeters
Inches
Min
Nom
Max
Min
Nom
Max
A
---
---
1.20
---
---
0.047
A1
0.25
0.30
0.35
0.010
0.012
0.014
b
0.35
0.40
0.45
0.014
0.016
0.018
D
7.95
8.00
8.05
0.313
0.315
0.317
D1
5.00 BSC
0.197 BSC
E
5.95
6.00
6.05
0.234
0.236
0.238
E1
3.00 BSC
0.118 BSC
e
1.00 BSC
0.039 BSC
Note:
Ball land: 0.45mm. Ball Opening: 0.35mm
PCB ball land suggested <= 0.35mm
W25N01GWxxIG/IT
- 63 -
11. ORDERING INFORMATION
Notes:
1. The “W” prefix is not included on the part marking.
2. Standard bulk shipments are in tray for WSON and TFBGA packages. For other packing options, please
specify when placing orders.
W(1) 25N 01G W xx I(1)
W = Winbond
25N = Serial SLC NAND Memory
01G = 1G-bit
W = 1.70V to 1.95V
ZE = 8-pad WSON 8x6mm
TB = 24-ball TFBGA 8x6-mm (5x5 ball array) TC = 24-ball TFBGA 8x6-mm (6x4 ball array)
I = Industrial (-40°C to +85°C)
(2)
G = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3)
and BUF=1 is the default value after power up
T = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3)
and BUF=0 is the default value after power up
W25N01GWxxIG/IT
Publication Release Date: March 07, 2017
- 64 - Preliminary – Revision C
11.1 Valid Part Numbers and Top Side Marking
The following table provides the valid part numbers for the W25N01GW SpiFlash Memory. Please contact
Winbond for specific availability by density and package type. Winbond SpiFlash memories use a 12-digit
Product Number for ordering. However, due to limited space, the Top Side Marking on all packages uses
an abbreviated 11-digit number.
Industrial Temperature:
PACKAGE TYPE
DENSITY
PRODUCT NUMBER
TOP SIDE MARKING
ZE
WSON-8 8x6mm
1G-bit
W25N01GWZEIG
W25N01GWZEIT
25N01GWZEIG
25N01GWZEIT
TB
TFBGA-24 8x6mm
(5x5-1 Ball Array)
1G-bit
W25N01GWTBIG
W25N01GWTBIT
25N01GWTBIG
25N01GWTBIT
TC
TFBGA-24 8x6mm
(6x4 Ball Array)
1G-bit
W25N01GWTCIG
W25N01GWTCIT
25N01GWTCIG
25N01GWTCIT
Note:
W25N01GWxxIG: BUF=1 (Buffer Read Mode) is the default value after power up. BUF bit can be written to 0.
W25N01GWxxIT: BUF=0 (Continuous Read Mode) is the default value after power up. BUF bit can be written to 1.
W25N01GWxxIG/IT
- 65 -
12. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A
10/17/2015
New Create Preliminary
B
08/24/2016
57
57
6, 57
6, 53, 63
34, 35
52
Updated tCLQV in AC parameter table
Updated tSHQZ in AC parameter table
Updated FR in AC parameter table
Updated Supply Voltage
Updated (Quad) Random Load Program Data description
Corrected a typo
C
03/07/2017
55
25
54
Corrected VOL/VOH in DC parameter table
Corrected description and table of Device Reset(FFh)
Modified Power-up Timing Figure.
Preliminary Designation
The “Preliminary” designation on a Winbond datasheet indicates that the product is not fully characterized.
The specifications are subject to change and are not guaranteed. Winbond or an authorized sales
representative should be consulted for current information before using this product.
Trademarks
Winbond and SpiFlash are trademarks of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems
or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for
other applications intended to support or sustain life. Furthermore, Winbond products are not intended for
applications wherein failure of Winbond products could result or lead to a situation wherein personal injury,
death or severe property or environmental damage could occur. Winbond customers using or selling these
products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
Information in this document is provided solely in connection with Winbond products. Winbond
reserves the right to make changes, corrections, modifications or improvements to this document
and the products and services described herein at any time, without notice.