TSP5071N - STMicroelectronics

TS5070

TS5071

PROGRAMMABLE CODEC/FILTER

COMBO 2ND GENERATION

COMPLETE CODEC AND FILTER SYSTEM

INCLUDING :

– TRANSMIT AND RECEIVE PCM CHANNEL

FILTERS

–µ-LAW OR A-LAW COMPANDING CODER

AND DECODER

– RECEIVE POWER AMPLIFIER DRIVES

300 Ω

– 4.096 MHz SERIAL PCM DATA (max)

PROGRAMMABLE FUNCTIONS :

– TRANSMIT GAIN : 25.4 dB RANGE, 0.1 dB

STEPS

– RECEIVE GAIN : 25.4 dB RANGE, 0.1 dB

STEPS

– HYBRID BALANCE CANCELLATION FIL-

TER

– TIME-SLOT ASSIGNMENT: UP TO 64

SLOTS/FRAME

– 2 PORTASSIGNMENT(TS5070)

– 6 INTERFACELATCHES(TS5070)

–AOR

-LAW

– ANALOG LOOPBACK

– DIGITAL LOOPBACK

DIRECT INTERFACE TO SOLID-STATE

SLICs

SIMPLIFIES TRANSFORMER SLIC, SINGLE

WINDINGSECONDARY

STANDARDSERIAL CONTROL INTERFACE

80 mW OPERATINGPOWER (typ)

1.5mWSTANDBY POWER (typ)

MEETS OR EXCEEDS ALL CCITT AND

LSSGRSPECIFICATIONS

TTL AND CMOS COMPATIBLE DIGITAL IN-

TERFACES

DESCRIPTION

TheTS5070seriesarethesecondgenerationcom-

bined PCM CODEC and Filter devices optimized

for digital switching applicationson subscriberand

trunkline cards.

Usingadvancedswitchedcapacitortechniquesthe

TS5070 and TS5071 combine transmit bandpass

and receive lowpass channel filters with a com-

panding PCM encoder and decoder. The devices

are A-lawand µ-law selectableand employ a con-

ventional serial PCM interface capable of being

clockedupto 4.096MHz.Anumberofprogramma-

ble functionsmay be controlled via a serial control

port.

Channel gains are programmable over a 25.4 dB

range in each direction, and a programmablefilter

is included to enable Hybrid Balancing to be ad-

justedto suit a widerange of loop impedancecon-

ditions.

Both transformerand activeSLIC interfacecircuits

with real or complex terminationimpedances can

be balanced by this filter, with cancellation in ex-

cessof 30dBbeingreadilyachievablewhenmeas-

uredacrossthepassbandagainststandardtestter-

mination networks.

ToenableCOMBOIIGtointerfacetotheSLICcon-

trol leads, a number of programmablelatches are

included ; each may be configuredas eitheran in-

put or an output. The TS5070 provides 6 latches

and the TS50715 latches.

December 1997

DIP20 (Plastic)

ORDERING NUMBER:TS5071N

PLCC28

ORDERING NUMBERS: TS5070FN

TS5070FNTR

1/32

TS5070 PIN FUNCTIONALITY (PLCC28)

No. Name Function

1 GND Ground Input(+0V)

2VF

0 Analog Output

SS Supply Input(-5V)

4 NC Not Connected

5 NC Not Connected

6 IL3 Digital Input or Outputdefined by LDR register content

7 IL2 Digital Input or Outputdefined by LDR register content

8FS

RDigital input

1 Digital input sampled by BCLK falling edge

10 DR0 Digital input sampled by BCLK falling edge

11 CO Digital output (shiftedout on CCLK rising edge)

12 CI Digital input (sampled on CCLK falling edge)

13 CCLK Digital input (clock)

14 CS Digital input (chip select forCI/CO)

15 MR Digital Input

16 BCLK Digital input (clock)

17 MCLK Digital input

18 DX0 Digital output clockedby BCLK rising edge

19 DX1 Digital output clockedby BCLK rising edge

20 TSX0 Open drain output (pulled low by active DX0 time slot)

21 TSX1 Open drain output (pulled low by active DX1 time slot)

22 FSXDigital input

23 IL5 Digital input or output defined by LDR registercontent

24 IL4 Digital input or output defined by LDR registercontent

25 IL1 Digital input or output defined by LDR registercontent

26 IL0 Digital input or output defined by LDR registercontent

27 VCC Supply input (+5V)

28 VFXI Analog input

HYBRID

BALANCE

FILTER

ENCODER

TX GAIN TX

TX TIME SLOT

Vref

HYBAL 1

HYBAL 2

HYBAL 3

TIME-SLOT

ASSIGNMENT

CTL REG.

RX TIME SLOT

RX GAIN

DECODER

TS5070/71

INTERFACE

LATCHES LATCH DIR

LATCH CONT.

CONTROL

INTERFACE

DX0

DX1

TSX0

TSX1

FSX

BCLK

FSR

DR0

DR1

MCLK

CCLK

VSS=-5VVCC=+5V

VFXI

VFRO

GND

IL5

IL4

IL3

IL2

IL1

IL0

D94TL135

TS5070FUNCTIONAL DIAGRAM

TS5070 - TS5071

2/32

BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC VCC to GND 7 V

VSS VSS to GND – 7 V

Voltage at VFXI VCC + 0.5 to VSS – 0.5 V

VIN Voltage at Any DigitalInput VCC + 0.5 to GND – 0.5 V

Current at VFRO ±100 mA

IOCurrent at Any DigitalOutput ±50 mA

Tstg Storage Temperature Range – 65, +150 °C

Tlead Lead Temperature Range (soldering, 10 seconds) 300 °C

TS5070 - TS5071

3/32

PIN CONNECTIONS

POWERSUPPLY, CLOCK

Name Pin

Type TS5070

FN TS5071

NFunction Description

VCC

VSS

GND

Positive Power

Supply

Negative

Power Supply

Ground

+5V±5%

–5V±5%

All analog and digitalsignals are referenced to this pin.

BCLK I 16 12 Bit Clock Bit clock input used to shift PCM data into and out of the

DRand DXpins. BCLK may vary from 64 kHz to 4.096

MHz in 8 kHz increments, and must be synchronous with

MCLK (TS5071 only).

MCLK I 17 12 Master Clock Master clock input used by the switched capacitor filters

and the encoder and decoder sequencing logic. Must be

512 kHz, 1. 536/1. 544 MHz,

2.048 MHz or 4.096 MHz and synchronous with BCLK.

BCLK and MCLK arewired together in the TS5071.

PLCC28

TS5070FN DIP20

TS5071N

TS5070 - TS5071

4/32

TRANSMIT SECTION

Name Pin

Type TS5070

FN TS5071

NFunction Description

FSXI 22 15 Transmit

Frame Sync. Normally a pulse or squarewave waveform withan 8 kHz

repetition rate is applied to this inputto definethe start of

the transmit time-slot assigned to this device (non-delayed

data mode) or the start of the transmit frame (delayed

data mode using the internal time-slot assignment

counter).

VFXI I 28 20 Transmit

Analog This is a high–impedance input. Voicefrequency signals

present on this input are encoded as an A–law orµ–law

PCM bit stream and shifted out on the selected DXpin.

DX0

DX10

018

19 13

–Transmit Data DX1 is available on theTS5070 only, DX0 is available on

all devices. These transmit data TRI–STATEoutputs

remain in the high impedance state except during the

assigned transmit time–slot on the assigned port, during

which the transmit PCM data byte is shifted out on the

rising edges of BCLK.

TSX0

TSX10

020

21 14

–Transmit

Time–slot TSX1 is available on the TS5070 only.

TSX0 is available on all devices. Normally these opendrain

outputs are floating in a high impedance state except

when a time–slotis active on one of the DXoutputs, when

the apppropriate TSXoutput pulls low to

enable a backplane line–driver. Should be strapped to

ground (GND) when not used.

RECEIVESECTION

Name Pin

Type TS5070

FN TS5071

NFunction Description

FSRI 8 6 Receive Frame

Sync. Normally a pulse or squarewave waveform withan 8 kHz

repetition rate is applied to this inputto definethe start of

the receive time–slot assigned to this device (non-delayed

frame mode) or the start of the receive frame (delayed

frame mode using the internal time-slot assignment

counter.

VFR0 0 2 2 Receive Analog The receive analog power amplifier output, capable of

driving load impedances as low as 300Ω(depending on

the peak overload levelrequired). PCM datareceived on

the assigned DRpin is decoded and appears at this output

as voice frequency signals.

DR0

DR1I

I10

–Receive Data DR1 is availableon the TS5070 only, DR0 isavailable on

all devices. These receive data input(s)are inactive

except during the assignedreceive time–slot of the

assigned port when the receive PCM data is shifted inon

the falling edges of BCLK.

TS5070 - TS5071

5/32

FUNCTIONAL DESCRIPTION

POWER-ONINITIALIZATION

When power is first applied, power-on reset cir-

cuitry initializes COMBO IIG and puts it into the

power-down state. The gain control registers for

the transmit and receive gain sections are pro-

grammed for no output, the hybrid balance circuit

is turned off, the power amp is disabled and the

device is in the non-delayed timing mode. The

Latch Direction Register (LDR) is pre-set with all

IL pins programmed as inputs, placing the SLIC

interface pins in a high impedance state. The

CI/O pin is set as an input ready for the first con-

trol byte of the initialization sequence.Other initial

states in the Control Register are indicated in Ta-

ble 2.

Aresetto thesesameinitialconditionsmayalso be

forcedbydrivingtheMR pinmomentarilyhigh.This

maybedoneeitherwhen powered-upor down.For

normaloperationthis pin must be pulledlow. If not

used,MR should be hard-wired to ground.

The desiredmodesforall programmablefunctions

may be initialized via the control port prior to a

Power-upcommand.

INTERFACE, CONTROL, RESET

Name Pin

Type TS5070

FN TS5071

NFunction Description

IL5

IL4

IL3

IL2

IL1

IL0

I/O

–

Interface

Latches IL5 throughIL0 are available on the TS5070,

IL4 throughIL0 are available on the TS5071.

Each interface Latch I/O pin may be individually

programmed as an input or an output determined by the

state of the corresponding bit inthe Latch Direction

state sensed on each input is latched into the interface

Latch Register (ILR) whenever control data is written to

COMBO IIG, while CS is low, and the information is

shifted out on the CO (or CI/O) pin. Whenconfigured as

outputs, control data written into the ILR appears at the

corresponding IL pins.

CCLK I 13 9 Control Clock This clock shifts serial control information into or out of CI

or CO (or CI/O) when the CS input is low depending on

the current instruction. CCLK may be asynchronous with

the othersystem clocks.

CI/O I/O – 8 Control Data

Input/output This is Control Data I/O pin wich is provided on the

TS5071. Serial control information is shifted into or out of

COMBO IIG on this pinwhen CS is low. The directionof

the data is determinedby the current instruction as defined

in Table 1.

–

Control Data

Input

Control Data

Output

These are separate controls, availables only on the

TS5070. They can be wired together if required.

CS I 14 10 Chip Select When this pins is low, control information can be written to

or read from the COMBO IIG via the CI and CO pins (or

CI/O).

MR I 15 11 Master Reset This logic input must be pulled low for normal operation of

COMBO IIG. When pulled momentarily high, all

programmable registers in the device are reset to the

states specified under ”Power–on Initialization”.

TS5070 - TS5071

6/32

POWER-DOWN STATE

Following a period of activity in the powered-up

state the power-down state may be re-entered by

writing any of the control instructions into the serial

control port with the ”P” bit set to ”1” It is recom-

mendedthat thechipbepowereddownbefore writ-

ing any additional instructions. In the power-down

state, all non-essentialcircuitry is de-activated and

theDX0andD

1outputsarein thehighimpedance

TRI-STATEcondition.

Thecoefficientsstoredin theHybridBalancecircuit

and theGain Controlregisters,the data in the LDR

and ILR, and all control bits remain unchanged in

the power-down state unless changed by writing

new data via the serialcontrol port,which remains

operational. The outputs of the Interface Latches

also remain active, maintainingthe ability to moni-

tor and control a SLIC.

TRANSMIT FILTERAND ENCODER

The Transmit section input, VFXI, is a high imped-

ance summinginputwhichis usedas thedifferenc-

ingpointfortheinternalhybridbalancecancellation

signal. No external componentsare needed to set

the gain. Following this circuit is a programmable

gain/attenuationamplifierwhichiscontrolledbythe

contents of the Transmit Gain Register (see Pro-

grammable Functions section). An active prefilter

then precedes the 3rd order high-pass and 5th or-

der low-pass switched capacitor filters. The A/D

converterhasacompressingcharacteristicaccord-

ing to the standardCCITT A or µ255 coding laws,

whichmustbe selectedbya controlinstructiondur-

ing initialization(see table1 and2).A precisionon-

chip voltagereferenceensuresaccurateand highly

stable transmission levels. Any offset voltage aris-

ing in the gain-set amplifier, the filters or the com-

paratoris cancelledbyaninternalauto-zerocircuit.

Each encode cycle begins immediately following

the assigned Transmit time-slot. The total signal

delay referencedto the startof the time-slot is ap-

proximately 165 µs (due to the Transmit Filter)

plus 125 µs (due to encoding delay), which totals

290 µs. Data is shifted out on DX0orD

1 during

the selected time slot on eight rising edges of

BCLK.

DECODERAND RECEIVEFILTER

PCM data is shifted into the Decoder’s Receive

PCMRegisterviatheDR0orDR1pinduringthe se-

lectedtime-slotonthe8fallingedgesof BCLK.The

Decoder consistsof an expandingDAC with either

Aorµ

255law decodingcharacteristic, which isse-

lectedbythesamecontrolinstructionusedtoselect

the Encode law during initialization. Following the

Decoderisa 5thorderlow-passswitchedcapacitor

filter with integral Sin x/x correction for the 8 kHz

sample and hold. A programmablegain amplifier,

which must be set by writing to the Receive Gain

Amplifier capable of driving a 300 Ωload to ±3.5

V, a 600 Ωload to ±3.8 Vor 15 kΩloadto ±4.0 V

at peak overload.

A decode cycle begins immediately after each re-

ceive time-slot, and 10 µs later the Decoder DAC

output is updated. The total signal delay is 10 µs

plus 120 µs (filter delay) plus 62.5 µs (1/2 frame)

whichgives approximately 190 µs.

PCM INTERFACE

TheFSXand FSRframe sync inputsdetermine the

beginning of the 8-bit transmit and receive time-

slots respectively. They may have any duration

from a single cycle of BCLK to one MCLK period

LOW. Two different relationships may be estab-

lishedbetweentheframesyncinputsandtheactual

time-slotson thePCM bussesby settingbit 3 inthe

Control Register (see table 2). Non delayed data

mode is similar to long-frame timing on the

ETC5050/60 series of devices : time-slots being

nominallycoincidentwith the risingedge of the ap-

propriate FS input. The alternative is to use De-

layed Data mode which is similar to short-frame

sync timing, in which each FS input must be high

at least a half-cycleof BCLK earlier than the time-

slot.

TheTime-SlotAssignmentcircuit onthedevicecan

onlybeusedwithDelayedDatatiming.Whenusing

Time-Slot Assignment, the beginning of the first

time-slot in a frame is identifiedby the appropriate

FSinput.Theactualtransmitandreceivetime-slots

are then determined by the internalTime-Slot As-

signment counters. Transmit and Receive frames

and time-slots may be skewed from each other by

any numberof BCLK cycles.

During each assigned transmit time-slot, the se-

lected DX0/1 output shifts data out from the PCM

TSX1 as appropriate) also pulls low for the first 7

1/2 bit times of the time-slot to control the TRI-

STATE Enable of a backplane line driver. Serial

PCM data is shifted into the selected DR0/1 input

during each assigned Receive time slot on the

falling edges of BCLK. DX0orD

1 and DR0or

1 are selectable on the TS5070 only.

SERIALCONTROL PORT

Control information and data are written into or

readback from COMBO IIG via the serial control

portconsistingofthecontrolclockCCLK; theserial

data input/output CI/O (or separate input CI, and

output CO on the TS5070only); and the Chip Se-

lect input CS. All control instructions require 2

bytes,as listedintable1, withtheexceptionof asin-

gle bytepower-up/downcommand. The byte1 bits

are used as follows: bit 7 specifies power-up or

power-down;bits 6, 5, 4 and 3 specifythe register

address; bit 2 specifies whetherthe instructions is

read or write; bit 1 specifies a one or two byte in-

TS5070 - TS5071

7/32

struction;and bit 0 isnot used.To shiftcontroldata

into COMBO IIG, CCLK must be pulsed high 8

timeswhile CSis low.Dataon the CI or CI/Oinput

is shifted into the serial input register on the falling

edge of each CCLK pulse. After all data is shifted

in, the contents of the input shift register are de-

coded, and mayindicatethat a 2nd byte of control

data will follow. Thissecondbyte mayeither be de-

finedby asecondbyte-wideCSpulseor mayfollow

thefirstcontinuously,i.e. it isnotmandatoryfor CS

to return high in betweenthe first and secondcon-

trolbytes.Onthefallingedgeof the8th CCLKclock

pulse in the2ndcontrolbyte the datais loadedinto

theappropriateprogrammableregister.CSmayre-

main low continuouslywhen programmingsucces-

siveregisters,ifdesired.HoweverCSshouldbeset

high when no data transfersare in progress.

ToreadbackinterfaceLatchdataor statusinforma-

tionfrom COMBOIIG,the first byte oftheappropri-

ateinstructionisstrobedinduringthefirstCSpulse,

asdefinedintable1.CS must thenbetakenlow for

a further8 CCLK cycles, during which the data is

shifted ontothe CO or CI/O pin on therisingedges

of CCLK. When CS is high the CO or CI/O pin is in

thehigh-impedanceTRI-STATE,enablingtheCI/O

pins of many devices to be multiplexed together.

Thus, to summarize, 2-byte READ and WRITEin-

structionsmay use either two8-bit wide CS pulses

or a single 16-bit wide CS pulse.

Function Byte 1 Byte 2

76543210

Single Byte Power–up/down PXXXXX0X None

Write Control Register

Read–back ControlRegister P

XSee Table 2

See Table 2

Write Latch Direction Register (LDR)

Read Latch Direction Register P

XSee Table 4

See Table 4

Write Latch Content Register (ILR)

Read Latch Content Register P

XSee Table 5

See Table 5

Write Transmit Time–slot/port

Read–back Transmit Time–slot/port P

XSee Table 6

See Table 6

Write Receive Time–slot/port

Read–back Receive Time–slot/port P

XSee Table 6

See Table 6

Write Transmit GainRegister

Read Transmit GainRegister P

XSee Table 7

See Table 7

Write Receive GainRegister

Read Receive Gain Register P

XSee Table 8

See Table 8

Write Hybrid Balance Register ≠1

Read Hybrid BalanceRegister ≠1P

XSee Table 9

See Table 9

Write Hybrid Balance Register ≠2

Read Hybrid BalanceRegister ≠2P

XSee Table 10

See Table 10

Write Hybrid Balance Register ≠3

Read Hybrid BalanceRegister ≠3P

Table 1: ProgrammableRegisterInstructions

PROGRAMMABLE FUNCTIONS

POWER-UP/DOWN CONTROL

Following power-on initialization, power-up and

power-down control may be accomplished by

writing any of the control instructions listed in ta-

ble 1 into COMBO IIG with the ”P” bit set to ”0”

for power-up or ”1” for power-down. Normally it is

recommendedthat all programmablefunctionsbe

initially programmed while the device is powered

down. Power state control can then be included

with the last programming instruction or the sepa-

rate single-byte instruction. Any of the program-

mable registers may also be modified while the

device is powered-up or down be setting the ”P”

bit as indicated.When the power up or down con-

trol is entered as a single byte instruction, bit one

(1) must be set to a 0.

When a power-up command is given, all de-acti-

vated circuits are activated, but the TRI-STATE

PCM output(s), DX0 (and DX1), will remain in the

high impedance state until the second FSXpulse

after power-up.

Notes: 1. Bit 7 of bytes 1 and 2 is always the first bitclocked into or out of the CI, CO or CI/CO pin.

2. ”P” is the power-up/down control bit, see ”Power-up” section (”0” = Power Up ”1” = Power Down).

TS5070 - TS5071

8/32

CONTROLREGISTERINSTRUCTION

The first byte of a READ or WRITE instruction to

the Control Register is as shown in table 1. The

second byte functionsare detailed in table2.

MASTER CLOCK FREQUENCY SELECTION

A Master clock must be provided to COMBO IIG

for operation of the filter and coding/decoding

functions. The MCLK frequency must be either

512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or

4.096 MHz and must be synchronouswith BCLK.

Bits F1 and F0 (see table 2) must be set during

initializationto selectthe correctinternal divider.

CODING LAW SELECTION

Bits ”MA” and ”IA” in table 2 permit the selection

of µ255 coding or A-law coding with or without

even-bit inversion.

ANALOGLOOPBACK

Analog Loopback mode is entered by setting the

”AL”and”DL” bitsin theControlRegisteras shown

in table 2. In the analogloopbackmode, the Trans-

mit input VFXI is isolated from the inputpin and in-

ternally connected to the VFRO output, forming a

loop from the Receive PCM Register back to the

TransmitPCM Register.The VFRO pinremainsac-

tive, and the programmed settings of the Transmit

and Receive gains remain unchanged, thus care

must be taken to ensure that overload levels are

notexceededanywherein theloop.

Hybrid balancing must be disabled for meaning

ful analogloopbackFunction.

DIGITALLOOPBACK

Digital Loopback mode is entered by setting the

”DL”bit in the ControlRegister asshownin table 2.

Bit Number Function

76543210

F1 F0 MA IA DN DL AL PP

MCLK = 512kHz

MCLK = 1. 536 or 1. 544 MHz

MCLK = 2.048 MHz *

MCLK = 4.096 MHz

Select µ. 255 Law *

A–law, Including Even Bit Inversion

A–Law, No Even Bit Inversion

1Delayed Data Timing

Non–delayed Data Timing *

Normal Operation *

Digital Loopback

Analog Loopback

1Power Amp Enabledin PDN

Power Amp Disabled in PDN *

Table 2: ControlRegister Byte 2 Functions

Table 3: Coding Law Conventions.

m255 Law

MSB LSB

True A-law with

even bit inversion

MSB LSB

A-law without

even bit inversion

MSB LSB

VIN = +Full Scale 100000001010101011111111

IN =0V 1

IN = -Full Scale 000000000010101001111111

Note: The MSB is always the first PCM bit shifted in or out of COMBO IIG.

(*) State at power-on initialization (bit 4 = 0)

TS5070 - TS5071

9/32

Thismode providesanother stageof pathverifica-

tionby enablingdata written into the ReceivePCM

Transmit time-slot at DX0orD

For Analog Loopback as well as for Digital Loop-

back PCM decoding continues and analog output

appears at VFRO. The output can be disabled by

pro gramming ”No Output” in the Receive Gain

INTERFACE LATCH DIRECTIONS

Immediately following power-on, all Interface

Latches assume they are inputs, and therefore all

IL pins are in a high impedance state. Each IL pin

maybe individuallyprogrammedasa logicinputor

output by writing the appropriateinstruction to the

LDR, see table 1 and 4. Bits L5-L0must be setby

writing the specific instruction to the LDR with the

L bits inthe secondbyte set as specifiedin table4.

Unused interface latches should be programmed

as outputs.For the TS5071, L5 should always be

programmedas an output.

(*) State at power-on initilization.

Note: L5 should be programmedas an output for the TS5071.

INTERFACE LATCH STATES

Interface Latches configured as outputs assume

the state determinedby the appropriatedatabit in

the 2-byte instruction written to the Latch Content

Latches configured as inputs will sense the state

applied by an external source, such as the Off-

Hook detect output of a SLIC. All bits of the ILR,

i.e. sensed inputs and the programmed state of

outputs, can be read back in the 2nd byte of a

READ from the ILR. It is recommended that, dur-

ing initialization, the state of IL pins to be config-

ured as outputs should first be programmed, fol-

lowed immediately by the Latch Direction

TIME-SLOTASSIGNMENT

COMBOIIGcan operatein eitherfixedtime-slot or

time-slot assignmentmode for selectingthe Trans-

mit and ReceivePCM time-slots. Followingpower-

on,the deviceis automaticallyin Non-DelayedTim-

ing mode,in whichthe time-slotalwaysbegins with

the leading (rising) edge of frame sync inputs FSX

and FSR. Time-Slot Assignment may only be used

with Delayed Data timing : see figure 6. FSXand

FSRmay have any phase relationship with each

other in BCLKperiod increments.

Bit Number

76543210

L0 L1 L2 L3 L4 L5 X X

Table4: Byte2 FunctionofLatchDirectionRegister

LNBit IL Direction

1Input *

Output

Bit Number Function

(note 1)

(note 2)

T4 3

T3 2

T2 1

T1 0

0X X XXXXX

Disable DXOutputs (transmit instruction) *

Disable DRInputs (receive instruction) *

10Assign One Binary CodedTime-slot from 0–63

Assign One Binary CodedTime-slot from 0–63

Enable DX0 Output,Disable DX1 Output

(Transmit instruction)

Enable DR0 Input, Disable DR1 Input

(Receive Instruction)

11Assign One Binary CodedTime-slot from 0–63

Assign One Binary CodedTime-slot from 0–63

Enable DX1 Output,Disable DX0 Output

(Transmit instruction)

Enable DR1 Input, Disable DR0 Input

(Receive Instruction)

Table 6: Byte2 of Time-slot and Port Assignment Instructions

Bit Number

76543210

D0 D1 D2 D3 D4 D5 X X

Table 5: InterfaceLatchData Bit Order

Notes:

1. The ”PS” bit MUST always be set to 0 for theTS5071.

2. T5 is the MSB of the time-slot assignment.

(*) State at power-on initialization

TS5070 - TS5071

10/32

Alternatively, the internal time-slot assignment

counters and comparatorscan be used to access

anytime-slotina frame,usingtheframesyncinputs

as markerpulses for the beginning of transmit and

receivetime-slot0. Inthis mode,a framemaycon-

sist ofup to 64time-slotsof 8 bitseach.A time-slot

isassignedbya2-byteinstructionasshownintable

1 and6. The last6 bits of the secondbyte indicate

the selected time-slot from 0-63 using straight bi-

nary notation. A new assignment becomes active

on the second frame following the end of the Chip

Select forthe second control byte.The ”EN”bit al-

lowsthePCMinputsDR0/1 oroutputsDX0/1 asap-

propriate, to be enabled or disabled.

Time-Slot Assignmentmode requires that the FSX

and FSRpulsesmustconformto thedelayedtiming

formatshown in figure6.

PORT SELECTION

On the TS5070 only, an additional capability is

available : 2 Transmit serial PCM ports, DX0 and

DX1,and2 receiveserialPCM ports,DR0 andDR1,

are providedto enabletwo-way space switching to

be implemented. Port selections for transmit and

receive are made within the appropriatetime-slot

assignmentinstructionusingthe”PS”bit in thesec-

ond byte.

On the TS5071,only ports DX0 and DR0 areavail-

able,therefore the ”PS” bit MUST always be set to

0 for thesedevices.

Table 6 shows the format for the second byte of

bothtransmitand receivetime-slotandportassign-

mentinstructions.

TRANSMIT GAIN INSTRUCTION BYTE2

The transmit gain can be programmed in 0.1 dB

steps by writing to the Transmit Gain Register as

defined in tables 1 and 7. This corresponds to a

range of 0 dBm0 levels at VFXI between 1.619

Vrms and 0.087 Vrms (equivalent to + 6.4 dBm to

– 19.0 dBm in 600 Ω).

To calculate the binary code for byte 2 of this in-

struction for any desired input 0 dBm0 level in

Vrms, take the nearest integer to the decimal

numbergiven by :

and convert to the binary equivalent.Some exam-

ples are given in table 7.

Bit Number 0dBm0 Test Leve at VFXI

7 6 5 4 3 2 1 0 In dBm (Into 600Ω) In Vrms (approx.)

0 0 0 0 0 0 0 0 No Output

0–19

– 18.9 0.087

0.088

1 0 1 1 1 1 1 1 0 0.775

1+6.3

+6.4 1.60

1.62

Table 7: Byte2 of Transmit Gain Instructions.

(*) State at power initialization

RECEIVE GAIN INSTRUCTION BYTE 2

The receive gain can be programmed in 0.1 dB

stepsbywritingtotheReceiveGainRegisterasde-

finedin table1 and8. Notethe followingrestriction

on outputdrive capability :

a) 0 dBm0 levels ≤8.1dBm at VFRO may be

driven into a load of ≥15 kΩto GND,

b) 0 dBm0 levels ≤7.6dBm at VFRO may be

driven into a load of ≥600 Ωto GND,

c) 0 dBm levels ≤6.9dBmat VFRO may be driven

into a load of ≥300 Ωto GND.

To calculate the binary code for byte 2 of this in-

struction for any desired output 0 dBm0 level in

Vrms,take the nearestintegerto the decimalnum-

ber given by :

d convert to the binary equivalent. Some exam-

ples are given in table 8.

200 X log10 (V/√6) +191

200 X log10 (V/√6) +174

TS5070 - TS5071

11/32

HYBRID BALANCEFILTER

The Hybrid Balance Filter on COMBO IIG is a

programmable filter consisting of a second-order

Bi-Quad section, Hybal1, followed by a first-order

section, Hybal2, and a programmable attenuator.

Either of the filter sections can be bypassed if

only one is required to achieve good cancellation.

A selectable 180 degree inverting stage is in-

cluded to compensate for interface circuits which

also invert the transmit input relative to the re-

ceive output signal. The Bi-Quad is intended

mainly to balance low frequency signals across a

transformer SLIC, and the first order section to

balance midrange to higher audio frequency sig-

nals. The attenuatorcan be programmed to com-

pensate for VFROtoVF

I echos in the range

of -2.5 to – 8.5 dB.

As a Bi-Quad, Hybal1 has a pair of low frequency

zeroes and a pair of complex conjugate poles.

When configuring the Bi-Quad, matching the

phase of the hybrid at low to midband frequencies

is most critical. Once the echo path is correctly

balanced in phase, the magnitudeof the cancella-

tion signal can be corrected by the programmable

attenuator.

The Bi-Quad mode of Hybal1 is most suitable for

balancinginterfaceswith transformershavinghigh

inductance of 1.5 Henries or more. An alternative

configuration for smaller transformers is available

byconvertingHybal1to a simplefirst-ordersection

witha singlereallowfrequencypoleand0 Hzzero.

In this mode,the pole/zerofrequencymay be pro-

grammed.

Many line interfaces can be adequately balanced

by use of the Hybal1 section only, in which case

the Hybal2 filter should be de-selected to bypass

it.

Hybal2, the higher frequencyfirst-order section, is

provided for balancing an electronic SLIC, and is

also helpful with a transformer SLIC in providing

additionalphase correction for mid and high-band

frequencies, typically 1 kHz to 3.4 kHz. Such a

correction is particularly useful if the test balance

impedanceincludes a capacitorof 100 nF or less,

such as the loaded and non-loadedloop test net-

works in the United States. Independent place-

ment of the pole and zero location is provided.

Bit State Function

7 0 Disable Hybrid Balance Circuit Completely.

No internal cancellation is provided. *

1 Enable Hybrid Balance Cancellation Path

6 0 Phase of the internal cancellation signal assumes inverted phase of the echo

path from VFROtoVF

1 Phase of the internal cancellation signal assumes no phase inversion in the line

interface.

5 0 Bypass Hybal 2Filter Section

1 Enable Hybal 2 Filter Section

G4–G0 Attenuation Adjustment for the Magnitude of the CancellationSignal. Range is

– 2.5 dB (00000) to – 8.5 dB (11000)

Table 9: HybridBalanceRegister 1 Byte2 Instruction.

Notes:

1. Maximum level into 300Ω; 2.Maximum level into 600Ω;3.R

≥15KΩ(*)State at power on initialization

(*) State at power on initialization

Setting= Please refer tosoftware TS5077 2

Bit Number 0dBm0 Test Leve at VFR0

7 6 5 4 3 2 1 0 In dBm (Into 600Ω) In Vrms (approx.)

0 0 0 0 0 0 0 0 No Output

0– 17.3

– 17.2 0.106

0.107

1 0 1 0 1 1 1 0 0 0.775

1 1 1 1 0 0 1 1 + 6.9 (note 1) 1.71

1 1 1 1 1 0 1 0 + 7.6 (note 2) 1.86

1 1 1 1 1 1 1 1 + 8.1 (note 3) 1.07

Table 8: Byte2 of ReceiveGain Instructions.

TS5070 - TS5071

12/32

Figure 1 shows a simplified diagram of the local

echo path for a typical application with a trans-

formerinterface. The magnitude and phase of the

local echo signal,measuredat VFXI, area function

of the termination impedance ZT, the line trans-

formerandtheimpedanceofthe2Wloop,ZL. Ifthe

impedancereflected backinto the transformerpri-

maryis expressedasZL’ thenthe echopath trans-

fer functionfrom VFROtoVF

XIis:

H(W) = ZL’ /(ZT+Z

’) (1)

Figure 1: Simplified Diagram of HybridBalance Circuit

PROGRAMMING THE FILTER

On initial power-up the Hybrid Balance filteris dis-

abled. Before the hybrid balance filter can be pro-

grammedit is necessaryto design the transformer

andterminationimpedanceinordertomeetsystem

2 W input return loss specifications,which are nor-

mally measured against a fixed test impedance

(600or 900Ωinmostcountries).Onlythencan the

echo path bemodeledand thehybridbalancefilter

programmed. Hybrid balancing is also measured

against a fixed test impedance, specified by each

national Telecom administration to provide ade-

quate control of talker and listener echo over the

majority of their network connections.This test im-

pedance is ZLin figure 1. The echo signaland the

degree of transhybrid loss obtained by the pro-

grammable filter must be measured fromthe PCM

digital input DR0, to the PCM digital output DX0,

eitherbydigitaltestsignalanalysisorbyconversion

back to analog by a PCM CODEC/Filter.

Three registers must be programmed in COMBO

IIG to fully configure the Hybrid Balance Filter as

follows:

invert/non-invert cancellation signal;

select/de-select Hybal2 filter section;

attenuatorsetting.

Register2: select/de-select Hybal1 filter;

set Hybal1 to Bi-Quad or 1st order;

program pole and zero frequency.

Register3 : programpolefrequencyin Hybal2filter;

programzerofrequencyinHybal2filter;

settings = Please refer to software

TS5077-2.

Standard filter design techniquesmay be used to

modelthe echo path(see equation(1)) and design

amatchinghybridbalancefilterconfiguration.Alter-

natively, the frequency response of the echo path

can be measuredand the hybridbalancefilter pro-

grammed to replicate it.

An Hybrid Balance filter design guide and soft-

ware optimization program are available under li-

cense from SGS-THOMSON Microelectronics (or-

der TS5077-2).

Bit Number Function

76543210

0 0 0 0 0 0 0 0 By Pass Hybal 1

Filter

XXXXXXXXPole/zero Setting

Table 10: Hybrid Balance Register 2 Byte 2 in-

structions

TS5070 - TS5071

13/32

APPLICATION INFORMATION

Figure 2 showsa typical applicationof the TS5070

togetherwith a transformerSLIC.

The design of the transformer is greatly simplified

duetotheon-chiphybridbalancecancellationfilter.

Onlyonesinglesecondarywindingis required(see

application note AN.091 - Designing a subscriber

line card module using the TS5070/COMBOIIG).

Figures 3 and 4 show an arrangement with SGS-

ThomsonmonolithicSLICS.

POWERSUPPLIES

Whilethepins of theTS5070and TS5071/COMBO

IIG devices are well protected against electrical

misuse, it is recommended that the standard

CMOS practice of applying GND to the device be-

foreanyotherconnectionsaremadeshouldalways

befollowed.Inapplicationswheretheprintedcircuit

card may be pluggedinto a hot socket with power

and clocks already present, an extra long ground

pinontheconnectorshouldbeusedandaSchottky

diode connected between VSS and GND. To mini-

mizenoise sourcesall groundconnectionstoeach

deviceshouldmeet at a commonpointas close as

possible to the GND pin in order to preventthe in-

teractionof groundreturn currentsflowing through

a common bus impedance. Power supply decou-

plingcapacitorsof0.1µFshouldbeconnectedfrom

this common device ground point to VCC and VSS

ascloseto thedevicepinsaspossible.VCCandVSS

should also be decoupledwith low effective series

resis-tancecapacitorsofatleast10µFlocatednear

the card edge connector.

TS5070 - TS5071

14/32

Figure 2: TransformerSLIC + COMBOIIG.

TS5070 - TS5071

15/32

Figure 4: Interfacewith L3092 + L3000 Silicon SLIC.

L3092

L3000

TS5070 - TS5071

16/32

ELECTRICAL OPERATING CHARACTERISTICS

Unlessotherwisenoted, limitsin BOLDcharacters

are guaranteedfor VCC =+5V±5%;V

SS =–5

V±5%.T

A= -40 °Cto85°C by correlationwith

100%electricaltestingat TA=25°C. All otherlimits

are assured by correlation with other production

tests and/or product design and characterisation.

AllsignalsreferencedtoGND.Typicalsspecifiedat

VCC= + 5 V,VSS =

−

5V,T

A=25°C.

DIGITALINTERFACE

Symbol Parameter Min. Typ. Max. Unit

VIL Input Low Voltage AllDigital Inputs (DC measurement) 0.7 V

VIH Input High Voltage All DigitalInputs (DC measurement) 2.0 V

VOL Output Low Voltage

DX0 and DX1, TSX0, TSX1 and CO, IL= 3.2mA

All Other Digital Outputs, IL= 1mA 0.4 V

VOH Output High VoltageDX0 and DX1 and CO, IL= -3.2mA

All other digital outputs exceptTSX,I

L= -1mA

All Digital Outputs, IL= -100µA2.4

VCC-0.5 V

IIL Input Low Current all Digital Inputs (GND < VIN <V

IL)-10 10 µA

IIH Input High Current all Digital Inputs Except MR (VIH <V

IN <V

CC)-10 10 µA

IIH Input High Current on MR -10 100 µA

IOZ Output Current in High Impedance State (TRI-STATE)

DX0 and DX1, CO and CI/O (as an input) IL5-IL0 as inputs

(GND < VO<V

CC)

-10 10 µA

ANALOG INTERFACE

Symbol Parameter Min. Typ. Max. Unit

IVFXI Input Current VFXI (-3.3V < VFXI < 3.3V) -10 10 µA

RVFXI Input Resistance VFXI (-3.3V < VFXI < 3.3V) 390 620 kΩ

VOSXInput offset voltage at VFXI

0dBm0 = -19dBm

0dBm0 = +6.4dBm 10

200 mV

RLVFRO Load Resistance at VFRO

0dBm0 = 8.1dBm

0dBm0 = 7.6dBm

0dBm0 = 6.9dBm

600

300

kΩ

Ω

CLVFRO Load Capacitance CLVFRO from VFRO to GND 200 pF

ROVFRO Output Resistance VFRO (steady zero PCM code applied to DR0 or

DR1) 13Ω

OSR Output Offset Voltage at VFRO (alternating ±zero PCM code applied

to DR0orD

1, 0dBm0 = 8.1dBm) -200 200 mV

TS5070 - TS5071

17/32

TIMING SPECIFICATIONS

Unlessotherwisenoted,limitsinBOLDcharactersare

guaranteedforVCC =+5V±5%;V

SS = -5V ±

A=-40°Cto85°C bycorrelationwith100 %elec-

trical testing at TA=25°C. All other limits are as-

sured by correlation with other production tests

and/orproduct design and characterization. All sig-

nals referenced to GND. Typicals specified at

VCC =+5V,V

SS =-5V,T

A=25°

C. All timingpa-

rametersaremeasuredatVOH =2.0VandVOL =0.7V.

See Definitions and Timing Conventions section

for test methods information.

ELECTRICAL OPERATING CHARACTERISTICS (continued)

POWERDISSIPATION

Symbol Parameter Min. Typ. Max. Unit

ICC0 Power Down Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V)

Interface Latches set as Outputs with no load

All over Inputs active, Power Amp Disabled

0.3 1.5 mA

-ISS0 Power Down Current (as above) 0.1 0.3 mA

ICC1 Power Up Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V)

No Load on Power Amp

Interface Latches set as Outputs with no Load 7 11 mA

-ISS1 Power Up Current (as above) 7 11 mA

ICC2 Power Down Currentwith Power Amp Enabled 2 4mA

-ISS2 Power Down Currentwith Power Amp Enabled 2 4mA

MASTER CLOCK TIMING

Symbol Parameter Min. Typ. Max. Unit

fMCLK Frequency of MCLK

(selection of frequency is programmable, see table 2) 512

1.536

1.544

2.048

4.096

kHz

MHz

tWMH Period ofMCLK High (measured from VIH to VIH, see note 1) 80 ns

tWML Period ofMCLK Low (measured from VIL to VIL, see note 1 ) 80 ns

tRM Rise Time of MCLK (measured from VIL or VIH)30ns

FM Fall Time of MCLK (measured from VIH to VIL)30

HBM Hold Time, BCLK Low to MCLK High (TS5070 only) 50 ns

tWFL Period ofFSXor FSRLow (Measured from VIL to VIL) 1 (*)

(*) MCLK period

TS5070 - TS5071

18/32

TIMING SPECIFICATIONS (continued)

PCM INTERFACE TIMING

Symbol Parameter Min. Typ. Max. Unit

fBCLK Frequency of BCLK (may vary from 64KHz to 4.096MHz in 8KHz

increments, TS5070 only) 64 4096 kHz

tWBH Period of BCLK High (measured from VIH to VIH)80 ns

tWBL Period of BCLK Low (measured from VIL to VIL)80 ns

tRB Rise Time of BCLK (measured from VIL to VIH)30ns

FB Fall Time of BCLK (measured from VIH to VIL)30ns

HBF Hold Time, BCLK Low to FSX/R High or Low 30 ns

tSFB Setup Time FSX/R High to BCLK Low 30 ns

tDBD Delay Time, BCLK High to Data Valid (load = 100pF plus 2 LSTTL

loads) 80 ns

tDBZ Delay Time from BCLK8 Low to Dx Disabled (if FSx already low);

FSx Low to Dx Disabled (if BCLK8 low);

BCLK9 High to Dx Disabled (if FSx still high) 15 80 ns

tDBT Delay Time fromBCLK and FSx Both High to TSx Low (Load = 100pF

plus 2 LSTTL loads) 60 ns

tZBT Delay Time from BCLK8 low to TSx Disabled (if FSx already low);

FSx Low to TSx Disabled (if BCLK8 low);

BCLK9 High to TSx Disabled (if FSx still high);

15 60 ns

tDFD Delay Time, FSx High to Data Valid (load = 100pF plus 2 LSTTL

loads, applies if FSx rises later than BCLK rising edge in non-

delayed data mode only)

80 ns

tSDB Setup Time, DR0/1 Valid to BCLK Low 30 ns

tHBD Hold Time, BCLK Low to DR0/1 Invalid 20 ns

Figure 5: Non DelayedData Timing (short frame mode)

TS5070 - TS5071

19/32

Figure 6: DelayedData Timing (short frame mode)

SERIALCONTROL PORTTIMING

Symbol Parameter Min. Typ. Max. Unit

fCCLK Frequency of CCLK 2.048 MHz

tWCH Period of CCLK High (measured from VIH to VIH)160 ns

tWCL Period of CCLK Low (measured from VIL to VIL)160 ns

tRC Rise Time of CCLK (measured from VIL to VIH)50ns

FC Fall Time of CCLK (measured from VIH to VIL)50ns

HCS Hold Time, CCLK Low to CS Low (CCLK1) 10 ns

tHSC Hold Time, CCLK Low to CS High (CCLK8) 100 ns

tSSC Setup Time, CS Transition to CCLK Low 70 ns

tSSCO Setup Time, CS Transition to CCLK High (to insure CO is not

enabled for singlebyte) 50 ns

tSDC Setup Time, CI (CI/O) Data in to CCLK low 50 ns

tHCD Hold Time, CCLK Low to CI (CI/O) Invalid 50 ns

tDCD Delay Time, CCLK High to CO (CI/O) Data Out Valid

(load = 100 pF plus 2 LSTTL loads) 80 ns

tDSD Delay Time, CS Low to CO (CI/O) Valid

(applies only if separate CS used for byte 2) 80 ns

tDDZ Delay Time, CS or CCLK9 High to CO (CI/O) High Impedance

(applies to earlier of CS high or CCLK9 high) 15 80 ns

INTERFACE LATCH TIMING

Symbol Parameter Min. Typ. Max. Unit

tSLC Setup Time, ILValid to CCLK 8 of Byte 1 Low.ILas Input 100 ns

tHCL Hold Time, ILValid from CCLK8 of Byte 1 Low. ILas Input 50 ns

tDCL Delay Time, CCLK 8 of Byte 2Low to IL.C

L= 50 pF.ILas Output 200 ns

MASTER RESET PIN

Symbol Parameter Min. Typ. Max. Unit

tWMR Duration of Master Reset High 1 µs

TS5070 - TS5071

20/32

Figure 7: ControlPort Timing

TS5070 - TS5071

21/32

TRANSMISSION CHARACTERISTICS

Unless otherwise noted, limits printed in BOLD

characters are guaranteedfor VCC =+5V±5%;

SS =–5V±5%,TA=-40°Cto85°Cbycorrelation

with 100 % electrical testing at TA=25°C (-40°C

to85°C for TS5070-Xand TS5071-X).

f = 1031.25 Hz, VFXI = 0 dBm0, DR0orD

1=0

dBm0PCMcode,HybridBalancefilterdisabled.All

other limits are assured by correlation with other

production tests and/or product design andchar-

acterization. All signals referenced to GND. dBm

levels are into 600 ohms. Typicals specified at

VCC =+5V,V

SS =-5V,T

A=25°C.

AMPLITUDERESPONSE

Symbol Parameter Min. Typ. Max. Unit

Absolute levels

The nominal 0 dBm 0 levels are :

VFXI 0 dB Tx Gain

25.4 dB Tx Gain

VFRO 0 dB Rx Attenuation (RL ≥15 kΩ)

0.5 dB Rx Attenuation (RL ≥600 Ω)

1.2 dB Rx Attenuation (RL ≥300 Ω)

25.4 dB Rx Attenuation

1.618

86.9

1.968

1.858

1.714

105.7

Vrms

mVrms

Vrms

mVrms

Maximum Overload

The nominal overload levels are :

A-law

VFXI 0 dB Tx Gain

25.4 dB Tx Gain

VFRO 0 dB Rx Attenuation (RL≥15 kΩ)

0.5 dB Rx Attenuation (RL≥300 Ω)

1.2 dB Rx Attenuation (RL≥300 Ω)

25.4 dB Rx Attenuation

µ-law

VFXI 0 dB Tx Gain

25.4 dB Tx Gain

VFRO 0 dB Rx Attenuation (RL≥15 kΩ)

0.5 dB Rx Attenuation (RL≥600 Ω)

1.2 dB Rx Attenuation (RL≥300 Ω)

25.4 dB Rx Attenuation

2.323

124.8

2.825

2.667

2.461

151.7

2.332

125.2

2.836

2.677

2.470

152.3

Vrms

mVrms

Vrms

mVrms

Vrms

mVrms

Vrms

mVrms

GXA

Transmit Gain Absolute Accurary

Transmit Gain Programmed for 0 dBm0 = 6.4 dBm, A-law

Measure Deviation of Digital Code from Ideal 0 dBm0 PCM Code

at DX0/1, f = 1031.25 Hz

TA=25°C, VCC = 5 V, VSS =–5V – 0.15 0.15 dB

GXAG

Transmit gain Variation with Programmed Gain

Programmed level from

-12.6dBm ≤0dBm ≤6.4dBm

Programmed level from

-19dBm ≤0dBm ≤12.7dBm

Note: ±0.1dB min/max is available as a selected part

Calculate the Deviation from the Programmed GainRelative to

GXA

i.e., GXAG = Gactual – Gprog – GXA

TA=25°C, VCC = 5 V, VSS =–5V

– 0.1

– 0.3

0.1

0.3

TS5070 - TS5071

22/32

AMPLITUDERESPONSE (continued)

Symbol Parameter Min. Typ. Max. Unit

GXAF Transmit Gain Variation with Frequency

Relative to1031.25 Hz (note 2)

-19 dBm < o dBm0 < 6.4 dBm

DR0 (or DR1) = 0 dBm0 Code

f = 60Hz

f = 200 Hz

f = 300 Hz to 3000 Hz

f = 3400 Hz

f = 4000 Hz

f >4600 Hz Measure Response at AliasFrequency from0 kHzto 4kHz

0 dBm0= 6.4dBm

VFXI= -4dBm0 (note2)

f =62.5 Hz

f =203.125 Hz

f =2093.750 Hz

f =2984.375 Hz

f =3296.875 Hz

f =3406.250 Hz

f =3984.375 Hz

f = 5250 Hz, Measure 2750Hz

f = 11750Hz, Measure 3750 Hz

f =49750 Hz, Measure 1750Hz

-1.8

-0.15

-0.7

-1.7

-0.15

-0.74

-26

-0.1

0.15

-14

-32

GXAT Transmit Gain Variation with Temperature

Measured RelativetoGXA,VCC= 5V,VSS= -5V-19dBm < 0dBm< 6.4dBm -0.1 0.1 dB

GXAV Transmit Gain Variation with Supply

VCC =5V±5%, VSS = -5V ±5%

Measured Relativeto GXA

TA=25°C, o dBm0= 6.4dBm -0.05 0.05 dB

GXAL Transmit Gain Variation with Signal Level

Sinusoidal Test Method, Reference Level = 0 dBm0

VFXI = -40 dBm0 to + 3 dBm0

VFXI = -50 dBm0 to -40 dBm0

VFXI = -55 dBm0 to -50 dBm0

-0.2

-0.4

-1.2

0.2

0.4

1.2

GRA Receive Gain Absolute Accuracy

0 dBm0 = 8.1 dBm, A-law

Apply 0 dBm0PCM Codeto DR0orDR

1 Measure VFRO, f =1015.625Hz

TA=25 °C, VCC =5V,V

SS = -5V -0.15 0.15 dB

GRAG Receive Gain Variation with Programmed Gain

Programmed levelfrom

-10.9dBm ≤0dBm ≤8.1dBm

Programmed levelfrom

-17.3dBm ≤0dBm ≤-11dBm

Note: ±0.1dB min/max is available as a selected part

Calculate the Deviation from the Programmed Gain Relative to GRA

I.e. GRAG = Gactual -Gprog - GRA TA=25

C, VCC = 5V, VSS = -5V

-0.1

-0.3

0.1

0.3

-24.9

-0.1

0.15

-13.5

-32

TS5070 - TS5071

23/32

AMPLITUDERESPONSE (continued)

Symbol Parameter Min. Typ. Max. Unit

GRAT Receive Gain Variation with Temperature

Measure Relative to GRA

VCC = 5V, VSS = -5V -17dBm < 0dBm0 < 8.1dBm -0.1 0.1 dB

GRAV Receive Gain Variation with Supply

Measured Relativeto GRA

VCC =5V±5%, VSS = -5V ±5%

TA=25°C, 0dBm 0 = 8.1 dBm -0.05 0.05 dB

GRAF Receive Gain Variation with Frequency

Relative to1015.625 Hz, (note 2)

DR0orD

1 = 0 dBm0 Code

-17.3dBm < 0 dBm0 < 8.1dBm

f = 200Hz

f = 300Hz to 3000Hz

f = 3400Hz

f = 4000Hz

GR = 0dBm0 = 8.1dBm

DR0 = -4dBm0

Relative to1015.625 (note2)

f = 296.875 Hz

f = 1906.250Hz

f = 2812.500Hz

f = 2984.375Hz

f = 3406.250Hz

f = 3984.375Hz

-0.25

-0.15

-0.7

-0.15

-0.74

0.15

-14

0.15

-13.5

GRAL Receive Gain Variation with Signal Level

Sinusoidal Test Method Reference Level = 0dBm0

DR0 = -40dBm0 to +3dBm0

DR0 = -50dBm0 to -40dBm0

DR0 = -55dBm0 to -50dBm0

DR0 = 3.1dBm0

RL= 600Ω, 0dBm0 = 7.6dBm

RL= 300Ω, 0dBm0 = 6.9dBm

-0.2

-0.4

-1.2

-0.2

0.2

0.4

1.2

0.2

TS5070 - TS5071

24/32

ENVELOPEDELAY DISTORTIONWITH FREQUENCY

Symbol Parameter Min. Typ. Max. Unit

DXA Tx Delay Absolute

f = 1600Hz 315 µs

DXR Tx Delay, Relative to DXA

f = 500 – 600 Hz

f = 600 – 800 Hz

f = 800 – 1000 Hz

f = 1000– 1600 Hz

f = 1600– 2600 Hz

f = 2600– 2800 Hz

f = 2800– 3000 Hz

220

145

105

155

µs

DRA Rx Delay, Absolute

f = 1600Hz 200 µs

DRR Rx Delay, Relative to DRA

f = 500 – 1000 Hz

f = 1000– 1600 Hz

f = 1600– 2600 Hz

f = 2600– 2800 Hz

f = 2800– 3000 Hz

–40

–30 90

125

175

µs

TS5070 - TS5071

25/32

NOISE

Symbol Parameter Min. Typ. Max. Unit

NXC Transmit Noise, C Message Weighted

µ-law Selected (note 3)

0 dBm0 = 6.4dBm

12 15 dBrnC0

NXP Transmit Noise, Psophometric Weighted

A-law Selected (note 3)

0 dBm0 = 6.4dBm

-74 -67 dBm0p

NRC Receive Noise, C Message Weighted

µ-law Selected

PCM code is alternating positive and negative zero

811dBrnC0

NRP Receive Noise, Psophometric Weighted

A-law Selected

PCM Code Equals Positive Zero

-82 -79 dBm0p

NRS Noise, Single Frequency

f = 0Hz to 100kHz, Loop Around Measurement VFXI = 0Vrms -53 dBm0

PPSRX Positive Power Supply Rejection Transmit

VCC =5V

DC + 100mVrms

f = 0Hz to 4000Hz (note 4)

f = 4kHz to 50kHz 30

30 dBp

dBp

NPSRX Negative Power Supply Rejection Transmit

VSS = -5VDC + 100mVrms

f = 0Hz to 4000Hz (note 4)

f = 4kHz to 50kHz 30

30 dBp

dBp

PPSRR Positive Power Supply Rejection Receive

PCM Code Equals Positive Zero

VCC =5V

DC + 100mVrms

Measure VFR0

f = 0Hz to 4000Hz

f = 4kHz to 25kHz

f = 25kHz to 50kHz

dBp

NPSRR Negative Power Supply Rejection Receive

PCM Code Equals Positive Zero

VSS = -5VDC + 100mVrms

Measure VFR0

f = 0Hz to 4000Hz

f = 4kHz to 25kHz

f = 25kHz to 50kHz

dBp

SOS Spurious Out-of Band Signals at the Channel Output

0dBm0 300Hz to 3400Hz input PCM code applied at DR0(D

Relative tof = 1062.5Hz

4600Hz to 7600Hz

7600Hz to 8400Hz

8400Hz to 50000Hz

-30

-40

-30

TS5070 - TS5071

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DISTORTION

Symbol Parameter Min. Typ. Max. Unit

STDX Signal to Total Distortion Transmit

Sinusoidal Test Method

Half Channel

Level = 3dBm0

Level = -30dBm0 to 0dBm0

Level = -40dBm0

Level = -45dBm0

dBp

STDR Signal to Total Distortion Receive

Sinusoidal Test Method

Half Channel

Level = 3dBm0

Level = -30dBm0 to 0dBm0

Level = -40dBm0

Level = -45dBm0

dBp

SFDX Single Frequency Distortion Transmit -46 dB

SFDR Single Frequency Distortion Receive -46 dB

IMD Intermodulation Distortion Transmit or Receive

Two Frequencies in the Range 300Hz to 3400Hz -41 dB

CROSSTALK

Symbol Parameter Min. Typ. Max. Unit

CTX-R Transmit to Receive Crosstalk,

0dBm0 Transmit Level

f = 300 to 3400Hz

DR = IdlePCM Code

-90 -75 dB

CTR-X Receive to Transmit Crosstalk,

0dBm0 Receive Level

f = 300 to 3400Hz (note 4)

-90 -70 dB

Notes:

1. Applies only to MCLK frequencies ≥1.536 MHz. At 512 kHz A 50:50 ±2 % duty cycle must be used.

2. A multi-tone test technique is used (peak/rms ≤9.5 dB).

3. Measured by groundedinput at VFXI.

4. PPSRX, NPSRX and CTR-X are measured with a – 50 dBm0 activation signal applied to VFXI.

A signalis Valid if it is above VIH or below VIL and invalidif it is between VIL and VIH. For the purpose of thespecification the following conditions

apply :

a) All input signals are defined as VIL = 0.4 V, VIH = 2.7 V, tR< 10 ns, tF10ns

b) tRis measured from VIL to VIH,t

Fis measured from VIH to VIL

c) Delay Times are measured from the input signal Valid to the clock input invalid

d) Setup Times are measured from the data input Validto the clock input invalid

e) Hold Times are measured from the clock signal Valid tothe data input invalid

f) Pulse widths are measured from VIL toVIL or from VIH to VIH

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DEFINITIONSAND TIMINGCONVENTIONS

DEFINITIONS

VIH VIH is the D.C. input level above which an input level is guaranteed to appear as a logical one.

This parameter is to be measured by performing a functional test at reduced clock speeds and

nominal timing (i.e. not minimum setup and hold times or output strobes), with the high level of

all driving signals set to VIH and maximum supply voltages applied to the device.

VIL VIL is the D.C. input level below which an input level is guaranteed to appear as a logical zero

the device. This parameter is measured in the same manner as VIH but with all driving signal

low levels set to VIL and minimum supply voltage applied to the device.

VOH VOH is the minimmum D.C. output level to which an output placed in a logical one state will

converge when loaded at the maximum specified load current.

VOL VOL is the maximum D.C. output level to which an output placed in a logical zero state will

converge when loaded at the maximum specified load current.

Threshold Region

Valid Signal The threshold region is the range of input voltages between VIL and VIH.

A signal is Valid if it is in one of the valid logic states. (i.e. above VIH or below VIL). In timing

specifications, a signal is deemed validat the instantit enters a valid state.

Invalid signal A signal is invalid if it is not in a valid logic state, i.e., when it is in the threshold region between

VIL and VIH. In timing specifications, a signal is deemed Invalid at the instant it enters the

threshold region.

TIMING CONVENTIONS

For the purpose of this timing specifications the following conventions apply :

Input Signals All input signals may be characterized as : VL= 0.4 V, VH= 2.4 V, tR < 10 ns, tF < 10 ns.

Period The period of the clock signal is designated as tPxx where xx represents the mnemonic of the

clock signal being specified.

Rise Time Rise times are designated as tRyy, where yy represents a mnemonic of the signal whose rise

time is being specified, tRyy is measured from VIL to VIH.

Fall Time Fall times are designated as tFyy, where yy represents a mnemonic of the signal whose fall

time is being specified, tFyy is measured from VIH to VIL.

Pulse Width High The high pulse width is designated as tWzzH, where zz represents the mnemonic of the input

or output signal whose pulse width is being specified. High pulse width are measured from VIH

to VIH.

Pulse Width Low The low pulse is designated as tWzzL’ where zz represents the mnemonic of the input or output

signal whose pulse width is being specified. Low pulse width are measuredfrom VIL to VIL.

Setup Time Setup times are designated as tSwwxx where ww represents the mnemonic of the input signal

whose setup time is being specified relative to a clock or strobe input represented by mnemonic

xx. Setup times are measured from the ww Valid to xx Invalid.

Hold Time Hold times are designated as THwwxx where ww represents the mnemonic of the input signal

whose hold time is being specified relative to a clock or strobe input represented by the

mnemonic xx. Hold times aremeasured from xx Valid to ww Invalid

Delay Time Delay times are designated as TDxxyy [H/L], where xx represents the mnemonic of the input

reference signal and yy represents the mnemonic of the output signal whose timing is being

specified relative to xx. The mnemonic may optionally be terminated by an H or L to specify the

high going or low going transition of the output signal. Maximum delay times are measured from

xx Valid to yy Valid. Minimum delay times are measured from xx Valid to yy Invalid. This

parameter is tested under the load conditions specified in the Conditions column of the Timing

Specifications section of this datasheet.

TS5070 - TS5071

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COMBO II SALES TYPE LIST

Ordering

Number Electrical

description Package Marking Packing

TS5070FN Stdandard

Selection

Datasheet

December

1997

PLCC28 TS5070FN Tubes

TS5070FNTR PLCC28 TS5070FN Tape

and reel

TS5071N PDIP20 TS5071N Tubes

TSW5070FN Relaxed

selection

(Gxa, Gra,

Grag, Gxag)

PLCC28 TS5070FN Tubes Param Page Conditions Min Max Unit

TSW5070FNTR PLCC28 TS5070FN Tape

and reel Gxa 22 -- -0.2 0.2 dB

TSW5071N PDIP20 TS5071N Tubes Gxag 22 -6.3dBm<0dbm0<6.4dBm -0.1 0.1 dB

-12.7dBm<0dBm0<-6.4dBm -0.2 0.2 dB

-19dBm<0dBm0<-12.8dBm -0.5 0.5 dB

Gra 23 -- -0.2 0.2 dB

Grag 23 -4.6dBm<0dBm0<8.1dBm -0.1 0.1 dB

-11dBm<0dBm0<-4.7dBm -0.2 0.2 dB

-17.3dBm<0dBm0<-11.1dBm -0.5 0.5 dB

TSP5070FN Special

selection

for

Grag/Gxag

PLCC28 TS5070FN Tubes Param Page Conditions Min Max Unit

TSP5070FNTR PLCC28 TS5070FN Tape

and reel Gxag 22 all programmed gains -0.1 0.1 dB

TSP5071N PDIP20 TS5071N Tubes Grag 23 all programmed gains -0.1 0.1 dB

TS5070 - TS5071

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PLCC28 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 12.32 12.57 0.485 0.495

B 11.43 11.58 0.450 0.456

D 4.2 4.57 0.165 0.180

D1 2.29 3.04 0.090 0.120

D2 0.51 0.020

E 9.91 10.92 0.390 0.430

e 1.27 0.050

e3 7.62 0.300

F 0.46 0.018

F1 0.71 0.028

G 0.101 0.004

M 1.24 0.049

M1 1.143 0.045

TS5070 - TS5071

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DIP20 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.254 0.010

B 1.39 1.65 0.055 0.065

b 0.45 0.018

b1 0.25 0.010

D 25.4 1.000

E 8.5 0.335

e 2.54 0.100

e3 22.86 0.900

F 7.1 0.280

I 3.93 0.155

L 3.3 0.130

Z 1.34 0.053

TS5070 - TS5071

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Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No

license is granted by implicationor otherwise under any patent or patentrights of SGS-THOMSON Microelectronics. Specification mentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-

THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express

written approval of SGS-THOMSON Microelectronics.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada- China - France- Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands-

Singapore - Spain - Sweden - Switzerland- Taiwan - Thailand - United Kingdom - U.S.A.

TS5070 - TS5071

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