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LM2660
SNVS135E –SEPTEMBER 1999–REVISED DECEMBER 2014
LM2660 Switched Capacitor Voltage Converter
1 Features 3 Description
The LM2660 CMOS charge-pump voltage converter
1• Inverts or Doubles Input Supply Voltage is a versatile unregulated switched capacitor inverter
• Narrow SOIC and VSSOP Packages or doubler. Operating from a wide 1.5-V to 5.5-V
• 6.5-ΩTypical Output Resistance supply voltage, the LM2660 uses two low-cost
capacitors to provide 100 mA of output current
• 88% Typical Conversion Efficiency at 100 mA without the cost, size and EMI related to inductor-
• Selectable Oscillator Frequency: 10 kHz/80 kHz based converters. With an operating current of only
• Optional External Oscillator Input 120 µA and operating efficiency greater than 90% at
most loads, the LM2660 provides ideal performance
2 Applications for battery-powered systems. LM2660 devices can be
operated directly in parallel to lower output
• Laptop Computers impedance, thus providing more current at a given
• Cellular Phones voltage.
• Medical Instruments The FC (frequency control) pin selects between a
• Operational Amplifier Power Supplies nominal 10-kHz or 80-kHz oscillator frequency. The
• Interface Power Supplies oscillator frequency can be lowered by adding an
external capacitor to the OSC pin. Also, the OSC pin
• Handheld Instruments may be used to drive the LM2660 with an external
space clock up to 150 kHz. Through these methods, output
space ripple frequency and harmonics may be controlled.
space Additionally, the LM2660 may be configured to divide
space a positive input voltage precisely in half. In this mode,
input voltages as high as 11 V may be used.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SOIC (8) 4.90 mm x 3.91 mm
LM2660 VSSOP (8) 3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM2660
SNVS135E –SEPTEMBER 1999–REVISED DECEMBER 2014
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Table of Contents
8.2 Functional Block Diagram......................................... 9
1 Features.................................................................. 18.3 Feature Description................................................... 9
2 Applications ........................................................... 18.4 Device Functional Modes........................................ 10
3 Description............................................................. 19 Application and Implementation ........................ 11
4 Revision History..................................................... 29.1 Application Information............................................ 11
5 Pin Configuration and Functions......................... 39.2 Typical Applications ............................................... 11
6 Specifications......................................................... 410 Power Supply Recommendations ..................... 16
6.1 Absolute Maximum Ratings ...................................... 411 Layout................................................................... 17
6.2 Handling Ratings....................................................... 411.1 Layout Guidelines ................................................. 17
6.3 Recommended Operating Conditions....................... 411.2 Layout Example .................................................... 17
6.4 Thermal Information.................................................. 412 Device and Documentation Support................. 18
6.5 Electrical Characteristics........................................... 512.1 Device Support .................................................... 18
6.6 Typical Characteristics.............................................. 612.2 Trademarks........................................................... 18
7 Parameter Measurement Information .................. 812.3 Electrostatic Discharge Caution............................ 18
7.1 Test Circuits.............................................................. 812.4 Glossary................................................................ 18
8 Detailed Description.............................................. 913 Mechanical, Packaging, and Orderable
8.1 Overview................................................................... 9Information........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2013) to Revision E Page
• Added Device Information and Handling Rating tables, Feature Description,Device Functional Modes,Application
and Implementation,Power Supply Recommendations,Layout,Device and Documentation Support, and
Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section ............. 1
Changes from Revision C (May 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 15
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5 Pin Configuration and Functions
SOIC (D) and VSSOP (DGK)
8 Pins
Top View
Pin Functions
PIN DESCRIPTION
TYPE
NUMBER NAME VOLTAGE INVERTER VOLTAGE DOUBLER
Frequency control for internal oscillator:
FC = open, fOSC = 10 kHz (typ);
1 FC Input Same as inverter.
FC = V+, fOSC = 80 kHz (typ);
FC has no effect when OSC pin is driven
externally.
Connect this pin to the positive terminal of charge-
2 CAP+ Power Same as inverter.
pump capacitor.
3 GND Ground Power supply ground input. Power supply positive voltage input.
Connect this pin to the negative terminal of
4 CAP−Power Same as inverter.
charge-pump capacitor.
5 OUT Power Negative voltage output. Power supply ground input.
Low-voltage operation input. Tie LV to GND when
input voltage is less than 3.5 V. Above 3.5 V, LV
6 LV Input can be connected to GND or left open. When LV must be tied to OUT.
driving OSC with an external clock, LV must be
connected to GND.
Oscillator control input. OSC is connected to an
internal 15-pF capacitor. An external capacitor can Same as inverter except that OSC cannot be
7 OSC Input be connected to slow the oscillator. Also, an driven by an external clock.
external clock can be used to drive OSC.
8 V+ Power Power supply positive voltage input. Positive voltage output.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage (V+ to GND, or GND to OUT) 6 V
LV (OUT −0.3 V) to (GND + V
3 V)
FC, OSC The least negative of V
(OUT −0.3 V)
or (V+ −6 V) to (V+ + 0.3
V)
V+ and OUT continuous output current 120 mA
Output short-circuit duration to GND (2) 1 second
Power dissipation SOIC (D)(3) 735 mW
Power dissipation VSSOP (DGK)(3) 500 mW
Lead temperature (soldering, 10 seconds) 300 °C
Operating junction temperature –40 85 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) OUT may be shorted to GND for one second without damage. However, shorting OUT to V+ may damage the device and should be
avoided. Also, for temperatures above 85°C, OUT must not be shorted to GND or V+, or device may be damaged.
(3) The maximum allowable power dissipation is calculated by using PDMax = (TJMax −TA)/RθJA, where TJMax is the maximum junction
temperature, TAis the ambient temperature, and RθJA is the junction-to-ambient thermal resistance of the specified package.
6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 2000
V(ESD) V
discharge
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
V+ (supply voltage) Inverter, LV = Open 3.5 5.5
Inverter, LV = GND 1.5 5.5
Doubler, LV = OUT 2.5 5.5
Junction temperature (TJ) –40 85 °C
6.4 Thermal Information LM2660
THERMAL METRIC(1) SOIC (D) VSSOP (DGK) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 170 250 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Limits in for typical (TYP) values are for TJ= 25°C, and limits in for minimum (MIN) and maximum (MAX) values apply over
the full operating temperature range; V+ = 5V, FC = Open, C1= C2= 150 μF, unless otherwise specified in the Test
Conditions.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Inverter, LV = Open 3.5 5.5
V+ Supply voltage RL= 1k Inverter, LV = GND 1.5 5.5 V
Doubler, LV = OUT 2.5 5.5
No Load FC = Open 0.12 0.5
IQSupply current mA
LV = Open FC = V+ 1 3
TA≤85°C, OUT ≤ −4 V 100
ILOutput current mA
TA> 85°C, OUT ≤ −3.8 V 100
TA≤85°C 6.5 10
ROUT Output resistance(2) IL= 100 mA Ω
TA> 85°C 12
FC = Open 5 10
fOSC Oscillator frequency OSC = Open kHz
FC = V+ 40 80
FC = Open 2.5 5
fSW Switching frequency(3) OSC = Open kHz
FC = V+ 20 40
FC = Open ±2
IOSC OSC input current µA
FC = V+ ±16
RL(1k) between V+and OUT 96% 98%
PEFF Power efficiency RL(500) between GND and OUT 92% 96%
IL= 100 mA to GND 88%
VOEFF Voltage conversion efficiency No Load 99% 99.96%
(1) In the test circuit, capacitors C1and C2are 0.2-Ωmaximum ESR capacitors. Capacitors with higher ESR will increase output resistance,
reduce output voltage and efficiency.
(2) Specified output resistance includes internal switch resistance and capacitor ESR.
(3) The output switches operate at one half of the oscillator frequency, fOSC = 2fSW.
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6.6 Typical Characteristics
(Circuit of Figure 12)
Figure 2. Supply Current vs Oscillator Frequency
Figure 1. Supply Current vs Supply Voltage
Figure 3. Output Source Resistance vs Supply Voltage Figure 4. Output Source Resistance vs Temperature
Figure 6. Output Voltage vs Oscillator Frequency
Figure 5. Output Voltage Drop vs Load Current
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Typical Characteristics (continued)
(Circuit of Figure 12)
Figure 8. Oscillator Frequency vs Supply Voltage
Figure 7. Oscillator Frequency vs External Capacitance (Fc = V+)
Figure 9. Oscillator Frequency vs Supply Voltage Figure 10. Oscillator Frequency vs Temperature
(Fc = Open) (Fc = V+)
Figure 11. Oscillator Frequency vs Temperature
(Fc = Open)
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FC
OSC
LM2660
LV
V+
CAP+
OUT
GND
OSCILLATOR Switch Array
Switch Drivers CAP-
LM2660
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8 Detailed Description
8.1 Overview
The LM2660 contains four large CMOS switches which are switched in a sequence to invert the input supply
voltage. Energy transfer and storage are provided by external capacitors. Figure 13 illustrates the voltage
conversion scheme. When S1and S3are closed, C1charges to the supply voltage V+. During this time interval
switches S2and S4are open. In the second time interval, S1and S3are open and S2and S4are closed, C1is
charging C2. After a number of cycles, the voltage across C2will be pumped to V+. Since the anode of C2is
connected to ground, the output at the cathode of C2equals −(V+) assuming no load on C2, no loss in the
switches, and no ESR in the capacitors. In reality, the charge transfer efficiency depends on the switching
frequency, the on-resistance of the switches, and the ESR of the capacitors.
Figure 13. Voltage Inverting Principle
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Changing Oscillator Frequency
The internal oscillator frequency can be selected using the Frequency Control (FC) pin. When FC is open, the
oscillator frequency is 10 kHz; when FC is connected to V+, the frequency increases to 80 kHz. A higher
oscillator frequency allows smaller capacitors to be used for equivalent output resistance and ripple, but
increases the typical supply current from 0.12 mA to 1 mA.
The oscillator frequency can be lowered by adding an external capacitor between OSC and GND. (See Typical
Characteristics.) Also, in the inverter mode, an external clock that swings within 100 mV of V+ and GND can be
used to drive OSC. Any CMOS logic gate is suitable for driving OSC. LV must be grounded when driving OSC.
The maximum external clock frequency is limited to 150 kHz.
The switching frequency of the converter (also called the charge pump frequency) is half of the oscillator
frequency.
NOTE
OSC cannot be driven by an external clock in the voltage-doubling mode.
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Feature Description (continued)
Table 1. LM2660 Oscillator Frequency Selection
FC OSC OSCILLATOR
Open Open 10 kHz
V+ Open 80 kHz
Open or V+ External Capacitor See Typical Characteristics
N/A External Clock External Clock
(inverter mode only) Frequency
8.4 Device Functional Modes
When V+ is applied to the LM2660, the device becomes enabled and will operate in which ever configuration the
device is placed (inverter, doubler, etc.).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LM2660 CMOS charge-pump voltage converter is a versatile unregulated switched capacitor inverter or
doubler. Operating from a wide 1.5 V to 5.5 V supply voltage, the LM2660 uses two low-cost capacitors to
provide 100 mA of output current without the cost, size and EMI related to inductor-based converters. With an
operating current of only 120 µA and operating efficiency greater than 90% at most loads, the LM2660 provides
ideal performance for battery-powered systems. LM2660 devices can be operated directly in parallel to lower
output impedance, thus providing more current at a given voltage.
9.2 Typical Applications
9.2.1 Voltage Inverter
Figure 14. LM2660 Voltage Inverter
9.2.1.1 Design Requirements
The main application of LM2660 is to generate a negative supply voltage. The voltage inverter circuit uses only
two external capacitors as shown in the Figure 14. The range of the input supply voltage is 1.5 V to 5.5 V. For a
supply voltage less than 3.5V, the LV pin must be connected to ground to bypass the internal regulator circuitry.
This gives the best performance in low voltage applications. If the supply voltage is greater than 3.5 V, LV may
be connected to ground or left open. The choice of leaving LV open simplifies the direct substitution of the
LM2660 for the LMC7660 Switched Capacitor Voltage Converter.
9.2.1.2 Detailed Design Procedure
The output characteristics of this circuit can be approximated by an ideal voltage source in series with a resistor.
The voltage source equals −(V+). The output resistance Rout is a function of the ON resistance of the internal
MOS switches, the oscillator frequency, and the capacitance and ESR of C1and C2. A good approximation is:
where
• RSW is the sum of the ON resistance of the internal MOS switches shown in Figure 13. (1)
High value, low ESR capacitors will reduce the output resistance. Instead of increasing the capacitance, the
oscillator frequency can be increased to reduce the 2/(fosc × C1) term. Once this term is trivial compared with RSW
and ESRs, further increasing in oscillator frequency and capacitance will become ineffective.
The peak-to-peak output voltage ripple is determined by the oscillator frequency, and the capacitance and ESR
of the output capacitor C2:
(2)
Again, using a low ESR capacitor will result in lower ripple.
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Typical Applications (continued)
9.2.1.2.1 Capacitor Selection
The output resistance and ripple voltage are dependent on the capacitance and ESR values of the external
capacitors. The output voltage drop is the load current times the output resistance, and the power efficiency is
where
• IQ(V+) is the quiescent power loss of the IC device, and
• IL2ROUT is the conversion loss associated with the switch on-resistance, the two external capacitors and their
ESRs. (3)
Since the switching current charging and discharging C1is approximately twice as the output current, the effect
of the ESR of the pumping capacitor C1is multiplied by four in the output resistance. The output capacitor C2is
charging and discharging at a current approximately equal to the output current, therefore, its ESR only counts
once in the output resistance. However, the ESR of C2directly affects the output voltage ripple. Therefore, low
ESR capacitors (Table 2) are recommended for both capacitors to maximize efficiency, reduce the output voltage
drop and voltage ripple. For convenience, C1and C2are usually chosen to be the same.
The output resistance varies with the oscillator frequency and the capacitors. In Figure 15, the output resistance
vs. oscillator frequency curves are drawn for three different tantalum capacitors. At very low frequency range,
capacitance plays the most important role in determining the output resistance. Once the frequency is increased
to some point (such as 20 kHz for the 150 μF capacitors), the output resistance is dominated by the ON
resistance of the internal switches and the ESRs of the external capacitors. A low value, smaller size capacitor
usually has a higher ESR compared with a bigger size capacitor of the same type. For lower ESR, use ceramic
capacitors.
Figure 15. Output Source Resistance vs Oscillator Frequency
Table 2. Low ESR Capacitor Manufacturers
MANUFACTURER CAPACITOR TYPE
Nichicon Corp. PL, PF series, through-hole aluminum electrolytic
AVX Corp. TPS series, surface-mount tantalum
Sprague 593D, 594D, 595D series, surface-mount tantalum
Sanyo OS-CON series, through-hole aluminum electrolytic
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Rout =
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9.2.1.2.2 Paralleling Devices
Any number of LM2660s can be paralleled to reduce the output resistance. Each device must have its own
pumping capacitor C1, while only one output capacitor Cout is needed as shown in Figure 16. The composite
output resistance is:
(4)
Figure 16. Lowering Output Resistance By Paralleling Devices
9.2.1.2.3 Cascading Devices
Cascading the LM2660s is an easy way to produce a greater negative voltage (as shown in Figure 17). If n is the
integer representing the number of devices cascaded, the unloaded output voltage Vout is (−nVin). The effective
output resistance is equal to the weighted sum of each individual device:
(5)
A three-stage cascade circuit shown in Figure 18 generates −3 Vin, from Vin.
Cascading is also possible when devices are operating in doubling mode. In Figure 19, two devices are
cascaded to generate 3 Vin.
An example of using the circuit in Figure 18 or Figure 19 is generating +15 V or −15 V from a +5 V input.
Note that, the number of n is practically limited since the increasing of n significantly reduces the efficiency and
increases the output resistance and output voltage ripple.
Figure 17. Increasing Output Voltage by Cascading Devices
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Figure 18. Generating −3VIN from +VIN
Figure 19. Generating +3VIN from +VIN
9.2.1.2.4 Regulating VOUT
It is possible to regulate the output of the LM2660 by use of a low dropout regulator (such as LP2951). The
whole converter is depicted in Figure 20. This converter can give a regulated output from −1.5 V to −5.5 V by
choosing the proper resistor ratio:
where
• Vref = 1.235 V (6)
The error flag on pin 5 of the LP2951 goes low when the regulated output at pin 4 drops by about 5%. The
LP2951 can be shutdown by taking pin 3 high.
Figure 20. Combining LM2660 With LP2951 to Make a Negative Adjustable Regulator
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Also, as shown in Figure 21 by operating LM2660 in voltage doubling mode and adding a linear regulator (such
as LP2981) at the output, we can get +5 V output from an input as low as +3 V.
Figure 21. Generating +5 V from +3 V Input Voltage
9.2.1.3 Application Curves
Figure 22. Efficiency vs Load Current Figure 23. Efficiency vs Oscillator Frequency
9.2.2 Positive Voltage Doubler
Figure 24. LM2660 Voltage Doubler
9.2.2.1 Design Requirements
The LM2660 can operate as a positive voltage doubler (as shown in the Figure 24). The doubling function is
achieved by reversing some of the connections to the device. The input voltage is applied to the GND pin with an
allowable voltage from 2.5 V to 5.5 V. The V+ pin is used as the output. The LV pin and OUT pin must be
connected to ground. The OSC pin can not be driven by an external clock in this operation mode. The unloaded
output voltage is twice of the input voltage and is not reduced by the diode D1's forward drop.
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9.2.2.2 Detailed Design Procedure
The Schottky diode D1is only needed for start-up. The internal oscillator circuit uses the V+ pin and the LV
pin (connected to ground in the voltage doubler circuit) as its power rails. Voltage across V+ and LV must be
larger than 1.5 V to insure the operation of the oscillator. During start-up, D1is used to charge up the voltage
at V+ pin to start the oscillator; also, it protects the device from turning-on its own parasitic diode and
potentially latching-up. Therefore, the Schottky diode D1should have enough current carrying capability to
charge the output capacitor at start-up, as well as a low forward voltage to prevent the internal parasitic
diode from turning-on. A Schottky diode like 1N5817 can be used for most applications. If the input voltage
ramp is less than 10V/ms, a smaller Schottky diode like MBR0520LT1 can be used to reduce the circuit size.
9.2.2.3 Application Curves
See Application Curves in the Voltage Inverter section.
10 Power Supply Recommendations
The LM2660 is designed to operate from as an inverter over an input voltage supply range between 1.5 V and
5.5 V when the LV pin is grounded. This input supply must be well regulated and capable to supply the required
input current. If the input supply is located far from the LM2660 additional bulk capacitance may be required in
addition to the ceramic bypass capacitors.
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FC
CAP+
LM2660
GND
CAP-
V+
OSC
LV
OUT
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11 Layout
11.1 Layout Guidelines
The high switching frequency and large switching currents of the LM2660 make the choice of layout important.
The following steps should be used as a reference to ensure the device is stable and maintains proper LED
current regulation across its intended operating voltage and current range:
• Place CIN on the top layer (same layer as the LM2660) and as close to the device as possible. Connecting
the input capacitor through short, wide traces to both the V+ and GND pins reduces the inductive voltage
spikes that occur during switching which can corrupt the V+ line.
• Place COUT on the top layer (same layer as the LM2660) and as close as possible to the OUT and GND pin.
The returns for both CIN and COUT should come together at one point, as close to the GND pin as possible.
Connecting COUT through short, wide traces reduce the series inductance on the OUT and GND pins that can
corrupt the VOUT and GND lines and cause excessive noise in the device and surrounding circuitry.
• Place C1on the top layer (same layer as the LM2660) and as close to the device as possible. Connect the
flying capacitor through short, wide traces to both the CAP+ and CAP– pins.
11.2 Layout Example
Figure 25. LM2660 Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM2660-MWC ACTIVE WAFERSALE YS 0 1 RoHS & Green Call TI Level-1-NA-UNLIM -40 to 85
LM2660M NRND SOIC D 8 95 Non-RoHS &
Non-Green Call TI Call TI -40 to 85 LM26
60M
LM2660M/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LM26
60M
LM2660MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 S01A
LM2660MX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LM26
60M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM2660MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM2660MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM2660MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM2660MX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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