Semiconductor Components Industries, LLC, 2003
April, 2003 - Rev. 1 1Publication Order Number:
NTD3055-150/D
NTD3055−150
Power MOSFET
9.0 Amps, 60 Volts
N-Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Typical Applications
•Power Supplies
•Converters
•Power Motor Controls
•Bridge Circuits
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain-to-Source Voltage VDSS 60 Vdc
Drain-to-Gate Voltage (RGS = 10 M) VDGR 60 Vdc
Gate-to-Source Voltage
- Continuous
- Non-repetitive (tp10 ms) VGS
VGS 20
30
Vdc
Drain Current
- Continuous @ TA = 25°C
- Continuous @ TA = 100°C
- Single Pulse (tp10 s)
ID
ID
IDM
9.0
3.0
27
Adc
Apk
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
PD28.8
0.19
2.1
1.5
W
W/°C
W
W
Operating and Storage Temperature Range TJ, Tstg - 55 to
175 °C
Single Pulse Drain-to-Source Avalanche
Energy - Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc,
L = 1.0 mH, IL(pk) = 7.75 A, VDS = 60 Vdc)
EAS 30 mJ
Thermal Resistance
- Junction-to-Case
- Junction-to-Ambient (Note 1)
- Junction-to-Ambient (Note 2)
RJC
RJA
RJA
5.2
71.4
100
°C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds TL260 °C
1. When surface mounted to an FR4 board using 0.5 sq. in pad size.
2. When surface mounted to an FR4 board using minimum recommended
pad size.
2500/Tape & Reel
9.0 AMPERES
60 VOLTS
RDS(on) = 122 m (Typ)
Device Package Shipping
ORDERING INFORMATION
NTD3055-150 DPAK 75 Units/Rail
http://onsemi.com
N-Channel
D
S
G
NTD3055-150-1 DPAK
Straight Lead 75 Units/Rail
NTD3055-150T4 DPAK
1
Gate 3
Source
2
Drain
4
Drain
DPAK
CASE 369C
(Surface Mount)
Style 2
MARKING DIAGRAMS
3150 Device Code
Y = Year
WW = Work Week
YWW
3150
123
4
YWW
3150
1
Gate 3
Source
2
Drain
4
Drain
DPAK
CASE 369D
(Straight Lead)
Style 2
123
4
NTD3055-150
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)
V(BR)DSS 60
--
70.2 -
-
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS -
--
-1.0
10
Adc
Gate-Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS - - ±100 nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)
VGS(th) 2.0
-3.0
6.4 4.0
-
Vdc
mV/°C
Static Drain-to-Source On-Resistance (Note 3)
(VGS = 10 Vdc, ID = 4.5 Adc) RDS(on) - 122 150 m
Static Drain-to-Source On-Voltage (Note 3)
(VGS = 10 Vdc, ID = 9.0 Adc)
(VGS = 10 Vdc, ID = 4.5 Adc, TJ = 150°C)
VDS(on) -
-1.4
1.1 1.9
-
Vdc
Forward Transconductance (Note 3) (VDS = 7.0 Vdc, ID = 6.0 Adc) gFS - 5.4 - mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss - 200 280 pF
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz
)
Coss - 70 100
Transfer Capacitance
f
=
1
.
0
MHz)
Crss - 26 40
SWITCHING CHARACTERISTICS (Note 4)
Turn-On Delay Time td(on) - 11.2 25 ns
Rise Time (VDD = 48 Vdc, ID = 9.0 Adc,
VGS =10Vdc
tr- 37.1 80
Turn-Off Delay Time VGS = 10 Vdc,
RG = 9.1 ) (Note 3) td(off) - 12.2 25
Fall Time
G)( )
tf- 23 50
Gate Charge QT- 7.1 15 nC
(VDS = 48 Vdc, ID = 9.0 Adc,
V
GS
= 10 Vdc
)
(
Note 3
)
Q1- 1.7 -
VGS
=
10
Vdc)
(Note
3)
Q2- 3.5 -
SOURCE-DRAIN DIODE CHARACTERISTICS
Forward On-Voltage (IS = 9.0 Adc, VGS = 0 Vdc) (Note 3)
(IS = 19 Adc, VGS = 0 Vdc, TJ = 150°C) VSD -
-0.98
0.86 1.20
-Vdc
Reverse Recovery Time trr - 28.9 - ns
(IS = 9.0 Adc, VGS = 0 Vdc,
dI
S
/dt = 100 A/
s
)
(
Note 3
)
ta- 21.6 -
dIS/dt
=
100
A/s)
(Note
3)
tb- 7.3 -
Reverse Recovery Stored Charge QRR - 0.036 - C
3. Pulse Test: Pulse Width ≤300 s, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
NTD3055-150
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3
TJ = -55°C
TJ = 100°C
0.6
10
1
100
1000
12
8
16
4
0
20
0
12
231
ID, DRAIN CURRENT (AMPS)
0
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics
ID, DRAIN CURRENT (AMPS)
0
0.1
8
04121624
Figure 3. On-Resistance versus
Gate-To-Source Voltage
ID, DRAIN CURRENT (AMPS)
Figure 4. On-Resistance versus Drain Current
and Gate Voltage
ID, DRAIN CURRENT (AMPS)
RDS(on), DRAIN-TO-SOURCE RESISTANCE ()
Figure 5. On-Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Drain-To-Source Leakage
Current versus Voltage
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
IDSS, LEAKAGE (nA)
20
-50 100750-25 125 175
34 7
040302010 60
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
4
8
16
8
VGS = 0 V
TJ = 150°C
TJ = 100°C
ID = 4.5 A
VGS = 10 V
VGS = 10 V
VDS ≥ 10 V
TJ = 25°C
VGS = 10 V
RDS(on), DRAIN-TO-SOURCE RESISTANCE ()
RDS(on), DRAIN-TO-SOURCE RESISTANCE
(NORMALIZED)
VGS = 9 V VGS = 7 V
5025
56
4675
VGS = 8 V
VGS = 6 V
VGS = 5 V
98
20
0.2
0.3
0.4
0.5
TJ = -55°C
TJ = 100°C
TJ = 25°C
0
0.1
84121624
VGS = 15 V
20
0.2
0.3
0.4
0.5
TJ = -55°C
TJ = 100°C
TJ = 25°C
150
0.8
1
1.2
1.4
1.6
1.8
2
2.2
50
TJ = 125°C
0
NTD3055-150
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4
VGS VDS
4
10
6
0
12
4
10
320
20100
C, CAPACITANCE (pF)
0
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation Figure 8. Gate-to-Source and
Drain-to-Source Voltage versus Total Charge
VGS, GATE-TO-SOURCE VOLTAGE (V)
1
100
10 10 100
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
RG, GATE RESISTANCE ()
Figure 10. Diode Forward Voltage versus
Current
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
IS, SOURCE CURRENT (AMPS)
t, TIME (ns)
560
01 6
0.6 0.920.840.760.68 1
6
2
0
8
10
GATE-T O-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V)
160
240
400
25
2ID = 9 A
TJ = 25°C
Q2
Q1VGS
QT
VDS = 30 V
ID = 9 A
VGS = 10 V
tr
td(off)
td(on)
tf
VGS = 0 V
TJ = 25°C
VGS = 0 VVDS = 0 V TJ = 25°C
Crss
Ciss
Coss
Crss
Ciss
2345
80
480
1555 78
8
16
0.1
100
10 100
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
TJ, STARTING JUNCTION TEMPERATURE (°C)
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
ID, DRAIN CURRENT (AMPS)
25 1251007550
24
8
0
32
VGS = 20 V
SINGLE PULSE
TC = 25°CID = 7.75 A
175150
1
10
1
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10 ms
10 s
1 ms
dc
100 s
NTD3055-150
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5
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
Figure 13. Thermal Response
t, TIME (s)
10
1
0.00001 0.001 0.01 0.1 100.0001 1
0.1
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
D = 0.5
0.2
0.1
SINGLE PULSE
0.05
0.01
NTD3055-150
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6
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
5.80
0.228
2.58
0.101
1.6
0.063
6.20
0.244
3.0
0.118
6.172
0.243
mm
inches
SCALE 3:1
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a
surface mount device is determined by TJ(max), the
maximum rated junction temperature of the die, RJA, the
thermal resistance from the device junction to ambient, and
the operating temperature, TA. Using the values provided
on the data sheet, PD can be calculated as follows:
PD = TJ(max) - TA
RJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device. For a
DPAK device, PD is calculated as follows.
PD = 175°C - 25°C
71.4°C/W = 2.1 Watts
The 71.4°C/W for the DPAK package assumes the use of
0.5 sq. in. source pad on a glass epoxy printed circuit board
to achieve a power dissipation of 2.1 W. There are other
alternatives to achieving higher power dissipation from the
surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
almost double the power dissipation with this method, one
will be giving up area on the printed circuit board which
can defeat the purpose of using surface mount technology.
For example, a graph of RJA versus drain pad area is shown
in Figure 14.
Figure 14. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
2.1 Watts
Board Material = 0.0625″
G−10/FR−4, 2 oz Copper
80
100
60
40
20 1086420
3.6 Watts
6.0 Watts
TA = 25°C
A, AREA (SQUARE INCHES)
TO AMBIENT ( C/W)°
RJA, THERMAL RESISTANCE, JUNCTION
θ
NTD3055-150
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7
PACKAGE DIMENSIONS
DPAK
CASE 369C-01
ISSUE O
D
A
K
B
R
V
S
FL
G
2 PL
M
0.13 (0.005) T
E
C
U
J
H
-T- SEATING
PLANE
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.235 0.245 5.97 6.22
B0.250 0.265 6.35 6.73
C0.086 0.094 2.19 2.38
D0.027 0.035 0.69 0.88
E0.018 0.023 0.46 0.58
F0.037 0.045 0.94 1.14
G0.180 BSC 4.58 BSC
H0.034 0.040 0.87 1.01
J0.018 0.023 0.46 0.58
K0.102 0.114 2.60 2.89
L0.090 BSC 2.29 BSC
R0.180 0.215 4.57 5.45
S0.025 0.040 0.63 1.01
U0.020 --- 0.51 ---
V0.035 0.050 0.89 1.27
Z0.155 --- 3.93 ---
123
4
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
DPAK
CASE 369D-01
ISSUE O
123
4
V
SA
K
-T-
SEATING
PLANE
R
B
F
GD3 PL
M
0.13 (0.005) T
C
E
JH
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.235 0.245 5.97 6.35
B0.250 0.265 6.35 6.73
C0.086 0.094 2.19 2.38
D0.027 0.035 0.69 0.88
E0.018 0.023 0.46 0.58
F0.037 0.045 0.94 1.14
G0.090 BSC 2.29 BSC
H0.034 0.040 0.87 1.01
J0.018 0.023 0.46 0.58
K0.350 0.380 8.89 9.65
R0.180 0.215 4.45 5.45
S0.025 0.040 0.63 1.01
V0.035 0.050 0.89 1.27
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
Z
Z0.155 --- 3.93 ---
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
NTD3055-150
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8
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NTD3055-150/D
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