EZ-PD™ CCG2 Datasheet
USB Type-C Port Controller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-93912 Rev. *M Revised July 11, 2018
USB Type-C Port Controller
General Description
EZ-PD™ CCG2 is a USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG2 provides a
complete USB Type-C and U1SB Power Delivery port control solution for passive cables, active cables, and powered accessories. It
can also be used in many upstream and downstream facing port applications. EZ-PD CCG2 uses Cypress’s proprietary M0S8
technology with a 32-bit, 48-MHz Arm® Cortex®-M0 processor with 32-KB flash and integrates a complete Type-C Transceiver
including the Type-C termination resistors RP, RD and RA.
Applications
■USB Type-C EMCA cables
■USB Type-C powered accessories
■USB Type-C upstream facing ports
■USB Type-C downstream facing ports
Features
32-bit MCU Subsystem
■48-MHz ARM Cortex-M0 CPU
■32-KB Flash
■4-KB SRAM
■In-system reprogrammable
Integrated Digital Blocks
■Integrated timers and counters to meet response times
required by the USB-PD protocol
■Run-time reconfigurable serial communication block (SCB)
with reconfigurable I2C, SPI, or UART functionality
Clocks and Oscillators
■Integrated oscillator eliminating the need for external clock
Type-C Support
■Integrated transceiver (baseband PHY)
■Integrated UFP (RD), EMCA (RA) termination resistors, and
current sources for DFP (RP)
■Supports one USB Type-C port
Low-Power Operation
■2.7-V to 5.5-V operation
■Two independent VCONN rails with integrated isolation
between the two
■Independent supply voltage pin for GPIO that allows 1.71-V to
5.5-V signaling on the I/Os
■Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.0 mA
System-Level ESD on CC and VCONN Pins
■± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
on IEC61000-4-2 level 4C
Packages
■1.63 mm × 2.03 mm, 20-ball wafer-level CSP (WLCSP) with
0.4-mm ball pitch
■2.5 mm × 3.5 mm × 0.6 mm 14-pin DFN
■4.0 mm × 4.0 mm, 0.55 mm 24-pin QFN
■Supports industrial (40 °C to +85 °C) and extended industrial
(40 °C to +105 °C) temperature ranges
Logic Block Diagram
Flash
(32 KB)
SRAM
(4 KB)
Serial Wire Debug
Programmable IO Matrix
CCG2: USB Type-C Cable Controller
CORTEX-M0
48 MHz
Integrated Digital Blocks I/O Subsystem
MCU Subsystem
Advanced High-Performance Bus (AHB)
CC5
GPIO6
Port
1 Timer, counter, pulse-width modulation block
2Serial communication block configurable as UART, SPI, or I2C
3Termination resistor denoting a UFP
4 Termination resistor denoting an EMCA
5 Configuration Channel
6 General-purpose input/output
7 Current Sources to indicate a DFP
Profiles and
Configurations
Baseband MAC
Baseband PHY
SCB2
(I2C, SPI, UART)
Integrated Rd3, Ra4,
and Rp7
VCONN1
VCONN2
VDDIO
TCPWM1
SCB2
(I2C, SPI, UART)
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 2 of 36
Available Firmware and Software Tools
EZ-PD Configuration Utility
The EZ-PD Configuration Utility is a GUI-based Microsoft Windows application developed by Cypress to guide a CCGx user through
the process of configuring and programming the chip. The utility allows users to:
1. Select and configure the parameters they want to modify
2. Program the resulting configuration onto the target CCGx device.
The utility works with the Cypress supplied CCG1, CCG2, CCG3, and CCG4 kits, which host the CCGx controllers along with a USB
interface. This version of the EZ-PD Configuration Utility supports configuration and firmware update operations on CCGx controllers
implementing EMCA and Display Dongle applications. Support for other applications, such as Power Adapters and Notebook port
controllers, will be provided in later versions of the utility.
You can download the EZ-PD Configuration Utility and its associated documentation at the following link:
http://www.cypress.com/documentation/software-and-drivers/ez-pd-configuration-utility
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 3 of 36
Contents
Functional Overview .........................................................4
CPU and Memory Subsystem .....................................4
USB-PD Subsystem (SS) ............................................5
System Resources .......................................................5
Peripherals ..................................................................6
GPIO ............................................................................6
Pinouts............................................................................... 7
Power .................................................................................9
Application Diagrams .....................................................10
Electrical Specifications .................................................19
Absolute Maximum Ratings....................................... 19
Device Level Specifications .......................................20
Digital Peripherals...................................................... 22
Memory...................................................................... 24
System Resources..................................................... 25
Ordering Information...................................................... 28
Ordering Code Definitions ......................................... 28
Packaging ........................................................................29
Acronyms ........................................................................32
Document Conventions ................................................. 33
Units of Measure ....................................................... 33
References and Links To Applications Collaterals .... 34
Document History Page .................................................35
Sales, Solutions, and Legal Information ...................... 36
Worldwide Sales and Design Support ....................... 36
Products ....................................................................36
PSoC®Solutions ........................................................36
Cypress Developer Community .................................36
Technical Support ......................................................36
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 4 of 36
Figure 1. EZ-PD CCG2 Block Diagram
Functional Overview
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in EZ-PD CCG2 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC). The WIC can wake the processor up
from the Deep Sleep mode, allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
The CPU also includes a serial wire debug (SWD) interface,
which is a 2-wire form of JTAG. The debug configuration used for
EZ-PD CCG2 has four break-point (address) comparators and
two watchpoint (data) comparators.
Flash
The EZ-PD CCG2 device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The flash block is designed to
deliver 1 wait-state (WS) access time at 48 MHz and with 0-WS
access time at 24 MHz. The flash accelerator delivers 85% of
single-cycle SRAM access performance on average. Part of the
flash module can be used to emulate EEPROM operation if
required.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
CCG2
32-bit
AHB-Lite
CPU Subsystem
SRAM
4 KB
SRAM Controller
SROM
8 KB
SROM Controller
FLASH
32 KB
Read Accelerator
SPCIF
Deep Sleep
Active/Sleep
SWD/TC
NVIC, IRQMX
Cortex
M0
48 MHz
FAST MUL
System Interconnect (Single Layer AHB)
I/O Subsystem
12 x GPIOs, 2 x OVTs
IOSS GPIO (3 x ports)
Peripherals
Peripheral Interconnect (MMIO)
PCLK
High Speed I/O Matrix
USB-PD SS
CC BB PHY
Power Modes
6 x TCPWM
DFT Logic
Test
DFT Analog
System Resources
Lite
Power
Clock
WDT
ILO
Reset
Clock Control
IMO
Sleep Control
PWRSYS
REFPOR
WIC
Reset Control
XRES
2 X VCONN
Pads, ESD
2 x SCB
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 5 of 36
USB-PD Subsystem (SS)
EZ-PD CCG2 has a USB-PD subsystem consisting of a USB
Type-C baseband transceiver and physical-layer logic. This
transceiver performs the BMC and the 4b/5b encoding and
decoding functions as well as the 1.2-V front end. This
subsystem integrates the required termination resistors to
identify the role of the EZ-PD CCG2 solution. RA is used to
identify EZ-PD CCG2 as an accessory or an electronically
marked cable. RD is used to identify EZ-PD CCG2 as a UFP in
a hybrid cable or a dongle. When configured as a DFP, integrated
current sources perform the role of RP or pull-up resistors. These
current sources can be programmed to indicate the complete
range of current capacity on VBUS defined in the Type-C spec.
EZ-PD CCG2 responds to all USB-PD communication. The
EZ-PD CCG2 USB-PD sub-system can be configured to
respond to SOP, SOP', or SOP” messaging.
The USB-PD sub-system contains a 8-bit SAR (Successive
Approximation Register) ADC for analog to digital conversions.
The ADC includes a 8-bit DAC and a comparator. The DAC
output forms the positive input of the comparator. The negative
input of the comparator is from a 4-input multiplexer. The four
inputs of the multiplexer are a pair of global analog multiplex
busses an internal bandgap voltage and an internal voltage
proportional to the absolute temperature. All GPIO inputs can be
connected to the global Analog Multiplex Busses through a
switch at each GPIO that can enable that GPIO to be connected
to the mux bus for ADC use. The CC1, CC2 and RD1 pins are
not available to connect to the mux busses.
Figure 2. USB-PD Subsystem
System Resources
Power System
The power system is described in detail in the section Power on
page 9. It provides assurance that voltage levels are as required
for each respective mode and either delay mode entry (on
power-on reset (POR), for example) until voltage levels are as
required for proper function or generate resets (Brown-Out
Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). EZ-PD
CCG2 can operate from three different power sources over the
range of 2.7 to 5.5 V and has three different power modes,
transitions between which are managed by the power system.
EZ-PD CCG2 provides Sleep and Deep Sleep low-power
modes.
Clock System
The clock system for EZ-PD CCG2 consists of the Internal Main
Oscillator (IMO) and the Internal Low-power Oscillator (ILO).
4b5b
Encoder
SOP
Detect
CRC
4b5b
Decoder
Tx_data
from AHB
Rx_data
to AHB
To/ from AHB
vref iref VDDD
To/From system Resources
SOP
Insert
8-bit ADC
From AMUX
CC detect
VConn2 detect
VConn1 detect
TX
RX
CC2
CC1
Ref
8kV IEC ESD
VCONN
Detect
Ra
Ra
Enable
Logic
8kV IEC ESD
Active
Rd
Rp
RD1
DB
Rd
Comp
Ra Enable
CC control
Enable Logic
TxRx Enable
BMC
Decoder
BMC
Encoder
Digital Baseband PHY Analog Baseband PHY
VCONN power logic
VCONN2
VCONN1
Deep Sleep
Vref & Iref Gen vref, iref
Tx
SRAM
Rx
SRAM
Deep Sleep Reference Enable
Functional, Wakeup Interrupts
VDDD
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 6 of 36
Peripherals
Serial Communication Blocks (SCB)
EZ-PD CCG2 has two SCBs, which can be configured to
implement an I2C, SPI, or UART interface. The hardware I2C
blocks implement full multi-master and slave interfaces capable
of multimaster arbitration. In the SPI mode, the SCB blocks can
be configured to act as master or slave.
In the I2C mode, the SCB blocks are capable of operating at
speeds of up to 1 Mbps (Fast Mode Plus) and have flexible
buffering options to reduce interrupt overhead and latency for the
CPU. These blocks also support I2C that creates a mailbox
address range in the memory of EZ-PD CCG2 and effectively
reduce I2C communication to reading from and writing to an
array in memory. In addition, the blocks support 8-deep FIFOs
for receive and transmit which, by increasing the time given for
the CPU to read data, greatly reduce the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripherals are compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/Os are implemented with GPIO in open-drain modes.
The I2C port on SCB 1 block of EZ-PD CCG2 is not completely
compliant with the I2C spec in the following respects:
■The GP IO cel l s for S C B 1 ' s I2C port are not overvoltage-tolerant
and, therefore, cannot be hot-swapped or powered up
independently of the rest of the I2C system.
■Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a
VOL maximum of 0.6 V.
■Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the bus load.
Timer/Counter/PWM Block (TCPWM)
EZ-PD CCG2 has six TCPWM blocks. Each implements a 16-bit
timer, counter, pulse-width modulator (PWM), and quadrature
decoder functionality. The block can be used to measure the
period and pulse width of an input signal (timer), find the number
of times a particular event occurs (counter), generate PWM
signals, or decode quadrature signals.
GPIO
EZ-PD CCG2 has up to 10 GPIOs in addition to the I2C and SWD
pins, which can also be used as GPIOs. The I2C pins from SCB
0 are overvoltage-tolerant. The number of available GPIOs vary
with the package. The GPIO block implements the following:
■Seven drive strength modes:
❐Input only
❐Weak pull-up with strong pull-down
❐Strong pull-up with weak pull-down
❐Open drain with strong pull-down
❐Open drain with strong pull-up
❐Strong pull-up with strong pull-down
❐Weak pull-up with weak pull-down
■Input threshold select (CMOS or LVTTL)
■Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode)
■Selectable slew rates for dV/dt related noise control to improve
EMI
During power-on and reset, the I/O pins are forced to the disable
state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed
I/O matrix is used to multiplex between various signals that may
connect to an I/O pin.
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 7 of 36
Pinouts
Group Name Pin Map
24-QFN
Ball Location
20-CSP
Pin Map
14-DFN Description
USB Type-C
Port
CC1 2 B4 3 USB PD connector detect/Configuration Channel 1
CC2 1 A4 N/A USB PD connector detect/Configuration Channel 2
RD1 3 B3 N/A Dedicated Rd resistor pin for CC1
Must be left open for cable applications and connected
together with CC1 ball for UFP or DFP with dead battery
applications
GPIOs and
serial interfaces
GPIO 22 C3 N/A GPIO / SPI_0_CLK / UART_0_ RX
GPIO 18 D3 13 GPIO / SPI_0_MOSI / UART_0_TX
GPIO 13 C2 10 GPIO / I2C_1_SDA / SPI_1_MISO / UART_1_RX
GPIO 10 D2 N/A GPIO / I2C_1_SCL / SPI_1_CLK / UART_1_TX
GPIO 15 B2 11 GPIO / SPI_1_SEL / UART_1_RTS
GPIO 14 N/A N/A GPIO
GPIO 17 N/A N/A GPIO
GPIO 21 N/A N/A GPIO
GPIO 23 N/A N/A GPIO
GPIO 24 N/A N/A GPIO
I2C_0_SCL 20 A3 1 GPIO / I2C_0_SCL / SPI_0_MISO / UART_0_RTS
I2C_0_SDA 19 A2 14 GPIO / I2C_0_SDA / SPI_0_SEL / UART_0_CTS
SWD _IO 11 E2 8 SWD IO / GPIO / UART_1_CTS / SPI_1_MOSI
SWD_CLK 12 D1 9 SWD clock / GPIO
RESET XRES 16 B1 12 Reset input
POWER VCONN1 5 E4 5 VCONN 1 input (4.0 V to 5.5 V)
VCONN2 4 C4 4 VCONN 2 input (4.0 V to 5.5 V)
VDDIO 8 E1 N/A 1.71-V to 5.5-V supply for I/Os
VCCD 7 A1 6 1.8-V regulator output for filter capacitor
VDDD 9 E3 7 VDDD supply input/output (2.7 V to 5.5 V)
VDDD 6 VDDD supply input/output (2.7 V to 5.5 V)
VSS
EPAD
N/A EPAD Ground supply
VSS D4 2Ground supply
VSS C1 Ground supply
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 8 of 36
Figure 3. 20-ball WLCSP EZ-PD CCG2 Ball Map (Bottom (Balls Up) View)
Figure 4. 14-pin DFN Pin Map (Top View)
Figure 5. 24-Pin QFN Pin Map (Top View)
4321
A
B
C
D
CC2
CC1
VCONN2
VSS
I2C_0_SDA
GPIO
I2C_0_SCL
RD1
GPIO
GPIO
GPIO
GPIO
VCCD
XRES
VSS
SWD_CLK
E
VCONN1 SWD_IO
VDDD VDDIO
14
13
12
11
10
9
8
1
2
3
4
5
6
7
I2C_0_SDA
GPIO
XRES
GPIO
GPIO
SWD_CLK
SWD_IO
I2C_0_SCL
VSS
CC1
VCONN2
VCONN1
VCCD
VDDD
1
2
3
4
5
6
CC2
CC1
RD1
VCONN2
VCONN1
VDDD
7
8
9
10
11
12
VCCD
VDDIO
VDDD
GPIO
SWD_IO
SWD_CLK
18
17
16
15
14
13
GPIO
GPIO
XRES
GPIO
GPIO
GPIO
24
23
22
21
20
19
GPIO
GPIO
GPIO
GPIO
I2C_0_SCL
I2C_0_SDA
EPAD
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 9 of 36
Power
The following power system diagram shows the set of power
supply pins as implemented in EZ-PD CCG2.
EZ-PD CCG2 can operate from three different power sources.
VCONN1 and VCONN2 pins can be used as connections to the
VCONN pins on a Type-C plug of a cable or VCONN-powered
accessory. Each of these inputs support operation over 4.0 to
5.5 V. An internal isolation between VCONN1 and VCONN2 pins
is provided allowing them to be at different levels simultaneously.
CCG2 can be used in EMCA applications with only one or both
VCONN pins as power sources. This is illustrated later in the
section on Applications. Besides being power inputs, each
VCONN pin is also internally connected to a RA termination
resistor required for EMCA and VCONN-powered accessories.
EZ-PD CCG2 can also be operate from 2.7 to 5.5 V when
operated from the VDDD supply pin. VCONN-powered
accessory applications require that CCG2 work down to 2.7 V. In
such applications, both the VDDD and VCONN pins should be
connected to the VCONN pin of the Type-C plug in the
accessory.
In UFP, DFP, and DRP applications, CCG2 can be operated from
VDDD as the only supply input. In such applications, the VCONN
pins are left open. In DFP applications, the lowest VDDD level
that CCG2 can operate is 3.0 V due to the need to support
disconnect detection thresholds of up to 2.7 V.
A separate I/O supply pin, VDDIO, allows the GPIOs to operate
at levels from 1.71 to 5.5 V. The VDDIO pin can be equal to or
less than the voltages connected to the VCONN1, VCONN2, and
VDDD pins. The independent VDDIO supply is not available on
the 14-DFN package. On this package, the VDDIO rail is
internally connected to the VDDD rails.
The VCCD output of EZ-PD CCG2 must be bypassed to ground
via an external capacitor (in the range of 1 to 1.6 µF; X5R
ceramic or better).
Bypass capacitors must be used from VDDD and VCONN pins
to ground; typical practice for systems in this frequency range is
to use a 0.1-µF capacitor. Note that these are simply rules of
thumb and that for critical applications, the PCB layout, lead
inductance, and the bypass capacitor parasitic should be
simulated to design and obtain optimal bypassing.
An example of the power supply bypass capacitors is shown in
Figure 6.
Figure 6. EZ-PD CCG2 Power and Bypass Scheme Example
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 10 of 36
Application Diagrams
Figure 7 to Figure 10 show the application diagrams of a Passive
EMCA application using CCG2 devices. Figure 7 and Figure 8
show the application using a single CCG2 device per cable
present at one of the two plugs, whereas Figure 9 and Figure 10
show the same with two CCG2 devices per cable present at each
plug. The VBUS signal, the SuperSpeed lines, HighSpeed lines,
and CC lines are connected directly from one end to another.
The application diagrams shown in Figure 7 a n d Figure 8 require
a single VCONN wire to run through the cable so that the CCG2
device can be powered irrespective of which plug is connected
to the host (DFP). However, in the application diagrams shown
in Figure 9 and Figure 10, the VCONN signal does not run
through the entire cable, but only runs to the respective VCONN
pin of the CCG2 device at each end of the plug. Also, only one
CCG2 device is powered at any given instance, depending on
which one is nearer to the DFP that supplies VCONN.
Note: Application diagram in Figure 8 requires external diodes
to operate in the extended VCONN voltage range of 2.7V to 5.5V.
Figure 7. Passive EMCA Application – Single EZ-PD CCG2 Per Cable (VCONN range between 4.0V to 5.5V)
VCONN 1
VBUS
CC
Type-C
Plug
GND
Type-C
Plug
VCONN 2
SuperSpeed and HighSpeed Lines
0.1uF
CCG2
VDDD
E3
1uF
A1 VCCD
VSS
C1
XRES
B1
SWD_
IO
SWD_
CLK
E2 D1
I2C_0
_SCL
I2C_0
_SDA
A3 A2
B4
CC1
GPIO
GPIO D3
C2
CC2 A4
E4 VCONN1 C4
VCONN2
VDDIO
E1
RD1 B3
VSS
D4
GPIO D2
GPIO B2
GPIO
C3
0.1uF
1uF
VDDIO
4.7 k
20-CSP
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 11 of 36
Figure 8. Passive EMCA Application – Single EZ-PD CCG2 Per Cable (VCONN range between 2.7V to 5.5V)
VCONN 1
VBUS
CC
Type-C
Plug
GND
Type-C
Plug
VCONN 2
SuperSpeed and HighSpeed Lines
CCG2
VDDD
E3
1uF
A1 VCCD
VSS
C1
XRES
B1
SWD_
IO
SWD_
CLK
E2 D1
I2C_0
_SCL
I2C_0
_SDA
A3 A2
B4
CC1
GPIO
GPIO D3
C2
CC2 A4
E4 VCONN1 C4
VCONN2
VDDIO
E1
1uF
0.1uF
0.1uF
RD1 B3
VSS
D4
GPIO D2
GPIO B2
GPIO
C3
NSR0620P2T5G
21
NSR0620P2T5G
21
Select a diode with VF less than 0.3V at 10mA
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 12 of 36
Figure 9. Passive EMCA Application – Single EZ-PD CCG2 Per Plug (VCONN range between 4.0V to 5.5V)
Figure 10. Passive EMCA Application – Single EZ-PD CCG2 Per Plug (VCONN range between 2.7V to 5.5V)
VCONN
VBUS
CC
Type-C
Plug
Type-C
Plug
VCONN
GND
SuperSpeed and HighSpeed Lines
CCG2
VDDD
E3
1uF
A1 VCCD
VSS
C1
XRES
B1
SWD_
IO
SWD_
CLK
E2 D1
I2C_0
_SCL
I2C_0
_SDA
A3 A2
B4
CC1
GPIO
GPIO D3
C2
CC2 A4
E4 VCONN1 C4
VCONN2
VDDIO
E1
1uF
0.1uF
RD1 B3
VSS
D4
GPIO D2
GPIO B2
GPIO
C3
CCG2
VDDD
E3
1uF
A1 VCCD
VSS
C1
XRES
B1
SWD_
IO
SWD_
CLK
E2 D1
I2C_0
_SCL
I2C_0
_SDA
A3 A2
B4
CC1
GPIO
GPIO D3
C2
CC2 A4
C4 VCONN2 E4
VCONN1
VDDIO
E1
1uF
0.1uF
RD1 B3
VSS
D4
GPIO D2
GPIO B2
GPIO
C3
VDDIO
VDDIO
4.7k
4.7k
VCONN1
VBUS
CC
Type-C Plug Type-C Plug
VCONN2
GND
SuperSpeed and HighSpeed Lines
CCG2
VDDD
B1
1uF
D1 VCCD
VSS
C1
XRES
D3
SWD_IO SWD_CLK
A3 A4
I2C_SCL I2C_SDA
B4 C4
D4
CC1
GPIO
GPIO C2
B2
CC2 C3
A1 VCONN1 D2
VCONN2
VDDIO
A2
1uF
0.1uF
RD1 B3
CCG2
VDDD
B1
1uF
D1 VCCD
VSS
C1
XRES
D3
SWD_IO SWD_CLK
A3 A4
I2C_SCL I2C_SDA
B4 C4
D4
CC1
GPIO
GPIO C2
B2
CC2 C3
A1 VCONN1 D2
VCONN2
VDDIO
A2
1uF
0.1uF
RD1 B3
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 13 of 36
Figure 11 shows a CCG2 device being used in a UFP application (tablet with a Type-C port) only as a power consumer.
The Type-C receptacle brings in HighSpeed and SuperSpeed lines, which are connected directly to the applications processor. The
VBUS line from the Type-C receptacle goes directly to the UFP (tablet) charger circuitry. The applications processor communicates
over the I2C signal with the CCG2 device, and the CC1 and CC2 lines from the Type-C receptacle are connected directly to the
respective CC1/2 pins of the CCG2 device.
Figure 11. Upstream Facing Port (UFP) Application – Tablet with a Type-C Port
Figure 12 shows a Notebook DRP application diagram using a
CCG2 device. The Type-C port can be used as a power provider
or a power consumer. The CCG2 device communicates with the
Embedded controller (EC) over I2C. It also controls the Data Mux
to route the High Speed signals either to the USB chipset (during
normal mode) or the DisplayPort Chipset (during Alternate
Mode). The SBU lines, SuperSpeed and HighSpeed lines are
routed directly from the Display Mux of the notebook to the
Type-C receptacle.
Optional FETs are provided for applications that need to provide
power for accessories and cables using the VCONN pin of the
Type-C receptacle. VBUS FETs are also used for providing
power over VBUS and for consuming power over VBUS. A
VBUS_DISCHARGE FET controlled by CCG2 device is used to
quickly discharge VBUS after the Type-C connection is
detached.
VBUS
Application
Processor
Type-C
Receptacle
HighSpeed Lines
CCG2
VDDD
E3
I2C_0_SDA
A2
GPIO
C3
VCCD XRES
A1 B1
VSS VSS
D4 C1
B4
CC1
GPIO
GPIO D3
C2
CC2 A4
E4 VCONN1
VDDIO
E1
1uF
RD1 B3
I2C_0_SCL
A3
GPIO D2
GPIO B2
SWD_IO
E2
1uF
SWD_CLK
D1
C4 VCONN2
1uF
5.0 V 1.8 V
Charger
Application
Processor/
Graphics
Controller
SuperSpeed Lines
1.8 V
INT
1.8 V
4.7 kΩ
4.7 kΩ
4.7 kΩ
390 pF 390 pF
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 14 of 36
Figure 12. Dual Role Port (DRP) Application
CCG2
24-QFN
VDDD
VDDD
VDDIO
VCCD
6
9
8
7
GPIO
GPIO
GPIO
13
10
23
GPIO 15
GPIO 18
GPIO 22
GPIO 21
GPIO 24
CC2 1
CC1 2
RD1 3
VCONN1
5
VCONN2
4
SWD_IO
11
SWD_CLK
12
GPIO
14
I2C_0_SCL
20
I2C_0_SDA
19
XRES
16
VSS
EPAD
1uF
3.3V VDDIO
VDDIO
1uF
VBUS_P_CTRL
VBUS_DISCHARGE
VBUS_C_CTRL
Type-C
Receptacle
VBUS
(5-20V)
VDDIO
I2C_INT
VBUS_SINK
VBUS_SOURCE
5.0V
5.0V
OPTIONAL
FETS for DFPs
SUPPORTING
VCONN
VBUS FETs for
CONSUMER PATH
CC1_VCONN_CTRL
CC2_VCONN_CTRL
VBUS_DISCHARGE
VBUS_C_CTRL
VBUS_P_CTRL
HPD
USB
Chipset
Embedded
Controller
HPD
DC/DC
CHARGER
GPIO 17
VBUS
VBUS_MON
390pF 390pF
VBUS FETs for
PROVIDER PATH
100kΩ
10kΩ
2.2kΩ
2.2kΩ
2.2kΩ
4.7kΩ
D+/-
SS
DisplayPort
Chipset
Data Mux
DP0/1/2/3
AUX+/-
SCL SDA GND
SS
HS/SS/DP/
SBU Lines
DP/DN
D+/-
SS
CC1
CC2
VBUS
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 15 of 36
Figure 13 shows a CCG2 receptacle-based Power Adapter
application in which the CCG2 device is used as a DFP. CCG2
integrates all termination resistors and uses GPIOs (VSEL_0
and VSEL_1) to indicate the negotiated power profile. The VBUS
voltage on the Type-C port is monitored using internal ADC to
detect undervoltage and overvoltage conditions on VBUS. To
ensure quick discharge of VBUS when the power adapter cable
is detached, a discharge path is also provided.
Figure 13. Downstream Facing Port (DFP) Application
CCG2
24-QFN
VDDD
VDDD
VDDIO
VCCD
6
9
8
7
GPIO
GPIO
GPIO
13
10
23
GPIO 15
GPIO 18
GPIO 22
GPIO 21
GPIO 24
CC2 1
CC1 2
RD1 3
VCONN1
5
VCONN2
4
SWD_IO
11
SWD_CLK
12
GPIO
14
GPIO
20
GPIO
19
XRES
16
VSS
EPAD
1uF
3.3V VDDIO
VDDIO
1uF
VBUS_P_CTRL
VBUS_DISCHARGE
Type-C
Receptacle
VBUS
(5-20V)
VBUS_IN
5.0V
5.0V
OPTIONAL
FETS for DFPs
SUPPORTING
VCONN
CC1_VCONN_CTRL
CC2_VCONN_CTRL
VBUS_DISCHARGE
VBUS_P_CTRL
DC/DC
OR
AC-DC
SECONDARY
(5-20V)
GPIO 17
VBUS
VBUS_MON
OPTIONAL VDDIO
SUPPLY. CAN SHORT
TO VDDD IN SINGLE
SUPPLY SYSTEMS
VSEL_1 and VSEL_0
CONTROL THE SECONDARY
SIDE OF AN AC-DC OR A DC-DC
TO SELECT THE VOLTAGE ON
VBUS_IN. AN EXAMPLE IS
SHOWN BELOW:
VSEL_1
VSEL_0
VSEL_1
VSEL_0
390pF 390pF
100kΩ
10kΩ
4.7kΩ
VSEL_1 VSEL_0 VBUS_IN
005V
019V
1015V
1120V
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 16 of 36
Figure 14 shows a USB Type-C to HDMI/DVI/VGA adapter appli-
cation, which enables connectivity between a PC that supports
a Type-C port with DisplayPort Alternate Mode support and a
legacy monitor that has HDMI/DVI/VGA interface. It enables
users of any Notebook that implements USB-Type C to connect
to other display types.
This application has a Type-C plug on one end and the legacy
video (HDMI/DVI/VGA) receptacle on the other end. This appli-
cation meets the requirements described in Section 4.3 of the
VESA DisplayPort Alt Mode on USB Type-C Standard Version
1.0. This application supports display output at a resolution of up
to 4K Ultra HD (3840x2160) at 60 Hz. It also supports the USB
Billboard Device Class, which is required by the USB PD speci-
fication for enumeration of any accessories that support
Alternate Mode when connected to a host PC.
Figure 14. USB Type-C to HDMI/DVI/VGA Dongle Application Diagram
Type-C
Plug
USB-Billboard
CY7C65210
HDMI/DVI/
VGA
Receptacle
Power OR
VBUS
VCONN
VBUS
D+/-
CC
SW for AUX
SBU_1/2
HotPlug Detect
2.2k:5%
2.2k:5%
SCLSDA
XRES INT 3.3V
CYPD2119
24QFN
CC1
RD1
CC2
2
3
1
EPAD
VCCD 7
P1.7 P2.1 P1.3 P1.0
18 10 13 22
VDDD1
VDDD2
VDDIO
VCONN1
5
6
9
8
VCONN2
P1.6
4
17
XRES
4.7KΩ16
P1.5
15
P2.3:P0.0 P0.1
1µF
P1.4
VCONN
3.3V
1µF
100KΩ,±1%
10KΩ,±1%
VBUS
P2.0
P2.2
SWD_CLK
SWD_IO
12
11
21
23
[24:19] 20
14
BuckBoost
5V
Regulator
3.3V
1.2V
DP to HDMI/
DVI/VGA
Convertor
3.3V 1.2V
Display Port
Data Lanes
2.2k:5%
VBUS_VCONN
VBUS_VCONN
1µF 0.1µF
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 17 of 36
Figure 15 shows a USB Type-C to DisplayPort adapter appli-
cation, which enables connectivity between a PC that supports
a Type-C port with DisplayPort Alternate Mode support and a
legacy monitor that has a DisplayPort interface.
Figure 15 shows a Type-C plug on one end and a DP/mDP plug
on the other end. The application meets the requirements
described in Section 4.2 of the VESA DisplayPort Alt Mode on
USB Type-C Standard Version 1.0 (Scenarios 2a and 2b USB
Type-C to DisplayPort Cables). It also supports the USB
Billboard Device Class, which is required by the USB PD speci-
fication for enumeration of any accessories that support
Alternate Mode when connected to a host PC.
Figure 15. USB Type-C to Display Port Application Diagram
Type-C
Plug
USB-Billboard
CY7C65210
mDP/
DP
Power OR
VBUS
VCONN
VBUS_VCONN
VBUS
D+/-
CC
Display Port
Data Lanes
SW for AUX
SBU_1/2 AUX_P/N
Paddle Card
HotPlug Detect
2.2k:5%
2.2k:5%
SCLSDA
XRES INT
VBUS_VCONN
CYPD2120
24QFN
CC1
RD1
CC2
2
3
1
EPAD
VCCD 7
P1.7 P2.1 P1.3 P1.0
18 10 13 22
VDDD1
VDDD2
VDDIO
VCONN1
5
6
9
8
VCONN2
P1.6
4
17
XRES
4.7KΩ16
P1.5
15
P2.3:P0.0 P0.1
1µF
P1.4
0.1µF
VCONN
VBUS_VCONN
1µF
100KΩ,±1%
10KΩ,±1%
VBUS
P2.0
P2.2
SWD_CLK
SWD_IO
12
11
21
23
[24:19] 20
14
2.2k:5%
Display Port
Data Lanes
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 18 of 36
Figure 16 shows a CCG2 Monitor/Dock application diagram. It enables connectivity
between a USB Type-C host system on the Upstream port and multiple Display/Data
devices on the Downstream port. This application has a USB Type-C receptacle on
the Upstream port, which supports data, power, and display. On the Downstream
port, this application supports: USB Type-A, Gigabit Ethernet, DisplayPort, and USB
Type-C receptacle.
The main features of this solution are:
■Powered from an external 24-V DC power adapter
■Provides up to 45 W (15 V at 3A) on the Upstream Type-C port and up to 15 W
(5 V at 3A) on the Downstream USB Type-C port
■Provides simultaneous 4K display output with USB 3.1 Gen 1 on the USB Type-A
port
■Four-lane display on the DisplayPort connector
■Multi-Stream support on DisplayPort and Downstream Type-C port
■USB 3.1 Gen 1 hub for USB port expansion
■Gigabit Ethernet using RJ45 connector
■Supports firmware upgrade of CCG2 controllers, HX3 Hub controller, and Billboard
controller
Figure 16. CCG2 in Dock/Monitor Application Diagram
Type-C
to
Notebook
USB-Billboard
CY7C65210
VBUS_US 5V
CC1
SBU_1/2
HotPlug Detect
2.2k:5%
2.2k:5%
SCLSDA
INT2
INT1 3.3V
DRP
CYPD2121
24QFN
CC1
RD1
CC2
2
3
1
EPAD
VCCD 7
P1.4 P0.0 P0.1
14 19 20
VDDD1
VDDD2
XRES
VDDIO
1µF
8
6
9
16
VCONN2
P1.6
4
17
VCONN1
4.7KΩ
5
P2.1
12
SWD_CLK_P1.2 P2.2
P1.5
0.1µF
3.3V
1µF
100KΩ,±1%
10KΩ,±1%
VBUS
SWD_IO_P1.1 11
23
15
5V 3.3V
1.2V
Type-C Mux
SS Data Lanes
2.2k:5%
100KΩ
1KΩ
100KΩ
Regulator
US_VBUS_P_CTRL
VSEL_1
VSEL_0
0.1µF
US_VBUS_DIS 22
100Ω
P1.3
P1.0
2.2k:5% 2.2k:5%
13
10
P1.7
P2.3
VSEL_0
VSEL_1
18
24
P2.0 21 HUB_VBUS_US
CC2
SDASCLHPD
DP
Spliter
DP
Port
USB
Hub
CYUSB3304
-68LTXC
HUB_VBUS_US
SS Data Lines
USB D+/-
USB D+/-
SYS_I2C_SDA
SYS_I2C_SCL
SYS_I2C_SCL
SYS_I2C_SCL
HS_DS2
HS_DS2
DS1
DS3
HS_DS4
USB Type-A
Receptacle
Ethernet GX3
CYUSB3610-
68LTXC
SS_DS4
Type-C
to
Device
VBUS_DS
VCONN
CC1
DS_HotPlug Detect
3.3V
DFP
CYPD2125
24QFN
RD1
CC1
CC2
3
2
1
EPAD
VCCD
7
P2.3P2.1P0.0P0.1
24
22
1920
VDDD1
VDDD2
XRES
VDDIO
1µF
8
6
9
16
VCONN2
P1.6
4
17
VCONN1
4.7KΩ
5
P2.0
12
SWD_CLKP2.2
P1.5
0.1µF
3.3V
1µF
100KΩ,±1%
10KΩ,±1%
VBUS
SWD_IO
11
23
15
Type-C Mux
SS Data Lines_2
100KΩ
1KΩ
100KΩ
US_VBUS_P_CTRL
0.1µF
DS_VBUS_DIS
21
100KΩ
P1.3
P1.0
2.2k:5%
2.2k:5% 13
10
P1.7
18
CC2
SDA SCL HPD HS_DS4
SYS_I2C_SDA
SYS_I2C_SCL
100KΩ
200KΩ
VCONN
100KΩ
200KΩ
P1.4
DS_I2C_INT
14
DP2
DP2
SS_DS4
DS_HotPlug Detect
5.0V
Power
5-20V
5-20V
Discharge
NFET
US_VBUS_DIS
SS Data Lines_1
Power In
Brick
Discharge
NFET
DS_VBUS_DIS
DS_I2C_INT
I2C Master
I2C Slave
I2C Master
CCG2 connected on the Upstream Port
CCG2 connected on the Downstream Port
Cypress USB3.0 HUB
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 19 of 36
Electrical Specifications
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings[1]
Parameter Description Min Typ Max Units Details/Conditions
VDDD_MAX Digital supply relative to VSS –0.5 – 6 V Absolute max
VCONN1_MAX Max supply voltage relative to VSS –– 6 VAbsolute max
VCONN2_MAX Max supply voltage relative to VSS –– 6 VAbsolute max
VDDIO_MAX Max supply voltage relative to VSS –– 6 VAbsolute max
VGPIO_ABS GPIO voltage –0.5 – VDDIO + 0.5 V Absolute max
VCC_ABS
Absolute max voltage for CC1 and
CC2 pins –– 6 VAbsolute max
IGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute max
IGPIO_injection
GPIO injection current, Max for
VIH > VDDD, and Min for VIL < VSS
–0.5 – 0.5 mA Absolute max, current
injected per pin
ESD_HBM Electrostatic discharge human
body model 2200 – – V –
ESD_CDM Electrostatic discharge charged
device model 500 – – V –
LU Pin current for latch-up –200 – 200 mA –
ESD_IEC_CON Electrostatic discharge
IEC61000-4-2 8000 – – V
Contact discharge on
CC1, CC2, VCONN1, and
VCONN2 pins
ESD_IEC_AIR Electrostatic discharge
IEC61000-4-2 15000 – – V
Air discharge for pins
CC1, CC2, VCONN1, and
VCONN2
Note
1. Usage above the absolute maximum conditions listed in Ta bl e 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 20 of 36
Device Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V,
except where noted.
Table 2. DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.PWR#1 VDDD Power supply input voltage 2.7 – 5.5 V UFP Applications
SID.PWR#1_A VDDD Power supply input voltage 3.0 – 5.5 V DFP/DRP Applications
SID.PWR#23 VCONN1 Power supply input voltage 4.0 – 5.5 V –
SID.PWR#23_A VCONN2 Power supply input voltage 4.0 – 5.5 V –
SID.PWR#13 VDDIO GPIO power supply 1.71 – 5.5 V –
SID.PWR#24 VCCD Output voltage (for core logic) – 1.8 – V –
SID.PWR#15 CEFC
External regulator voltage bypass on
VCCD
11.31.6 µF X5R ceramic or better
SID.PWR#16 CEXC
Power supply decoupling capacitor
on VDDD
–1– µF X5R ceramic or better
SID.PWR#25 Power Supply Decoupling Capacitor
on VCONN1 and VCONN2
–0.1– µF X5R ceramic or better
Active Mode, VDDD = 2.7 to 5.5 V. Typical values measured at VDD = 3.3 V.
SID.PWR#12 IDD12 Supply current – 7.5 – mA
VCONN1 or VCONN2 = 5 V,
TA = 25 °C,
CC I/O IN Transmit or
Receive, RA disconnected,
no I/O sourcing current, CPU
at 12 MHz
Sleep Mode, VDDD = 2.7 to 5.5 V
SID25A IDD20A
I2C wakeup. WDT ON. IMO at
48 MHz –2.03.0mA
VDDD = 3.3 V, TA = 25 °C, all
blocks except CPU are ON,
CC I/O ON, no I/O sourcing
current
Deep Sleep Mode, VDDD = 2.7 to 3.6 V (Regulator on)
SID_DS_RA IDD_DS_RA
VCONN1 = 5.0, RA termination
disabled – 100 – µA
VCONN1, VCONN2 = 5 V,
TA = 25 °C.
RA termination disabled on
VCONN1 and VCONN2, see
SID.PD.7.
VCONN leaker circuits
turned off during deep sleep
SID34 IDD29
VDDD = 2.7 to 3.6 V. I2C wakeup and
WDT ON –50– µA
RA switch disabled on
VCONN1 and VCONN2.
VDDD = 3.3 V, TA = 25 °C
SID_DS IDD_DS VDDD = 2.7 to 3.6 V. CC wakeup ON – 2.5 – µA
Power source = VDDD,
Type-C not attached, CC
enabled for wakeup, RP
disabled
XRES Current
SID307 IDD_XR Supply current while XRES asserted – 1 10 µA–
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 21 of 36
I/O
Table 3. AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.CLK#4 FCPU CPU frequency DC –48 MHz 3.0 V VDDD 5.5 V
SID.PWR#20 TSLEEP Wakeup from sleep mode – 0 – µs Guaranteed by
characterization
SID.PWR#21 TDEEPSLEEP Wakeup from Deep Sleep mode – – 35 µs
24-MHz IMO.
Guaranteed by charac-
terization
SID.XRES#5 TXRES External reset pulse width 5 – – µs Guaranteed by
characterization
SYS.FES#1 T_PWR_RDY
Power-up to “Ready to accept I2C /
CC command” – 5 25 ms Guaranteed by
characterization
Table 4. I/O DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.GIO#37 VIH[2] Input voltage HIGH threshold 0.7 × VDDIO –– VCMOS input
SID.GIO#38 VIL Input voltage LOW threshold – – 0.3 × VDDIO VCMOS input
SID.GIO#39 VIH[2] LVTTL input, VDDIO < 2.7 V 0.7× VDDIO –– V –
SID.GIO#40 VIL LVTTL input, VDDIO < 2.7 V – – 0.3 × VDDIO V–
SID.GIO#41 VIH[2] LVTTL input, VDDIO 2.7 V 2.0 – – V –
SID.GIO#42 VIL LVTTL input, VDDIO 2.7 V – – 0.8 V –
SID.GIO#33 VOH Output voltage HIGH level VDDIO – 0.6 – – V IOH = 4 mA at 3-V
VDDIO
SID.GIO#34 VOH Output voltage HIGH level VDDIO – 0.5 – – V IOH = 1 mA at 1.8-V
VDDIO
SID.GIO#35 VOL Output voltage LOW level – – 0.6 V IOL = 4 mA at 1.8-V
VDDIO
SID.GIO#36 VOL Output voltage LOW level – – 0.6 V IOL = 8 mA at 3 V VDDIO
SID.GIO#5 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ –
SID.GIO#6 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ –
SID.GIO#16 IIL
Input leakage current (absolute
value) –– 2nA
25 °C, VDDIO = 3.0
V.Guaranteed by
characterization
SID.GIO#17 CIN Input capacitance – – 7 pF Guaranteed by
characterization
SID.GIO#43 VHYSTTL Input hysteresis LVTTL 25 40 – mV
VDDIO 2.7 V.
Guaranteed by
characterization.
SID.GPIO#44 VHYSCMOS Input hysteresis CMOS 0.05 × VDDIO ––mV
Guaranteed by
characterization
SID69 IDIODE
Current through protection diode to
VDDIO/Vss – – 100 µAGuaranteed by
characterization
SID.GIO#45 ITOT_GPIO
Maximum total source or sink chip
current – – 200 mA Guaranteed by
characterization
Note
2. VIH must not exceed VDDIO + 0.2 V.
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 22 of 36
XRES
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Pulse Width Modulation (PWM) for GPIO Pins
Table 5. I/O AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID70 TRISEF Rise time 2 – 12 ns 3.3-V VDDIO, Cload = 25 pF
SID71 TFALLF Fall time 2 – 12 ns 3.3-V VDDIO, Cload = 25 pF
Table 6. XRES DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.XRES#1 VIH Input voltage HIGH threshold 0.7 ×
VDDIO
––VCMOS input
SID.XRES#2 VIL Input voltage LOW threshold – – 0.3 ×
VDDIO
VCMOS input
SID.XRES#3 CIN Input capacitance – – 7 pF Guaranteed by
characterization
SID.XRES#4 VHYSXRES Input voltage hysteresis – – 0.05 ×
VDDIO
mV Guaranteed by characterization
Table 7. PWM AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.TCPWM.3 TCPWMFREQ Operating frequency –Fc –MHz Fc max = CLK_SYS. Maximum
= 48 MHz.
SID.TCPWM.4 TPWMENEXT Input trigger pulse width –2/Fc –ns For all Trigger Events
SID.TCPWM.5 TPWMEXT Output trigger pulse width –2/Fc –ns
Minimum possible width of
Overflow, Underflow, and CC
(Counter equals Compare
value) outputs
SID.TCPWM.5A TCRES Resolution of counter –1/Fc –ns Minimum time between
successive counts
SID.TCPWM.5B PWMRES PWM resolution –1/Fc –ns Minimum pulse width of PWM
output
SID.TCPWM.5C QRES Quadrature inputs resolution –1/Fc –ns Minimum pulse width between
quadrature-phase inputs
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 23 of 36
I2C
Table 8. Fixed I2C DC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID149 II2C1 Block current consumption at 100 kbps – – 60 µA–
SID150 II2C2 Block current consumption at 400 kbps – – 185 µA–
SID151 II2C3 Block current consumption at 1 Mbps – – 390 µA–
SID152 II2C4 I2C enabled in Deep Sleep mode – – 1.4 µA–
Table 9. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID153 FI2C1 Bit rate – – 1 Mbps –
Table 10. Fixed UART DC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID160 IUART1
Block current consumption at
100 Kbps – – 125 µA Guaranteed by
characterization
SID161 IUART2
Block current consumption at
1000 Kbps – – 312 µA Guaranteed by
characterization
Table 11. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID162 FUART Bit rate – – 1 Mbps Guaranteed by
characterization
Table 12. Fixed SPI DC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID163 ISPI1 Block current consumption at 1 Mbps – – 360 µA Guaranteed by
characterization
SID164 ISPI2 Block current consumption at 4 Mbps – – 560 µA Guaranteed by
characterization
SID165 ISPI3 Block current consumption at 8 Mbps – – 600 µA Guaranteed by
characterization
Table 13. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID166 FSPI
SPI Operating frequency (Master; 6X
oversampling) – – 8 MHz Guaranteed by
characterization
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 24 of 36
Memory
Table 14. Fixed SPI Master Mode AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID167 TDMO
MOSI Valid after SClock driving
edge – – 15 ns Guaranteed by
characterization
SID168 TDSI
MISO Valid before SClock
capturing edge 20 – – ns
Full clock, late MISO
sampling. Guaranteed
by characterization
SID169 THMO Previous MOSI data hold time 0 – – ns
Referred to Slave
capturing edge.
Guaranteed by
characterization
Table 15. Fixed SPI Slave Mode AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID170 TDMI
MOSI Valid before Sclock
Capturing edge 40 – – ns Guaranteed by
characterization
SID171 TDSO
MISO Valid after Sclock driving
edge – – 42 + 3 * TCPU ns
TCPU = 1/FCPU.
Guaranteed by
characterization.
SID171A TDSO_EXT
MISO Valid after Sclock driving
edge in Ext Clk mode – – 48 ns Guaranteed by
characterization
SID172 THSO Previous MISO data hold time 0 – – ns Guaranteed by
characterization
SID172A TSSELSCK SSEL Valid to first SCK Valid edge 100 – – ns Guaranteed by
characterization
Table 16. Flash AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.MEM#4 TROWWRITE[3] Row (block) write time (erase and
program) – – 20 ms Row (block) =
128 bytes
SID.MEM#3 TROWERASE[3] Row erase time – – 13 ms –
SID.MEM#8 TROWPROGRAM[3] Row program time after erase – – 7 ms –
SID178 TBULKERASE[3] Bulk erase time (32 KB) – – 35 ms –
SID180 TDEVPROG[3] Total device program time – – 7.5 seconds Guaranteed by
characterization
SID181 FEND Flash endurance 100 K – – cycles Guaranteed by
characterization
SID182 FRET1
Flash retention. TA 55 °C, 100 K
P/E cycles 20 – – years Guaranteed by
characterization
SID182A FRET2
Flash retention. TA 85 °C, 10 K
P/E cycles 10 – – years Guaranteed by
characterization
Note
3. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 25 of 36
System Resources
Power-on-Reset (POR) with Brown Out
SWD Interface
Internal Main Oscillator
Table 17. Imprecise Power On Reset (PRES)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID185 VRISEIPOR Rising trip voltage 0.80 – 1.50 V Guaranteed by
characterization
SID186 VFALLIPOR Falling trip voltage 0.75 – 1.4 V Guaranteed by
characterization
Table 18. Precise Power On Reset (POR)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID190 VFALLPPOR
BOD trip voltage in active and
sleep modes 1.48 – 1.62 V Guaranteed by
characterization
SID192 VFALLDPSLP BOD trip voltage in Deep Sleep 1.1 – 1.5 V Guaranteed by
characterization
Table 19. SWD Interface Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.SWD#1 F_SWDCLK1 3.3 V VDDIO 5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU
clock frequency
SID.SWD#2 F_SWDCLK2 1.8 V VDDIO 3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU
clock frequency
SID.SWD#3 T_SWDI_SETUP T = 1/f SWDCLK 0.25*T – – ns Guaranteed by
characterization
SID.SWD#4 T_SWDI_HOLD T = 1/f SWDCLK 0.25*T – – ns Guaranteed by
characterization
SID.SWD#5 T_SWDO_VALID T = 1/f SWDCLK – – 0.5 * T ns Guaranteed by
characterization
SID.SWD#6 T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns Guaranteed by
characterization
Table 20. IMO DC Specifications
(Guaranteed by Design)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID218 IIMO IMO operating current at 48 MHz – – 1000 µA–
Table 21. IMO AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.CLK#13 FIMOTOL
Frequency variation at 24, 36,
and 48 MHz (trimmed) – – ±2 % –
SID226 TSTARTIMO IMO startup time – – 7 µs Guaranteed by
characterization
SID229 TJITRMSIMO RMS jitter at 48 MHz –145 –ps Guaranteed by
characterization
FIMO –IMO frequency 24 –48 MHz –
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 26 of 36
Internal Low-Speed Oscillator
Power Down
Table 22. ILO DC Specifications
(Guaranteed by Design)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID231 IILO ILO operating current at 32 kHz – 0.3 1.05 µA Guaranteed by
Characterization
SID233 IILOLEAK ILO leakage current – 2 15 nA Guaranteed by Design
Table 23. ILO AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID234 TSTARTILO ILO startup time – – 2 ms Guaranteed by
characterization
SID236 TILODUTY ILO duty cycle 40 50 60 %Guaranteed by
characterization
SID.CLK#5 FILO ILO Frequency 20 40 80 kHz –
Table 24. PD DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.PD.1 Rp_std DFP CC termination for default
USB Power 64 80 96 µA –
SID.PD.2 Rp_1.5A DFP CC termination for 1.5A
power 166 180 194 µA –
SID.PD.3 Rp_3.0A DFP CC termination for 3.0A
power 304 330 356 µA –
SID.PD.4 Rd UFP CC termination 4.59 5.1 5.61 kΩ –
SID.PD.5 Rd_DB UFP Dead Battery CC termi-
nation on RD1 and CC2 4.08 5.1 6.12 kΩ
All supplies forced to 0 V
and 0.6 V applied at RD1
or CC2
SID.PD.6 RAPower cable termination 0.8 1.0 1.2 kΩ
All supplies forced to 0 V
and 0.2 V applied at
VCONN1 or VCONN2
SID.PD.7 Ra_OFF Power cable termination -
Disabled 0.4 0.75 –MΩ
2.7 V applied at VCONN1
or VCONN2 with RA
disabled
SID.PD.8 Rleak_1 VCONN leaker for 0.1-µF load – – 216 kΩ
Managed Active Cable
(MAC) discharge
SID.PD.9 Rleak_2 VCONN leaker for 0.5-µF load – – 41.2 kΩ
SID.PD.10 Rleak_3 VCONN leaker for 1.0-µF load – – 19.6 kΩ
SID.PD.11 Rleak_4 VCONN leaker for 2.0-µF load – – 9.8 kΩ
SID.PD.12 Rleak_5 VCONN leaker for 5.0-µF load – – 4.1 kΩ
SID.PD.13 Rleak_6 VCONN leaker for 10-µF load – – 2.0 kΩ
SID.PD.14 Ileak Leaker on VCONN1 and VCONN2
for discharge upon cable detach 150 – – µA –
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 27 of 36
Analog-to-Digital Converter
Table 25. ADC DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.ADC.1 Resolution ADC resolution – 8 – bits Guaranteed by characterization
SID.ADC.2 INL Integral non-linearity –1.5 –1.5 LSB Guaranteed by characterization
SID.ADC.3 DNL Differential non-linearity –2.5 –2.5 LSB Guaranteed by characterization
SID.ADC.4 Gain Error Gain error –1 – 1 LSB Guaranteed by characterization
Table 26. ADC AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.ADC.5 SLEW_Max Rate of change of sampled voltage
signal – – 3 V/ms Guaranteed by characterization
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 28 of 36
Ordering Information
The EZ-PD CCG2 part numbers and features are listed in Table 27.
Ordering Code Definitions
Table 27. EZ-PD CCG2 Ordering Information
Part Number Application Type-C Ports Termination Resistor Role Package
CYPD2103-20FNXIT Cable 1 RA[4] Cable 20-ball CSP
CYPD2103-14LHXIT Cable 1 RA[4] Cable 14-pin DFN
CYPD2104-20FNXIT Accessory 1 RD[5] Accessory 20-ball CSP
CYPD2105-20FNXIT Active Cable 1 RA[4] Active Cable 20-ball CSP
CYPD2119-24LQXIT C-DP 1 RD[5] UFP 24-pin QFN
CYPD2120-24LQXIT C-HDMI 1 RD[5] UFP 24-pin QFN
CYPD2121-24LQXIT Dock/Monitor Upstream port 1 RP[6], RD[5] DRP 24-pin QFN
CYPD2122-20FNXIT Tablet 1 RP[6], RD[5] DRP 20-ball CSP
CYPD2122-24LQXI Notebook 1 RP[6], RD[5] DRP 24-pin QFN
CYPD2122-24LQXIT Notebook 1 RP[6], RD[5] DRP 24-pin QFN
CYPD2125-24LQXIT Dock/Monitor Downstream port 1 RP[6] DFP 24-pin QFN
CYPD2134-24LQXIT DFP 1 RP[6] DFP 24-pin QFN
CYPD2134-24LQXQT DFP 1 RP[6] DFP 24-pin QFN
T = Tape and Reel
Temperature Grade:
I = Industrial (40 °C to 85 °C), Q = Extended Industrial (40 °C to105 °C)
Pb-free
Package Type: XX = FN, LH or LQ
FN = CSP; LH = DFN; LQ = QFN
Number of pins in the package: XX = 14, 20, or 24
Device Role: Unique combination of role and termination:
X = 0 or 1 or 2 or 3 or 4 or 5 or 9
Feature: Unique Applications:
X = 0 or 1 or 2 or 3
Number of Type-C Ports: 1 = 1 Port
Product Type: 2 = Second-generation product family, CCG2
Marketing Code: PD = Power Delivery product family
Company ID: CY = Cypress
CY XX
PD 21XXX
-I
XX T
Notes
4. Termination resistor denoting an EMCA.
5. Termination resistor denoting an accessory or upstream facing port.
6. Termination resistor denoting a downstream facing port.
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 29 of 36
Packaging
Table 28. Package Characteristics
Parameter Description Conditions Min Typ Max Units
TAOperating ambient temperature Industrial –40 25 85 °C
Extended Industrial 105 °C
TJOperating junction temperature Industrial –40 – 100 °C
Extended Industrial 125 °C
TJA Package JA (20-ball WLCSP) – – 66 – °C/W
TJC Package JC (20-ball WLCSP) – – 0.7 – °C/W
TJA Package JA (14-pin DFN) – – 31 – °C/W
TJC Package JC (14-pin DFN) – – 59 – °C/W
TJA Package JA (24-pin QFN) – – 22 – °C/W
TJC Package JC (24-pin QFN) – – 29 – °C/W
Table 29. Solder Reflow Peak Temperature
Package Maximum Peak Temperature Maximum Time within 5 °C of Peak Temperature
20-ball WLCSP 260 °C 30 seconds
14-pin DFN 260 °C 30 seconds
24-pin QFN 260 °C 30 seconds
Table 30. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package MSL
20-ball WLCSP MSL 1
14-pin DFN MSL 3
24-pin QFN MSL 3
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 30 of 36
Figure 17. 20-ball WLCSP (1.63 × 2.03 × 0.55 mm) FN20B Package Outline, 001-95010
001-95010 *B
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 31 of 36
Figure 18. 14-pin DFN (2.5 × 3.5 × 0.6 mm), LH14A, 0.95 × 3.00 E-Pad (Sawn) Package Outline, 001-96312
Figure 19. 24-Pin QFN (4 × 4 × 0.55 mm), LQ24A, 2.65 × 2.65 E-Pad (Sawn) Package Outline, 001-13937
001-96312 **
001-13937 *G
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 32 of 36
Acronyms
Table 31. Acronyms Used in this Document
Acronym Description
ADC analog-to-digital converter
API application programming interface
ARM®advanced RISC machine, a CPU architecture
CC configuration channel
CCG2 Cable Controller Generation 2
CPU central processing unit
CRC cyclic redundancy check, an error-checking
protocol
CS current sense
DFP downstream facing port
DIO digital input/output, GPIO with only digital capabil-
ities, no analog. See GPIO.
DRP dual role port
EEPROM electrically erasable programmable read-only
memory
EMCA
a USB cable that includes an IC that reports cable
characteristics (e.g., current rating) to the Type-C
ports
EMI electromagnetic interference
ESD electrostatic discharge
FPB flash patch and breakpoint
FS full-speed
GPIO general-purpose input/output
IC integrated circuit
IDE integrated development environment
I2C, or IIC Inter-Integrated Circuit, a communications
protocol
ILO internal low-speed oscillator, see also IMO
IMO internal main oscillator, see also ILO
I/O input/output, see also GPIO
LVD low-voltage detect
LVTTL low-voltage transistor-transistor logic
MCU microcontroller unit
NC no connect
NMI nonmaskable interrupt
NVIC nested vectored interrupt controller
opamp operational amplifier
OCP overcurrent protection
OVP overvoltage protection
PCB printed circuit board
PD power delivery
PGA programmable gain amplifier
PHY physical layer
POR power-on reset
PRES precise power-on reset
PSoC®Programmable System-on-Chip™
PWM pulse-width modulator
RAM random-access memory
RISC reduced-instruction-set computing
RMS root-mean-square
RTC real-time clock
RX receive
SAR successive approximation register
SCL I2C serial clock
SDA I2C serial data
S/H sample and hold
SPI Serial Peripheral Interface, a communications
protocol
SRAM static random access memory
SWD serial wire debug, a test protocol
TX transmit
Type-C
a new standard with a slimmer USB connector and
a reversible cable, capable of sourcing up to
100 W of power
UART Universal Asynchronous Transmitter Receiver, a
communications protocol
USB Universal Serial Bus
USBIO USB input/output, CCG2 pins used to connect to a
USB port
XRES external reset I/O pin
Table 31. Acronyms Used in this Document (continued)
Acronym Description
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 33 of 36
Document Conventions
Units of Measure
Table 32. Units of Measure
Symbol Unit of Measure
°C degrees Celsius
Hz hertz
KB 1024 bytes
kHz kilohertz
kkilo ohm
Mbps megabits per second
MHz megahertz
Mmega-ohm
Msps megasamples per second
µA microampere
µF microfarad
µs microsecond
µV microvolt
µW microwatt
mA milliampere
ms millisecond
mV millivolt
nA nanoampere
ns nanosecond
ohm
pF picofarad
ppm parts per million
ps picosecond
ssecond
sps samples per second
Vvolt
Table 32. Units of Measure (continued)
Symbol Unit of Measure
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 34 of 36
References and Links To Applications Collaterals
Knowledge Base Articles
■Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and
CCG4 - KBA210740
■Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™
CCG4 Using PSoC® Programmer and MiniProg3 - KBA96477
■CCGX Frequently Asked Questions (FAQs) - KBA97244
■Handling Precautions for CY4501 CCG1 DVK - KBA210560
■Cypress EZ-PD™ CCGx Hardware - KBA204102
■Difference between USB Type-C and USB-PD - KBA204033
■CCGx Programming Methods - KBA97271
■Getting started with Cypress USB Type-C Products -
KBA04071
■Type-C to DisplayPort Cable Electrical Requirements
■Dead Battery Charging Implementation in USB Type-C
Solutions - KBA97273
■Termination Resistors Required for the USB Type-C Connector
– KBA97180
■VBUS Bypass Capacitor Recommendation for Type-C Cable
and Type-C to Legacy Cable/Adapter Assemblies – KBA97270
■Need for Regulator and Auxiliary Switch in Type-C to
DisplayPort (DP) Cable Solution - KBA97274
■Need for a USB Billboard Device in Type-C Solutions –
KBA97146
■CCG1 Devices in Type-C to Legacy Cable/Adapter Assemblies
– KBA97145
■Cypress USB Type-C Controller Supported Solutions –
KBA97179
■Termination Resistors for Type-C to Legacy Ports – KBA97272
■Handling Instructions for CY4502 CCG2 Development Kit –
KBA97916
■Thunderbolt™ Cable Application Using CCG3 Devices -
KBA210976
■Power Adapter Application Using CCG3 Devices - KBA210975
■Methods to Upgrade Firmware on CCG3 Devices - KBA210974
■Device Flash Memory Size and Advantages - KBA210973
■Applications of EZ-PD™ CCG4 - KBA210739
Application Notes
■AN96527 - Designing USB Type-C Products Using Cypress’s
CCG1 Controllers
■AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™
CCG2
■AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2
■AN210403 - Hardware Design Guidelines for Dual Role Port
Applications Using EZ-PD™ USB Type-C Controllers
■AN210771 - Getting Started with EZ-PD™ CCG4
Reference Designs
■EZ-PD™ CCG2 Electronically Marked Cable Assembly
(EMCA) Paddle Card Reference Design
■EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution
■CCG1 USB Type-C to DisplayPort Cable Solution
■CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution
■EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution
■CCG1 Electronically Marked Cable Assembly (EMCA) Paddle
Card Reference Design
■CCG1 USB Type-C to Legacy USB Device Cable Paddle Card
Reference Schematics
■EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle
■EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution
■CCG2 20W Power Adapter Reference Design
■CCG2 18W Power Adapter Reference Design
■EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference
Design Kit
Kits
■CY4501 CCG1 Development Kit
■CY4502 EZ-PD™ CCG2 Development Kit
■CY4531 EZ-PD CCG3 Evaluation Kit
■CY4541 EZ-PD™ CCG4 Evaluation Kit
Datasheets
■CCG1 Datasheet: USB Type-C Port Controller with Power
Delivery
■CYPD1120 Datasheet: USB Power Delivery Alternate Mode
Controller on Type-C
■CCG3: USB Type-C Controller Datasheet
■CCG4: Two-Port USB Type-C Controller Datasheet
EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *M Page 35 of 36
Document History Page
Description Title: EZ-PD™ CCG2 Datasheet USB Type-C Port Controller
Document Number: 001-93912
Revision ECN Orig. of
Change
Submission
Date Description of Change
*E 4680071 GAYA 03/07/2015 Release to web
*F 4718374 AKN 04/09/2015 Added 24-pin QFN pin and package information.
Added DRP and DFP Application diagrams
*G 4774142 AKN 06/15/2015
Changed datasheet status from Preliminary to Final.
Updated Logic Block Diagram.
Changed number of GPIOs to 10 and added a note about the number of GPIOs
varying depending on the package.
Updated Power and Digital Peripherals section.
Updated Application diagrams.
Added SID.PWR#1_A parameter.
Added CYPD2122-20FNXIT part in Ordering Information.
Removed Errata.
*H 4979175 VGT 10/23/2015
Updated Figure 1 and Figure 5.
Added VCC_ABS spec and updated the SID.ADC.4 parameter.
Added “Guaranteed by characterization” note for the following specs:
SID.GIO#16, SID.GIO#17, SID.XRES#3, SID 160 to SID 172A, SID 2226, SID
229, SID.ADC.1 to SID.ADC.5.
*I 5028128 VGT 12/04/2015
Updated Application Diagrams:
Added Figure 14.
Added Figure 15.
Added Figure 16.
Updated Ordering Information.
Added part numbers CYPD2119-24LQXIT, CYPD2120-24LQXIT,
CYPD2121-24LQXIT, CYPD2125-24LQXIT.
*J 5186972 VGT 03/28/2016
Updated temperature ranges in Features.
Updated Ta b le 28.
Updated Ordering Information.
*K 5303957 VGT 06/13/2016
Added Available Firmware and Software Tools.
Updated Figure 8: Per the USB PD3.0 spec, SOP” implementation is no longer
valid for passive cables.
Updated Figure 11, Figure 12, and Figure 13.
Added descriptive notes for the application diagrams.
Added References and Links To Applications Collaterals.
Updated Ordering Information.
Updated Cypress logo and copyright information.
*L 5387677 VGT 08/02/2016 Added CYPD2122-24LQXI part number in Ordering Information.
*M 6097993 VGT 07/11/2018
Added Figure 8 and Figure 10.
Updated the title of Figure 7 and Figure 9.
Added “Note: Application diagram in Figure 8 requires external diodes to
operate in the extended VCONN voltage range of 2.7V to 5.5V” in Application
Diagrams.
Updated Figure 17 (Spec 001-95010 from *A to *B).
Updated Figure 19 (Spec 001-13937 from *F to *G).
Added compliance to USB Specification.
Updated Cypress Logo and Copyright year.
EZ-PD™ CCG2 Datasheet
© Cypress Semiconductor Corporation 2014-2018 This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
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provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device
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shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-93912 Rev. *M Revised July 11, 2018 Page 36 of 36
Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB
Type-C™ Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third party software tools, including sample code, to modify
the firmware for Cypress USB products. Modification of such firmware could cause the firmware/hardware combination to no longer comply with the relevant USB-IF specification. You are solely
responsible ensuring the compliance of any modifications you make, and you must follow the compliance requirements of USB-IF before using any USB-IF trademarks or logos in connection with any
modifications you make. In addition, if Cypress modifies firmware based on your specifications, then you are responsible for ensuring compliance with any desired standard or specifications as if you
had made the modification. CYPRESS IS NOT RESPONSIBLE IN THE EVENT THAT YOU MODIFY OR HAVE MODIFIED A CERTIFIED CYPRESS PRODUCT AND SUCH MODIFIED PRODUCT
NO LONGER COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS.
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