DRAM MODULE M372C0805BT0-C
Buffered 8Mx72 DIMM
Revision 0.1
June 1998
(4Mx16 & 4Mx4 base)
DRAM MODULE M372C0805BT0-C
Revision History
Version 0.0 (Sept. 1997)
• Removed two AC parameters tCACP(access time from CAS) and tAAP(access time from col. addr.) in AC CHARACTERISTICS.
• Changed the parameter tCAC(access time from CAS) from 18ns to 20ns @ -5 in AC CHARACTERISTICS.
Version 0.1 (June 1998)
• The 3rd.(4th.) generation of 64M(16M) DRAM components are applied for this module.
DRAM MODULE M372C0805BT0-C
M372C0805BT0-C Fast Page Mode
8M x 72 DRAM DIMM with ECC Using 4Mx16 & 4Mx4, 4K Refresh, 5V
The Samsung M372C0805BT0-C is a 8Mx72bits Dynamic
RAM high density memory module. The Samsung
M372C0805BT0-C consists of eight 4Mx16bits & four
4Mx4bits CMOS DRAMs in TSOP-II 400mil packages and two
16 bits driver IC in TSSOP package mounted on a 168-pin
glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor
is mounted on the printed circuit board for each DRAM. The
M372C0805BT0-C is a Dual In-line Memory Module and is
intended for mounting into 168 pin edge connector sockets.
GENERAL DESCRIPTION
PD Note :PD & ID Terminals must each be pulled up through a register to VCC at the next higher
level assembly. PDs will be either open (NC) or driven to VSS via on-board buffer circuits.
ID Note : IDs will be either open (NC) or connected directly to VSS without a buffer.
• Part Identification
- M372C0805BT0-C (4096cycles/64ms Ref. TSOP ll)
• Fast Page Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
• TTL compatible inputs and outputs
• Single 5V±10% power supply
• JEDEC standard pinout & Buffered PDpin
• Buffered input except RAS and DQ
• PCB : Height(1000mil), double sided component
PIN NAMES
Pins marked ′*′ are not used in this module.
Pin Names Function
A0, B0, A1 - A11 Address Input(4K ref.)
DQ0 - DQ71 Data In/Out
W0, W2 Read/Write Enable
OE0, OE2 Output Enable
RAS0 - RAS3 Row Address Strobe
CAS0, 1,4,5 Column Address Strobe
VCC Power(+5V)
VSS Ground
NC No Connection
PDE Presence Detect Enable
PD1 - 8 Presence Detect
ID0 - 1 ID bit
RSVD Reserved Use
RFU Reserved for Future Use
PD & ID Table
PD : 0 for Vol of Drive IC & 1 for N.C
ID : 0 for Vss & 1 for N.C
Pin 50NS 60NS
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
0
0
1
1
0
0
0
0
0
0
1
1
0
1
1
0
ID0
ID1 0
00
0
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
DQ16
DQ17
VSS
RSVD
RSVD
VCC
W0
CAS0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
*CAS2
RAS0
OE0
VSS
A0
A2
A4
A6
A8
A10
A12
VCC
RFU
RFU
VSS
OE2
RAS2
CAS4
*CAS6
W2
VCC
RSVD
RSVD
DQ18
DQ19
VSS
DQ20
DQ21
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ22
DQ23
VCC
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
VSS
DQ28
DQ29
DQ30
DQ31
VCC
DQ32
DQ33
DQ34
DQ35
VSS
PD1
PD3
PD5
PD7
ID0
VCC
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
VSS
DQ36
DQ37
DQ38
DQ39
VCC
DQ40
DQ41
DQ42
DQ43
DQ44
VSS
DQ45
DQ46
DQ47
DQ48
DQ49
VCC
DQ50
DQ51
DQ52
DQ53
VSS
RSVD
RSVD
VCC
RFU
CAS1
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
*CAS3
RAS1
RFU
VSS
A1
A3
A5
A7
A9
A11
*A13
VCC
RFU
B0
VSS
RFU
RAS3
CAS5
*CAS7
PDE
VCC
RSVD
RSVD
DQ54
DQ55
VSS
DQ56
DQ57
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ58
DQ59
VCC
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ62
DQ63
VSS
DQ64
DQ65
DQ66
DQ67
VCC
DQ68
DQ69
DQ70
DQ71
VSS
PD2
PD4
PD6
PD8
ID1
VCC
PERFORMANCE RANGE
Speed tRAC tCAC tRC tPC
-C50 50ns 18ns 90ns 35ns
-C60 60ns 20ns 110ns 40ns
FEATURES
DRAM MODULE M372C0805BT0-C
DQ16-DQ19
DQ20-DQ35
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
0.1 or 0.22uF Capacitor
under each DRAM To all DRAMs
A0
B0
A1-A11
W0, OE0
W2, OE2
U0-U2,U6-U8
U3-U5,U9-U11
U0-U11
U0-U2,U6-U8
U3-U5,U9-U11
RAS0
W0
OE0
A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CAS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A1-A11
DQ0
DQ1
DQ2
DQ3
U0
U1
U2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
U6
U7
U8
RAS3
W2
OE2
B0
CAS4
A1-A11
RAS1
DQ52-DQ55
DQ56-DQ71
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
U3
U4
U5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
U9
U10
U11
RAS2
CAS1 CAS5
DQ0-DQ15 DQ36-DQ51
DRAM MODULE M372C0805BT0-C
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one Fast Page mode cycle time, tPC.
* NOTE :
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
ICC1*
ICC2
ICC3*
ICC4*
ICC5
ICC6*
I(IL)
I(OL)
VOH
VOL
Symbol Speed M372C0805BT0 Unit
Min Max
ICC1 -50
-60 -
-760
700 mA
mA
ICC2 Don′t care -100 mA
ICC3 -50
-60 -
-760
700 mA
mA
ICC4 -50
-60 -
-540
480 mA
mA
ICC5 Don′t care -30 mA
ICC6 -50
-60 -
-760
700 mA
mA
II(L)
IO(L) Don′t care -10
-10 10
10 uA
uA
VOH
VOL Don′t care 2.4
--
0.4 V
V
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
Item Symbol Rating Unit
Voltage on any pin relative VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Output Current
VIN, VOUT
VCC
Tstg
PD
IOS
-1 to +7.0
-1 to +7.0
-55 to +125
12
50
V
V
°C
W
mA
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
*1 : VCC+2.0V at pulse width≤20ns, which is measured at VCC.
*2 : -2.0V at pulse width≤20ns, which is measured at VSS.
Item Symbol Min Typ Max Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
4.5
0
2.4
-1.0*2
5.0
0
-
-
5.5
0
VCC*1
0.8
V
V
V
V
: Operating Current * (RAS, CAS, Address cycling @tRC=min)
: Standby Current (RAS=CAS=W=VIH)
: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
: Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
: Input Leakage Current (Any input 0≤VIN≤Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V≤VOUT≤Vcc)
: Output High Voltage Level (IOH = -5mA)
: Output Low Voltage Level (IOL = 4.2mA)
DRAM MODULE M372C0805BT0-C
CAPACITANCE (TA = 25°C, f = 1MHz)
Item Symbol Min Max Unit
Input capacitance[A0, B0, A1 - A11]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0 - RAS3]
Input capacitance[CAS0, 1,4,5]
Input/Output capacitance[DQ0 - 71]
CIN1
CIN2
CIN3
CIN4
CDQ
-
-
-
-
-
20
20
31
20
24
pF
pF
pF
pF
pF
Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF
Parameter Symbol -50 -60 Unit Note
Min Max Min Max
Random read or write cycle time tRC 90 110 ns
Read-modify-write cycle time tRWC 133 155 ns
Access time from RAS tRAC 50 60 ns 3,4
Access time from CAS tCAC 18 20 ns 3,4,5,11
Access time from column address tAA 30 35 ns 3,10,11
CAS to output in Low-Z tCLZ 5 5 ns 3,11
Output buffer turn-off delay tOFF 518 520 ns 6,11
Transition time(rise and fall) tT150 150 ns 2
RAS precharge time tRP 30 40 ns
RAS pulse width tRAS 50 10K 60 10K ns
RAS hold time tRSH 18 20 ns 11
CAS hold time tCSH 45 55 ns 11
CAS pulse width tCAS 13 10K 15 10K ns
RAS to CAS delay time tRCD 18 32 18 40 ns 4,11
RAS to column address delay time tRAD 13 20 13 25 ns 10,11
CAS to RAS precharge time tCRP 10 10 ns 11
Row address set-up time tASR 5 5 ns 11
Row address hold time tRAH 8 8 ns 11
Column address set-up time tASC 0 0 ns 12
Column address hold time tCAH 10 10 ns 12
Column address to RAS lead time tRAL 30 35 ns 11
Read command set-up time tRCS 0 0 ns
Read command hold referencde to CAS tRCH 0 0 ns 8
Read command hold referenced to RAS tRRH -2 -2 ns 8,11
Write command hold time tWCH 10 10 ns
Write command pulse width tWP 10 10 ns
Write command to RAS lead time tRWL 20 20 ns 11
Write command to CAS lead time tCWL 13 15 ns 15
Data in set-up time tDS -2 -2 ns 9,11
Data in hold time tDH 15 15 ns 9,11
Refresh period tREF 64 64 ms
Write command set-up time tWCS 0 0 ns 7
CAS to W delay time tCWD 36 40 ns 7,15
Column address to W delay time tAWD 48 55 ns 7
CAS prechange to W delay time tCPWD 53 60 ns 7
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
DRAM MODULE M372C0805BT0-C
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
Parameter Symbol -50 -60 Unit Note
Min Max Min Max
RAS ro W delay time tRWD 73 85 ns 7,11
CAS setup time(CAS-before-RAS refresh) tCSR 10 10 ns 11,16
CAS hold time(CAS-before-RAS refresh) tCHR 8 8 ns 11
RAS to CAS precharge time tRPC 3 3 ns 11
Access time from CAS precharge tCPA 35 40 ns 3,11
Fast page mode cycle time tPC 35 40 ns
Fast page mode read-modify-write cycle time tPRWC 76 85 ns
CAS precharge time(Fast page cycle) tCP 10 10 ns 13
RAS pulse width(Fast page cycle) tRASP 50 200K 60 200K ns
RAS hold time from CAS precharge tRHCP 35 40 ns 11
W to RAS precharge time(C-B-R refresh) tWRP 15 15 ns 11
W to RAS hold time(C-B-R refresh) tWRH 8 8 ns 11
OE access time tOEA 18 20 ns 11
OE to data delay tOED 18 20 ns 11
Output buffer turn off delay time from OE tOEZ 518 520 ns 11
OE command hold time tOEH 13 15 ns
PDE to Valid PD bit tPD 10 10 ns
PDE to PD bit Inactive tPDOFF 2 7 2 7 ns
Present Detect Read Cycle
DRAM MODULE M372C0805BT0-C
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref-
erence levels for measuring timing of input signals. Transition
times are measured between VIH(min) and VIL(max) and are
assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
Assumes that tRCD≥tRCD(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operat-
ing parameter. They are included in the data sheet as electri-
cal characteristics only. If tWCS≥tWCS(min) the cycle is an
early write cycle and the data out pin will remain high imped-
ance for the duration of the cycle. If tRWD≥tRWD(min),
tCWD≥tCWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min).
The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data
out(at access time) is indeterminate.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles.
Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
tASC, tCAH are referenced to the earlier CAS falling edge.
tCP is specified from the last CAS rising edge in the previous
cycle to the first CAS falling edge in the next cycle.
tCWD is referenced to the later CAS falling edge at word read-
modify-write cycle.
tCWL is specified from W falling edge to the earlier CAS rising
edge.
tCSR is referenced to earlier CAS falling low before RAS tran-
sition low.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DRAM MODULE M372C0805BT0-C
tCRP
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VOH -
VOL -
DQ
READ CYCLE
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCRP
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC tCAH
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN DATA-OUT
tOEZ
tRRH tRCH
Don′t care
Undefined
tRCS
tOFF
DRAM MODULE M372C0805BT0-C
tWCS
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VIH -
VIL -
DQ
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCRP
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC tCAH
tCRP
tWP
tDS tDH
tWCH
tCWL
tRWL
Don′t care
DATA-IN
Undefined
DRAM MODULE M372C0805BT0-C
tOED
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VIH -
VIL -
DQ
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCRP
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC tCAH
tCRP
DATA-IN
tWP
Don′t care
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tCWL
tRWL
tDS tDH
tOEH
Undefined
DRAM MODULE M372C0805BT0-C
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VI/OH -
VI/OL -
DQ
ROW
ADDR
tRAS tRWC tRP
tRSHtRCD tCAS
tCSH
tRAD
tASR tRAH tASC tCAH
tCRP
VALID
tWP
Don′t care
READ - MODIFY - WRTIE CYCLE
tRWL
tCWL
tOEZ
tOEA
tOED
tAWD
tCWD
tRWD
DATA-OUT
Undefined
VALID
DATA-IN
tRAC
tAA tCAC
tCLZ
tDS tDH
COLUMN
ADDRESS
DRAM MODULE M372C0805BT0-C
tRCH
tOEZ
tCLZ
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VOH -
VOL -
DQ
COLUMN
ADDRESS
ROW
ADDR
tRHCP
tRASP
tCAS
tASC
tRAD
tASR tRAH
tASC
tCAH
tCRP
VALID
Don′t care
FAST PAGE READ CYCLE
tOEZ
tRRH
DATA-OUT
Undefined
VALID
DATA-OUT
NOTE : DOUT = OPEN
COLUMN
ADDRESS COLUMN
ADDRESS
tRSH
tCAS
tRCD
tPC
¡ó
tCSH tCAH tASC tCAH
¡ó
¡ó
¡ó
tRCH
¡ó
tRCS tRCStRCS
tOEA
tCAC tOEA
tCAC tOEA
tCAC
VALID
DATA-OUT
tCLZ
tOFF
tAA tOFF
tAA
tCLZ tOFF
tOEZ
tRAC
tAA
¡ó
¡ó
tCP
tCAS
tRP
tCP
DRAM MODULE M372C0805BT0-C
tASC
tCAH
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VIH -
VIL -
DQ
COLUMN
ADDRESS
ROW
ADDR
tRHCP
tRASP
tCAS
tRAD
tASR tRAH
tASC
tCRP
VALID
Don′t care
FAST PAGE WRITE CYCLE ( EARLY WRITE )
DATA-IN
Undefined
VALID
DATA-IN
tDS
NOTE : DOUT = OPEN
COLUMN
ADDRESS COLUMN
ADDRESS
tRSH
tCAS
tRCD
tPC
¡ó
tCSH tCAH tASC tCAH
¡ó
¡ó
¡ó
tWCS tWCH
tWCS
VALID
DATA-IN
¡ó
¡ó
tWP
tCWL
tWP
tWCH
tWP
tWCS tWCH
tCWL
tRWL
tCWL
tDH tDS tDH tDS tDH
¡ó
¡ó
¡ó
tRP
tCP
tCP
tCAS
tPC
DRAM MODULE M372C0805BT0-C
tCAC
tASCtASC
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VI/OH -
VI/OL -
DQ
ROW
ADDR
tCSH tRASP
tASR
VALID
Don′t care
FAST PAGE READ - MODIFY - WRITE CYCLE
DATA-OUT
Undefined
tRCD tCP
tRAD
tCAH
tWP
tDH
COL.
ADDR COL.
ADDR
tCAS tCAS
tCRP
tCAH tRAL
tPRWC
tRCS tCWL
tCWD
tAWD
tRWD
tWP
tCWD
tAWD
tCWL
tAA
tRAC
tOEA
tCLZ
tCAC
tOEZ
tCPWD
tOED
VALID
DATA-IN VALID
DATA-OUT VALID
DATA-IN
tCLZ
tDS
tOEA
tAA tDH
tDS
tOEZ
tOED
tRWL
tRP
tRSH
tRAH
DRAM MODULE M372C0805BT0-C
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL - ROW
ADDR
tRAS tRC tRP
tASR tRAH
tCRP
Don′t care
RAS - ONLY REFRESH CYCLE
Undefined
NOTE : W, OE, DIN = Don′t care
DOUT = OPEN
tRPC tCRP
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don′t care
RAS VIH -
VIL -
CAS VIH -
VIL -
tRAS tRC tRP
tWRP
tRPC
tRP
tCP
tCHR
tCSR
WVIH -
VIL -
tWRH
tOFF
tRPC
VOH -
VOL -
DQ OPEN
DRAM MODULE M372C0805BT0-C
tWRH
tOFF
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VOH -
VOL -
DQ
HIDDEN REFRESH CYCLE ( READ )
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCHRtRCD
tRAD
tASR tRAH tASC tCAH
tCRP
tRCS
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN
tRRH
Don′t care
tRSH
tOEZ
tWRP
Undefined
tRC
DATA-OUT
tRP tRP
tRAS
DRAM MODULE M372C0805BT0-C
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VIH -
VIL -
DQ
HIDDEN REFRESH CYCLE ( WRITE )
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCHR
tRCD
tRAD
tASR tRAH tASC tCAH
tCRP
Don′t care
tRSH
DATA-IN
tWRP
tWRH
Undefined
tRC
NOTE : DOUT = OPEN
tWCH
tWP
tDH
tRPtRP tRAS
tDS
tWCS
DRAM MODULE M372C0805BT0-C
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL - COLUMN
ADDRESS
tRAS
tRSH
tCHR
tRAL
tCSR tCPT
tRP
tCAS
tASC tCAH
READ CYCLE
VOH -
VOL - DATA-OUT
DQ
tOFF
tCLZ
WRITE CYCLE
VIH -
VIL - DATA-IN
DQ
tDH
tDS
WVIH -
VIL - tWP
tCWD
tCWL
tRWL
READ-MODIFY-WRITE tAWD
VIH -
VIL -
OE
tOEA
tAA
tCAC
tDS
tDH
VALID
DATA-OUT
VI/OH -
VI/OL -
DQ
Don′t care
Undefined
VIH -
VIL -
OE
tOEA tOEZ
OE VIH -
VIL -
tRCS
tCLZ tOEZ
tOED
tWRP tWRH tRRH
tRCH
tRCS tCAC
tAA
VIH -
VIL -
W
tWRP tWRH
tWCS tWCH
tCWL
VIH -
VIL -
W
tWP
tRWL
tWRP tWRH
VALID
DATA-IN
NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM.
DRAM MODULE M372C0805BT0-C
Don′t care
Undefined
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don′t care
RAS VIH -
VIL -
CAS VIH -
VIL -
tRASS tRPS
tRPC
tWRP
tCHS
tRP
tCP
tCSR
WVIH -
VIL -
tWRH
tOFF
tRPC
OPEN
VOH -
VOL -
DQ
TEST MODE IN CYCLE
NOTE : OE, A = Don′t care
RAS VIH -
VIL -
CAS VIH -
VIL -
tRAS tRC tRP
tRPC
tWTS
tRPC
tRP
tCP
tCHR
tCSR
WVIH -
VIL -
tWTH
tOFF
OPEN
VOH -
VOL -
DQ
DRAM MODULE M372C0805BT0-C
PACKAGE DIMENSIONS
5.250
5.014
Units : Inches (millimeters)
0.050
0.039±.002
0.01Max
(0.25 Max)
R 0.079
(R 2.000)
0.250
(6.350)
1.450
(36.830) 2.150
(54.61)
0.350
0.100Min
(2.540Min)
0.700
(17.780)
(1.000±.050)
(1.270)
0.100 Min
(2.540 Min)
Detail C
.118DIA±.004
(3.000DIA±.100)
(8.890)
A B C
0.250
(6.350)
.450
(11.430) 4.550
(115.57)
0.157±0.004
(4.000±0.100)
0.054
(1.372)
(127.350)
(133.350)
1.000
(25.40)
0.118
(3.000)
0.250
(6.350)
Detail A
0.1230±.0050
(3.125±.125)
Detail B
0.079±.0040
(2.000±.100)
Tolerances : ±.005(.13) unless otherwise specified
The used device is 4Mx16 & 4Mx4 DRAM with Fast Page mode, TSOP II.
DRAM Part No. : M372C0805BT0 -K4F641611B & K4F170411C
0.118
(3.000)
0.250
(6.350)
0.1230±.0050
(3.125±.125)
0.079±.0040
(2.000±.100)
0.150Max
(3.81Max)
0.050±0.0039
(1.270±0.10)
0.157 Min
(3.99 Min)
( Back view )
( Front view )
