24AA65/P - Microchip - Pdf.Support

24AA65/24LC65/24C65

Device Selection Table

Features:

• Voltage Operating Range: 1.8V to 6.0V

- Peak writ e curr ent 3 mA at 6.0V

- Maximum read current 150 μA at 6.0V

- Standby current 1 μA, typical

• Industry Standard Two-Wire Bus Protocol I2C™

Compatible

• 8-B yte Page, or Byte mo des Availab le

• 2 ms Typical Write Cycle Time, Byte or Page

• 64-Byte Input Cache for Fast Write Loads

• Up to 8 devices may be connected to the same

bus for up to 512K bits total memory

• Including 100 kHz (1.8V ≤ Vcc < 4.5V) and 400

kHz (4.5V ≤ VCC ≤ 6.0V) Comp atibilit y

• Programmable Block Security Options

• Programmable Endurance Options

• Schmitt Trigger, Filtered Inputs for Noise

Suppression

• Output Slop e Control t o El im ina te Gro und Bounce

• Self-Timed Erase and Write Cycles

• Power-on/off Data Protection Circuitry

• Endurance:

- 10,000,000 E/W cy cles for a High Endura nce

Block

- 1,000,000 E/W cycles for a Standard

Endurance Block

• Electros t atic Discha rge Prote cti on > 4000V

• Data Retention > 200 years

• 8-pin PDIP/SOIJ Packages

• Temperature Ranges

• Pb-Free and RoHS Compliant

Description:

The Microchip Technology Inc. 24AA65/24LC65/

24C65 (2 4XX6 5)* is a “sm art ” 8K x 8 Seria l Ele ctrica ll y

Erasable PROM. This device has been developed for

advanced, low-power applications such as personal

communications, and provides the systems designer

with flexibility through the use of many new user-pro-

gramm able fea tures. The 24 XX65 offer s a reloca table

4K bit block of ultra-high-endurance memory for data

that chang es fr equ ent ly. Th e rem ain der of the arra y, or

60K bit s, is rated at 1, 000,000 era se/write (E/W) c ycles

ensured. The 24XX65 features an input cache for fast

wri te lo ad s wit h a capa ci ty of eig ht page s , or 64 b yt es.

This device also features programmable security

options for E/W protection of critical data and/or code

of up to fifteen 4K blocks. Functional address lines

allow the connection of up to eight 24XX65’s on the

same bus for up to 512K bits contiguous EEPROM

memory. Advanced CMOS technology makes this

device ideal for low-power nonvolatile code and data

applications. The 24XX65 is available in the standard

8-pin plastic DIP and 8-pin surface mount SOIJ

package.

Package Types

Part Number VCC Range Page Size Temp. Ranges Packages

24AA65 1.8-6.0V 64 Bytes C P, SM

24LC65 2.5-6.0V 64 Bytes C, I P, SM

24C65 4.5 -6.0V 64 Bytes C, I, E P, SM

- Industrial (I) -40°C to +85°C

- Automotive (E) -40°C to +125°C

24XX65

SCL

SDA

24XX65

SCL

SDA

PDIP

SOIJ

64K I2C™ Smart Serial™ EEPROM

*24XX65 is used in this document as a generic part

number for the 24AA65/24LC65/24C65 devices.

24AA65/24LC65/24C65

Block Diagram Pin Function Table

HV Generator

EEPROM

Array

Page Lat ches

YDEC

XDEC

Sense Amp.

R/W Control

Memory

Control

Logic

I/O

Control

Logic

SDA

SCL

VCC

VSS

I/O

A2A1A0

Cache

Name Function

A0, A1, A2 User Configurable Chip Selects

VSS Ground

SDA Serial Address/Data/I/O

SCL Serial Clock

VCC +1.8V to 6.0V Power Supply

NC No Internal Connection

24AA65/24LC65/24C65

1.0 ELECTRICAL CHARAC TERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins......................................................................................................................................................≥ 4 kV

TABLE 1-1: DC CHARACTERISTICS

FIGURE 1-1: BUS TIMING START/STOP

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This i s a stres s ratin g only and functio nal operati on of the devic e at thos e or any other co nditio ns abov e thos e

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability.

DC CHARACTERISTICS

VCC = +1.8V to +6.0V

Commercial (C): TA =0°C to +70°C

Industrial (I): TA =-40°C to +85°C

Automotive (E): TA =-40°C to +125°C

Parameter Sym Min Max Units Conditions

A0, A1, A2, SCL and SDA pins:

High-level input voltage

Low-level input voltage

Hyster es is of Sc hm itt Trigger inputs

Low-level output voltage

VIH

VIL

VHYS

VOL

.7 VCC

—

.05 VCC

—

.3 VCC

—

.40

V(Note 1)

IOL = 3.0 mA

Input leakage current ILI —±1μAVIN = .1V to VCC

Output lea ka ge current ILO —±1μAVOUT = .1V to VCC

Pin capacitance

(all inputs/ou tpu t s) CIN, COUT —10pFVCC = 5.0V (Note 1)

TA = 25°C, FCLK = 1 MHz

Operati ng current ICC Write

ICC Read —

—3

150 mA

μAVCC = 6.0V, SCL = 400 kHz

VCC = 6.0V, SCL = 400 kHz

Standby current ICCS —5μAVCC = 5.0V, SCL = SDA = VCC

A0, A1, A2 = VSS

Note 1: This parameter is periodically sampled and not 100% tested.

TSU:STA THD:STA

VHYS

TSU:STO

Start Stop

SCL

SDA

24AA65/24LC65/24C65

TABLE 1-2: AC CHARACTERISTICS

FIGURE 1-2: BUS TIMING DATA

Parameter Symbol VCC = 1.8V-6.0V

STD. Mode VCC = 4.5-6.0V

FAST Mode Units Remarks

Min Max Min Max

Clock frequency FCLK —100 — 400kHz

Clock high time THIGH 4000 — 600 — ns

Clock low time TLOW 4700 — 1300 — ns

SDA and SCL rise time TR— 1000 — 300 ns (Note 1)

SDA and SCL fall time TF— 300 — 300 ns (Note 1)

Start condition setup time THD:STA 4000 — 600 — ns After this peri od the firs t

clock pulse is generated

Start condition setup time TSU:STA 4700 — 600 — ns Only relevant for

repeated Start condition

Data input hold time THD:DAT 0— 0 —ns

Data input setup time TSU:DAT 250 — 100 — ns

Stop condition setup time TSU:STO 4000 — 600 — ns

Output valid from clock TAA — 3500 — 900 ns (Note 2)

Bus free time TBUF 4700 — 1300 — ns Time the bus must be

free before a new

transmission can start

Output fall time from VIH min to

VIL max TOF — 250 20 + 0.1

CB250 ns (Note 1), CB ≤ 100 pF

Input filter spike suppression

(SDA and SCL pins) TSP 50 — 50 — ns (Note 3)

Write cycle time TWR — 5 — 5 ms/page (Note 4)

Endurance

High Endurance Block

Rest of Array 10M

1M —

—10M

1M —

—cycles 25°C, (Note 5)

Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combi ne d TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a Ti specification for standard operation.

4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write

cache for total time.

5: This parameter is not tes ted but ensured by characterization. For endu rance estimates in a specif ic

applic ation, pleas e cons ult th e Total En duranc e™ Mod el whic h can be down loade d at www.microch ip.co m.

SCL

SDA

OUT

TSU:STA

TSP

TAA

TLOW

THIGH

THD:STA THD:DAT TSU:DAT TSU:STO

TBUF

TAA

24AA65/24LC65/24C65

2.0 FUNCTIONAL DESCRIPTION

The 24XX65 supports a bidirectional two-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, and a device

receiving data as receiver. The bus must be controlled

by a master device which generates the serial clock

(SCL), c ontrol s the bus acce ss a nd ge nerates the S tart

and Stop conditions , whil e the 24XX65 works as sl ave.

Both master and slave can operate as transmitter or

receive r, but the master device determines which mode

is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stab le when ever th e clock lin e is high . Change s in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figur e 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain high.

3.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.3 S top Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each dat a transf er is initiated w ith a S tart condition an d

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. Th e mast er device mus t ge nera te a n ex tra c lock

pulse which is associated with this Acknowledge bit.

A device that acknowledges must pull down the SDA

line during the Acknowledge clock pulse in such a way

that the SD A line is sta ble low d uring the high pe riod of

the ack nowledge relat ed clock pu lse. Of co urse, setup

and hold times must be taken into account. During

reads, a maste r mus t sign al an e nd of dat a to the sl ave

by NOT gene rating an Acknowl edge bit on the las t byte

that has been cl ocke d out o f the slave . In th is ca se , the

slave (24 XX65) mus t leav e the dat a line high to en able

the master to generate the Stop condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24XX65 does not generate any

Acknowledge bits if an internal program-

ming cycle is in prog res s.

SCL

SDA

(A) (B) (D) (D) (A)(C)

Start

Condition Address or

Acknowledge

Valid

Data

Allowed

To Change

Stop

Condition

24AA65/24LC65/24C65

3.6 Device Addressing

A control byte is the first byte received following the

S tar t condition from the m aster device . The co ntrol byte

consists of a four-bit control code, for the 24XX65 this

is set as ‘1010’ binary for read and write operations.

The next three bits of the control byte are the device

select bits (A2, A1, A0). They are used by the master

device to select which of the eight devices are to be

accessed. These bits are in effect the three Most

Significant bits of the word address. The last bit of the

control byte defines the operation to be performed.

When set to a one a read operation is selected, when

set to a z ero a wri te operation is sele cted. The n ext two

bytes received define the address of the first data byte

(Figure 4-1). Because only A12..A0 are used, the

upper three address bits must be zeros. The Most

Signific ant bit of the Most Significan t Byte is trans ferred

first. Following the Start condition, the 24XX65

monitors the SDA bus checking the device type

identifier being transmitted. Upon receiving a ‘1010’

code and appropriate device select bits, the slave

device (24XX65) output s an Acknowledge si gnal on the

SDA lin e. Dep en din g u pon the st ate of the R/W bi t, th e

24XX65 will select a read or write operation.

FIGURE 3-2: CONTROL BYTE

ALLOCATION

4.0 WRITE OPERATION

4.1 Byte Write

Following the Start condition from the master, the con-

trol code (four bits), the device select (three bits), and

the R/W bit which is a logic low, is placed onto the bus

by the master transmitter. This indicates to the

addressed slave receiver (24XX65) that a byte with a

word address will follow after it has generated an

Acknowledge bit during the ninth clock cycle. There-

fore, the next byte transmitted by the master is the

high-order byte of the word address and will be written

into the Address Pointer of the 24XX65. The next byte

is the Least Significant Address Byte. After receiving

another Acknowledge signal from the 24XX65, the

master device will transmit the data word to be written

into the addressed memory location. The 24XX65

acknowledges again and the master generates a Stop

condition. This initiates the internal write cycle, and

during this time the 24XX65 will not generate

Acknowledge signals (Figure 4-1).

4.2 Page Write

The write cont rol byte , word address and the first data

byte are transmitted to the 24XX65 in the same way as

in a byte write. But instead of generating a Stop

condition, the master transmits up to eight pages of

eight data bytes each (64 bytes total), which are

temporarily stored in the on-chip page cache of the

24XX65. They will be written from the cache into the

EEPROM array after the master has transmitted a S top

condition. After the receipt of each word, the six lower

order Address Pointer bits are internally incremented by

one. The higher order seven bits of the word address

remain constant. If the master should transmit more

than eight bytes prior to generating the Stop condition

(writi ng across a page boundary), t he address counter

(lower three bits) will roll over and the pointer will be

incremente d to poi nt to the n ext line in the ca che. Th is

can continue to occur up to eight times or until the cache

is full, at which time a Stop condition should be

generated by the master. If a Stop condition is not

received, t he cache poi nter w ill roll over to the f irst lin e

(byte 0) of the cache, and any further data received will

overwrite pr eviously captur ed data. The Stop conditio n

can be sent at any t ime dur ing the tran sfe r. As with the

byte write operation, once the Stop condition is received

an internal write cycle will begin. The 64-byte cache will

continue to capture data until a Stop condition occurs or

the operation is aborted (Figure 4-2).

Operatio n Control Code Device Select R/W

Read 1010 Device Address 1

Write 1010 Device Address 0

SLAVE ADDRESS

1010A2 A1 A0

R/W A

START READ/WRITE

24AA65/24LC65/24C65

FIGURE 4-1: BYTE WRITE

FIGURE 4-2: PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 8-2)

FIGURE 4-3: CURRENT ADDRESS READ

000

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte Word

Address (1) Word

Address (0) Data

Bus

Master

SDA Line

Bus

Control

Byte Word

Address (1) S

Activity

Activity:

Data n Data n + 7

Word

Address (0)

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte Data n

24AA65/24LC65/24C65

FIGURE 4-4: RANDOM READ

FIGURE 4-5: SEQUENTIAL READ

SDA Line

Bus

Control

Byte Word

Address (1) S

Activity A

Data n

000

Word

Address (0)

TControl

Byte

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Data n Data n + 1 Data n + 2 Data n + X

24AA65/24LC65/24C65

5.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There a re three ba sic types

of read operat ions: current address read , rand om rea d

and sequential read.

5.1 Current Address Read

The 24XX65 contains an address counter that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous access

(either a re ad or wri te opera tion) was to addre ss n (n is

any legal address), the next current address read

operatio n wou ld acc ess dat a f rom add ress n + 1. U pon

receipt of the slav e address w ith R/W bit s et to one, the

24XX65 issues an acknowledge and transmits the

eight-bit data word. The master will not acknowledge

the tr ansfer bu t does ge nerate a Stop con dition an d the

24XX65 discontinues transmission (Figure 4-3).

5.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this typ e of re ad ope r atio n, fi rst the w o rd ad dres s must

be set. This is done b y sendi ng the word address to the

24XX65 as p art of a write operati on (R/W bit se t to ‘0’).

Aft er the word add res s is sent, the master generates a

Start condition following the acknowledge. This

terminates the write operation, but not before the

internal Address Pointe r is se t. Then t he master i ssue s

the control byte again, but with the R /W bit set to a one.

The 24XX65 will then issue an acknowledge and

transmit the eight-bit data word. The master will not

acknowledge the transfer, but does generate a Stop

condition which causes the 24XX65 to discontinue

transmission (Figure 4-4).

5.3 Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24XX65 transmits the

first data byte, the master issues an acknowledge as

opposed to t he Stop co ndition used in a r andom read.

This acknowledge directs the 24XX65 to transmit the

next sequentially addressed 8-bit word (Figure 4-5).

Following the final byte transmitted to the master, the

master will NOT generate an acknowledge, but will

generate a S top condition.

To provide sequential reads the 24XX65 contains an

internal Address Pointer which is incremented by one

at the completion of each operation. This Address

Pointer allows the entire memory contents to be serially

read during one operati on .

5.4 Contiguous Addressing Across

Multiple Devices

The device select bits A2, A1, A0 can be used to

expand the contiguous address space for up to 512K

bits by adding up to eight 24XX65's on the same bus.

In this c ase , s oftware c an us e A0 o f th e con trol b yte as

address bit A13, A1 as address bit A14 and A2 as

address bit A15.

5.5 Noise Protection

The SCL and SDA inputs have filter circuits which

suppress noise spikes to assure proper device

operatio n even o n a nois y bus. Al l I/O li nes inc orpora te

Schmitt T ri ggers for 400 kHz (Fast mo de) compa tibility.

5.6 High Endurance Block

The location of the high endurance block within the

memory map is programmed by setting the leading bit

7 (S/HE) of the con figuration by te to ‘0’ . Th e up per bits

of the address loaded in this command will determine

which 4K block within the memory map will be set to

high endurance. This block will be capable of

10,000,0 00 eras e/w ri te cy cle s typ ic al (Fig ure 8-1).

The high endurance block will retain its value as the

high endurance block even if it resides within the

security block range. The high endurance setting

always takes precedence to the security setting.

Note: The high endurance block cannot be

changed after the security option has been

set with a length greater than zero. If the

H.E. bloc k is not program med by th e user,

the default location is the highest block of

memory which starts at location 0x1E00

and ends at 0x1FFF.

24AA65/24LC65/24C65

5.7 Security Options

The 24XX65 has a sophisticated mechanism for write

protecting portions of the array. This write-protect

function is programmable and allows the user to pr otect

0-15 contiguous 4K blocks. The user sets the security

option by sending to the device the starting block

number for the protected region and the number of

blocks to be protected. All parts will come from the

factory in the default configuration with the starting

block number set to 15 and the number of protected

blocks set to zero. THE SECURITY OPTION CAN BE

SET ONLY ONCE WITH A LENGTH GREATER THAN

ZERO.

To invoke th e s ec urit y o pti on, a W r it e c om ma nd is se nt

to the device with the leading bit (bit 7) of the first

address byte set to a ‘1’ (Figure 8-1). Bits 1-4 of the first

address byte define the starting block number for the

protected region.

For exam ple, i f the s tart ing bl ock n umber is to b e set to

5, the first address byte would be 1XX0101X. Bits 0, 5

and 6 of the f irst ad dress by te are disregar ded by the

device and can be either high or low. The device will

acknowledge after the first address byte. A byte of

“don’t care” bits is then sent by the master, with the

device acknowledging afterwards. The third byte sent

to the dev ic e h as bit 7 (S/H E) s et h igh and bit 6 (R) s et

low. Bits 4 and 5 are “don’t cares” and bits 0-3 define

the number of blocks to be write-protected. For exam-

ple, if three blocks are to be protected, the third byte

would be 10XX0011. After the third byte is sent to the

device, it will acknowledge and a Stop bit is then sent

by the master to complete the command.

If one of the security blocks coincides with the high

endurance block, the high endurance setting will take

precedence. Also, if the range of the security blocks

enc ompass the hi gh endur ance bl ock wh en the se cu-

rity option is set, the security block range will be set

accordi ng ly, bu t the hig h enduranc e b loc k will con tinu e

to retain the high endurance setting. As a result, the

memory blocks preceding the high endu rance block will

be set as secure sections.

During a normal write sequence, if an attempt is made

to write to a protected address, no data will be written

and the device will not report an error or abort the

command. If a Write command is attempted across a

secure boundary , un protected addresses will be writte n

and protected addresses will not.

5.8 Security Configuration Read

The st atus o f the secu re portion of memory can be read

by using the same technique as programming this

option except the read bit (bit 6) of the configuration

byte is set t o a one . Aft er the c onfigu ration byte i s sen t,

the device will acknowledge and then se nd two bytes of

data to the master just as in a normal read sequence.

The master must acknowledge the first byte and not

acknowledge the second, and then send a Stop bit to

end the sequence. The upper fou r bit s of both of thes e

bytes w ill alway s be rea d as ‘1’s. The lowe r four bits of

the first byte contains the starting secure block. The

lower four bits of the second byte contains the number

of secure blocks. The default starting secure block is

fifteen and the default number of secure blocks is zero

(Figure 8-1).

6.0 ACKNOWLED GE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

comma nd has been is sued from the master , th e device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycl e, then no ACK will be returne d.

If the cycle is complete, then the device will return the

ACK and the master can then proceed with the next

Read or Write command. See Figure 6-1 for flow

diagram.

FIGURE 6-1: ACKNOWLEDGE

POLLING FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

24AA65/24LC65/24C65

7.0 PAGE CACHE AND ARRAY

MAPPING

The cache is a 64-byte (8 pages x 8 bytes) FIFO buffer .

The cache allows the loading of up to 64 bytes of data

before the write cycle is actually begun, effectively

providing a 64-byte burst write at the maximum bus

rate. When ever a Write command is initi ated, the cache

start s load ing and wi ll contin ue to load un til a Stop bit is

received to start the internal write cycle. The total

length of the write cycle will depend on how many

pages are loaded into the cache before the Stop bit is

given. Maximum cycle time for each p age is 5 ms. Even

if a page is only partially loaded, it will still require the

same cy cle time a s a full page. If more than 64 bytes of

data are loaded before the Stop bit is given, the

Address Pointer will ‘wrap around’ to the beginning of

cache page 0 and existing bytes in the cache will be

overwritten. The device will not respond to any

comm ands w hile the wr ite cycle is in progr ess.

7.1 Cache Write Starting at a Page

Boundary

If a Write command begins at a page boundary

(address bits A2, A1 and A0 are zero), then all data

loaded into the cache will be written to the array in

sequential addresses. This includes writing across a

4K block boundary. In the example shown below,

(Figure 8-2) a Write command is initiated starting at

byte 0 of page 3 with a fully loaded cache (64 bytes).

The firs t by te in the cach e i s wri tte n to by te 0 o f page 3

(of the array), with the remaining pages in the cache

written to seque ntial p age s in the array. A wri te cyc le is

executed after each page is written. Since the write

begins at page 3 and 8 pages are loaded into the

cache, the last 3 pages of the cache are written to the

next row in the array.

7.2 Cache Write Starting at a

Non-Page Boundary

When a Writ e comm and is in iti ated tha t does not begin

at a page boundary (i.e., address bits A2, A1 and A0

are not all zero), it is important to note how the data is

loaded in to the cache , and how the dat a in the cache is

written to the arra y . When a W rite command begins, th e

first byte loaded into the cache is always loaded into

page 0. The byte within page 0 of the cache where the

load be gins is determined by the three Lea st Significant

Address bits (A2, A1, A0) that were sent as part of the

W rite command . If the Write co mmand does no t start at

byte 0 of a p age a nd the ca ch e i s ful ly lo aded, the n th e

last byte(s) loaded into the cache will roll around to

page 0 o f the ca ch e and fi ll th e remain ing e mp t y by tes .

If more than 6 4 bytes of dat a are load ed into the ca che,

data already loa ded will be overwr itte n. In the e xam pl e

shown in Figure 8-3, a Write command has been

initiated starting at byte 2 of page 3 in the array with a

fully l oad ed cache of 64 bytes . Si nc e t he cac he s tarted

loading at byte 2, the last two bytes loaded into the

cache will ‘roll over' and be loaded into the first two

bytes of page 0 (of the cache). When the Stop bit is

sent, page 0 of the cache is written to page 3 of the

array. The remaining pages in the cache are then

loaded sequentially to the array. A write cycle is

execute d afte r each p age is written . If a p artially loaded

page in the cache remains when the Stop bit is sent,

only the bytes that have been loaded will be written to

the array.

7.3 Power Management

The design incorporates a power Standby mode when

not in u se and auto matically powers of f after the normal

terminat ion of any operation when a S top bit is received

and all internal functions are complete. This includes

any error conditions (i.e., not receiving an Acknowl-

edge or Stop condition per the two-wire bus specifica-

tion). The device also incorporates VDD monitor

circuitry to prevent inadvertent writes (data corruption)

during l ow voltage conditio ns. The VDD monitor circuitry

is po wered o ff when the dev ice is in Standby mode in

order to further reduce power consumption.

8.0 PIN DESCRIPTIONS

8.1 A0, A1, A2 Chip Address Inputs

The A0..A2 input s are use d by the 24XX6 5 for m ult ipl e

device operation and conform to the two-wire bus

standard. The levels applied to these pins define the

address block occupied by the device in the address

map. A parti cu lar de vice is s ele cte d by transmit ting th e

corresponding bits (A2, A1, A0) in the control byte

(Figure 3-2 and Figure 8-1).

8.2 SDA Serial Address/Data Input/

Output

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

resistor to VCC (typic al 10 KΩ for 100 kHz, 2 KΩ for 400

kHz).

For norma l data trans fer SDA is allowed to change onl y

during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

8.3 SCL Serial Clock

This inpu t is used to sy nchronize the data tra nsfer from

and to the device.

24AA65/24LC65/24C65

FIGURE 8-1: CONTROL SEQUENCE BIT ASSIGNMENTS

Control Byte

0R/W

0101 A

Address Byte 1

00S A

•••

Address Byte 0

Slave

Address

Device

Select

Bits

•••

Configuration Byte

XR X

Block

Count

S/HE

0101 X

XXX

XX1 X

Starting Block

Number

XXX

X11 X

111 1N

111 1

Number of

Blocks to

Protect

ACK

Data from Device

Acknowledge

from

Master

Data from Device

Acknowledges from Device

0101 B

XX1 B

XXX

XXN

X01 X

Acknowledges from Device

0101 X

XXX

XX1 X

High Endurance

Block Number

XXX

X10 X

111 1

ACK

Data from Device

Acknowledges from Device

0101 B

XX1 B

XXX

000

X00 X

Acknowledges from Device

Starting Block

Number

Number of

Blocks to

Protect

S/HE

Security Read

Security Write

High Endurance Block Read

High Endurance Block Write

High Endurance

Block Number

24AA65/24LC65/24C65

FIGURE 8-2: CACHE WRITE TO THE ARRAY ST ARTING AT A PAGE BOUNDARY

FIGURE 8-3: CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY

1Write command initiated at byte 0 of page 3 in the array;

First data byte is loaded into the cache byte 0. 2 64 bytes of data are loaded into cache.

3Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array.

Write cycle is executed after every page is written.

4 Remaining pages in cache are written

to sequential pages in array.

cache

byte 0

cache

byte 1 • • • cache

byte 7

cache page 1

bytes 8-15 • • •

page 0

cache page 2

bytes 16-23

cache page 7

bytes 56-63

page 1 page 2 • • • byte 7 • • •

page 4 • • • page 7page 3

cache page 0

Last page in cache written to page 2 in next row.

array row n

array row n + 1

page 0 page 1 page 2

byte 0 byte 1 page 4 page 7

1 Write command initiated; 64 bytes of data

loaded into cache starting at byte 2 of page 0.

2 Last 2 bytes loaded 'roll over'

to beginning.

Last 2 bytes

loaded into

page 0 of cache.

4 Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array.

Write cycle is executed after every page is written.

cache

byte 1

cache

byte 2 • • • cache

byte 7

cache page 1

bytes 8-15 • • •

page 0

cache page 2

bytes 16-23

cache page 7

bytes 56-63

page 1 page 2 • • • • • •

page 4 • • • page 7page 3

Remaining bytes in cache are

written sequentially to array.

array

row n

array

row

n + 1

cache

byte 0

Last 3 pages in cache written to next row in array.

page 1 page 2

byte 0 byte 2byte 1 page 4 page 7

byte 7byte 3 byte 4

page 0

24AA65/24LC65/24C65

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

XXXXXXXX

T/XXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIJ (5.28 mm) Example:

24LC65

0110017

I/SM

24LC65

I/P017

0310

XXXXXXXX

YYWWNNN

T/XXXXXX

*Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric trac eab ili ty code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the fu ll Micr ochip part nu mber ca nnot be m arked on one line , it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

24AA65/24LC65/24C65





  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#/!#

 '!#&.0

1,21!'!&$& "!**&"&&!

 3&'!&"&4#*!(!!&4%&&#&

&&255***''54

6&! 7,8.

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

&&  = = 

##44!!   - 

1!&&   = =

"#&"#>#& .  - -

##4>#& .   <

: 9&  -< -? 

&& 9  - 

9#4!!  <  

69#>#& )  ? 

9*9#>#& )  < 

: *+ 1 = = -

NOTE 1

123

  * ,<1

24AA65/24LC65/24C65

 ! ""#$%& !'



 :@(@.5.@&##(%'#:,

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

: 8&   = -

##44!!   = <

&#%%+   = 

: >#& . ? = <?

##4>#& .  = -<

: 9&  - = --

3&9& 9  = ?

3& IA = <A

9#4!!   = 

9#>#& ) -? = 

#%& D= = A

#%&1&&' E= = A

  * ,?1

24AA65/24LC65/24C65

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

24AA65/24LC65/24C65

APPENDIX A: REVISION HISTORY

Revision J

Corrections to Section 1.0, Electrical Characteristics.

Revision K (07/2008)

Revised Temperature ranges; Ambient temperature;

Revised Package Drawings; Replaced On-line

Support; Revised Product ID System.

24AA65/24LC65/24C65

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchi p.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Microchip con sultant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPP ORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical s upport is a vailable through the web si te

at: http://support.microchip.com

24AA65/24LC65/24C65

READER RESP ONSE

It is ou r intentio n to provide you w it h th e b es t do cument ation po ss ib le to ensure suc c es sfu l u se of y ou r M ic roc hip prod-

uct. If you wi sh to prov ide you r comment s on org aniza tion, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

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Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21073K24AA65/24LC65/24C65

1. What are the best features of this document ?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

24AA65/24LC65/24C65

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: 24AA65 - 64K I2C 1.8V Serial EEPROM (100 kHz)

24AA65T - 64K I2C 1.8V Serial EEPROM (100 kHz)

24LC65 - 64K I2C Serial EEPROM (100 kHz/400 kHz)

24LC65T - 64K I2C Serial EEPROM (Tape and Reel)

24C65 - 64K I2C 4.5V Serial EEPROM (400 kHz)

24C65T - 64K I2C 4.5V Serial EEPROM (Tape and Reel)

Temperature

Range: I= -40°C to +85°C

E= -40°C to +125°C

Package: P = Plastic DIP (300 mil Body)

SM = Plastic SOIJ (5.28 mm Body, EIAJ standard)

Examples:

a) 24LC65T-I/SM: 64 Kbit Smart Serial,

Tape and Reel, 5.28 mm SOIJ package,

Industrial temperature, 2.5V

b) 24LC65-I/P: 64 Kbit Smart Serial,

Industrial temperature, PDIP package,

2.5V

c) 24AA65T-/SM: 64 Kbit Smart Serial,

Tape and Reel, 5.28 mm SOIJ package,

Commercial temperature, 1.8V

d) 24C65-E/P: 64 Kbit Smart Serial,

Automotive temperature, PDIP, 5V

24AA65/24LC65/24C65

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce

and may be supers eded by updates . I t is you r r es ponsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC and SmartShunt are registered trademarks

of Microchip Technology Incorporated in the U.S.A. and ot her

countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Prog ra m ming , IC SP, ICEPIC , Mi n d i , M iW i , M PASM, M P L A B

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

PICDEM.net, PICtail , PIC32 logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Tot al

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in t he

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasc a , IL

Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Los A n ge les

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangko k

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Cop e nha gen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

WORLDWIDE SALES AND SERVICE

01/02/08