SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DTrimmed Offset Voltage:
TLC279 . . . 900 µV Max at 25°C,
VDD = 5 V
DInput Offset Voltage Drift ...Typically
0.1 µV/Month, Including the First 30 Days
DWide Range of Supply Voltages Over
Specified Temperature Range:
0°C to 70°C...3 V to 16 V
−40°C to 85°C...4 V to 16 V
−55°C to 125°C...4 V to 16 V
DSingle-Supply Operation
DCommon-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix
and I-Suffix Versions)
DLow Noise ...Typically 25 nV/√Hz
at f = 1 kHz
DOutput Voltage Range Includes Negative
Rail
DHigh Input Impedance ...10
12 Ω Typ
DESD-Protection Circuitry
DSmall-Outline Package Option Also
Available in Tape and Reel
DDesigned-In Latch-Up Immunity
description
The TLC274 and TLC279 quad operational
amplifiers combine a wide range of input offset
voltage grades with low offset voltage drift, high
input impedance, low noise, and speeds
approaching that of general-purpose BiFET
devices.
These devices use Texas Instruments silicon-
gate LinCMOS technology, which provides
offset voltage stability far exceeding the stability
available with conventional metal-gate
processes.
The extremely high input impedance, low bias
currents, and high slew rates make these
cost-effective devices ideal for applications which
have previously been reserved for BiFET and
NFET products. Four offset voltage grades are
available (C-suffix and I-suffix types), ranging
from the low-cost TLC274 (10 mV) to the high-
precision TLC279 (900 µV). These advantages, in
combination with good common-mode rejection
and supply voltage rejection, make these devices
a good choice for new state-of-the-art designs as
well as for upgrading existing designs.
Copyright 2001, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
−1200
Percentage of Units − %
V
IO
− Input Offset Voltage − µV
30
1200
0−600 0 600
5
10
15
20
25 VDD = 5 V
TA = 25°C
N Package
DISTRIBUTION OF TLC279
INPUT OFFSET VOLTAGE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
D, J, N, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4IN+
NC
GND
NC
3IN+
1IN+
NC
VDD
NC
2IN+
FK PACKAGE
(TOP VIEW)
1IN −
1OUT
NC
3OUT
3IN − 4OUT
4IN −
2IN −
2OUT
NC
NC − No internal connection
290 Units Tested From 2 Wafer Lots
LinCMOS is a trademark of Texas Instruments.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
In general, many features associated with bipolar technology are available on LinCMOS operational
amplifiers, without the power penalties of bipolar technology. General applications such as transducer
interfacing, analog calculations, amplifier blocks, active filters, and signal buffering are easily designed with the
TLC274 and TLC279. The devices also exhibit low voltage single-supply operation, making them ideally suited
for remote and inaccessible battery-powered applications. The common-mode input voltage range includes the
negative rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up.
The TLC274 and TLC279 incorporate internal ESD-protection circuits that prevent functional failures at voltages
up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling
these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
TAVIOmax
AT 25°CSMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
PLASTIC
DIP
(N)
TSSOP
(PW)
CHIP
FORM
(Y)
0°C to 70°C
900 µV
2 mV
5 mV
10 mV
TLC279CD
TLC274BCD
TLC274ACD
TLC274CD
—
—
—
—
—
—
—
—
TLC279CN
TLC274BCN
TLC274ACN
TLC274CN
—
—
—
TLC274CPW
—
—
—
TLC274Y
900 µV
TLC279ID
—
—
TLC279IN
—
—
−40°C to 85°C
900 µV
2 mV
TLC279ID
TLC274BID
—
—
—
—
TLC279IN
TLC274BIN
—
—
—
—
−40°C to 85°C
2 mV
5 mV
TLC274BID
TLC274AID
—
—
—
—
TLC274BIN
TLC274AIN
—
—
—
—
5 mV
10 mV
TLC274AID
TLC274ID
—
—
—
—
TLC274AIN
TLC274IN
—
—
—
—
−55°C to 125°C900 µV
10 mV TLC279MD
TLC274MD TLC279MFK
TLC274MFK TLC279MJ
TLC274MJ TLC279MN
TLC274MN —
——
—
The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC279CDR).
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
equivalent schematic (each amplifier)
VDD
P4
P3
R6
N5R2
P2
R1
P1
IN−
IN+
N1
R3 D1 R4 D2
N2
GND
N3
R5 C1
N4
R7
N6 N7
OUT
P6P5
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC274Y chip information
These chips, when properly assembled, display characteristics similar to the TLC274C. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (11) IS INTERNALLY CONNECTED
TO BACK SIDE OF CHIP.
+
−1OUT
1IN+
1IN−
VDD
(4)
(6)
(3)
(2)
(5)
(1)
−
+
(7) 2IN+
2IN−
2OUT
11
GND
+
−3OUT
3IN+
3IN−
(13)
(10)
(9)
(12)
(8)
−
+
(14)
4OUT 4IN+
4IN−
68
108
(1) (2) (3) (4) (5) (6) (7)
(8)
(9)(10)
(11)
(12)(13)
(14)
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input) −0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, lO (each output) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current into VDD 45 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of GND 45 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current at (or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M suffix −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package 260°C. . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package 300°C. . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at the noninverting input with respect to the inverting input.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING TA = 125°C
POWER RATING
D950 mW 7.6 mW/°C608 mW 494 mW —
FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
J1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
N1575 mW 12.6 mW/°C 1008 mW 819 mW —
PW 700 mW 5.6 mW/°C448 mW — —
recommended operating conditions
C SUFFIX I SUFFIX M SUFFIX
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
Supply voltage, VDD 3 16 4 16 4 16 V
Common-mode input voltage, VIC
VDD = 5 V −0.2 3.5 −0.2 3.5 0 3.5
V
Common-mode input voltage, VIC VDD = 10 V −0.2 8.5 −0.2 8.5 0 8.5 V
Operating free-air temperature, TA0 70 −40 85 −55 125 °C
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
†TLC274C, TLC274AC,
TLC274BC, TLC279C
UNIT
PARAMETER
TEST CONDITIONS
TA†
MIN TYP MAX
UNIT
TLC274C
VO = 1.4 V,
VIC = 0,
25°C 1.1 10
TLC274C
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 12
mV
TLC274AC
VO = 1.4 V,
VIC = 0,
25°C 0.9 5 mV
VIO
Input offset voltage
TLC274AC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 6.5
VIO Input offset voltage
TLC274BC
VO = 1.4 V,
VIC = 0,
25°C 340 2000
TLC274BC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 3000
V
TLC279C
VO = 1.4 V,
VIC = 0,
25°C 320 900 µV
TLC279C
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 1500
αVIO Average temperature coefficient of input
offset voltage 25°C to
70°C1.8 µV/°C
IIO
Input offset current (see Note 4)
25°C 0.1 60
pA
IIO Input offset current (see Note 4)
VO = 2.5 V,
VIC = 2.5 V
70°C 7 300 pA
IIB
Input bias current (see Note 4)
VO = 2.5 V, VIC = 2.5 V 25°C0.6 60
pA
IIB Input bias current (see Note 4) 70°C 40 600 pA
VICR
Common-mode input voltage range
25°C−0.2
to
4
−0.3
to
4.2 V
VICR
Common-mode input voltage range
(see Note 5) Full range −0.2
to
3.5 V
25°C 3.2 3.8
V
OH
High-level output voltage V
ID
= 100 mV, R
L
= 10 kΩ0°C3 3.8 V
VOH
High-level output voltage
VID = 100 mV,
RL = 10 kΩ
70°C 3 3.8
V
25°C 0 50
V
OL
Low-level output voltage V
ID
= −100 mV, I
OL
= 0 0°C0 50 mV
VOL
Low-level output voltage
VID = −100 mV,
IOL = 0
70°C 0 50
mV
Large-signal differential voltage
25°C 5 23
A
VD
Large-signal differential voltage
amplification
V
O
= 0.25 V to 2 V
,
R
L
= 10 kΩ0°C4 27 V/mV
AVD
amplification
VO = 0.25 V to 2 V,
RL = 10 kΩ
70°C 4 20
V/mV
25°C 65 80
CMRR Common-mode rejection ratio V
IC
= V
ICR
min 0°C 60 84 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
70°C 60 85
dB
Supply-voltage rejection ratio
25°C 65 95
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
V
DD
= 5 V to 10 V, V
O
= 1.4 V 0°C60 94 dB
kSVR
(∆VDD/∆VIO)
VDD = 5 V to 10 V,
VO = 1.4 V
70°C 60 96
dB
VO = 2.5 V,
VIC = 2.5 V,
25°C 2.7 6.4
I
DD
Supply current (four amplifiers) VO = 2.5 V,
No load
VIC = 2.5 V, 0°C3.1 7.2 mA
IDD
Supply current (four amplifiers)
No load
70°C 2.3 5.2
mA
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
†TLC274C, TLC274AC,
TLC274BC, TLC279C
UNIT
PARAMETER
TEST CONDITIONS
TA†
MIN TYP MAX
UNIT
TLC274C
VO = 1.4 V,
VIC = 0,
25°C 1.1 10
TLC274C
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 12
mV
TLC274AC
VO = 1.4 V,
VIC = 0,
25°C 0.9 5 mV
VIO
Input offset voltage
TLC274AC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 6.5
VIO Input offset voltage
TLC274BC
VO = 1.4 V,
VIC = 0,
25°C 390 2000
TLC274BC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 3000
V
TLC279C
VO = 1.4 V,
VIC = 0,
25°C 370 1200 µV
TLC279C
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 1900
αVIO Average temperature coefficient of
input offset voltage 25°C to
70°C2µV/°C
IIO
Input offset current (see Note 4)
25°C 0.1 60
pA
IIO Input offset current (see Note 4)
VO =.5 V,
VIC = 5 V
70°C 7 300 pA
IIB
Input bias current (see Note 4)
V
O
=.5 V,
VIC = 5 V 25°C0.7 60
pA
IIB Input bias current (see Note 4) 70°C 50 600 pA
VICR
Common-mode input voltage range
25°C−0.2
to
9
−0.3
to
9.2 V
VICR
Common-mode input voltage range
(see Note 5) Full range −0.2
to
8.5 V
25°C 8 8.5
V
OH
High-level output voltage V
ID
= 100 mV, R
L
= 10 kΩ0°C7.8 8.5 V
VOH
High-level output voltage
VID = 100 mV,
RL = 10 kΩ
70°C 7.8 8.4
V
25°C 0 50
V
OL
Low-level output voltage V
ID
= −100 mV, I
OL
= 0 0°C0 50 mV
VOL
Low-level output voltage
VID = −100 mV,
IOL = 0
70°C 0 50
mV
Large-signal differential voltage
25°C 10 36
A
VD
Large-signal differential voltage
amplification
V
O
= 1 V to 6 V, R
L
= 10 kΩ0°C7.5 42 V/mV
AVD
amplification
VO = 1 V to 6 V,
RL = 10 kΩ
70°C 7.5 32
V/mV
25°C 65 85
CMRR Common-mode rejection ratio V
IC
= V
ICR
min 0°C 60 88 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
70°C 60 88
dB
Supply-voltage rejection ratio
25°C 65 95
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
V
DD
= 5 V to 10 V, V
O
= 1.4 V 0°C60 94 dB
kSVR
(∆VDD/∆VIO)
VDD = 5 V to 10 V,
VO = 1.4 V
70°C 60 96
dB
VO = 5 V,
VIC = 5 V,
25°C 3.8 8
I
DD
Supply current (four amplifiers) VO = 5 V,
No load
VIC = 5 V, 0°C4.5 8.8 mA
IDD
Supply current (four amplifiers)
No load
70°C 3.2 6.8
mA
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
†TLC274I, TLC274AI,
TLC274BI, TLC279I
UNIT
PARAMETER
TEST CONDITIONS
TA†
MIN TYP MAX
UNIT
TLC274I
VO = 1.4 V,
VIC = 0,
25°C 1.1 10
TLC274I
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 13
mV
TLC274AI
VO = 1.4 V,
VIC = 0,
25°C 0.9 5 mV
VIO
Input offset voltage
TLC274AI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 7
VIO Input offset voltage
TLC274BI
VO = 1.4 V,
VIC = 0,
25°C 340 2000
TLC274BI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 3500
V
TLC279I
VO = 1.4 V,
VIC = 0,
25°C 320 900 µV
TLC279I
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 2000
αVIO Average temperature coefficient of input
offset voltage 25°C to
85°C1.8 µV/°C
IIO
Input offset current (see Note 4)
25°C 0.1 60
pA
IIO Input offset current (see Note 4)
VO = 2.5 V,
VIC = 2.5 V
85°C 24 1000 pA
IIB
Input bias current (see Note 4)
VO = 2.5 V, VIC = 2.5 V 25°C0.6 60
pA
IIB Input bias current (see Note 4) 85°C 200 2000 pA
VICR
Common-mode input voltage range
25°C−0.2
to
4
−0.3
to
4.2 V
VICR
Common-mode input voltage range
(see Note 5) Full range −0.2
to
3.5 V
25°C 3.2 3.8
V
OH
High-level output voltage V
ID
= 100 mV, R
L
= 10 kΩ−40°C3 3.8 V
VOH
High-level output voltage
VID = 100 mV,
RL = 10 kΩ
85°C 3 3.8
V
25°C 0 50
V
OL
Low-level output voltage V
ID
= −100 mV, I
OL
= 0 −40°C0 50 mV
VOL
Low-level output voltage
VID = −100 mV,
IOL = 0
85°C 0 50
mV
Large-signal differential voltage
25°C 5 23
A
VD
Large-signal differential voltage
amplification
V
O
= 0.25 V to 2 V
,
R
L
= 10 kΩ−40°C3.5 32 V/mV
AVD
amplification
VO = 0.25 V to 2 V,
RL = 10 kΩ
85°C 3.5 19
V/mV
25°C 65 80
CMRR Common-mode rejection ratio V
IC
= V
ICR
min −40°C 60 81 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
85°C 60 86
dB
Supply-voltage rejection ratio
25°C 65 95
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
V
DD
= 5 V to 10 V, V
O
= 1.4 V −40°C60 92 dB
kSVR
(∆VDD/∆VIO)
VDD = 5 V to 10 V,
VO = 1.4 V
85°C 60 96
dB
VO = 2.5 V,
VIC = 2.5 V,
25°C 2.7 6.4
I
DD
Supply current (four amplifiers) VO = 2.5 V,
No load
VIC = 2.5 V, −40°C3.8 8.8 mA
IDD
Supply current (four amplifiers)
No load
85°C 2.1 4.8
mA
†Full range is −40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
†TLC274I, TLC274AI,
TLC274BI, TLC279I
UNIT
PARAMETER
TEST CONDITIONS
TA†
MIN TYP MAX
UNIT
TLC274I
VO = 1.4 V,
VIC = 0,
25°C 1.1 10
TLC274I
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 13
mV
TLC274AI
VO = 1.4 V,
VIC = 0,
25°C 0.9 5 mV
VIO
Input offset voltage
TLC274AI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 7
VIO Input offset voltage
TLC274BI
VO = 1.4 V,
VIC = 0,
25°C 390 2000
TLC274BI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 3500
V
TLC279I
VO = 1.4 V,
VIC = 0,
25°C 370 1200 µV
TLC279I
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 2900
αVIO Average temperature coefficient of input
offset voltage 25°C to
85°C2µV/°C
IIO
Input offset current (see Note 4)
25°C 0.1 60
pA
IIO Input offset current (see Note 4)
VO = 5 V,
VIC = 5 V
85°C 26 1000 pA
IIB
Input bias current (see Note 4)
VO = 5 V, VIC = 5 V 25°C0.7 60
pA
IIB Input bias current (see Note 4) 85°C 220 2000 pA
VICR
Common-mode input voltage range
25°C−0.2
to
9
−0.3
to
9.2 V
VICR
Common-mode input voltage range
(see Note 5) Full range −0.2
to
8.5 V
25°C 8 8.5
V
OH
High-level output voltage V
ID
= 100 mV, R
L
= 10 kΩ−40°C7.8 8.5 V
VOH
High-level output voltage
VID = 100 mV,
RL = 10 kΩ
85°C 7.8 8.5
V
25°C 0 50
V
OL
Low-level output voltage V
ID
= −100 mV, I
OL
= 0 −40°C0 50 mV
VOL
Low-level output voltage
VID = −100 mV,
IOL = 0
85°C 0 50
mV
Large-signal differential voltage
25°C 10 36
A
VD
Large-signal differential voltage
amplification
V
O
= 1 V to 6 V, R
L
= 10 kΩ−40°C7 47 V/mV
AVD
amplification
VO = 1 V to 6 V,
RL = 10 kΩ
85°C 7 31
V/mV
25°C 65 85
CMRR Common-mode rejection ratio V
IC
= V
ICR
min −40°C 60 87 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
85°C 60 88
dB
Supply-voltage rejection ratio
25°C 65 95
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
V
DD
= 5 V to 10 V, V
O
= 1.4 V −40°C60 92 dB
kSVR
(∆VDD/∆VIO)
VDD = 5 V to 10 V,
VO = 1.4 V
85°C 60 96
dB
VO = 5 V,
VIC = 5 V,
25°C 3.8 8
I
DD
Supply current (four amplifiers) VO = 5 V,
No load
VIC = 5 V, −40°C5.5 10 mA
IDD
Supply current (four amplifiers)
No load
85°C 2.9 6.4
mA
†Full range is −40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC274M, TLC279M
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX
UNIT
TLC274M
VO = 1.4 V,
VIC = 0,
25°C 1.1 10
mV
VIO
Input offset voltage
TLC274M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 12 mV
VIO Input offset voltage
TLC279M
VO = 1.4 V,
VIC = 0,
25°C 320 900
V
TLC279M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 3750 µV
αVIO Average temperature coefficient of input
offset voltage 25°C to
125°C2.1 µV/°C
IIO
Input offset current (see Note 4)
25°C 0.1 60 pA
IIO Input offset current (see Note 4)
VO = 2.5 V,
VIC = 2.5 V
125°C 1.4 15 nA
IIB
Input bias current (see Note 4)
VO = 2.5 V, VIC = 2.5 V 25°C0.6 60 pA
IIB Input bias current (see Note 4) 125°C 9 35 nA
VICR
Common-mode input voltage range
25°C0
to
4
−0.3
to
4.2 V
VICR
Common-mode input voltage range
(see Note 5) Full range 0
to
3.5 V
25°C 3.2 3.8
V
OH
High-level output voltage V
ID
= 100 mV, R
L
= 10 kΩ−55°C3 3.8 V
VOH
High-level output voltage
VID = 100 mV,
RL = 10 kΩ
125°C 3 3.8
V
25°C 0 50
V
OL
Low-level output voltage V
ID
= −100 mV, I
OL
= 0 −55°C0 50 mV
VOL
Low-level output voltage
VID = −100 mV,
IOL = 0
125°C 0 50
mV
Large-signal differential voltage
25°C 5 23
A
VD
Large-signal differential voltage
amplification
V
O
= 0.25 V to 2 V
,
R
L
= 10 kΩ−55°C3.5 35 V/mV
AVD
amplification
VO = 0.25 V to 2 V,
RL = 10 kΩ
125°C 3.5 16
V/mV
25°C 65 80
CMRR Common-mode rejection ratio V
IC
= V
ICR
min −55°C 60 81 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
125°C 60 84
dB
Supply-voltage rejection ratio
25°C 65 95
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
V
DD
= 5 V to 10 V, V
O
= 1.4 V −55°C60 90 dB
kSVR
(∆VDD/∆VIO)
VDD = 5 V to 10 V,
VO = 1.4 V
125°C 60 97
dB
VO = 2.5 V,
VIC = 2.5 V,
25°C 2.7 6.4
I
DD
Supply current (four amplifiers) VO = 2.5 V,
No load
VIC = 2.5 V, −55°C4 10 mA
IDD
Supply current (four amplifiers)
No load
125°C 1.9 4.4
mA
†Full range is −55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 10 V (unless) otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC274M, TLC279M
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX
UNIT
TLC274M
VO = 1.4 V,
VIC = 0,
25°C 1.1 10
mV
VIO
Input offset voltage
TLC274M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 12 mV
VIO Input offset voltage
TLC279M
VO = 1.4 V,
VIC = 0,
25°C 370 1200
V
TLC279M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩFull range 4300 µV
αVIO Average temperature coefficient of input
offset voltage 25°C to
125°C2.2 µV/°C
IIO
Input offset current (see Note 4)
25°C 0.1 60 pA
IIO Input offset current (see Note 4)
VO = 5 V,
VIC = 5 V
125°C 1.8 15 nA
IIB
Input bias current (see Note 4)
VO = 5 V, VIC = 5 V 25°C0.7 60 pA
IIB Input bias current (see Note 4) 125°C 10 35 nA
VICR
Common-mode input voltage range
25°C0
to
9
−0.3
to
9.2 V
VICR
Common-mode input voltage range
(see Note 5) Full range 0
to
8.5 V
25°C 8 8.5
V
OH
High-level output voltage V
ID
= 100 mV, R
L
= 10 kΩ−55°C7.8 8.5 V
VOH
High-level output voltage
VID = 100 mV,
RL = 10 kΩ
125°C 7.8 8.4
V
25°C 0 50
V
OL
Low-level output voltage V
ID
= −100 mV, I
OL
= 0 −55°C0 50 mV
VOL
Low-level output voltage
VID = −100 mV,
IOL = 0
125°C 0 50
mV
Large-signal differential voltage
25°C 10 36
A
VD
Large-signal differential voltage
amplification
V
O
= 1 V to 6 V, R
L
= 10 kΩ−55°C7 50 V/mV
AVD
amplification
VO = 1 V to 6 V,
RL = 10 kΩ
125°C 7 27
V/mV
25°C 65 85
CMRR Common-mode rejection ratio V
IC
= V
ICR
min −55°C 60 87 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
125°C 60 86
dB
Supply-voltage rejection ratio
25°C 65 95
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
V
DD
= 5 V to 10 V, V
O
= 1.4 V −55°C60 90 dB
kSVR
(∆VDD/∆VIO)
VDD = 5 V to 10 V,
VO = 1.4 V
125°C 60 97
dB
VO = 5 V,
VIC = 5 V,
25°C 3.8 8
I
DD
Supply current (four amplifiers) VO = 5 V,
No load
VIC = 5 V, −55°C6.0 12 mA
IDD
Supply current (four amplifiers)
No load
125°C 2.5 5.6
mA
†Full range is −55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER TEST CONDITIONS TA
TLC274C, TLC274AC,
TLC274AC,
TLC274BC, TLC279C UNIT
A
MIN TYP MAX
25°C 3.6
R = 10 ,
V
IPP
= 1 V 0°C 4
SR
Slew rate at unity gain
RL = 10 Ω,
CL = 20 PF,
VIPP = 1 V
70°C 3
V/ s
SR Slew rate at unity gain
L
C
L
= 20
P
F,
See Figure 1
25°C 2.9 V/µs
See Figure 1
V
IPP
= 2.5 V 0°C 3.1
VIPP = 2.5 V
70°C 2.5
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C 25 nV/√Hz
VO = VOH,
CL = 20 PF,
25°C 320
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 10 kΩ,
CL = 20 PF,
See Figure 1
0°C 340 kHz
BOM
Maximum output-swing bandwidth
RL = 10 kΩ,
See Figure 1
70°C 260
kHz
VI = 10 mV,
CL = 20 PF,
25°C 1.7
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 PF, 0°C2MHz
B1
Unity-gain bandwidth
See Figure 3
70°C 1.3
MHz
VI = 10 mV,
f = B1,
25°C 46°
φmPhase margin VI = 10 mV,
CL = 20 PF,
f = B1,0°C47°
m
Phase margin
CL = 20 PF,
70°C 44°
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER TEST CONDITIONS TA
TLC274C, TLC274AC,
TLC274AC,
TLC274BC, TLC279C UNIT
A
MIN TYP MAX
25°C 5.3
R = 10 ,
V
IPP
= 1 V 0°C 5.9
SR
Slew rate at unity gain
RL = 10 Ω,
CL = 20 PF,
VIPP = 1 V
70°C 4.3
V/ s
SR Slew rate at unity gain
L
C
L
= 20
P
F,
See Figure 1
25°C 4.6 V/µs
See Figure 1
V
IPP
= 5.5 V 0°C 5.1
VIPP = 5.5 V
70°C 3.8
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C 25 nV/√Hz
VO = VOH,
CL = 20 PF,
25°C 200
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 10 kΩ,
CL = 20 PF,
See Figure 1
0°C 220 kHz
BOM
Maximum output-swing bandwidth
RL = 10 kΩ,
See Figure 1
70°C 140
kHz
VI = 10 mV,
CL = 20 PF,
25°C 2.2
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 PF, 0°C2.5 MHz
B1
Unity-gain bandwidth
See Figure 3
70°C 1.8
MHz
VI = 10 mV,
f = B1,
25°C 49°
φmPhase margin VI = 10 mV,
CL = 20 PF,
f = B1,
See Figure 3
0°C 50°
m
Phase margin
CL = 20 PF,
See Figure 3
70°C 46°
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC274I, TLC274AI,
TLC274BI, TLC279I
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX
UNIT
25°C 3.6
R = 10 k ,
V
IPP
= 1 V −40°C 4.5
SR
Slew rate at unity gain
RL = 10 kΩ,
CL = 20 PF,
VIPP = 1 V
85°C 2.8
V/ s
SR Slew rate at unity gain
L
C
L
= 20
P
F,
See Figure 1
25°C 2.9 V/µs
See Figure 1
V
IPP
= 2.5 V −40°C 3.5
VIPP = 2.5 V
85°C 2.3
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C 25 nV/√Hz
VO = VOH,
CL = 20 PF,
25°C 320
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 10 kΩ,
CL = 20 PF,
See Figure 1
−40°C 380 kHz
BOM
Maximum output-swing bandwidth
RL = 10 kΩ,
See Figure 1
85°C 250
kHz
VI = 10 mV,
CL = 20 PF,
25°C 1.7
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 PF, −40°C2.6 MHz
B1
Unity-gain bandwidth
See Figure 3
85°C 1.2
MHz
VI = 10 mV,
f = B1,
25°C 46°
φmPhase margin VI = 10 mV,
CL = 20 PF,
f = B1,
See Figure 3
−40°C 49°
m
Phase margin
CL = 20 PF,
See Figure 3
85°C 43°
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC274I, TLC274AI,
TLC274BI, TLC279I
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX
UNIT
25°C 5.3
R = 10 ,
V
IPP
= 1 V −40°C 6.7
SR
Slew rate at unity gain
RL = 10 Ω,
CL = 20 PF,
VIPP = 1 V
85°C 4
V/ s
SR Slew rate at unity gain
L
C
L
= 20
P
F,
See Figure 1
25°C 4.6 V/µs
See Figure 1
V
IPP
= 5.5 V −40°C 5.8
VIPP = 5.5 V
85°C 3.5
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C 25 nV/√Hz
VO = VOH,
CL = 20 PF,
25°C 200
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 10 kΩ,
CL = 20 PF,
See Figure 1
−40°C 260 kHz
BOM
Maximum output-swing bandwidth
RL = 10 kΩ,
See Figure 1
85°C 130
kHz
VI = 10 mV,
CL = 20 PF,
25°C 2.2
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 PF, −40°C3.1 MHz
B1
Unity-gain bandwidth
See Figure 3
85°C 1.7
MHz
VI = 10 mV,
f = B1,
25°C 49°
φmPhase margin VI = 10 mV,
CL = 20 PF,
f = B1,
See Figure 3
−40°C 52°
m
Phase margin
CL = 20 PF,
See Figure 3
85°C 46°
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC274M, TLC279M
UNIT
PARAMETER
TEST CONDITIONS
T
AMIN TYP MAX
UNIT
25°C 3.6
R = 10 k ,
V
IPP
= 1 V −55°C 4.7
SR
Slew rate at unity gain
RL = 10 kΩ,
CL = 20 PF,
VIPP = 1 V
125°C 2.3
V/ s
SR Slew rate at unity gain
L
C
L
= 20
P
F,
See Figure 1
25°C 2.9 V/µs
See Figure 1
V
IPP
= 2.5 V −55°C 3.7
VIPP = 2.5 V
125°C 2
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C 25 nV/√Hz
VO = VOH,
CL = 20 PF,
25°C 320
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 10 kΩ,
CL = 20 PF,
See Figure 1
−55°C 400 kHz
BOM
Maximum output-swing bandwidth
RL = 10 kΩ,
See Figure 1
125°C 230
VI = 10 mV,
CL = 20 PF,
25°C 1.7
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 PF, −55°C2.9 MHz
B1
Unity-gain bandwidth
See Figure 3
125°C 1.1
VI = 10 mV,
f = B1,
25°C 46°
φmPhase margin VI = 10 mV,
CL = 20 PF,
f = B1,
See Figure 3
−55°C 49°
m
Phase margin
CL = 20 PF,
See Figure 3
125°C 41°
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC274M, TLC279M
UNIT
PARAMETER
TEST CONDITIONS
T
AMIN TYP MAX
UNIT
25°C 5.3
R = 10 ,
V
IPP
= 1 V −55°C 7.1
SR
Slew rate at unity gain
RL = 10 Ω ,
CL = 20 PF,
VIPP = 1 V
125°C 3.1
V/ s
SR Slew rate at unity gain
L
C
L
= 20
P
F,
See Figure 1
25°C 4.6 V/µs
See Figure 1
V
IPP
= 5.5 V −55°C 6.1
VIPP = 5.5 V
125°C 2.7
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C 25 nV/√Hz
VO = VOH,
CL = 20 PF,
25°C 200
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 10 kΩ,
CL = 20 PF,
See Figure 1
−55°C 280 kHz
BOM
Maximum output-swing bandwidth
RL = 10 kΩ,
See Figure 1
125°C110
kHz
VI = 10 mV,
CL = 20 PF,
25°C 2.2
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 PF, −55°C3.4 MHz
B1
Unity-gain bandwidth
See Figure 3
125°C 1.6
MHz
VI = 10 mV,
f = B1,
25°C 49°
φmPhase margin VI = 10 mV,
CL = 20 PF,
f = B1,
See Figure 3
−55°C 52°
m
Phase margin
CL = 20 PF,
See Figure 3
125°C 44°
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC274Y
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
VIO Input offset voltage VO = 1.4 V,
RS = 50 Ω,VIC = 0,
RL = 10 kΩ1.1 10 mV
IIO Input offset current (see Note 4)
VO = 2.5 V,
VIC = 2.5 V
0.1 pA
IIB Input bias current (see Note 4) VO = 2.5 V, VIC = 2.5 V 0.6 pA
VICR Common-mode input voltage range (see Note 5) −0.2
to
4
−0.3
to
4.2 V
VOH High-level output voltage VID = 100 mV, RL = 10 kΩ3.2 3.8 V
VOL Low-level output voltage VID = −100 mV, IOL = 0 0 50 mV
AVD Large-signal differential voltage amplification VO = 0.25 V to 2 V, RL = 10 kΩ5 23 V/mV
CMRR Common-mode rejection ratio VIC = VICRmin 65 80 dB
kSVR Supply-voltage rejection ratio (∆VDD/∆VIO) VDD = 5 V to 10 V, VO = 1.4 V 65 95 dB
IDD Supply current (four amplifiers) VO = 2.5 V,
No load VIC = 2.5 V, 2.7 6.4 mA
electrical characteristics, VDD = 10 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC274Y
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
VIO Input offset voltage VO = 1.4 V,
RS = 50 Ω,VIC = 0,
RL = 10 kΩ1.1 10 mV
IIO Input offset current (see Note 4)
VO = 5 V,
VIC = 5 V
0.1 pA
IIB Input bias current (see Note 4) VO = 5 V, VIC = 5 V 0.7 pA
VICR Common-mode input voltage range (see Note 5) −0.2
to
9
−0.3
to
9.2 V
VOH High-level output voltage VID = 100 mV, RL = 10 kΩ8 8.5 V
VOL Low-level output voltage VID = −100 mV, IOL = 0 0 50 mV
AVD Large-signal differential voltage amplification VO = 1 V to 6 V, RL = 10 kΩ10 36 V/mV
CMRR Common-mode rejection ratio VIC = VICRmin 65 85 dB
kSVR Supply-voltage rejection ratio (∆VDD/∆VIO) VDD = 5 V to 10 V, VO = 1.4 V 65 95 dB
IDD Supply current (four amplifiers) VO = 5 V,
No load VIC = 5 V, 3.8 8 mA
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, VDD = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLC274Y
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
SR
Slew rate at unity gain
RL = 10 k
Ω
,
CL = 20 PF,
VIPP = 1 V 3.6
V/ s
SR Slew rate at unity gain
RL = 10 kΩ,
See Figure 1
CL = 20 PF,
VIPP = 2.5 V 2.9 V/µs
VnEquivalent input noise voltage f = 1 kHz, RS = 20 Ω,See Figure 2 25 nV/√Hz
BOM Maximum output-swing bandwidth VO = VOH,
See Figure 1 CL = 20 PF, RL = 10 kΩ,320 kHz
B1Unity-gain bandwidth VI = 10 mV, CL = 20 PF, See Figure 3 1.7 MHz
φmPhase margin VI = 10 mV,
See Figure 3 f = B1, CL = 20 PF, 46°
operating characteristics, VDD = 10 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLC274Y
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
SR
Slew rate at unity gain
RL = 10 k
Ω
,
CL = 20 PF,
VIPP = 1 V 5.3
V/ s
SR Slew rate at unity gain
RL = 10 kΩ,
See Figure 1
CL = 20 PF,
VIPP = 5.5 V 4.6 V/µs
VnEquivalent input noise voltage f = 1 kHz, RS = 20 Ω,See Figure 2 25 nV/√Hz
BOM Maximum output-swing bandwidth VO = VOH,
See Figure 1 CL = 20 PF, RL = 10 kΩ,200 kHz
B1Unity-gain bandwidth VI = 10 mV, CL = 20 PF, See Figure 3 2.2 MHz
φmPhase margin VI = 10 mV,
See Figure 3 f = B1, CL = 20 PF, 49°
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLC274 and TLC279 are optimized for single-supply operation, circuit configurations used for the
various tests often present some inconvenience since the input signal, in many cases, must be offset from
ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to
the negative rail. A comparison of single-supply versus split-supply test circuits is shown below . The use of either
circuit gives the same result.
−
+
VDD
CLRL
VIVIRL
CL
−
+
VDD+
VDD−
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
VO
VO
Figure 1. Unity-Gain Amplifier
VDD
−
+
VDD+
−
+
1/2 VDD
20 Ω
VO
2 kΩ
20 Ω
VDD−
20 Ω20 Ω
2 kΩ
VO
(b) SPLIT SUPPLY(a) SINGLE SUPPLY
Figure 2. Noise-Test Circuit
VDD
−
+
10 kΩ
100 Ω
CL
1/2 VDD
VIVI
CL
100 Ω
10 kΩ
−
+
VDD+
VDD−
(b) SPLIT SUPPLY(a) SINGLE SUPPLY
VOVO
Figure 3. Gain-of-100 Inverting Amplifier
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
input bias current
Because of the high input impedance of the TLC274 and TLC279 operational amplifiers, attempts to measure
the input bias current can result in erroneous readings. The bias current at normal room ambient temperature
is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are
offered to avoid erroneous measurements:
1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using
a picoammeter) with no device in the test socket. The actual input bias current can then be calculated
by subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the
servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires that a
device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not
feasible using this method.
V = VIC
148
17
Figure 4. Isolation Metal Around Device Inputs (J and N packages)
low-level output voltage
To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise
results in the device low-level output being dependent on both the common-mode input voltage level as well
as the differential input voltage level. When attempting to correlate low-level output readings with those quoted
in the electrical specifications, these two conditions should be observed. If conditions other than these are to
be used, please refer to Figures 14 through 19 in the Typical Characteristics of this data sheet.
input offset voltage temperature coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no e ffect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 1 kHz (b) BOM > f > 1 kHz (c) f = BOM (d) f > BOM
Figure 5. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage Distribution 6, 7
αVIO Temperature coefficient of input offset voltage Distribution 8, 9
vs High-level output current
10, 11
VOH
High-level output voltage
vs High-level output current
vs Supply voltage
10, 11
12
VOH
High-level output voltage
vs Supply voltage
vs Free-air temperature
12
13
vs Common-mode input voltage
14, 15
VOL
Low-level output voltage
vs Common-mode input voltage
vs Differential input voltage
14, 15
16
VOL Low-level output voltage
vs Differential input voltage
vs Free-air temperature
16
17
OL
vs Free-air temperature
vs Low-level output current
17
18, 19
vs Supply voltage
20
AVD
Large-signal differential voltage amplification
vs Supply voltage
vs Free-air temperature
20
21
AVD
Large-signal differential voltage amplification
vs Free-air temperature
vs Frequency
21
32, 33
IIB Input bias current vs Free-air temperature 22
IIO Input offset current vs Free-air temperature 22
VIC Common-mode input voltage vs Supply voltage 23
IDD
Supply current
vs Supply voltage
24
IDD Supply current
vs Supply voltage
vs Free-air temperature
24
25
SR
Slew rate
vs Supply voltage
26
SR Slew rate
vs Supply voltage
vs Free-air temperature
26
27
Normalized slew rate vs Free-air temperature 28
VO(PP) Maximum peak-to-peak output voltage vs Frequency 29
B1
Unity-gain bandwidth
vs Free-air temperature
30
B1Unity-gain bandwidth
vs Free-air temperature
vs Supply voltage
30
31
vs Supply voltage
34
φm
Phase margin
vs Supply voltage
vs Free-air temperature
34
35
φm
Phase margin
vs Free-air temperature
vs Load capacitance
35
36
VnEquivalent input noise voltage vs Frequency 37
Phase shift vs Frequency 32, 33
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
−5
0
Percentage of Units − %
VIO − Input Offset Voltage − mV 5
60
−4 −3 −2 −1 0 1 2 34
10
20
30
40
50 TA= 25°C
N Package
DISTRIBUTION OF TLC274
INPUT OFFSET VOLTAGE
ÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑ
753 Amplifiers Tested From 6 Wafer Lots
VDD = 5 V
Figure 7
50
40
30
20
10
43210−1−2−3−4
60
5
VIO − Input Offset Voltage − mV
Percentage of Units − %
0−5
N Package
TA = 25°C
VDD = 10 V
DISTRIBUTION OF TLC274
INPUT OFFSET VOLTAGE
ÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑ
753 Amplifiers Tested From 6 Wafer Lots
Figure 8
50
40
30
20
10
86420−2−4−6−8
60
10
αVIO − Temperature Coefficient − µV/°C
Percentage of Units − %
0
−10
N Package
TA = 25°C to 125°C
ÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑ
324 Amplifiers Tested From 8 Wafer Lots
Outliers:
(1) 20.5 V/°C
DISTRIBUTION OF TLC274 AND TLC279
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
VDD = 5 V
Figure 9
−10
0
Percentage of Units − %
αVIO − Temperature Coefficient − µV/°C10
60
−8 −6 −4 −2 0 2 4 6 8
10
20
30
40
50
Outliers:
TA = 25°C to 125°C
N Package
(1) 21.2 V/C
DISTRIBUTION OF TLC274 AND TLC279
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
ÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑ
324 Amplifiers Tested From 8 Wafer Lots
VDD = 10 V
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 10
0
0
− High-Level Output Voltage − V
IOH − High-Level Output Current − mA
−10
5
−2 −4 −6 −8
1
2
3
4TA = 25°C
VDD = 5 V
VDD = 4 V
VDD = 3 V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VOH
VID = 100 mV
Q
Figure 11
0
0
IOH − High-Level Output Current − mA
−4
0
16
−10 −20 −30
2
4
6
8
10
12
14 VDD = 16 V
VDD = 10 V
VID = 100 mV
TA = 25°C
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
− High-Level Output Voltage − VVOH
−35−5 −15 −25
Figure 12
0
VDD − Supply Voltage − V
162 4 6 8 10 12 14
14
12
10
8
6
4
2
16
0
VID = 100 mV
RL = 10 kΩ
TA = 25°C
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
− High-Level Output Voltage − VVOH
Figure 13
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VDD−1.7
VDD−1.8
VDD−1.9
VDD−2
VDD−2.1
VDD−2.2
VDD−2.3
1007550250−25−50
VDD−1.6
12
5
TA − Free-Air Temperature − °C
VDD−2.4
−75
IOH = −5 mA
VID = 100 mA
VDD = 5 V
VDD = 10 V
− High-Level Output Voltage − VV
OH
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 14
0
300
− Low-Level Output Voltage − mV
VIC − Common-Mode Input Voltage − V 4
700
123
400
500
600 TA = 25°C
IOL = 5 mA
VDD = 5 V
VID = −100 mV
VID = −1 V
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VOL
650
350
450
550
Figure 15
2500VIC − Common-Mode Input Voltage − V
300
350
400
450
500
246810
VDD = 10 V
IOL = 5 mA
TA = 25°C
VID = −1 V
VID = −2.5 V
VID = −100 mV
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
− Low-Level Output Voltage − mVVOL
13579
Figure 16
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
0VID − Differential Input Voltage − V −10−2 −4 −6 −8
800
700
600
500
400
300
200
100
0
VDD = 5 V
VDD = 10 V
− Low-Level Output Voltage − mVVOL
IOL = 5 mA
VIC = |VID/2|
TA = 25°C
−9−1 −3 −5 −7
Figure 17
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
−75
0125
900
−50 −25 0 25 50 75 100
100
200
300
400
500
600
700
800
VIC = 0.5 V
VID = −1 V
IOL = 5 mA
VDD = 5 V
VDD = 10 V
TA − Free-Air Temperature − °C
− Low-Level Output Voltage − mVVOL
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 18
0IOL − Low-Level Output Current − mA
1
8
01 2 3 4 5 6 7
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9 VID = −1 V
VIC = 0.5 V
TA = 25°C
VDD = 3 V
VDD = 4 V
VDD = 5 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
− Low-Level Output Voltage − VVOL
Figure 19
0IOL − Low-Level Output Current − mA
3
30
05 10 15 20 25
0.5
1
1.5
2
2.5 TA = 25°C
VIC = 0.5 V
VID = −1 V
VDD = 10 V
ÑÑÑÑÑ
ÑÑÑÑÑ
VDD = 16 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
− Low-Level Output Voltage − VVOL
Figure 20
0
60
16
02 4 6 8 10 12 14
10
20
30
40
50
VDD − Supply Voltage − V
TA = −55°C
RL = 10 kΩ
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
ÑÑÑÑ
TA = 25°C
ÑÑÑÑ
TA = 85°C
ÑÑÑÑ
TA = 125°C
ÑÑÑ
TA = 0°C
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
A
VD
Voltage Amplification − V/mV
Figure 21
−75
50
125
0−50 −25 0 25 50 75 100
5
10
15
20
25
30
35
40
45
VDD = 5 V
VDD = 10 V
RL = 10 kΩ
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − V/mV
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 22
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
0.1 125
10000
45 65 85 105
1
10
100
1000
25
− Input Bias and Offset Currents − pA
VDD = 10 V
VIC = 5 V
See Note A
ÑÑÑ
ÑÑÑ
IIB
IIB IIO
and
TA − Free-Air Temperature − °C
ÑÑ
ÑÑ
IIO
NOTE A: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
Figure 23
COMMON-MODE
INPUT VOLTAGE POSITIVE LIMIT
vs
SUPPLY VOLTAGE
0VDD − Supply Voltage − V
16
16
02 4 6 8 10 12 14
2
4
6
8
10
12
14 TA = 25°C
IC
V − Common-Mode Input Voltage − V
Figure 24
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
0VDD − Supply Voltage − V
10
16
02 4 6 8 10 12 14
2
4
6
8
VO = VDD/2
No Load TA = −55°C
− Supply Current − mAIDD
1
3
5
7
9
ÑÑÑÑ
ÑÑÑÑ
TA = 70°C
ÑÑÑÑÑ
ÑÑÑÑÑ
TA = 125°C
ÑÑÑ
TA = 0°C
ÑÑÑÑ
ÑÑÑÑ
TA = 25°C
Figure 25
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
−75
− Supply Current − mA
4
125
0
1
2
3
−50 −25 0 25 50 75 100
No Load
VO = VDD/2
VDD = 10 V
VDD = 5 V
5
6
7
8
IDD
TA − Free-Air Temperature − °C
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 26
0VDD − Supply Voltage − V 16
02 4 6 8 10 12 14
1
2
3
4
5
6
7
8
CL = 20 pF
RL = 10 kΩ
VIPP = 1 V
AV = 1
See Figure 1
TA = 25°C
SLEW RATE
vs
SUPPLY VOLTAGE
µsSR − Slew Rate − V/
Figure 27
TA − Free-Air Temperature − °C125−50 −25 0 25 50 75 100
8
7
6
5
4
3
2
1
0
−75
CL = 20 pF
See Figure 1
AV = 1
RL = 10 kΩ
ÑÑÑÑÑ
ÑÑÑÑÑ
VDD = 10 V
VDD = 5 V
VIPP = 1 V
VDD = 5 V
VIPP = 2.5 V
VDD = 10 V
VIPP = 1 V
SLEW RATE
vs
FREE-AIR TEMPERATURE
ÑÑÑÑÑ
VIPP = 5.5 V
µsSR − Slew Rate − V/
Figure 28
−75
Normalized Slew Rate
TA − Free-Air Temperature − °C125
−50 −25 02550 75 100
AV = 1
VIPP = 1 V
RL = 10 kΩ
CL = 20 pF
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
1.5
VDD = 10 V
VDD = 5 V
NORMALIZED SLEW RATE
vs
FREE-AIR TEMPERATURE
Figure 29
10 f − Frequency − kHz
10
10000
0
1
2
3
4
5
6
7
8
9
100 1000
VDD = 10 V
VDD = 5 V
See Figure 1
RL = 10 kΩ
TA = 125°C
TA = 25°C
TA = −55°C
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
− Maximum Peak-to-Peak Output Voltage − V
VO(PP)
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 30
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 3
−75 TA − Free-Air Temperature − °C
3
125
1−50 −25 0 25 50 75 100
1.5
2
2.5
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
− Unity-Gain Bandwidth − MHzB1
Figure 31
See Figure 3
TA = 25°C
CL = 20 pF
VI = 10 mV
0VDD − Supply Voltage − V
2.5
16
12 4 6 8 10 12 14
1.5
2
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
− Unity-Gain Bandwidth − MHzB1
10 f − Frequency − Hz 10 M
0.1 100 1 k 10 k 100 k 1 M
1
10
102
103
104
105
106
150°
120°
90°
60°
30°
0°
180°
TA = 25°C
RL = 10 kΩ
VDD = 5 V
AVD
Phase Shift
107
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
Phase Shift
AVD − Large-Signal Differential
ÁÁ
ÁÁ
AVD Voltage Amplification
Figure 32
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
10 f − Frequency − Hz 10 M
0.1 100 1 k 10 k 100 k 1 M
1
10
102
103
104
105
106
180°
0°
30°
60°
90°
120°
150°
VDD = 10 V
RL = 10 kΩ
TA = 25°C
AVD
Phase Shift
107
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
Phase Shift
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD Voltage Amplification
Figure 33
Figure 34
0
− Phase Margin
VDD − Supply Voltage − V
53°
16
2 4 6 8 10 12 14
51°
CL = 20 pF
TA = 25°C
VI = 10 mV
See Figure 3
45°
PHASE MARGIN
vs
SUPPLY VOLTAGE
φm
52°
50°
49°
48°
47°
46°
Figure 35
−75 125
40°−50 −25 0 25 50 75 100
42°
44°
VDD = 5 V
CL = 20 pF
VI = 10 mV
See Figure 3
TA − Free-Air Temperature − °C
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
− Phase Marginφm
50°
46°
48°
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 36
0CL − Capacitive Load − pF 100
25°20 40 60 80
30°
35°
See Figure 3
VI = 10 mV
TA = 25°C
VDD = 5 V
PHASE MARGIN
vs
LOAD CAPACITANCE
− Phase Margin φm
45°
50°
40°
10 30 50 70 90
Figure 37
1
− Equivalent Input Noise Voltage −
f − Frequency − Hz
400
1000
0
100
200
300
10 100
VDD = 5 V
TA = 25°C
RS = 20 Ω
See Figure 2
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
nV/ Hz
Vn
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
single-supply operation
While the TLC274 and TLC279 perform well using dual power supplies (also called balanced or split supplies),
the design is optimized for single-supply operation. This design includes an input common-mode voltage range
that encompasses ground as well as an output voltage range that pulls down to ground. The supply voltage
range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly available for
TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC274 and TLC279 permits the use of very large resistive values to implement
the voltage divider, thus minimizing power consumption.
The TLC274 and TLC279 work well in conjunction with digital logic; however , when powering both linear devices
and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require RC decoupling.
R4
VO
VDD
R2
R1
VI
VREF R3 C
0.01 µF
−
+
VREF = VDD R3
R1 + R3
VO = (VREF − VI)R4
R2 + VREF
Figure 38. Inverting Amplifier With Voltage Reference
LogicLogicLogic
−
+
−
+
(a) COMMON SUPPLY RAILS
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
Logic Logic Logic Power
Supply
Power
Supply
VO
VO
Figure 39. Common Versus Separate Supply Rails
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input characteristics
The TLC274 and TLC279 are specified with a minimum and a maximum input voltage that, if exceeded at either
input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially
in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit
is specified at VDD − 1 V at TA = 25°C and at VDD − 1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC274 and TLC279 very
good input of fset voltage drift characteristics relative to conventional metal-gate processes. Of fset voltage drift
in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC274 and
TLC279 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and
sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good
practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC274 and TLC279 result in a very low
noise current, which is insignificant in most applications. This feature makes the devices especially favorable
over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit
greater noise currents.
VI
(a) NONINVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER
−
+
(b) INVERTING AMPLIFIER
VI
−
+
−
+
VIVOVOVO
Figure 40. Guard-Ring Schemes
output characteristics
The output stage of the TLC274 and TLC279 is designed to sink and source relatively high amounts of current
(see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can
cause device damage under certain conditions. Output current capability increases with supply voltage.
All operating characteristics of the TLC274 and TLC279 were measured using a 20-pF load. The devices drive
higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at
lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many cases, adding
a small amount of resistance in series with the load capacitance alleviates the problem.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
output characteristics (continued)
−
+
2.5 V
VO
CL
−2.5 V
VI
(d) TEST CIRCUIT
TA = 25°C
f = 1 kHz
VIPP = 1 V
(a) CL = 20 pF, RL = NO LOAD (b) CL = 130 pF, RL = NO LOAD
(c) C
L
= 150 pF, R
L
= NO LOAD
Figure 41. Effect of Capacitive Loads and Test Circuit
Although the TLC274 and TLC279 possess excellent high-level output voltage and current capability, methods
for boosting this capability are available, if needed. The simplest method involves the use of a pullup resistor
(RP) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages to the
use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a comparatively
large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance between
approximately 60 Ω and 180 Ω, depending on how hard the op amp input is driven. With very low values of RP,
a voltage offset from 0 V at the output occurs. Second, pullup resistor RP acts as a drain load to N4 and the gain
of the operational amplifier is reduced at output voltage levels where N5 is not supplying the output current.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
output characteristics (continued)
−
+
VI
VDD
RP
VO
R2
R1 RL
IP
IF
IL
−
+
C
IP = Pullup current required
by the operational amplifier
(typically 500 µA)
VO
Rp =VDD − VO
IF + IL + IP
Figure 42. Resistive Pullup to Increase VOH
Figure 43. Compensation for
Input Capacitance
feedback
Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.
electrostatic discharge protection
The TLC274 and TLC279 incorporate an internal electrostatic discharge (ESD) protection circuit that prevents
functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be
exercised, however, when handling these devices as exposure to ESD may result in the degradation of the
device parametric performance. The protection circuit also causes the input bias currents to be
temperature-dependent and have the characteristics of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC274 and
TLC279 inputs and outputs were designed to withstand −100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
5 V
0.016 µF
−
+
Low Pass
HIgh Pass
Band Pass
R = 5 kΩ (3/d−1)
(see Note A)
−
+
0.016 µF
10 kΩ
10 kΩ
10 kΩ
−
+
VI
5 kΩ
10 kΩ
10 kΩ
1/4
TLC274
TLC274
1/4
1/4
TLC274
NOTE A: d = damping factor, 1/Q
Figure 44. State-Variable Filter
−
+
−
+
100 kΩ
VO
N.O.
Reset
0.5 µF
Mylar
H.P.
5082-2835
12 V
VI
TLC274
1/4
TLC274
1/4
Figure 45. Positive-Peak Detector
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
−
+
VI
(see Note A) 1.2 kΩ
4.7 kΩ
0.1 µF
22 kΩ
47 kΩ
0.01 µF
TIS193
15 Ω
0.47 µF
100 kΩ
1 kΩ
20 kΩ
TL431 TIP31
10 kΩ
250 µF,
25 V
+
−VO
(see Note B)
110 Ω
1/4
TLC274
NOTES: B. VI = 3.5 V to 15 V
C. VO = 2 V, 0 to 1 A
Figure 46. Logic-Array Power Supply
−
+
R1
9 V
100 kΩ
0.1 µF
R3
10 kΩ
10 kΩVO (see Note B)
VO (see Note A)
R2
TLC274
1/4
1/4
TLC274
47 kΩ
C
100 kΩ
9 V
fO = 1
4C(R2) R1
R2
NOTES: A. VO(PP) = 8 V
B. VO(PP) = 4 V
Figure 47. Single-Supply Function Generator
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
−
+
−
+
100 kΩ10 kΩ
5 V
VI−
VI+
−5 V
−
+
10 kΩ95 kΩ
VO
R1, 10 kΩ
(see Note A)
1/4
TLC279
1/4
TLC279
1/4
TLC279
10 kΩ
NOTE C: CMRR adjustment must be noninductive.
Figure 48. Low-Power Instrumentation Amplifier
−
+
5 V
VI
VO
R
10 MΩ
2C
540 pF
10 MΩ
R
270 pF
CC
270 pF
5 MΩ
R/2
TLC274
1/4
fNOTCH +1
2pRC
Figure 49. Single-Supply Twin-T Notch Filter
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC274ACD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) Call TI Level-1-260C-UNLIM
TLC274ACDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) Call TI Level-1-260C-UNLIM
TLC274ACDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274ACDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274ACN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC274ACNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC274AID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) Call TI Level-1-260C-UNLIM
TLC274AIDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) Call TI Level-1-260C-UNLIM
TLC274AIDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274AIN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC274AINE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC274BCD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274BCDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274BCDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274BCDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274BCN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC274BCNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC274BID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC274BIDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274BIDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274BIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274BIN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC274BINE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC274CD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274CDB ACTIVE SSOP DB 14 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274CDBG4 ACTIVE SSOP DB 14 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274CDBR ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274CDBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274CDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274CDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC274CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC274CNSLE OBSOLETE SO NS 14 TBD Call TI Call TI
TLC274CNSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274CNSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274CPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274CPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC274CPWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
TLC274CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274CPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC274INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC274IPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274MD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274MDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274MDR ACTIVE SOIC D 14 TBD Call TI Call TI
TLC274MDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC274MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI
TLC274MJ OBSOLETE CDIP J 14 TBD Call TI Call TI
TLC274MJB OBSOLETE CDIP J 14 TBD Call TI Call TI
TLC279CD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC279CDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC279CDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC279CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC279CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC279CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC279ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC279IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC279IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC279IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC279IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC279INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC279MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI
TLC279MJB OBSOLETE CDIP J 14 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 5
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC274ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC274AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC274BCDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC274BIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC274CDBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TLC274CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC274CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC274CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
TLC274CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLC274IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC274IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLC279CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC279IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC274ACDR SOIC D 14 2500 367.0 367.0 38.0
TLC274AIDR SOIC D 14 2500 367.0 367.0 38.0
TLC274BCDR SOIC D 14 2500 367.0 367.0 38.0
TLC274BIDR SOIC D 14 2500 367.0 367.0 38.0
TLC274CDBR SSOP DB 14 2000 367.0 367.0 38.0
TLC274CDR SOIC D 14 2500 367.0 367.0 38.0
TLC274CDR SOIC D 14 2500 333.2 345.9 28.6
TLC274CNSR SO NS 14 2000 367.0 367.0 38.0
TLC274CPWR TSSOP PW 14 2000 367.0 367.0 35.0
TLC274IDR SOIC D 14 2500 367.0 367.0 38.0
TLC274IPWR TSSOP PW 14 2000 367.0 367.0 35.0
TLC279CDR SOIC D 14 2500 367.0 367.0 38.0
TLC279IDR SOIC D 14 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
