CAT93C86 (Rev. C)
© 2008 SCILLC. All rights reserved 1 Doc. No. MD-1091 Rev. R
Characteristics subject to change without notice
16K-Bit Microwire Serial EEPROM
FEATURES
High speed operation: 3MHz
Low power CMOS technology
1.8 to 5.5 volt operation
Selectable x8 or x16 memory organization
Self-timed write cycle with auto-clear
Hardware and software write protection
Power-up inadvertant write protection
Sequential read
Program enable (PE) pin
1,000,000 Program/erase cycles
100 year data retention
Commercial, industrial and automotive
temperature ranges
RoHS-compliant packages
PIN CONFIGURATION
PDIP (L)
SOIC (V, X)
TDFN (ZD4)
CS 1 8 VCC
SK 2 7 PE
DI 3 6 ORG
DO 4
5 GND
SOIC (W)
PE 1 8 ORG
VCC 2 7 GND
CS 3 6 DO
SK 4
5DI
PIN FUNCTION (1)
Pin Name Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC Power Supply
GND Ground
ORG Memory Organization
PE Program Enable
Notes:
(1) When the ORG pin is connected to VCC, x16 organization is
selected. When it is connected to ground, x8 pin is selected.
If the ORG pin is left unconnected, then an internal pull-up
device will select the x16 organization.
DESCRIPTION
The CAT93C86 is a 16K-bit Serial EEPROM memory
device which is configured as either registers of 16
bits (ORG pin at VCC) or 8 bits (ORG pin at GND).
Each register can be written (or read) serially by using
the DI (or DO) pin. The CAT93C86 is manufactured
using Catalyst’s advanced CMOS EEPROM floating
gate technology. The device is designed to endure
1,000,000 program/erase cycles and has a data
retention of 100 years. The device is available in 8-pin
DIP, 8-pin SOIC and 8-pad TDFN pa ckages.
FUNCTIONAL SYMBOL
For Ordering Information details, see page 12.
CS
SK
PE
ORG
DO
DI
V
CC
GND
CAT93C86 (Rev. C)
Doc. No. MD-1091 Rev. R 2 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS (1)
Parameters Ratings Units
Temperature Under Bia s –55 to +125 ºC
Storage Temperature –65 to 150 ºC
Voltage on any Pin with Respect to Ground(2) -2.0 to +VCC +2.0 V
VCC with Respect to Ground -2.0 to +7.0 V
Package Power Dissipation Capability (TA = 25ºC) 1.0 W
Lead Soldering Temperature (10 seconds) 300 ºC
Output Short Circuit Current(3) 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Reference Test Method Min Units
NEND(4) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte
TDR(4) Data Retention MIL-STD-883, Test Method 1008 100 Years
VZAP(4) ESD Susceptibility MIL-STD-883 , Test Method 3015 2000 V
ILTH(4)(5) Latch-Up JEDEC Standard 17 100 mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V unless otherwise specified.
Symbol Parameter Test Conditi ons Min Typ Max Units
ICC1 Power Supply Current (Write) fSK = 1MHz; VCC = 5.0V 3 mA
ICC2 Power Supply Current (Read) fSK = 1MHz; VCC = 5.0V 500 µA
ISB1 Power Supply Current
(Standby) (x8 Mode) CS = 0V ORG = GND 10 µA
ISB2 Power Supply Current
(Standby) (x16Mode) CS = 0V ORG = Float or VCC 0 10 µA
ILI Input Leakage Current VIN = 0V to VCC 1 µA
ILO Output Leakage Current
(Including ORG pin) VOUT = 0V to VCC, CS = 0V 1 µA
VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V
VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 VCC + 1 V
VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 VCC x 0.2 V
VIH2 Input High Voltage 1.8V ≤ VCC < 4.5V VCC x 0.7 VCC + 1 V
VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V; IOL = 2.1mA 0.4 V
VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V; IOH = -400µA 2.4 V
VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V; IOL = 1mA 0.2 V
VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V; IOH = -100µA VCC - 0.2 V
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) These parameters are tested initially and after a design or process change that affects the parameter.
(5) Latch-up protection is provided for stresses up to 100 mA pn address and data pins from –1V to VCC +1V.
CAT93C86 (Rev. C)
© 2008 SCILLC. All rights reserved 3 Doc. No. MD-1091 Rev. R
Characteristics subject to change without notice
PIN CAPACITANCE (1)
Symbol Test Conditions Min Typ Max Units
COUT Output Capacitance (DO) VOUT = 0V 5 pF
CIN Input Capacitance (CS, SK, DI, ORG) VIN = 0V 5 pF
POWER-UP TIMING (1)(2)
Symbol Parameter Max Units
tPUR Power-u p to Read Operation 1 ms
tPUW Power-up to Write Operation 1 ms
A.C. TEST CONDITIONS
Input Rise and Fall Times ≤ 50ns
Input Pulse Voltages 0.4V to 2.4V 4.5V ≤ VCC ≤ 5.5V
Timing Reference Voltages 0.8V, 2.0V 4.5V ≤ VCC ≤ 5.5V
Input Pulse Voltages 0.2VCC to 0.7VCC 1.8V ≤ VCC ≤ 4.5V
Timing Reference Voltages 0.5VCC 1.8V ≤ VCC ≤ 4.5V
A.C. CHARACTERISTICS
VCC =
1.8V-5.5V VCC =
2.5V-5.5V VCC =
4.5V-5.5V
Symbol Parameter Test
Conditions Min Max Min Max Min Max Units
tCSS CS Setup Time 200 100 50 ns
tCSH CS Hold Time 0 0 0 ns
tDIS DI Setup Time 200 100 50 ns
tDIH DI Hold Time 200 100 50 ns
tPD1 Output Delay to 1 1 0.5 0.15 µs
tPD0 Output Delay to 0 CL = 100pF(3) 1 0.5 0.15 µs
tHZ(1) Output Delay to High-Z 400 200 100 ns
tEW Program/Erase Pulse Width 5 5 5 ms
tCSMIN Minimum CS Low Time 1 0.5 0.15 µs
tSKHI Minimum SK High Time 1 0.5 0.15 µs
tSKLOW Minimum SK Low Time 1 0.5 0.15 µs
tSV Output Delay to Status Valid 1 0.5 0.1 µs
SKMAX Maximum Clock Frequency DC 500 DC 1000 DC 3000 kHz
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in the “AC Test Conditions” table.
CAT93C86 (Rev. C)
Doc. No. MD-1091 Rev. R 4 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
INSTRUCTION SET
Address Data
Instruction Start
Bit Opcode x8 x16 x8 x16 Comments
READ 1 10 A10-A0 A9-A0 Read Address AN– A0
ERASE 1 11 A10-A0 A9-A0 Clear Address AN– A0
WRITE 1 01 A10-A0 A9-A0 D7-D0 D15-D0 Write Address AN– A0
EWEN 1 00 11XXXXXXXXX 11XXXXXXXX Write Enable
EWDS 1 00 00XXXXXXXXX 00XXXXXXXX Write Disable
ERAL 1 00 10XXXXXXXXX 10XXXXXXXX Clear All Addresses
WRAL 1 00 01XXXXXXXXX 01XXXXXXXX D7-D0 D15-D0 Write All Addresses
DEVICE OPERATION
The CAT93C86 is a 16,384-bit nonvolatile memory
intended for use with industry standard
microprocessors. The CAT93C86 can be organized
as either registers of 16 bits or 8 bits. When organized
as X16, seven 13-bit instructions control the reading,
writing and erase operations of the device. When
organized as X8, seven 14-bit instructions control the
reading, writing and erase operations of the device.
The CAT93C86 operates on a single power supply
and will generate on chip, the high voltage required
during any write operation.
Instructions, addresses, and write data are clocked
into the DI pin on the rising edge of the clock (SK).
The DO pin is normally in a high impedance state
except when reading data from the device, or when
checking the ready/busy st atus after a write operation.
The ready/busy status can be determined after the
start of a write operation by selecting the device (CS
high) and polling the DO pin; DO low indicates that the
write operation is not completed, while DO high
indicates that the device is ready for the next
instruction. If necessary, the DO pin may be placed
back into a high impedance state during chip select by
shifting a dummy “1” into the DI pin. The DO pin will
enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high
impedance state is recommended in applications
where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2-bit (or 4-bit) opcode, 10-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations).
Note: The Write, Erase, Write all and Erase all
instructions require PE=1. If PE is left floating, 93C86
is in Program Enabled mode. For Write Enable and
Write Disable instruction PE = don’t care.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C86
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data
bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (tPD0 or tPD1).
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to
toggle, the device will automatically increment to the
next address and shift out the next data word in a
sequential READ mode. As long as CS is
continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches to the end of the address
space, then loops back to address 0. In the
sequential READ mode, only the initial data word is
preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for
a minimum of tCSMIN. The falling edge of CS will start
the self clocking clear and data store cycle of the
memory location specified in the instruction. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO
pin. Since this device features Auto-Clear before
write, it is NOT necessary to erase a memory location
before it is written into.
CAT93C86 (Rev. C)
© 2008 SCILLC. All rights reserved 5 Doc. No. MD-1091 Rev. R
Characteristics subject to change without notice
Figure 1. Sychronous Data Timing
Figure 2. Read Instruction Timing
Figure 3. Write Instruction Timing
SK
DI
CS
DO
tDIS tPD0,tPD1 tCSMIN
tCSS
tDIS tDIH
tSKHI tCSH
VALID VALID
DATA VALID
tSKLOW
SK
CS
DI
DO HIGH-Z
11 0
ANA-–1 A0
Dummy 0 D15 . . . D0
or
D7 . . . D0
1111111 11111111
Address + 1
D15 . . .D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Don't Care
SK
CS
DI
D
O
tCSMIN
STANDBY
HIGH-Z
HIGH-Z
101
ANAN-1 A0DND0
BUSY
READY
STATUS
VERIFY
tSV tHZ
tEW
CAT93C86 (Rev. C)
Doc. No. MD-1091 Rev. R 6 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
Erase
Upon receiving an ERASE command and address,
the CS (Chip Select) pin must be deasserted for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear cycle of the selected memory
location. The clocking of the SK pin is not necessary
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO
pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Erase/Write Enable and Disable
The CAT93C86 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the
EWEN (write enable) instruction. Once the write
instruction is enabled, it will remain enabled until
power to the device is removed, or the EWDS
instruction is sent. The EWDS instruction can be used
to disable all CAT93C86 write and clear instructions,
and will prevent any accidental writing or clearing of
the device. Data can be read normally from the device
regardless of the write enable/disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip
Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO
pin. Once cleared, the contents of all memory bits
return to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO
pin. It is not necessary for all memory locations to be
cleared before the WRAL command is executed.
Figure 4. Erase Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH-Z
HIGH-Z
1
ANAN-1
BUSY READY
STATUS VERIFY
tSV tHZ
tEW
tCS
11
A0
CAT93C86 (Rev. C)
© 2008 SCILLC. All rights reserved 7 Doc. No. MD-1091 Rev. R
Characteristics subject to change without notice
PACKAGE OUTLINE DRAWINGS
PDIP 8-Lead 300mils (L) (1)(2)
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MS-001.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
E1
D
A
L
eb
b2
A1
A2
E
eB
c
TOP VIEW
SIDE VIEW END VIEW
PIN # 1
IDENTIFICATION
SYMBOL MIN NOM MAX
A5.33
A1 0.38
A2 2.92 3.30 4.95
b 0.36 0.46 0.56
b2 1.14 1.52 1.78
c 0.20 0.25 0.36
D 9.02 9.27 10.16
E 7.62 7.87 8.25
e 2.54 BSC
E1 6.10 6.35 7.11
eB 7.87 10.92
L 2.92 3.30 3.80
CAT93C86 (Rev. C)
Doc. No. MD-1091 Rev. R 8 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
SOIC 8-Lead 150mils (V) (1)(2)
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MS-012.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
E1 E
A
A1
h
θ
Lc
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
A1.35 1.75
A1 0.10 0.25
b0.33 0.51
c0.19 0.25
D4.80 5.00
E5.80 6.20
E1 3.80 4.00
e1.27 BSC
h0.25 0.50
L0.40 1.27
θ0º 8º
SYMBOL MIN NOM MAX
CAT93C86 (Rev. C)
© 2008 SCILLC. All rights reserved 9 Doc. No. MD-1091 Rev. R
Characteristics subject to change without notice
SOIC 8-Lead EIAJ 208mils (X) (1)(2)
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ standard EDR-7320.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
θ
E1
eb
SIDE VIEW
TOP VIEW
E
D
PIN#1 IDENTIFICATION
END VIEW
A1
A
Lc
SYMBOL MIN NOM MAX
A2.03
A1 0.05 0.25
b 0.36 0.48
c 0.19 0.25
D 5.13 5.33
E 7.75 8.26
E1 5.13 5.38
e 1.27 BSC
L 0.51 0.76
θ0º 8º
CAT93C86 (Rev. C)
Doc. No. MD-1091 Rev. R 10 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
TDFN 8-Pad 3 x 3mm (ZD4) (1)(2)
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-229.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
E2
A3
eb
A
A1
SID E VIEW BOTTOM VI EW
E
D
TOP VIEW
PIN#1 INDEX AREA
PIN#1 ID
FRONT VIEW
A1
A
L
D2
SYMBOL MIN NOM MAX
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.23 0.30 0.37
D 2.90 3.00 3.10
D2 2.20 — 2.50
E 2.90 3.00 3.10
E2 1.40 — 1.80
e0.65TYP
L 0.20 0.30 0.40
CAT93C86 (Rev. C)
© 2008 SCILLC. All rights reserved 11 Doc. No. MD-1091 Rev. R
Characteristics subject to change without notice
EXAMPLE OF ORDERING INFORMATION(1)
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a 93C86VI-GT3 (SOIC, Industrial Temperature, 1.8V to 5.5V, NiPdAu, Tape & Reel, 3,000/Reel)
(4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE.) For additional
information, please contact your ON Semiconductor sales office.
(5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2,000/Reel, i.e., CAT93C86XI-T2.
(6) For additional package and temperature options, please contact your nearest ON Semiconductor sales office.
Prefix Device # Suffix
CAT 93C86 V I -1.8 -G T3 Rev C
(4)
Company ID
Product Numbe
r
93C86
Temperature Range
I = Industrial (-40°C - 85°C)
A = Automotive (-40°C - 105°C)
E = Extende d (-40°C to + 125°C)
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Package
L = PDIP
V = SOIC, JEDEC
W = SOIC, JEDEC
X = SOIC, EIAJ(5)
ZD4 = TDFN (3x3mm)
Tape & Reel
T: Tape & Reel
2: 2,000/Reel(5)
3: 3,000/Reel
Operating Voltage
Blank (VCC = 2.5V to 5.5V)
1.8 (VCC = 1.8V to 5.5V)
Die Revision
93C86: C
For Product Top Mark Codes, click here:
http://www.catsemi.com/techsupport/producttopmark.asp
CAT93C86 (Rev. C)
Doc. No. MD-1091 Rev. R 12 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
REVISION HISTORY
Date Rev. Comments
14-May-04 L
New Data Sheet Created From CAT93C46/56/57/66/86. Parts
CAT93C56, CAT93C56, CAT93C57, CAT93C66, CAT93C76 and
CAT93C86 have been separated into single data she ets
Add Die Revision ID Letter
Update Features
Update Description
Update Pin Condition
Add Functional Diagram
Update Pin Function
Update D.C. Operating Characteristics
Update Pin Capacitance
Update Instruction Set
Update Device Operation
Update Ordering Information
10-Aug-04 M
Added TDFN Package pin out
03-Sep-04 N
Minor changes
13-Oct-06 O
Update Features
Update Pin Configuration
Update Pin Functions
Update D.C. Operating Characteristics (VCC Range)
Update A.C. Characteristics (VCC Range)
Update Ordering Information
21-May-08 P
Update Package Outline Drawings
Add Top Mark Code Link
Update Document Layout
29-Oct-08 R Change logo and fine pri nt to ON Semiconductor
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to
any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIL LC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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