RFG50N06LE, RFP50N06LE, RF1S50N06LESM Data Sheet Title FG5 06L P50 6LE 1S5 06L M) bt A, V, 22 m, gic vel anwer OSTs) utho October 1999 50A, 60V, 0.022 Ohm, Logic Level N-Channel Power MOSFETs Features These N-Channel enhancement mode power MOSFETs are manufactured using the latest manufacturing process technology. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. * rDS(ON) = 0.022 File Number 4072.3 * 50A, 60V * Temperature Compensating PSPICE(R) Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature Formerly developmental type TA49164. * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information Symbol PART NUMBER PACKAGE D BRAND RFG50N06LE TO-247 FG50N06L RFP50N06LE TO-220AB FP50N06L RF1S50N06LESM TO-263AB F50N06LE G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, i.e. RF1S50N06LESM9A. S Packaging JEDEC STYLE TO-247 JEDEC TO-220AB SOURCE DRAIN GATE SOURCE DRAIN GATE DRAIN (BOTTOM SIDE METAL) DRAIN (FLANGE) eyrds terrpoon, gic vel JEDEC TO-263AB DRAIN (FLANGE) GATE SOURCE anwer OS- (c)2001 Fairchild Semiconductor Corporation RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A RFG50N06LE, RFP50N06LE, RF1S50N06LESM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg RFG50N06LE, RFP50N06LE, RF1S50N06LESM 60 60 10 50 Refer to Peak Current Curve Refer to UIS Curve 142 0.95 -55 to 175 UNITS V V V A W W/oC oC oC oC 300 260 CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS ID = 250A, VGS = 0V, Figure 13 60 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250A, Figure 12 1 - 3 V VDS = 55V, VGS = 0V - - 1 A VDS = 50V, VGS = 0V, TC = 150oC - - 250 A A Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) IDSS IGSS rDS(ON) Turn-On Time tON Turn-On Delay Time td(ON) Gate Charge at 5V Threshold Gate Charge - 10 - - 0.022 VDD = 30V, ID = 50A, RL = 0.6, VGS = 5V, RGS = 2.5 Figures 10, 18, 19 - - 230 ns 20 - ns 170 - ns td(OFF) - 48 - ns tf - 90 - ns tOFF - - 165 ns - 96 120 nC Fall Time Total Gate Charge - ID = 50A, VGS = 5V, Figure 11 - tr Turn-Off Time VGS = 10V - Rise Time Turn-Off Delay Time TEST CONDITIONS Qg(TOT) VGS = 0V to 10V Qg(5) VGS = 0V to 5V Qg(TH) VGS = 0V to 1V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance Junction to Case RJC Thermal Resistance Junction to Ambient RJA VDD = 48V, ID = 50A, RL = 0.96 (Figures 21, 21) VDS = 25V, VGS = 0V, f = 1MHz Figure 14 - 57 70 nC - 2.2 2.7 nC - 2100 - pF - 600 - pF - 230 - pF - - 1.05 oC/W TO-247 - - 30 oC/W TO-220AB and TO-263AB - - 80 oC/W MIN TYP MAX UNITS ISD = 45A - - 1.5 V ISD = 45A, dISD/dt = 100A/s - - 125 ns Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD Diode Reverse Recovery Time trr TEST CONDITIONS NOTES: 2. Pulse test: pulse width 80s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). (c)2001 Fairchild Semiconductor Corporation RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A RFG50N06LE, RFP50N06LE, RF1S50N06LESM Unless Otherwise Specified 1.2 60 1.0 50 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 0.2 40 30 20 10 0 0 0 25 50 75 100 125 150 175 25 50 TC , CASE TEMPERATURE ( oC) 75 100 125 175 150 TC, CASE TEMPERATURE ( oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 ZJC, NORMALIZED THERMAL IMPEDANCE 1 0.5 PDM 0.2 0.1 0.1 t1 t2 0.05 0.02 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE TC = 25oC TJ = MAX RATED 100 100s 1ms 10 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA (c)2001 Fairchild Semiconductor Corporation 200 1000 IDM, PEAK CURRENT CAPABILITY (A) ID, DRAIN CURRENT (A) 500 TC = 25oC VGS = 10V VGS = 5V 100 THERMAL IMPEDANCE MAY LIMIT CURRENT IN THIS REGION FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I=I 25 10 10-5 10-4 10-3 10-2 150 10-1 100 101 t, PULSE WIDTH (s) FIGURE 5. PEAK CURRENT CAPABILITY RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A RFG50N06LE, RFP50N06LE, RF1S50N06LESM IAS, AVALANCHE CURRENT (A) 300 Unless Otherwise Specified tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] If R 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R = 0 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC (Continued) 100 TC = 25oC VGS = 4V 75 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 50 VGS = 3V 25 VGS = 2.5V 1 0.01 NOTE: 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 0 100 0 1.5 3.0 4.5 VDS, DRAIN TO SOURCE VOLTAGE (V) VDD = 15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 80 -55oC 25oC ID = 12.5A 175oC 75 50 25 ON RESISTANCE (m) 100 FIGURE 7. SATURATION CHARACTERISTICS rDS(ON), DRAIN TO SOURCE IDS(ON), DRAIN TO SOURCE CURRENT (A) 6.0 Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING 1.5 3.0 4.5 VGS, GATE TO SOURCE VOLTAGE (V) ID = 100A 60 40 ID = 25A 20 0 2.0 6.0 3.0 2.5 4.0 3.5 4.5 5.0 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 2.5 VDD = 30V, I D = 50A, R L= 0.6 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 600 tr 500 400 td(OFF) 300 tf 200 td(ON) 100 0 ID = 50A VDD = 15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 0 SWITCHING TIME (ns) VGS = 10V VGS = 5V ID, DRAIN CURRENT (A) Typical Performance Curves VGS = 5V, ID = 50A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 0.5 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () FIGURE 10. SWITCHING TIME vs GATE RESISTANCE (c)2001 Fairchild Semiconductor Corporation 50 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE ( oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A RFG50N06LE, RFP50N06LE, RF1S50N06LESM Typical Performance Curves Unless Otherwise Specified (Continued) 2.0 1.2 1.0 0.5 -40 FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 0.9 0.8 -80 CISS 2000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 1000 COSS 500 CRSS 160 0 40 80 120 TJ, JUNCTION TEMPERATURE ( oC) 200 5.0 60 VDD = BVDSS VDD = BVDSS 45 3.75 RL =1.2 IG(REF) = 1.2mA VGS = 5V 2.5 30 15 PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS 0 20 ---------------------I G ( ACT ) 25 1.25 0 I G ( REF ) 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) -40 FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE VDS , DRAIN TO SOURCE VOLTAGE (V) 2500 0 1.0 200 0 40 80 120 160 TJ, JUNCTION TEMPERATURE ( oC) 1500 1.1 VGS , GATE TO SOURCE VOLTAGE (V) 1.5 0 -80 C, CAPACITANCE (pF) ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250A t, TIME (s) I G ( REF ) 80 ---------------------I G ( ACT ) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS tP + RG VDS IAS VDD VDD - VGS DUT 0V tP IAS 0 0.01 tAV FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT (c)2001 Fairchild Semiconductor Corporation FIGURE 17. UNCLAMPED ENERGY WAVEFORMS RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A RFG50N06LE, RFP50N06LE, RF1S50N06LESM Test Circuits and Waveforms (Continued) tON tOFF td(ON) VDS td(OFF) tr VDS tf 90% 90% RL VGS + - DUT 10% 10% 0 VDD 90% RGS VGS VGS 0 10% FIGURE 18. SWITCHING TIME TEST CIRCUIT 50% 50% PULSE WIDTH FIGURE 19. RESISTIVE SWITCHING WAVEFORMS VDS VDD RL Qg(TOT) VDS Qg(10) OR Qg(5) VGS + VDD VGS DUT Ig(REF) VGS = 2V 0 VGS = 1V FOR L2 DEVICES Qg(TH) VGS = 20V VGS = 10V FOR L2 DEVICES VGS = 10V VGS = 5V FOR L2 DEVICES Ig(REF) 0 FIGURE 20. GATE CHARGE TEST CIRCUIT (c)2001 Fairchild Semiconductor Corporation FIGURE 21. GATE CHARGE WAVEFORMS RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A RFG50N06LE, RFP50N06LE, RF1S50N06LESM PSPICE Electrical Model SUBCKT 50N06LE 2 1 3 ; rev 8/11/95 CA 12 8 3.73e-9 CB 15 14 3.73e-9 CIN 6 8 2.08e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD LDRAIN DPLCAP DRAIN 2 5 10 5 51 ESLC 11 - RDRAIN 6 8 EVTHRES + 19 8 + LGATE GATE 1 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD + 17 EBREAK 18 50 - IT 8 17 1 EVTEMP RGATE + 18 22 9 20 21 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.75e-3 RGATE 9 20 1.0 RLDRAIN 2 5 40 RLGATE 1 9 60 RLSOURCE 3 7 30 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 6.15e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B DBREAK + RSLC2 ESG LDRAIN 2 5 4.0e-9 LGATE 1 9 6.0e-9 LSOURCE 3 7 3.0e-9 RLDRAIN RSLC1 51 EBREAK 11 7 17 18 66.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RLSOURCE S1A 12 S2A S1B CA 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 VBAT 5 8 EDS - - IT 14 + + 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD RBREAK 15 14 13 13 8 - + 8 22 RVTHRES VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),4))} .MODEL DBODYMOD D (IS = 1.70e-12 RS = 3.20e-3 TRS1 = 1.75e-3 TRS2 = 1.75e-6 CJO = 2.55e-9 IKF = 13 XTI = 5.2 TT = 7.00e-8 M = 0.47) .MODEL DBREAKMOD D (RS = 1.70e-1 IKF = 0.1 TRS1 = 2.00e-3 TRS2 = 8.00e-7) .MODEL DPLCAPMOD D (CJO = 2.00e-9 IS = 1e-30 VJ = 1.1 M = 0.83 N = 10) .MODEL MMEDMOD NMOS (VTO = 2.00 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.0) .MODEL MSTROMOD NMOS (VTO = 2.42 KP = 128 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.60 KP = 0.01 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10.0 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.13e-3 TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 1.20e-2 TC2 = 6.00e-5) .MODEL RSLCMOD RES (TC1 = 2.00e-3 TC2 = 1.00e-6) .MODEL RSOURCEMOD RES (TC1 = 2.00e-3 TC2 =-1.00e-5) .MODEL RVTHRESMOD RES (TC1 = -2.50e-3 TC2 = -8.50e-6) .MODEL RVTEMPMOD RES (TC1 = -2.00e-3 TC2 = 5.00e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5.3 VOFF= -2.5) VON = -2.5 VOFF= -5.3) VON = -1.4 VOFF= 0.5) VON = 0.5 VOFF= -1.4) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2001 Fairchild Semiconductor Corporation RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST FASTrTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM PowerTrench QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER SMART STARTTM Star* PowerTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM UHCTM UltraFETTM VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H