©2001 Fairchild Semiconductor Corporation RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
50A, 60V, 0.022 Ohm, Logic Level
N-Channel Power MOSFETs
These N-Channel enhancement mode power MOSFETs are
manufactured using the latest manufacturing process
technology. This process, which uses feature sizes
approaching those of LSI circuits, gives optimum utilization
of silicon, resulting in outstanding performance. They were
designed for use in applications such as switching
regulators, switching converters, motor drivers, and relay
drivers. These transistors can be operated directly from
integrated circuits.
Formerly developmental type TA49164.
Features
• 50A, 60V
•r
DS(ON)
= 0.022
Ω
• Temperature Compensating PSPICE
®
Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
•175
o
C Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
Ordering Information
PART NUMBER PACKAGE BRAND
RFG50N06LE TO-247 FG50N06L
RFP50N06LE TO-220AB FP50N06L
RF1S50N06LESM TO-263AB F50N06LE
NOTE: When ordering, use the entire part number. Add the suffix 9A
to obtain the TO-263AB variant in tape and reel, i.e.
RF1S50N06LESM9A.
D
G
S
JEDEC STYLE TO-247 JEDEC TO-220AB
JEDEC TO-263AB
DRAIN
(BOTTOM
SIDE METAL)
SOURCE
DRAIN
GATE GATE
DRAIN (FLANGE)
SOURCE
DRAIN
DRAIN
(FLANGE)
GATE
SOURCE
Data Sheet October 1999 File Number
4072.3
T
itle
F
G5
0
6L
P
50
6
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0
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©2001 Fairchild Semiconductor Corporation RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFG50N06LE, RFP50N06LE,
RF1S50N06LESM UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DSS
60 V
Drain to Gate Voltage (R
GS
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
60 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±
10 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
50
Refer to Peak Current Curve
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Refer to UIS Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
142
0.95
W
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 250
µ
A, V
GS
= 0V, Figure 13 60 - - V
Gate Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 250
µ
A, Figure 12 1 - 3 V
Zero Gate Voltage Drain Current I
DSS
V
DS
= 55V, V
GS
= 0V - - 1
µ
A
V
DS
= 50V, V
GS
= 0V, T
C
= 150
o
C - - 250
µ
A
Gate to Source Leakage Current I
GSS
V
GS
=
±
10V - - 10
µ
A
Drain to Source On Resistance (Note 2) r
DS(ON)
I
D
= 50A, V
GS
= 5V, Figure 11 - - 0.022
Ω
Turn-On Time t
ON
V
DD
= 30V, I
D
= 50A,
R
L
= 0.6
Ω
, V
GS
= 5V,
R
GS
= 2.5
Ω
Figures 10, 18, 19
- - 230 ns
Turn-On Delay Time t
d(ON)
-20- ns
Rise Time t
r
- 170 - ns
Turn-Off Delay Time t
d(OFF)
-48- ns
Fall Time t
f
-90- ns
Turn-Off Time t
OFF
- - 165 ns
Total Gate Charge Q
g(TOT)
V
GS
= 0V to 10V V
DD
= 48V,
I
D
= 50A,
R
L
= 0.96
Ω
(Figures 21, 21)
- 96 120 nC
Gate Charge at 5V Q
g(5)
V
GS
= 0V to 5V - 57 70 nC
Threshold Gate Charge Q
g(TH)
V
GS
= 0V to 1V - 2.2 2.7 nC
Input Capacitance C
ISS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
Figure 14
-2100- pF
Output Capacitance C
OSS
- 600 - pF
Reverse Transfer Capacitance C
RSS
- 230 - pF
Thermal Resistance Junction to Case R
θ
JC
- - 1.05
o
C/W
Thermal Resistance Junction to Ambient R
θ
JA
TO-247 - - 30
o
C/W
TO-220AB and TO-263AB - - 80
o
C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V
SD
I
SD
= 45A - - 1.5 V
Diode Reverse Recovery Time t
rr
I
SD
= 45A, dI
SD
/dt = 100A/
µ
s--125ns
NOTES:
2. Pulse test: pulse width
≤
80
µ
s, duty cycle
≤
2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
©2001 Fairchild Semiconductor Corporation RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
20
10
0
25 50 75 100 125 150
30
50
40
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
175
60
t, RECTANGULAR PULSE DURATION (s)
10-5 10-3 10-2 10-1 100
0.01
2
0.1
1
10-4 101
ZθJC, NORMALIZED
THERMAL IMPEDANCE
SINGLE PULSE
0.5
0.2
0.1
0.05
0.01
0.02
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
VDS, DRAIN TO SOURCE VOLTAGE (V)
1 10 100
1
100
10
ID, DRAIN CURRENT (A)
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
100µs
10ms
1ms
500
200
TC = 25oC
TJ = MAX RATED
t, PULSE WIDTH (s)
1000
10
10-5 10-4 10-3 10-2 10-1 100101
100
IDM, PEAK CURRENT CAPABILITY (A)
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 5V
THERMAL IMPEDANCE
MAY LIMIT CURRENT
IN THIS REGION
VGS = 10V
TC = 25oC
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
©2001 Fairchild Semiconductor Corporation RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
NOTE: Refer to Intersil Application Notes AN9321 and AN9322
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves Unless Otherwise Specified (Continued)
10
100
1
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 150oC
STARTING TJ = 25oC
1 10 1000.01 0.1
300
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(I
AS*R)/(1.3*RATED BV
DSS - VDD) +1]
0
25
75
0 1.5 3.0 4.5 6.0
50
100
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 3V
VGS = 5V
VGS = 10V
VGS = 2.5V
VGS = 4V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
0 3.0 4.5 6.01.5
0
25
50
75
100
175oC
IDS(ON), DRAIN TO SOURCE CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
-55oC25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
20
40
60
80
0
3.0
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(ON), DRAIN TO SOURCE
2.0
ID = 100A
3.5 4.5 5.0
ID = 50A
ID = 12.5A
ID = 25A
4.02.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
ON RESISTANCE (mΩ)
200
20 30 40 500
500
400
300
100
010
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
600
tr
td(OFF)
tf
td(ON)
VDD = 30V, ID = 50A, RL= 0.6Ω
0.5
1.0
1.5
2.0
-80 -40 0 40 80 120 160
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
2.5
200
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 5V, ID = 50A
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
©2001 Fairchild Semiconductor Corporation RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves Unless Otherwise Specified (Continued)
-80 -40 0 40 80 120 160
NORMALIZED GATE
THRESHOLD VOLTAGE
TJ, JUNCTION TEMPERATURE (oC)
200
2.0
1.0
0.5
0
1.5
VGS = VDS, ID = 250µA
1.2
1.0
0.9
0.8
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
200
1.1
ID = 250µA
2500
2000
1000
0
0 5 10 15 20 25
C, CAPACITANCE (pF)
CRSS
1500
CISS
COSS
VDS, DRAIN TO SOURCE VOLTAGE (V)
500
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
60
45
30
15
0
20
IG REF()
IG ACT()
----------------------t, TIME (µs) 80
IG REF()
IG ACT()
----------------------
5.0
3.75
2.5
1.25
0
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS , GATE TO SOURCE VOLTAGE (V)
RL =1.2Ω
IG(REF) = 1.2mA
VGS = 5V
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
VDD = BVDSS VDD = BVDSS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
©2001 Fairchild Semiconductor Corporation RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms (Continued)
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10) OR Qg(5)
VGS = 5V FOR
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
VGS = 1V FOR
L2 DEVICES
L2 DEVICES
VGS = 10V
VGS = 10V FOR
L2 DEVICES
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
©2001 Fairchild Semiconductor Corporation RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
PSPICE Electrical Model
SUBCKT 50N06LE 2 1 3 ; rev 8/11/95
CA 12 8 3.73e-9
CB 15 14 3.73e-9
CIN 6 8 2.08e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 66.5
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 4.0e-9
LGATE 1 9 6.0e-9
LSOURCE 3 7 3.0e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.75e-3
RGATE 9 20 1.0
RLDRAIN 2 5 40
RLGATE 1 9 60
RLSOURCE 3 7 30
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.15e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),4))}
.MODEL DBODYMOD D (IS = 1.70e-12 RS = 3.20e-3 TRS1 = 1.75e-3 TRS2 = 1.75e-6 CJO = 2.55e-9 IKF = 13 XTI = 5.2 TT = 7.00e-8 M = 0.47)
.MODEL DBREAKMOD D (RS = 1.70e-1 IKF = 0.1 TRS1 = 2.00e-3 TRS2 = 8.00e-7)
.MODEL DPLCAPMOD D (CJO = 2.00e-9 IS = 1e-30 VJ = 1.1 M = 0.83 N = 10)
.MODEL MMEDMOD NMOS (VTO = 2.00 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.0)
.MODEL MSTROMOD NMOS (VTO = 2.42 KP = 128 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.60 KP = 0.01 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10.0 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.13e-3 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 1.20e-2 TC2 = 6.00e-5)
.MODEL RSLCMOD RES (TC1 = 2.00e-3 TC2 = 1.00e-6)
.MODEL RSOURCEMOD RES (TC1 = 2.00e-3 TC2 =-1.00e-5)
.MODEL RVTHRESMOD RES (TC1 = -2.50e-3 TC2 = -8.50e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.00e-3 TC2 = 5.00e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.3 VOFF= -2.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -5.3)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.4 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.4)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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