74LVC240A
Document number: DS35886 Rev. 2 - 2
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74LVC240A
NEW PROD UCT
OCTAL BUFFER/LINE DRIVER WITH 3 STATE OUTPUTS
Description
The 74LVC240A provides two 4-bit buffers/drivers with separate
output-enable (OE) inputs. When OE is low, the device passes data
from the A inputs to the Y outputs. When OE is high, the outputs are in
the high-impedance state.
The device is designed for operation with a power supply range of
1.65V to 3.6V.
The inputs are tolerant to 5.5V allowing this device to be used in a
mixed voltage environment. The device is fully specified for partial
power down applications using IOFF. The IOFF circuitry disables the
output preventing damaging current backflow when the device is
powered down.
Features
Supply Voltage Range from 1.65V to 3.6V
Sinks or Sources 24 ma at VCC = 3V
CMOS Low Power Consumption
IOFF Supports Partial -Power Down Operation
Inputs or Outputs Accept up to 5.5V
Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage
Applications
Schmitt Trigger Action at All Inputs
Typical VOLP (Quiet Output Ground Bounce) Less than 0.8V with
VCC = 3.3V and TA = +2C
Typical VOHV (Quiet Output dynamic VOH) Greater than 2.0V with
VCC = 3.3V and TA = +2C
ESD Protection Tested per JESD 22
Exceeds 200-V Machine Model (A115)
Exceeds 2000-V Human Body Model (A114)
Exceeds 1000-V Charged Device Model (C101)
Latch-Up Exceeds 250mA per JESD 78, Class I
All devices are:
Totally Lead-Free & Fully RoHS compliant (Notes 1 & 2)
Halogen and Antimony Free.“Green” Device (Note 3)
Pin Assignments
1
3
2
4
5
6
7
8
Vcc
(Top View )
TSSOP-20
GND 10
9
13
14
12
11
17
18
16
15
19
20
1OE
1A2
2Y4
2Y3
1A3
2Y2
1A4
2Y1
1A1 2OE
1Y2
2A4
2A3
1Y3
2A2
1Y4
2A1
1Y1
Top Transparent View
3
2
4
5
6
7
8
9
13
14
12
17
18
16
15
19
11 20
110
Vcc
2OE
1Y2
2A4
2A3
1Y3
2A2
1Y4
2A1
1Y1
GND 1OE
1A2
2Y4
2Y3
1A3
2Y2
1A4
2Y1
1A1
QFN-20
()
terminal 1
index area
Applications
General Purpose Logic
Bus Driving
Power Down Signal Isolation
Wide Array of Products Such as:
PCs, Notebooks, Netbooks, Ultrabooks
Networking Computer Peripherals, Hard Drives, CD/DVD
ROM
TV, DVD, DVR, Set Top Box
Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen and Antimony free,
"Green" and Lead-Free.
3. Halogen and Antimony free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
74LVC240A
Document number: DS35886 Rev. 2 - 2
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74LVC240A
NEW PROD UCT
Ordering Information
74 LVC 240A xxx -13
Logic Device
Function
Package
Packing
74 : Logic Prefix
240 :
Octal
Buffer/Line
Driver with 3
State Outputs
T20 : TSSOP-20
-13 : 13” Tape & Reel
Q20 : QFN-20
Part Number
Package
Code
Package
(Note 4 & 5)
Package Size
13” Tape and Reel
Quantity
Part Number Suffix
74LVC240AT20-13
T20
TSSOP-20
6.4mm X 6.5mm X 1.2mm
0.65 mm lead pitch
2500/Tape & Reel
-13
74LVC240AQ20-13
Q20
V-QFN4525-20
2.5mm X 4.5mm X 0.95mm
0.50 mm lead pitch
2500/Tape & Reel
-13
Notes: 4. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at
http://www.diodes.com/datasheets/ap02001.pdf.
5. V-QFN4525-20 is a JEDEC recognized naming convention that specifies the package thickness category as V and the number 4525 describes the
package as 4.5mm X 2.5mm.
Pin Descriptions
Pin Number
Pin Name
Description
1
OE1
Output Enable 1
2
1A1
Data Input
3
2Y4
Data Output
4
1A2
Data Input
5
2Y3
Data Output
6
1A3
Data Input
7
2Y2
Data Output
8
1A4
Data Input
9
2Y1
Data Output
10
GND
Ground
11
2A1
Data Input
12
1Y4
Data Output
13
2A2
Data Input
14
1Y3
Data Output
15
2A3
Data Input
16
1Y2
Data Output
17
2A4
Data Input
18
1Y1
Data Output
19
OE2
Output Enable 2
20
Vcc
Supply Voltage
Logic Diagram
1
1OE
1A2 16 1Y2
4
1A3 14 1Y3
6
1A4 12 1Y4
8
1A1 18 1Y1
2
19
2OE
2A2 72Y2
13
2A3 52Y3
15
2A4 32Y4
17
2A1 92Y1
11
Function Table
(Each 4-Bit Buffer)
INPUTS
OUTPUT
OE
A
Y
L
H
L
L
L
H
H
X
Z
74LVC240A
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74LVC240A
NEW PROD UCT
Absolute Maximum Ratings (Notes 6 & 7)
Symbol
Description
Rating
Unit
ESD HBM
Human Body Model ESD Protection
2
kV
ESD CDM
Charged Device Model ESD Protection
1
kV
ESD MM
Machine Model ESD Protection
200
V
VCC
Supply Voltage Range
-0.5 to +7.0
V
VI
Input Voltage Range note 3
-0.5 to +7.0
V
IIK
Input Clamp Current VI< 0V
-20
mA
IOK
Output Clamp Current VO< 0V
-50
mA
IO
Continuous output current - 0.5V < VO Vcc + 0.5V
±50
mA
ICC
Continuous current through Vcc
100
mA
IGND
Continuous current through GND
-100
mA
TJ
Operating Junction Temperature
-40 to +150
°C
TSTG
Storage Temperature
-65 to +150
°C
PTOT
Total Power Dissipation
500
mW
Notes: 6. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device
operation should be within recommend values.
7. Forcing the maximum allowed voltage could cause a condition exceeding the maximum current or conversely forcing the maximum current could
cause a condition exceeding the maximum voltage. The ratings of both current and voltage must be maintained within the controlled range.
Recommended Operating Conditions (Note 8)
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
Supply Voltage
Operating
1.65
3.6
V
Data Retention Only
1.5
V
VI
Input Voltage
0
5.5
V
VO
Output Voltage
0
VCC
V
IOH
High-Level Output Current
VCC = 1.65V
-4
mA
VCC = 2.3V
-8
VCC = 2.7V
-12
VCC = 3.0V
-24
IOL
Low-Level Output Current
VCC = 1.65V
4
mA
VCC = 2.3V
8
VCC = 2.7V
12
VCC = 3.0V
24
Δt/ΔV
Input Transition Rise or Fall Rate
10
ns/V
TA
Operating Free-Air Temperature
-40
+125
°C
Note: 8. Unused inputs should be held at VCC or Ground.
74LVC240A
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74LVC240A
NEW PROD UCT
Electrical Characteristics
Symbol
Parameter
Test Conditions
VCC
TA = -40°C to +85°C
TA = -40°C to +125°C
Unit
Min
Max
Min
Max
VIH
High-Level Input
Voltage
1.65V to 1.95V
VCC X 0.65
VCC X 0.65
V
2.3V to 2.7V
1.7
1.7
3.0V to 3.6V
2
2
VIL
Low-Level input
voltage
1.65V to 1.95V
VCC X 0.35
VCC X 0.35
V
2.3V to 2.7V
0.7
0.7
3.0V to 3.6V
0.8
0.8
VOH
High-Level
Output Voltage
IOH = -50 μA
1.65V to 3.6V
VCC-0.2
VCC-0.3
IOH = -4 mA
1.65V
1.2
1.05
IOH = -8 mA
2.3V
1.7
1.65
V
IOH = -12 mA
2.7V
2.2
2.05
3.0V
2.4
2.48
IOH = -24 mA
3.0V
2.3
2.0
VOL
Low-Level Output
Voltage
IOL = 100 μA
1.65V to 3.6V
0.2
0.3
V
IOL = 4 mA
1.65V
0.45
0.65
IOL = 8 mA
2.3V
0.60
0.80
IOL = 12 mA
2.7V
0.40
0.60
IOL = 24 mA
3.0V
0.55
0.80
IOFF
Power Down
Leakage Current
VI or VO = 0 or 5.5V
0V
±10
20
μA
II
Input Current
Control Pins
VI =GND or 5.5V
0 to 3.6V
±5
± 20
μA
IOZ
Z-state Current
Including Input
Current
I/O Pins
VI =GND or 5.5V
VO = 0 to 5.5V
3.6V
±5
± 20
uA
ICC
Supply Current
VI = GND or VCC, IO=0
3.6V
10
40
μA
∆ICC
Additional Supply
Current
One input at Vcc-0.6V
Io= 0A
2.7V to 3.6V
500
5000
μA
Ci
Input
Capacitance
Control Pins
VI = GND or
VCC
0V to 3.6V
4.0 typical
4.0 typical
pF
I/O Pins
5.5 typical
5.5 typical
Switching Characteristics
Symbol
Parameter
Test
Conditions
VCC
TA = +25°C
-40°C to +85°C
-40°C to +125°C
Unit
Min
Typ
Max
Min
Max
Min
Max
tPD
Propagation
Delay AN to YN
Figure 1
1.8V± 0.15V
1.0
6.0
12.2
1.0
13.1
1.0
16.9
ns
2.5V± 0.2V
1.0
3.9
7.8
1.0
8.4
1.0
8.9
2.7V
1.0
4.2
8.1
1.0
8.9
1.0
9.0
3.3V± 0.3V
1.5
3.8
7.6
1.5
8.1
1.5
8.3
tEN
Enable Time
OE
to YN
Figure 1
1.8V± 0.15V
1.0
7.0
14.8
1.0
15.3
1.0
22.5
ns
2.5V± 0.2V
1.0
4.5
10.0
1.0
10.5
1.0
12.4
2.7V
1.0
5.4
8.5
1.0
9.5
1.0
11.0
3.3 ± 0.3V
1.5
4.4
7.0
1.5
8.5
1.5
9.0
tDIS
Disable Time
OE
to YN
Figure 1
1.8V± 0.15V
1.0
7.8
16.5
1.0
17.0
1.0
18.2
ns
2.5V± 0.2V
1.0
4.0
9.0
1.0
9.5
1.0
10.7
2.7V
1.0
4.3
7.5
1.0
8.5
1.0
10.0
3.3V± 0.3V
1.7
4.0
6.0
1.7
7.5
1.7
9.0
tsk(0)
Output Skew
Time
3.3V± 0.3V
1.0
1.5
ns
74LVC240A
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74LVC240A
NEW PROD UCT
Operating Characteristics
TA = +25°C
Symbol
Parameter
Test Conditions
VCC
Typ
Unit
Cpd
Power Dissipation
Capacitance per Gate
F= 10 MHz
Outputs Enabled
1.8V ± 0.15V
9.9
pF
2.5V ± 0.2V
10.2
3.3V ± 0.3V
10.6
Package Characteristics
Symbol
Parameter
Package
Test Conditions
Min
Typ
Max
Unit
θJA
Thermal Resistance
Junction-to-Ambient
TSSOP-20
(Note 9)
74
°C/W
θJC
Thermal Resistance
Junction-to-Case
TSSOP-20
(Note 9)
15
°C/W
θJA
Thermal Resistance
Junction-to-Ambient
V-QFN4525-20
(Note 9)
67
°C/W
θJC
Thermal Resistance
Junction-to-Case
V-QFN4525-20
(Note 9)
20
°C/W
Note: 9. Test conditions for TSSOP-20 and V-QFN4525-20: Devices mounted on 4 layer FR-4 substrate PC board, 2oz copper, with minimum recommended
pad layout per JESD 51-7.
74LVC240A
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Parameter Measurement Information
RL
RL
CL
(see Note A)
From Output
Under Test
VLOAD
Open
GND
S1
VCC
Inputs
VM
VLOAD
CL
RL
V∆
VI
tr/tf
1.8V±0.15V
VCC
≤2ns
VCC/2
2 x VCC
30pF
1KΩ
0.15V
2.5V±0.2V
VCC
≤2ns
VCC/2
2 x VCC
30pF
500Ω
0.15V
2.7V
2.7V
≤2.5ns
1.5V
6V
50pF
500Ω
0.3V
3.3V±0.3V
2.7V
≤2.5ns
1.5V
6V
50pF
500Ω
0.3V
Input
tW
VMVM
Vl
0 V
Output
Control VMVM
Vl
0 V
tPZL
tPZH
VM
VLOAD/2
VM
tPHZ
VOH
VOL
VOH - V
Output
Waveform 1
S1 at VLOAD
(see Note B) VOL + V
Output
Waveform 2
S1 at GND
(see Note B)
tPLZ
0V
Voltage Waveform Enable and Disable Times
Low and High Level Enabling
Voltage Waveform Pulse Duration
Input VMVM
Vl
0 V
tPHL
tPLH
tPHL
VMVM
VM
tPLH
VOH
VOL
VOH
VOL
Output
Output VM
Voltage Waveform Propagation Delay Times
Inverting and Non Inverting Outputs
Notes: A. Includes test lead and test apparatus capacitance.
B. All pulses are supplied at pulse repetition rate ≤ 10 MHz.
C. Inputs are measured separately one transition per measurement.
D. tPLZ and tPHZ are the same as tdis.
E. tPZL and tPZH are the same as tEN0
F. tPLH and tPHL are the same as tPD.
Figure 1 Load Circuit and Voltage Waveforms
TEST
S1
tPLH/tPHL
Open
tPLZ/tPZL
VLOAD
tPHZ/tPZH
GND
74LVC240A
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74LVC240A
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Marking Information
(1) TSSOP20
Part Number
Package
74LVC240AT20
TSSOP-20
(2) QFN-20 (V-QFN4525-20)
Part Number
Package
74LVC240AQ20
V-QFN4525-20
74LVC240A
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74LVC240A
NEW PROD UCT
Package Outline Dimensions (All Dimensions in mm)
Please see http://www.diodes.com/package-outlines.html for the latest version.
(1) TSSOP-20
(2) QFN-20 (V-QFN4525-20)
TSSOP-20
Dim
Min
Max
Typ
A
-
1.20
-
A1
0.05
0.15
-
A2
0.80
1.05
-
b
0.19
0.30
-
c
0.09
0.20
-
D
6.40
6.60
6.50
E
6.20
6.60
6.40
E1
4.30
4.50
4.40
e
0.65 BSC
L
0.45
0.75
0.60
L1
1.0 REF
θ1
-
θ2
10°
14°
12°
θ3
10°
14°
12°
All Dimensions in mm
V-QFN4525-20
Dim
Min
Max
Typ
A
0.75
0.85
0.80
A1
0.00
0.05
0.02
A3
-
-
0.15
b
0.18
0.30
0.23
D
4.45
4.55
4.50
D2
2.85
3.15
3.00
E
2.45
2.55
2.50
E2
0.85
1.15
1.00
e
0.50BSC
L
0.30
0.50
0.40
Z
-
-
0.385
Z1
-
-
0.885
All Dimensions in mm
ID MARK
PIN 1
e
D
EE1
A2 A
A1
b
DETAIL
Seating Plane

Gauge Plane
0.25
L
L1


AA3
Seating Plane
A1
(Pin #1 ID)
D
E
b (20x)
E2
L(20x)
D2
e
Z(4x)
Z1(4x)
74LVC240A
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Suggested Pad Layout
Please see http://www.diodes.com/package-outlines.html for the latest version.
(1) TSSOP-20
(2) QFN-20 (V-QFN4525-20)
Dimensions
Value (in mm)
C
0.650
X
0.420
X1
6.270
Y
1.789
Y1
4.160
Y2
7.720
Dimensions
Value (in mm)
C
0.500
X
0.330
X1
0.600
X2
3.200
X3
3.830
X4
4.800
Y
0.600
Y1
1.200
Y2
0.830
Y3
2.800
Y1 Y2
Y (20x)
X (20x) C
X1
X4
Y3
Y2
X3
X2
Y1
Y
XC
X1
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IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes
without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the
application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or
trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume
all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated
website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and
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This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the
final and determinative format released by Diodes Incorporated.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express
written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any
use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related
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representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems.
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