HM628512A Series
524288-word × 8-bit High Speed CMOS Static RAM
ADE-203-640A (Z)
Rev. 1.0
Dec. 2, 1996
Description
The Hitachi HM628512A is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density,
higher performance and low power consumption by employing 0.5 µm Hi-CMOS process technology. The
device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II or 600-mil plastic DIP,
is available for high density mounting. The HM628512A is suitable for battery backup system.
Features
• Single 5 V supply
• Access time: 55/70 ns (max)
• Power dissipation
Active: 50 mW/MHz (typ)
Standby: 10 µW (typ)
• Completely static memory. No clock or timing strobe required
• Equal access and cycle times
• Common data input and output: Three state output
• Directly TTL compatible: All inputs and outputs
• Battery backup operation
HM628512A Series
2
Ordering Information
Type No. Access time Package
HM628512ALP-5
HM628512ALP-7 55 ns
70 ns 600-mil 32-pin plastic DIP (DP-32)
HM628512ALP-5SL
HM628512ALP-7SL 55 ns
70 ns
HM628512ALFP-5
HM628512ALFP-7 55 ns
70 ns 525-mil 32-pin plastic SOP (FP-32D)
HM628512ALFP-5SL
HM628512ALFP-7SL 55 ns
70 ns
HM628512ALTT-5
HM628512ALTT-7 55 ns
70 ns 400-mil 32-pin plastic TSOP II (TTP-32D)
HM628512ALTT-5SL
HM628512ALTT-7SL 55 ns
70 ns
HM628512ALRR-5
HM628512ALRR-7 55 ns
70 ns 400-mil 32-pin plastic TSOP II reverse (TTP-32DR)
HM628512ALRR-5SL
HM628512ALRR-7SL 55 ns
70 ns
HM628512A Series
3
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SS
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
V
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
CC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SS
V
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
CC
(Top view)
HM628512ALP Series
HM628512ALFP Series HM628512ALTT Series
HM628512ALRR Series
(Top view)
(Top view)
Pin Description
Pin name Function
A0 to A18 Address input
I/O0 to I/O7 Data input/output
CS Chip select
OE Output enable
WE Write enable
VCC Power supply
VSS Ground
HM628512A Series
4
Block Diagram
•
•
•
•
•
•
••
•
•
•
I/O0
I/O7
CS
WE
OE
A13A17A15A8 A10A11
V
V
CC
SS
Row
Decoder
Memory Matrix
1,024 4,096
Column I/O
Column Decoder
Input
Data
Control
×
Timing Pulse Generator
Read/Write Control
A16
A9 A14
A12
A7
A1
A0
A2
A5
A6
A3
A4
A18
HM628512A Series
5
Function Table
WE CS OE Mode VCC current Dout pin Ref. cycle
×H×Not selected ISB, ISB1 High-Z —
H L H Output disable ICC High-Z —
H L L Read ICC Dout Read cycle
L L H Write ICC Din Write cycle (1)
L L L Write ICC Din Write cycle (2)
Note: ×: H or L
Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage VCC –0.5 to +7.0 V
Voltage on any pin relative to VSS VT–0.5*1 to VCC + 0.3*2V
Power dissipation PT1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –10 to +85 °C
Notes: 1. –3.0 V for pulse half-width ≤ 30 ns
2. Maximum voltage is 7.0 V
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
VSS 000V
Input high voltage VIH 2.2 — VCC + 0.3 V
Input low voltage VIL –0.3*1 — 0.8 V
Note: 1. –3.0 V for pulse half-width ≤ 30 ns
HM628512A Series
6
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10% , VSS = 0 V)
Parameter Symbol Min Typ*1Max Unit Test conditions
Input leakage current |ILI|——1µA Vin = VSS to VCC
Output leakage current |ILO|——1µACS = VIH or OE = VIH or
WE = VIL, VI/O = VSS to VCC
Operating power supply current: DC ICC — 8 15 mA CS = VIL,
others = VIH/VIL, II/O = 0 mA
Operating power supply
current HM628512A-5 ICC1 — 45 70 mA Min cycle, duty = 100%
CS = VIL, others = VIH/VIL
II/O = 0 mA
HM628512A-7 ICC1 —40 60 mA
Operating power supply current ICC2 — 10 20 mA Cycle time = 1 µs,
duty = 100%
II/O = 0 mA, CS ≤ 0.2 V
VIH ≥ VCC – 0.2 V, VIL ≤ 0.2
V
Standby power supply current: DC ISB —1 3 mACS = VIH
Standby power supply current (1): DC ISB1 —2*
2100*2µA Vin ≥ 0 V, CS ≥ VCC – 0.2 V
—2*
350*3µA
Output low voltage VOL — — 0.4 V IOL = 2.1 mA
Output high voltage VOH 2.4 — — V IOH = –1.0 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. This characteristics is guaranteed only for L version.
3. This characteristics is guaranteed only for L-SL version.
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter Symbol Typ Max Unit Test conditions
Input capacitance*1Cin — 8 pF Vin = 0 V
Input/output capacitance*1CI/O —10pFV
I/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
HM628512A Series
7
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
• Input pulse levels: 0.8 V to 2.4 V
• Input rise and fall time: 5 ns
• Input and output timing reference levels: 1.5 V
• Output load: 1 TTL Gate + CL (100 pF) (HM628512A-7)
1 TTL Gate + CL (50 pF) (HM628512A-5)
(Including scope & jig)
Read Cycle
HM628512A
-5 -7
Parameter Symbol Min Max Min Max Unit Notes
Read cycle time tRC 55 — 70 — ns
Address access time tAA — 55 — 70 ns
Chip select access time tCO — 55 — 70 ns
Output enable to output valid tOE — 25 — 35 ns
Chip selection to output in low-Z tLZ 10 — 10 — ns 2
Output enable to output in low-Z tOLZ 5 — 5 — ns 2
Chip deselection to output in high-Z tHZ 0 20 0 25 ns 1, 2
Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2
Output hold from address change tOH 10 — 10 — ns
HM628512A Series
8
Write Cycle
HM628512A
-5 -7
Parameter Symbol Min Max Min Max Unit Notes
Write cycle time tWC 55 — 70 — ns
Chip selection to end of write tCW 50 — 60 — ns 4
Address setup time tAS 0 — 0 — ns 5
Address valid to end of write tAW 50 — 60 — ns
Write pulse width tWP 40 — 50 — ns 3, 12
Write recovery time tWR 0 — 0 — ns 6
WE to output in high-Z tWHZ 0 20 0 25 ns 1, 2, 7
Data to write time overlap tDW 25 — 30 — ns
Data hold from write time tDH 0—0—ns
Output active from output in high-Z tOW 5 — 5 — ns 2
Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 7
Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later
transition of CS going low or WE going low. A write ends at the earlier transition of CS going high
or WE going high. tWP is measured from the beginning of write to the end of write.
4. tCW is measured from CS going low to the end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measured from the earlier of WE or CS going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.
8. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10.Dout is the read data of next address.
11.If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
12.In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention. tWP ≥ tDW min + tWHZ max
HM628512A Series
9
Timing Waveforms
Read Timing Waveform (WE = VIH)
tAA
tCO
tRC
tLZ tOE
tOLZ
tHZ
tOHZ
Valid Data
Address
CS
OE
Dout
tOH
HM628512A Series
10
Write Timing Waveform (1) (OE Clock)
tWC
tCW
tWP
tAS
tOHZ
tDW tDH
tAW tWR
*8
Address
OE
CS
WE
Dout
Din Valid Data
HM628512A Series
11
Write Timing Waveform (2) (OE Low Fixed)
Address
CS
WE
Dout
Din
tWC
tCW tWR
tAW tWP
tAS tWHZ tOW
tOH
tDW tDH
*11
*9 *10
*8
Valid Data
HM628512A Series
12
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Test conditions*3
VCC for data retention VDR 2——V CS ≥ VCC – 0.2 V, Vin ≥ 0 V
Data retention current ICCDR —1*
450*1µAV
CC = 3.0 V, Vin ≥ 0 V
CS ≥ VCC – 0.2 V
—1*
415*2µA
Chip deselect to data retention time tCDR 0 — — ns See retention waveform
Operation recovery time tR5——ms
Notes: 1. For L-version and 20 µA (max.) at Ta = 0 to 40°C.
2. For SL-version and 3 µA (max.) at Ta = 0 to 40°C.
3. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin
levels (address, WE, OE, I/O) can be in the high impedance state.
4. Typical values are at VCC = 3.0 V, Ta = 25°C and specified loading, and not guaranteed.
Low VCC Data Retention Timing Waveform (CS Controlled)
VCC
4.5 V
2.2 V
0 V
CS
tCDR tR
CS ≥ VCC – 0.2 V
VDR
Data retention mode
HM628512A Series
13
Package Dimensions
HM628512ALP Series (DP-32) Unit: mm
0.51 Min
2.54 Min 5.08 Max
0.25+ 0.11
– 0.05
2.54 ± 0.25 0.48 ± 0.10 0° – 15°
41.90
42.50 Max
13.4
13.7 Max
1.20 15.24
32 17
116
2.30 Max 1.20
Hitachi Code
JEDEC Code
EIAJ Code
Weight
DP-32
—
SC-613
5.1 g
HM628512A Series
14
HM628512ALFP Series (FP-32D) Unit: mm
0.15 M
0.40 ± 0.08
20.45
1.00 Max
1.27
11.30
1.42
3.00 Max
0.22 ± 0.05
20.95 Max
32 17
116
0 – 8°
0.80 ± 0.20
14.14 ± 0.30
0.10
Hitachi Code
JEDEC Code
EIAJ Code
Weight
FP-32D
—
—
1.3 g
0.38 ± 0.06
+ 0.12
– 0.10
0.15
0.20 ± 0.04
HM628512A Series
15
HM628512ALTT Series (TTP-32D) Unit: mm
1.27
0.21 M
0.42 ± 0.08
0.10
10.16
20.95
21.35 Max 17
16
32
1
1.20 Max
0 – 5°
0.13 ± 0.05
0.17 ± 0.05
11.76 ± 0.20
0.50 ± 0.10
1.15 Max
0.80
Hitachi Code
JEDEC Code
EIAJ Code
Weight
TTP-32D
MO-133CA
—
0.51 g
0.40 ± 0.06
0.125 ± 0.04
HM628512A Series
16
HM628512ALRR Series (TTP-32DR) Unit: mm
1.27
0.21 M
0.42 ± 0.08
0.10
10.16
20.95
21.35 Max 16
17
1
32
1.20 Max
0 – 5°
0.13 ± 0.05
0.17 ± 0.05
11.76 ± 0.20
0.50 ± 0.10
1.15 Max
0.80
Hitachi Code
JEDEC Code
EIAJ Code
Weight
TTP-32DR
MO-133CA
—
0.51 g
0.40 ± 0.06
0.125 ± 0.04
HM628512A Series
17
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other
reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such
use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested
to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Tel: 415-589-8300
Fax: 415-583-4207
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 0628-585000
Fax: 0628-778322
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
HM628512A Series
18
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
0.0 Sep. 12, 1996 Initial issue K. Imato K. Imato
1.0 Dec. 2, 1996 Deletion of preliminary
