GENLINX TMII GS9025 Serial Digital Receiver PRELIMINARY DATA SHEET DESCRIPTION * SMPTE 259M compliant The GS9025 provides automatic cable equalization and high performance clock and data recovery for serial digital signals. The GS9025 receives either single-ended or differential serial digital data and outputs differential clock and retimed data signals at PECL levels (800mV). The onboard cable equalizer provides up to 40dB of gain at 200MHz which typically results in equalization of greater than 350m of high quality cable at 270Mb/s. * operational to 540Mb/s * automatic cable equalization (typically greater than 350m of high quality cable at 270Mb/s) * adjustment-free operation * auto-rate selection (5 rates) with manual override * single external VCO resistor for operation with five input data rates * data rate indication output * system friendly: serial data outputs muted and serial clock remains active when input data is lost * operation independent of SAV/EAV sync signals * signal strength indicator output * output 'eye' monitor (OEM) with large signal amplitude and power down option * carrier detect with programmable threshold level * power savings mode (output serial clock disable) * 44 pin MQFP The GS9025 operates in either auto or manual data rate selection mode. In both modes, the GS9025 requires only one external resistor to set the VCO centre frequency and provides adjustment free operation. The GS9025 has dedicated pins to indicate signal strength/carrier detect, LOCK and data rate. Optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. In addition, the GS9025 provides an 'Output Eye Monitor' (OEM) which allows the verification of signal integrity after equalization, prior to reslicing. The serial clock outputs can be disabled to reduce power consumption. The GS9025 operates from a single +5 or -5 volt supply. APPLICATIONS Cable equalization plus clock and data recovery for all high speed serial digital interface applications involving SMPTE 259M and other data standards. ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE GS9025-CQM 44 pin MQFP Tray 0C to 70C GS9025-CTM 44 pin MQFP Tape 0C to 70C A/D COSC DDI LOCK ANALOG DIGITAL MUX DDI CARRIER DETECT PHASELOCK HARMONIC LOGIC MUTE SDO SDI SDI + -- FREQUENCY ACQUISITION VARIABLE GAIN EQ STAGE SDO CLK_EN PHASE DETECTOR SCO SCO OEM EYE MONITOR 3 BIT COUNTER DIVISION AUTO EQ CONTROL SMPTE AUTO/MAN + AGC CAP CD_ADJ SSI/CD CHARGE PUMP LF+ LFS LF- VCO DECODER SS0 SS1 SS2 CBG RVCO BLOCK DIAGRAM Revision Date: November 2000 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 521 - 63 - 05 GS9025 FEATURES ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE Supply Voltage (VS) 5.5V Input Voltage Range (any input) VCC+0.5 to VEE-0.5V 0C TA 70C Operating Temperature Range GS9025 -65C TS 150C Storage Temperature Range Lead Temperature (soldering, 10 sec) 260C DC ELECTRICAL CHARACTERISTICS VCC = 5.0v, VEE = 0V, TA = 0C to 70C unless otherwise shown. PARAMETER SYMBOL TYP MAX UNITS 4.75 5.0 5.25 V 1 CLK_EN = 0 - 115 - mA 1 CLK_EN = 1 - 125 - mA 1 CLK_EN = 0, OEM active - 135 - mA 1 CLK_EN = 1, OEM active - 145 - mA 1 - 2.5 - V 1 DDI/DDI Common Mode Input Voltage Range VEE+(VDIFF/2) 0.4 to 4.6 VCC-(VDIFF/2) V DDI/DDI Differential Drive 200 800 2000 mV 1 AGC+/AGC- Common Mode Voltage - 2.7 - V 1 OEM Bias Potential - 4.5 - V VSSI/CD = 2.4V - +120 - A VSSI/CD = 0.4V (Muted) - -1.0 - mA VCC Supply Current S SDI/SDI Common Mode Voltage SSI/CD Output Current NOTES TEST LEVEL MIN Supply Voltage CONDITIONS 1 1 3 AUTO/MAN, SMPTE, SS[2:0] Input Voltage High 2.0 - - V Low - - 0.8 V CLK_EN Input Voltage High 2.5 - - V Low - - 0.8 V LOCK Output Sink Current 500 - - A 4 1 SS[2:0] Output Voltage High 4.4 4.7 - V 3 1 Low - 0.2 0.4 V 180 300 - A 3 1 SS[2:0] Source Current Auto Mode 3 1 1 2 GENNUM CORPORATION 521 - 63 - 05 DC ELECTRICAL CHARACTERISTICS (Continued) VCC = 5.0v, VEE = 0V, TA = 0C to 70C unless otherwise shown. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES TEST LEVEL Auto Mode 0.6 1 - mA 3 1 SS[2:0] Source Current Manual Mode - - 0 A 3 1 SS[2:0] Sink Current Manual Mode - 0.8 5 A 3 1 NOTES TEST LEVELS 1. VDIFF is the differential input signal swing. 1. 100% tested at 25C. 2. See DESCRIPTION. 2. Guaranteed by design. 3. Pins SS[2:0] are outputs in AUTO mode and inputs in MANUAL mode. 3. Inferred or correlated value. 4. LOCK is an open collector output and requires an external pullup resistor. AC ELECTRICAL CHARACTERISTICS VCC = 5.0V, VEE = 0V, TA = 0C to 70C unless otherwise shown. RLF = 1k, CLF1 = 15nF, CLF2 = 5.6pF PARAMETER SYMBOL CONDITIONS TYP MAX UNITS 143 - 540 Mb/s at 200MHz - 40 - dB 270Mb/s, 300m - 300 - ps p-p 540Mb/s, 100m - 275 - ps p-p - - 0.1 dB 2 - 15 % 2 Data Rate Maximum Equalizer Gain Additive Jitter tJ Jitter Transfer Function Peaking Frequency Drift when PLL loses lock Lock Time Synchronous Switch tSWITCH < 0.5s, 270Mb/s - 1 - s 0.5s<tSWITCH<10ms - 1 - ms tSWITCH > 10ms - 4 - ms - 10 - 600 800 -200 200 Lock Time Asynchronous Switch SDO/SDO, SCO/SCO Output Signal Swing 75 DC Load SDO to SCO Synchronization SDO/SDO, SCO/SCO Rise & Fall Times 20 - 80%, TA =25C NOTES TEST LEVELS MIN 1 see Figs 7-11 1 1 2 ms 2 2 1000 mVp-p 3 1 0 200 ps 2 300 400 ps 2 NOTES TEST LEVELS 1. Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie: line 10 switching for component NTSC). 1. 100% tested at 25C. 2. Asynchronous switching refers to switching the input data from one source to another source which is at a different data rate. 3. Inferred or correlated value. 2. Guaranteed by design. 4. Evaluated using test setup Figure 1. 3. Assuming 75 pullup resistors on SDO/SDO and SCO/SCO. DATA TEKTRONIX GigaBERT 1400 TRANSMITTER DATA GS9028 CABLE DRIVER BELDEN 8281 CABLE EB9025 BOARD TEKTRONIX GigaBERT 1400 ANALYZER CLOCK TRIGGER Fig. 1 Test Setup for Figures 6 - 11 3 GENNUM CORPORATION 521 - 63 - 05 GS9025 SS[2:0] Sink Current COSC 40 39 38 37 36 35 34 VEE LOCK 41 VCC SSI/CD 42 CLK_EN A/D 43 VEE SMPTE 44 OEM VCC_75 PIN CONNECTIONS SDO VCC 4 30 VEE VEE 5 GS9025 29 SCO SDI 6 TOP VIEW 28 SCO SDI 7 27 VEE VCC 8 26 AUTO/MAN VEE 9 25 SS0 CD_ADJ 10 24 SS1 AGC- 11 23 SS2 13 14 15 16 17 18 19 20 21 22 VCC 12 CBG 31 RVCO 3 RVCO_RTN VCC_75 VEE SDO LF- 32 LFS 2 LF+ DDI VEE VEE VCC 33 AGC+ 1 GS9025 DDI PIN DESCRIPTIONS NUMBER SYMBOL TYPE DESCRIPTION 1, 2 DDI/DDI I Digital data inputs (Differential ECL/PECL). 3, 44 VCC_75 I Power supply connection for internal 75 pullup resistors connected to DDI/DDI. 4, 8, 13, 22, 35 VCC I Most positive power supply connection. 5, 9, 14, 18, 27, 30, 33, 34, 37 VEE I Most negative power supply connection. 6, 7 SDI/SDI I Differential analog data inputs. 10 CD_ADJ I Carrier detect threshold adjust. 11, 12 AGC-, AGC+ I External AGC capacitor. 15 LF+ I Loop filter component connection. 16 LFS I Loop filter component connection. 17 LF- I Loop filter component connection. 19 RVCO_RTN I Frequency setting resistor return connection. 20 RVCO I Frequency setting resistor connection. 21 CBG I Internal bandgap voltage filter capacitor. 23, 24, 25 SS[2:0] I/O 26 AUTO/MAN I Data rate indication (auto mode) or data rate select (manual mode). TTL/CMOS compatible I/O. In auto mode these pins can be left unconnected. Auto or manual mode select. TTL/CMOS compatible input. 4 GENNUM CORPORATION 521 - 63 - 05 PIN DESCRIPTIONS (Continued) SYMBOL TYPE DESCRIPTION 28, 29 SCO/SCO O Serial clock output. SCO/SCO are differential current mode outputs and require external 75 pullup resistors. 31, 32 SDO/SDO O Equalized and reclocked serial digital data outputs. SDO/SDO are differential current mode outputs and require external 75 pullup resistors. 36 CLK_EN I Clock enable. When HIGH, the serial clock outputs are enabled. 38 COSC I Timing control capacitor for internal system clock. 39 LOCK O Lock indication. When HIGH, the GS9025 is locked. LOCK is an open collector output and requires an external 10k pullup resistor. 40 SSI/CD O Signal strength indicator/Carrier detect. 41 A/D I Analog/Digital select. 42 SMPTE I SMPTE/Other data rate select. TTL/CMOS compatible input. 43 OEM O Output `Eye' monitor. OEM is a single ended current mode output and requires an external 50 pullup resistor. GS9025 NUMBER 5 GENNUM CORPORATION 521 - 63 - 05 TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25C unless otherwise shown) 50 5.00 40 4.50 GAIN (dB) 35 4.00 3.50 30 GS9025 SSI/CD OUTPUT VOLTAGE (V) 45 25 20 15 3.00 10 5 2.50 0 50 100 150 200 250 300 350 400 450 0 500 1 10 100 1000 FREQUENCY (MHz) CABLE LENGTH (m) Fig. 2 SSI/CD Voltage vs. Cable Length (Belden 8281)(CD_ADJ = 0V) Fig. 3 Equalizer Gain vs. Frequency j1 j2 j0.5 5.0 CD_ADJ VOLTAGE (V) 4.5 j0.2 j5 4.0 3.5 270 3000 3.0 1620 -j0.2 2.5 -j5 810 2.0 200 250 300 350 400 CABLE LENGTH (m) -j0.5 -j2 -j1 Frequencies in MHz, impedances normalized to 50 Fig. 5 Input Impedance 450 450 400 400 ADDITIVE JITTER p-p (ps) TYPICAL ERROR FREE CABLE LENGTH (m) Fig. 4 Carrier Detect Adjust Voltage Threshold Characteristics 350 300 250 200 540Mb/s 350 270Mb/s 300 250 200 150 100 50 150 0 90 180 270 360 450 540 630 0 100 200 300 400 DATA RATE (Mb/s) CABLE LENGTH (m) Fig. 6 Error Free Cable Length vs. Data Rate Fig. 7 Additive Jitter vs. Input Cable Length (Belden 8281) 6 GENNUM CORPORATION 521 - 63 - 05 GS9025 Fig. 8 Output Jitter (143Mb/s, 300m) Fig. 9 Output Jitter (270Mb/s, 300m) Fig. 10 Output Jitter (360Mb/s, 300m) Fig. 11 Output Jitter (540Mb/s, 100m) DETAILED DESCRIPTION variation of the inverse cable loss characteristic with cable length. The gain stage provides up to 40dB of gain at 200MHz which typically results in equalization of greater than 350m at 270Mb/s of Belden 8281 cable. The GS9025 Serial Digital Receiver is a bipolar integrated circuit containing a built-in cable equalizer and reclocker. Serial digital signals are applied to either the analog SDI/SDI or digital DDI/DDI inputs. Signals applied to the SDI/SDI inputs are equalized and then passed to a multiplexer. Signals applied to the DDI/DDI inputs bypass the equalizer and go directly to the multiplexer. The analog/digital select pin (A/D) determines which signal is then passed to the reclocker. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by an external differential AGC filter capacitor (AGC+/AGC-) providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. Packaged in a 44 pin MQFP, the receiver operates from a single 5V supply to data rates of 540Mb/s. Typical power consumption is 575mW. 1. CABLE EQUALIZER The automatic cable equalizer is designed to equalize serial digital data signals between 30Mb/s and 540Mb/s. The equalized signal is DC restored, thereby restoring its logic threshold to its corrective level regardless of shifts due to AC coupling. The serial data signal is connected to the input pins (SDI/SDI) either differentially or single ended. The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the 7 GENNUM CORPORATION 521 - 63 - 05 noisy environments, it is not recommended to leave this pin floating. Connecting this pin to VEE disables the SDO/SDO muting function and allows for maximum possible cable length equalization. 2. SIGNAL STRENGTH INDICATION/CARRIER DETECT The GS9025 incorporates an analog signal strength indicator/carrier detect (SSI/CD) output indicating both the presence of a carrier and the amount of equalization applied to the signal. The voltage output of this pin versus cable length (signal strength) is shown in Figures 2 and 12. 4. OUTPUT EYE MONITOR SSI/CD OUTPUT VOLTAGE (V) 5 4 5. RECLOCKER The reclocker receives a differential serial data stream from the internal multiplexer. It locks an internal clock to the incoming data and outputs the differential PECL retimed data signal and recovered clock on outputs SDO/SDO and SCO/SCO, respectively. The timing between the output and clock signals is shown below. 3 CD_ADJ CONTROL RANGE 2 1 0 0 50 100 150 200 250 300 350 400 450 500 SDO CABLE LENGTH (m) Fig. 12 When the signal strength decreases to the level set at the "Carrier Detect Threshold Adjust" pin, the SSI/CD voltage goes to a logic "0" state (0.8 V) and can be used to drive other TTL/CMOS compatible logic inputs. In addition, when loss of carrier is detected the SDO/SDO outputs are muted (set to a known static state). SCO 50% Fig. 13 The reclocker contains four main functional blocks: the Phase Locked Loop, Frequency Acquisition, Logic Circuit, and Auto/Manual Data Rate Select. 3. CARRIER DETECT THRESHOLD ADJUST This feature has been designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. The use of a Carrier Detect function with a fixed internal reference does not solve this problem since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. To alleviate this problem, the GS9025 provides a user adjustable threshold to meet the unique conditions that exist in each user's application. Override and internal default settings have also been provided to give the user total flexibility. 5.1. Phase Locked Loop (PLL) The Phase Locked Loop locks the internal PLL clock to the incoming data rate. A simplified block diagram of the PLL is shown below. The main components are the VCO, the phase detector, the charge pump, and the loop filter. The threshold level at which loss of carrier is detected is adjustable via external resistors at the CD_ADJ pin. The control voltage at the CD_ADJ pin is set by a simple resistor divider circuit (see Typical Application Circuit). The threshold level is adjustable from 200m to 350m. By default (no external resistors), the threshold is typically 320m. In 8 GENNUM CORPORATION 521 - 63 - 05 GS9025 The GS9025 also provides an 'Output Eye Monitor' (OEM) which allows the verification of signal integrity after equalization, prior to reslicing. The OEM pin is an open collector current output that requires an external 50 pullup resistor. When the pullup resistor is not used, the OEM block is disabled and the internal OEM circuit is powered down. The OEM provides a 100mVp-p signal when driving a 50 oscilloscope input. With 0m of cable (800mV input signal levels), the SSI/CD output voltage is approximately 4.5V. As the cable length increases, the SSI/CD voltage decreases linearly providing accurate correlation between the SSI/CD voltage and cable length. DDI/DDI The VCO and an internal divider generate the PLL clock. Divider moduli of 1, 2, and 4 allow the PLL to lock to data rates from 143Mb/s to 540Mb/s. The divider modulus is set by the AUTO/MAN, SMPTE, and SS[2:0] pins (see Auto/Manual Data Rate Select section for further details). In addition, a manually selectable modulus 8 divider allows operation at data rates as low as 30Mb/s. 2 PHASE DETECTOR INTERNAL PLL CLOCK DIVISION CHARGE PUMP LF+ LFS The phase detector compares the phase of the PLL clock with the phase of the incoming data signal and generates error correcting timing pulses. The phase detector design provides a linear transfer function between the input phase and output timing pulses maximizing the input jitter tolerance of the PLL. VCO LF- RVCO LOOP FILTER RLF CLF1 5.1.3. Charge Pump CLF2 The charge pump takes the phase detector output timing pulses and creates a charge packet that is proportional to the system phase error. A unique differential charge pump design insures that the output phase does not drift when data transitions are sparse. This makes the GS9025 ideal for SMPTE 259M applications where pathological signals have data transition densities of 0.05. Fig. 14 5.1.1. VCO The VCO is a differential low phase noise, factory trimmed design that provides increased immunity to PCB noise and precise control of the VCO center frequency. The VCO operates between 30 and 540Mb/s and has a pull range of 15% about the center frequency. A single low impedance external resistor, RVCO, sets the VCO center frequency (see Figure 15). The low impedance RVCO minimizes thermal noise and reduces the PLL's sensitivity to PCB noise. 5.1.4. Loop Filter The loop filter integrates the charge pump packets and produces a VCO control voltage. The loop filter is comprised of three external components which are connected to pins LF+, LFS, and LF-. The loop filter design is fully differential giving the GS9025 increased immunity to PCB board noise. For a given RVCO value, the VCO can oscillate at one of two frequencies. When SMPTE = SS0 = logic 1, the VCO center frequency corresponds to the L curve. For all other SMPTE/ SS0 combinations, the VCO center frequency corresponds to the H curve (H is approximately 1.5 x L). The loop filter components are critical in determining the loop bandwidth and damping of the PLL. Choosing these component values is discussed in detail in the PLL DESIGN GUIDELINES section. Recommended values for SMPTE259M applications are shown in the Typical Application Circuit. 800 VCO REQUENCY (MHz) 700 600 500 5.2. Frequency Acquisition 400 H The core PLL is able to lock if the incoming data rate and the PLL clock frequency are within the PLL capture range (which is slightly larger than the loop bandwidth). To assist the PLL to lock to data rates outside of the capture range, the GS9025 uses a frequency acquisition circuit. 300 L 200 SMPTE=1 SSO=1 100 0 0 200 400 600 800 1000 1200 1400 1600 1800 The frequency acquisition circuit sweeps the VCO control voltage such that the VCO frequency changes from -10% to +10% of the center frequency. Figure 16 shows a typical sweep waveform. RVCO () Fig. 15 The recommended RVCO value for auto rate SMPTE 259M applications is 365. 9 GENNUM CORPORATION 521 - 63 - 05 GS9025 5.1.2. Phase Detector 5.4.1. Auto Mode (AUTO/MAN = 1) tsys tswp VLF A Tcycle Tcycle = tswp + tsys TABLE 1 Fig. 16 The VCO frequency starts at point A and sweeps up attempting to lock. If lock is not established during the up sweep, the VCO is then swept down. The system is designed such that the probability of locking within one cycle period is greater than 0.999. If the system does not lock within one cycle period, it will attempt to lock in the subsequent cycle. In manual mode, the divider modulus is fixed for all cycles. In auto mode, each subsequent cycle is based on a different divider moduli as determined by the internal 3-bit counter. AUTO/MAN = 1 (AUTO MODE) H, L = VCO center frequency as per figure 15. SMPTE SS[2:0] DIVIDER MODULI PLL CLOCK 1 000 4 H/4 1 001 2 L/2 1 010 2 H/2 1 011 1 L 1 100 1 H 1 101 - - 4 C LF1 t swp = ---------------3I CP 1 110 - - 1 111 - - The nominal sweep time is approximately 121s when CLF1 = 15nF and CP = 165A (RVCO = 365). 0 000 4 H/4 0 001 4 H/4 0 010 2 H/2 0 011 2 H/2 0 100 1 H 0 101 - - 0 110 - - 0 111 - - The average sweep time, tswp, is determined by the loop filter component, CLF1, and the charge pump current, CP: An internal system clock determines tsys (see the Logic Circuit section). 5.3. Logic Circuit The GS9025 is controlled by a finite state logic circuit which is clocked by an asynchronous system clock. That is, the system clock is completely independent of the incoming data rate. The system clock runs at low frequencies, relative to the incoming data rate, and thus reduces interference to the PLL.The period of the system clock is set by the COSC capacitor and is: 5.4.2. Manual Mode (AUTO/MAN = 0) 4 In manual mode, the GS9025 divider moduli is fixed. In this mode, the SS[2:0] pins are inputs and set the divider moduli according to Table 2. tsys = 9.6 x 10 x COSC [seconds] The recommended value for tsys is 450s (COSC = 4.7nF) 5.4. Auto/Manual Data Rate Select 6. LOCKING The GS9025 can operate in either auto or manual data rate select mode. The mode of operation is selected by a single input pin (AUTO/MAN). The GS9025 indicates lock when three conditions are satisfied: 1. input data is detected 2. the incoming data signal and the PLL clock are phase locked 3. the system is not locked to a harmonic 10 GENNUM CORPORATION 521 - 63 - 05 GS9025 In auto mode, the GS9025 uses a 3-bit counter to automatically cycle through five (SMPTE=1) or three (SMPTE=0) different divider moduli as it attempts to acquire lock. In this mode, the SS[2:0] pins are outputs and indicate the current value of the divider moduli according to the table below. Note that for SMPTE = 0 and divider moduli of 2 and 4, the PLL can correctly lock for two values of SS[2:0]. SS[2:0] DIVIDER MODULI PLL CLOCK 1 000 4 H/4 1 001 2 L/2 TABLE 3 1 010 2 H/2 SWITCHING TIME LOCK TIME 1 011 1 L < 0.5s 10s 1 100 1 H 0.5s - 10ms 2tsys 1 101 8 L/8 > 10ms 2Tcycle + 2tsys 1 110 8 H/8 1 111 - - 0 000 4 H/4 0 001 4 H/4 0 010 2 H/2 0 011 2 H/2 0 100 1 H 0 101 1 H 0 110 8 H/8 0 111 - - AUTO/MAN = 1 (MANUAL MODE) H, L = VCO center frequency as per figure 15. GS9025 SMPTE When input data to the GS9025 is removed, the GS9025 latches the current state of the counter (divider modulus). Therefore, when data is reapplied, the GS9025 begins the lock procedure at the previous locked data rate. As a result, in synchronous switching applications, the GS9025 locks very quickly. The nominal lock time depends on the switching time and is summarized in the table below: TABLE 2 In asynchronous switching applications (including power up) the lock time is determined by the frequency acquisition circuit as described above. In manual mode, the frequency acquisition circuit may have to sweep over an entire cycle (depending on initial conditions) to acquire lock resulting in a maximum lock time of 2Tcycle + 2tsys. In auto tune mode, the maximum lock time is 6Tcycle + 2tsys since the frequency acquisition circuit may have to cycle through 5 possible counter states (depending on initial conditions) to acquire lock. The nominal value of Tcycle for the GS9025 operating in a typical SMPTE 259M application is approximately 1.3ms. The GS9025 defines the presence of input data when at least one data transition occurs every 1s. The GS9025 assumes that it is NOT locked to a harmonic if the pattern `101' or `010' (in the reclocked data stream) occurs at least once every tsys/3 seconds. Using the recommended component values, this corresponds to approximately 150s. (In an harmonically locked system, all bit cells are double clocked and the above patterns become `110011' and `001100', respectively.) The GS9025 has a dedicated LOCK output (pin 39) indicating when the device is locked. It should be noted that in synchronous switching applications where the switching time is less than 0.5s, the LOCK output will NOT be de-asserted and the data outputs will NOT be muted. 8. OUTPUT DATA MUTING The GS9025 internally mutes the SDO and SDO outputs when the device is not locked. When muted, SDO/SDO are latched providing a logic state to the subsequent circuit and avoiding a condition where noise could be amplified and appear as data. The output data muting timing is shown in Figure 17. 7. LOCK TIME The lock time of the GS9025 depends on whether the input data is switching synchronously or asynchronously. Synchronous switching refers to the case where the input data is changed from one source to another source which is at the same data rate (but different phase). Asynchronous switching refers to the case where the input data to the GS9025 is changed from one source to another source which is at a different data rate. NO DATA TRANSITIONS DDI LOCK SDO VALID DATA OUTPUTS MUTED VALID DATA Fig. 17 11 GENNUM CORPORATION 521 - 63 - 05 9. CLOCK ENABLE This response has (wP1,wBW,wP2) where: 1 zero (wZ) and three poles 1 w Z = ----------------------C LF1 R LF 1 w P1 = -------------------------------------L C LF1 R LF - --------R LF GS9025 When CLK_EN is high, the GS9025 SCO/SCO outputs are enabled. When CLK_EN is low, the SCO/SCO outputs are tri-stated and float to VCC. Disabling the clock outputs results in a power savings of 10%. It is recommended that the CLK_EN input be hard wired to the desired state. For applications which do not require the clock output, CLK_EN should be connected to Ground and the SCO/SCO outputs should be connected to VCC. R LF w BW = --------L 10. STRESSFULL DATA PATTERNS All PLL's are susceptible to stressful data patterns which can introduce bit errors in the data stream. PLL's are most sensitive to patterns which have long run lengths of 0's or 1's (low data transition densities for a long period of time). The GS9025 has been designed to operate with low data transition densities such as the SMPTE 259M pathological signal (data transition density = 0.05). 1 w P2 = ----------------------C LF2 RLF The bode plot for this transfer function is plotted in Figure 19. The reclocking performance of the GS9025 is primarily determined by the PLL. Thus, it is important that the system designer is familiar with the basic PLL design equations. A model of the GS9025 PLL is shown below. The main components are the phase detector, the VCO, and the external loop filter components. AMPLITUDE 11. PLL DESIGN GUIDELINES PHASE DETECTOR Oi + WZ CP KPD - WP2 Fig. 19 Oo The 3dB bandwidth approximately: RLF CLF1 WBW FREQUENCY VCO 2 K Ns LOOP FILTER WP1 CLF2 of the transfer function is wBW w BW w 3dB = ---------------------------------------------------------------------- -----------2 0.78 w BW ( w BW w P2 ) ----------+ ---------------------------------1-2 w P2 w BW 1 - 2 -----------wP2 Fig. 18 11.1. Transfer Function The transfer function of the PLL is defined as Oo/Oi and can be approximated as: 11.2. Transfer Function Peaking There are two causes of peaking in the PLL transfer function given by Equation 1. sC LF1 R LF + 1 Oo 1 ------- = ---------------------------------------------------------------- --------------------------------------------------------L L 2 Oi s CLF1 R LF - --------- + 1 s C LF2 L + s --------- + 1 R LF R LF The first is quadratic: Equation 1 where N L = ------------------DI CP K L 2 s C LF2 L + s --------- + 1 R LF and which has: N is the divider modulus 1 wo = -------------------C LF2 L D is the data density (=0.5 for NRZ data) ICP is the charge pump current in Amps and R LF2 Q = RLF ----------L This response is critically damped for Q = 0.5. K is the VCO gain in Hz/V 12 GENNUM CORPORATION 521 - 63 - 05 Thus, to avoid peaking: C LF2 1 R LF ------------ < --2 L or L 1 -------------------------- --------- > 4 RLF2 C LF2 R LF Therefore, wP2 > 4 wBW The second is the zero-pole combination: 350 300 250 200 150 GS9025 However, it is desirable to keep wP2 as low as possible to reduce the high frequency content on the loop filter. CHANGE PUMP CURRENT (A) 400 100 50 0 s ------- + 1 sC LF1 R LF + 1 wZ ---------------------------------------------------------- = -------------------s-+1 1 +1 --------s C LF1 RLF - -------- w P1 R LF 0 200 400 600 800 1000 1200 1400 1600 1800 RVCO () Fig. 20 11.4. SPICE Simulations This causes lift in the transfer function given by: More detailed analysis of the GS9025 PLL can be done using SPICE. A SPICE model of the PLL is shown below: w P1 1 20 LOG ---------- = 20 LOG --------------------wZ wZ 1 - ----------w BW PHII G1 IN+ To keep peaking to less than 0.05dB: wZ < 0.0057wBW V1 PHIO LF E1 2 K IN- Ns RLF 1 11.3. Selection of Loop Filter Components Based on the above analysis, the loop filter components should be selected for a given PLL bandwidth, 3dB, as follows: CLF1 R2 CLF2 NOTE: PHII, PHIO, LF, and 1 are node names in the SPICE netlist. 1. Calculate Fig. 21 2N L = -------------ICP K where: ICP is the charge pump current and is a function of the RVCO resistor and is obtained from Figure 21. K = 90MHz/V for VCO frequencies corresponding to the L curve. K = 140MHz/V for VCO frequencies corresponding to the H curve. N is the divider modulus 2. Choose RLF = 2(3.14)3dB(0.78)L 4. Choose CLF2 = L/4(RLF) V1 is used to generate the input phase waveform. G1 compares the input and output phase waveforms and generates the charge pump current, CP. The loop filter components integrate the charge pump current to establish the loop filter voltage. E1 creates the output phase waveform (PHIO) by multiplying the loop filter voltage by the value of the Laplace transform (2K/Ns). The net list for the model is given below. The .PARAM statements are used to set values for CP, K, N, and D. CP is determined by the RVCO resistor and is obtained from Figure 20. (L, H and N can be obtained from Table 1 or Table 2) 3. Choose CLF1 = 174L/(RLF) The model consists of a voltage controlled current source (G1), the loop filter components (RLF, CLF1, and CLF2) a voltage controlled voltage source (E1), and a voltage source (V1). R2 is necessary to create a DC path to ground for Node 1. 2 2 13 GENNUM CORPORATION 521 - 63 - 05 RSOURCE ZO DDI RLOAD RSOURCE 12. I/O DESCRIPTION GS9025 DDI ZO Fig. 24 12.1. High Speed Analog Inputs (SDI/SDI) SDI/SDI are high impedance inputs differential or single-ended input drive. which accept Figure 22 shows the recommended interface when a singleended serial digital signal is used. 75 Figure 25 shows the recommended interface when the GS9025 digital inputs are driven single-endedly. In this case, the input must be AC-coupled and a matching resistor (Zo) must be used. DDI 10nF ZO SDI 75 113 10nF GS9025 DDI GS9025 SDI Fig. 25 Fig. 22 12.2. High Speed Digital Inputs (DDI/DDI) DDI/DDI are high impedance inputs which accept differential or single-ended input drive. Two conditions must be observed when interfacing to these inputs: 1. Input signal amplitudes are between 200 and 2000 mV 2. The common mode input voltage range is as specified in the DC Characteristics table. Commonly used interface examples are shown in Figures 23 through 25. Figure 23 illustrates the simplest interface to the GS9025 digital inputs. In this example, the driving device generates the PECL level signals (800mV amplitudes) having a common mode input range between 0.4 and 4.6V. This scheme is recommended when the trace lengths are less than 1in. The value of the resistors depends on the output driver circuitry. When the DDI and the DDI inputs are not used, either pins 44 and 1 or pins 2 and 3 should be connected to VCC in order to saturate one input of the differential amplifier. 12.3. High Speed Outputs (SDO/SDO and SCO/SCO) SDO/SDO and SCO/SCO are current mode outputs that require external pullups (see Figure 26). The output signal swings are 800mV when 75 resistors are used. A diode can be placed between VCC and the pullups to shift the signal levels down by approximately 0.7 volts. When the output traces are longer than 1in, controlled impedance traces should be used. The pullup resistors should be placed at the end of the output traces as they terminate the trace in its characteristic impedance (75). VCC 75 75 75 75 SDO SDO GS9025 SCO SCO DDI GS9025 DDI VCC Fig. 23 Fig. 26 14 GENNUM CORPORATION 521 - 63 - 05 GS9025 When trace lengths become greater than 1in, controlled impedance traces should be used. The recommended interface is shown in Figure 25. In this case, a parallel resistor (RLOAD) is placed near the GS9025 inputs to terminate the controlled impedance trace. The value of RLOAD should be 2 times the value of the characteristic impedance of the trace. In addition, series resistors, RSOURCE, can be placed near the driving chip to serve as source terminations. They should be equal to the value of the trace impedance. Assuming 800mV output swings at the driver, RLOAD = 100, RSOURCE = 50 and ZO = 50. SPICE NETLIST * GS9025 PLL Model .PARAM ICP = 165E-6 KF= 90E+6 .PARAM N = 1 D = 0.5 .PARAM PI = 3.14 .IC V(Phio) = 0 .ac dec 30 1k 10meg RLF 1 LF 1000 CLF1 1 0 15n CLF2 0 LF 15p E_LAPLACE1 Phio 0 LAPLACE {V(LF)} {(2*PI*KF)/(N*s)} G1 0 LF VALUE{D * ICP/(2*pi)*V(Phii, Phio)} V1 2 0 DC 0V AC 1V R2 0 1 1g .END TYPICAL APPLICATION CIRCUIT VCC VCC 50 1n VCC VCC VCC 4.7n 10k VCC VCC 38 37 36 35 34 OEM SMPTE A/D SSI/CD LOCK COSC VEE CLK_EN VCC VEE 3 VCC_75 SDO 31 4 VCC VEE 30 5 VEE SCO 29 6 SDI SCO 28 7 SDI VEE 27 AUTO/MAN 26 10n 8 GS9025 TOP VIEW VCC 11 AGC- SS2 23 15 16 17 18 Power supply decoupling capacitors are not shown. 100p 20 21 22 365 (1%) 1k 15n VCC 19 VCC 14 CBG 13 RVCO 12 All resistors in ohms, all capacitors in microfarads, unless otherwise stated. RVCO_RTN 24 VEE SS1 LF- CD_ADJ LFS 10 LF+ 25 VEE SS0 VCC VEE AGC+ 9 VCC 4 x 75 see Note 2 To GS9020 VCC } To LED Driver (optional) VCC 0.1 0.1 5.6p NOTES 1. It is recommended that the DDI/DDI inputs are not driven when the SDI/SDI inputs are being used. This minimizes crosstalk between the DDI/DDI and SDI/SDI inputs and maximizes performance. 2. These resistors are not needed if the internal pull-up resistors on the GS9020 are used. TABLE 4: RVCO = 365, H = 540MHz, L = 360MHz SMPTE SS[2:0] DATA RATE (Mb/s) LOOP BANDWIDTH 1 000 143 850kHz 1 001 177 1.40MHz 1 010 270 1.70MHz 1 011 360 3.0MHz 1 100 540 4.0MHz 15 GENNUM CORPORATION 521 - 63 - 05 GS9025 100k Pot (Optional) 39 32 VCC VCC 40 SDO VCC 75 10n VCC 41 DDI 2 37.5 42 33 DDI 75 75 43 VEE 1 From GS9024 see Note 1 44 VCC_75 VCC PACKAGE DIMENSIONS 13.20 0.25 10.00 0.10 GS9025 13.20 0.25 10.00 0.10 PIN 1 0.80 BSC 0.45 MAX 0.30 MIN 5 to 16 0.20 MIN 0 MIN 2.20 MAX 1.85 MIN 7 MAX 0 MIN 2.55 MAX 0.23 MAX. 0.35 MAX 0.15 MIN 0.3 MAX. RADIUS 5 to 16 0.88 NOM. 0.13 MIN. RADIUS 1.60 REF All dimensions in millimetres 44 pin MQFP CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION REVISION NOTES: PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change. Clarified symbols for pin numbers 28, 29, 31, and 32; Changed SSI/CD to SSI/CD. For latest product information, visit www.gennum.com GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright August 1997 Gennum Corporation. All rights reserved. Printed in Canada. 16 521 - 63 - 05