LM3280TL/NOPB - NATIONAL SEMICONDUCTOR

LM3280

LM3280 Adjustable Step-Down DC-DC Converter and 3 LDOs for RF Power

Management

Literature Number: SNOSAU4A

January 2007

LM3280

Adjustable Step-Down DC-DC Converter and 3 LDOs for RF

Power Management

General Description

The LM3280 is a multi-functional Power Management Unit,

optimized for low-power handheld applications such as Cel-

lular Phones.

The LM3280 incorporates three low-dropout LDO voltage

regulators and one step down PWM DC-DC converter with an

internal Bypass FET. The step down converter's output volt-

age can be set using an analog input (VCON) for optimizing

efficiency of the RF PA at various power levels. The LDO op-

erates a nominal output voltage of 2.85V and maximum load

current capability of 20mA for a reference voltage required by

linear RF power amplifiers. The LM3280 additionally features

a separate enable pin for each output.

The LM3280 is available in a 16-pin lead free micro SMD

package.

Features

■2MHz (typ.) PWM Switching Frequency

■Operates from a single Li-Ion cell (2.7V to 5.5V)

■Adjustable Output Voltage (0.8V to 3.6V) DC-DC

■High-efficiency synchronous buck converter

■300mA Maximum load capability (PWM mode)

■500mA Maximum load capability (Bypass mode)

■PWM, Forced and Automatic Bypass Mode

■3 Low-dropout and fast transient response LDOs

■16-pin micro SMD Package

■Current Overload Protection

■Thermal Overload Protection

Applications

■Cellular Phones

■Hand-Held Radios

■Battery Powered RF Devices

Typical Application

20181901

FIGURE 1. LM3280 Typical Application

LM3280 Adjustable Step-Down DC-DC Converter and 3 LDOs for RF Power Management

Connection Diagrams

20181902

16–Bump Thin Micro SMD Package, Large Bump

See NS Package Number TLA16QQA

Order Information

Order Number LDO3

Option

Package

Marking (Note)

Supplied As

LM3280TL 2.85V

(Default)

XYTT V001 250 Units, Tape and Reel

LM3280TLX 2.85V

(Default)

XYTT V001 3000 Units, Tape and Reel

LM3280TL-275 2.75V* XYTT V002 250 Units, Tape and Reel

LM3280TLX-275 2.75V* XYTT V002 3000 Units, Tape and Reel

LM3280TL-280 2.80V* XYTT V003 250 Units, Tape and Reel

LM3280TLX-280 2.80V* XYTT V003 3000 Units, Tape and Reel

LM3280TL-290 2.90V* XYTT V004 250 Units, Tape and Reel

LM3280TLX-290 2.90V* XYTT V004 3000 Units, Tape and Reel

Note: The package marking “XY” designates the date code. “TT” is a NSC internal code for die traceability.

*: The other 3 options apart from the default are available on request, contact your local sales representative.

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LM3280

Pin Descriptions

Pin # Name Description

A1 LDO1 LDO1 Output.

B1 LDO2 LDO2 Output.

C1 LDO3 LDO3 Output.

D1 ENLDO3 LDO3 Enable Input. Set this digital input high to turn on LDO3. (ENBUCK pin must be also set high.) For

turning LDO3 off, set low.

A2 SVIN Analog, Signal, and LDO Supply Input.

B2 FB Buck Converter Feedback Analog Input. Connect to the output at the output filter capacitor.

C2 ENLDO2 LDO2 Enable Input. Set this digital input high to turn on LDO2. (ENBUCK pin must be also set high.) For

turning LDO2 off, set low.

D2 VCON Buck Converter Voltage Control Analog Input. This pin controls VOUT in PWM mode. Set: VOUT = 3 x

VCON. Do not leave floating.

A3 SGND Analog, Signal, and LDO Ground.

B3 ENBUCK Buck Converter Enable Input. Set this digital input high after Vin >2.7V for normal operation. For shutdown,

set low.

C3 ENLDO1 LDO1 Enable Input. Set this digital input high to turn on LDO1. (ENBUCK pin must be also set high.) For

turning LDO1 off, set low.

D3 BYP Forced Bypass Input. Use this digital input to command operation in Bypass mode. Set BYP low (<0.4V)

for normal operation.

A4 BYPOUT Bypass FET Drain. Connect to the output capacitor. Do not leave floating.

B4 PVIN Buck Converter Power Supply Voltage Input to the internal PFET switch and Bypass FET.

C4 SW Buck Converter Switch Node connection to the internal PFET switch and NFET synchronous rectifier.

Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current

Limit of the PWM Buck Converter.

D4 PGND Buck Converter Power Ground.

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LM3280

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

SVIN, PVIN to SGND −0.2V to +6.0V

PGND to SGND −0.2V to +0.2V

ENs, FB, BYP, VCON (SGND −0.2V)

to (SVIN +0.2V)

w/6.0V max

SW, BYPOUT (PGND −0.2V)

to (PVIN +0.2V)

w/6.0V max

PVIN to SVIN −0.2V to +0.2V

Continuous Power Dissipation

(Note 3) Internally Limited

Junction Temperature (TJ-MAX)+150°C

Storage Temperature Range −65°C to +150°C

Maximum Lead Temperature

(Soldering, 10 sec.) +260°C

ESD Rating (Note 4)

Human Body Model

Machine Model

2k V

200 V

Operating Ratings (Notes 1, 2)

Input Voltage Range 2.7V to 5.5V

Recommended Load Current

PWM Mode: 0mA to 300mA

Bypass Mode: 0mA to 500mA

LDO: 0mA to 20mA

Junction Temperature (TJ) Range −30°C to +125°C

Ambient Temperature (TA) Range

(Note 5)

−30°C to +85°C

Thermal Properties

Junction-to-Ambient Thermal Resistance

(θJA), TLA16 Package (Note 6)

48 °C/W

General Electrical Characteristics (Notes 2, 7) Limits in standard typeface are for TA = TJ = 25°C. Limits

in boldface type apply over the full operating ambient temperature range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted,

specifications apply to the LM3280 with: VIN = ( SVIN = PVIN = ) 3.6V, ENBUCK = 3.6V, ENLDO1 = ENLDO2 = ENLDO3 = BYP = 0V,

FB = 2V, VCON = 0.267V.

Symbol Parameter Conditions Min. Typ. Max Units

IQShutdown Supply Current ENBUCK = 0V,

FB = SW = VCON = 0V,

BYPOUT = 0V

0.1 3µA

No Load Supply Current ENBUCK = 3.6V,

BYPOUT = 0V

720 800 µA

ENBUCK = 3.6V,

BYPOUT = 0V,

ENLDO1 = 3.6V

920 1300 µA

ENBUCK = BYP = 3.6V 720 800 µA

ENBUCK = BYP = 3.6V,

ENLDO1 = 3.6V

920 1300 µA

VIH Logic High Input Threshold Voltage for

ENx, BYP

FB = 0V 1.2 V

VIL Logic Low Input Threshold Voltage for

ENx, BYP

FB = 0V 0.4 V

IPDWN Logic Input Pull Down Current for ENx,

BYP

ENx, BYP = 3.6V 5 10 µA

THSD Thermal Shutdown Temperature (Note 7) 150 °C

Hysteresis Temperature (Note 7) 25 °C

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LM3280

Buck Electrical Characteristics (Notes 2, 7) Limits in standard typeface are for TA = TJ = 25°C. Limits in

boldface type apply over the full operating ambient temperature range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted,

specifications apply to the LM3280 with: VIN = ( SVIN = PVIN = ) 3.6V, ENBUCK = 3.6V, ENLDO1 = ENLDO2 = ENLDO3 = BYP = 0V,

FB = 2V, VCON = 0.267V.

Symbol Parameter Conditions Min. Typ. Max Units

VFB_ MIN Feedback Voltage at Minimum Setting VCON = 0.267V 0.75 0.800 0.85 V

VFB_ MAX Feedback Voltage at Maximum Setting VCON = 1.20V, VIN = 4.2V 3.528 3.600 3.672 V

OVP Over-Voltage Protection Threshold (Note 9) 330 400 mV

VBYPASS− Auto Bypass Detection Negative

Threshold

(Note 10) 160 250 320 mV

VBYPASS+ Auto Bypass Detection Positive

Threshold

(Note 10) 350 450 540 mV

RDSON (P) Pin-Pin Resistance for PFET ISW = 500mA, FB = 0V 320 450 mΩ

RDSON (N) Pin-Pin Resistance for N-FET ISW = - 200mA 310 450 mΩ

RDSON (BYP) Pin-Pin Resistance for Bypass FET IBYPOUT = 500mA 85 120 mΩ

ILIM-PWM Switch Current Limit FB = 0V (Note 12) 700 820 940 mA

ILIM-BYP Bypass FET Current Limit (Note 13) 800 1000 1200 mA

FOSC Internal Oscillator Frequency 1.8 22.2 MHz

Gain VCON to VOUT Gain 0.267V ≤ VCON ≤ 1.20V,

VIN = 4.2V 3 V/V

ICON VCON Input Leakage Current VCON = 1.2V 10 nA

Buck System Characteristics (Note 2) The following spec table entries are guaranteed by design if the

component values in the typical application circuit are used. These parameters are not guaranteed by production testing.

Symbol Parameter Conditions Min Typ Max Units

TRESPONSE Time for VOUT to Rise from

0.8V to 3.4V in PWM Mode

VIN = 4.2V, COUT = 4.7µF,

RLOAD = 15Ω

L = 2.2 µH (ISAT > 0.94A)

25 µs

TSTARTUP Time for VOUT to rise to 3.4V

in PWM Mode

(Note 14)

VIN = 4.2V, COUT = 4.7µF,

RLOAD = 15Ω

L = 2.2µH (ISAT = 0.94A)

EN = Low to High

36 µs

CCON VCON Input Capacitance VIN = 3.6V, VCON = 1V,

Test Freq. = 100kHz 15 pF

TON_BYP Bypass FET Turn On Time In

Bypass Mode

VIN = 3.6V, VCON = 0.267V,

COUT = 4.7µF, RLOAD = 15Ω

BYP = Low to High

30 µs

TBYP Auto Bypass Detect Delay

Time

(Note 10) 10 15 20 µs

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LM3280

LDO1, 2, and 3 Electrical Characteristics (Notes 2, 7) Limits in standard typeface are for TA = TJ =

25°C. Limits in boldface type apply over the full operating ambient temperature range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise

noted, specifications apply to the LM3280 with: VIN = 3.6V, ENBUCK = 3.6V, BYP = 0V, FB = 2V, VCON = 0.267V, ENLDOx = 3.6V

(Note 16).

Symbol Parameter Conditions Min Typ Max Units

VLDO LDO Output Voltage

Accuracy

VLDO = 2.85V, IOUT = 1mA -1

-2

ΔVLDO Line Regulation VIN = VLDO(nom) + 0.5V to 5.5V,

IOUT = 1mA

0.1 %/V

Load Regulation IOUT = 1mA to 20mA 0.01 0.04 %/mA

ILIM_LDO LDO Current Limit (Note 15) 30 40 55 mA

IPU Pull-Up Current (Note 15) 40 60 80 mA

RPD Pull-Down Resistance IOUT = -50mA,

ENBUCK = all ENLDO = 0V

10 13.5 17 Ω

VDROP Dropout Voltage IOUT = 20mA (Note 17) 70 115 mV

LDO1, 2, and 3 System Characteristics (Note 2) The following spec table entries are guaranteed by

design if the component values in the typical application circuit are used. Unless otherwise noted, specifications apply to the LM3280

with: VIN = 3.6V. These parameters are not guaranteed by production testing.

Symbol Parameter Conditions Min Typ Max Units

PSRR Power Supply Ripple Rejection

Ratio

Test Freq. = 1KHz, VRIPPLE = 0.5Vpp

COUT = 1µF, IOUT = 1mA, BYP = VIN

55 dB

TLDO_ON Time to reach 90% of VLDO(nom)

after ENLDO signal goes high.

VIN = ENBUCK = 3V,

COUT = 1µF,

ENLDOx = Low to High,

RLOAD = 270Ω

50 100 µs

VIN = 3V,

COUT = 1µF,

ENBUCK = ENLDOx = Low to High,

RLOAD = 270Ω

80 130 µs

TLDO_OFF Time to reach 0.1V of VLDO after

ENLDO signal goes low.

VIN = 3V,

COUT = 1µF,

ENLDOx = High to Low,

IOUT = 0mA

50 200 µs

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,

see the Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pins.

Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ

= 125°C (typ.).

Note 4: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200pF

capacitor discharged directly into each pin. National Semiconductor recommends that all integrated circuits be handled with appropriate precautions. Failure to

observe proper ESD handling techniques can result in damage.

Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be de-

rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation

of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following

equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).

Note 6: Junction-to-ambient thermal resistance (θJA) is taken from thermal measurements, performed under the conditions and guidelines set forth in the JEDEC

standard JESD51-7. A 1" x 1", 4 layer, 1.5oz. Cu board was used for the measurements. The θJA, which is performed under the 4 layer cellphone board condition,

is 86°C/W.

Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 8: The LM3280 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for

a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin

low until the input voltage exceeds 2.7V.

Note 9: Over-Voltage protection (OVP) threshold is the voltage above the nominal VOUT where the OVP comparator turns off the PFET switch while in PWM

mode.

Note 10: SVIN is compared to the programmed output voltage (VOUT). When SVIN – VOUT falls below VBYPASS− for longer than TBYP the Bypass FET turns on

and the switching FETs turn off. This is called the Bypass mode. The device comes out of Bypass mode when SVIN – VOUT exceeds VBYPASS+ for longer than

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LM3280

TBYP, and PWM mode returns. The hysteresis for the bypass detection threshold VBYPASS+ – VBYPASS− will always be positive and will be approximately 200mV

(typ.).

Note 11: Shutdown current includes leakage current of PFET and Bypass FET.

Note 12: Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from SW pin ramped up until cycle by cycle current limit is activated).

Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Closed loop current limit is the peak inductor

current measured in the application circuit by increasing output current until output voltage drops by 10%.

Note 13: The current is defined as the load current at which the BYPOUT voltage is 1V lower than PVIN.

Note 14: The startup time is the time to reach 90% of 3.4V nominal output voltage from the ENBUCK being low to high.

Note 15: The current is defined as the load current at which the LDOx voltage is 1.0V lower than the nominal output voltage.

Note 16: The ENLDOx means that the one of ENLDO1, ENLDO2, and ENLDO3 is set high (> 1.2V) and the others are set 0V.

Note 17: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100mV below the nominal voltage.

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LM3280

Typical Performance Characteristics (VIN = ENBUCK = 3.6V, ENLDOx = BYP = 0V, TA = 25°C, unless

otherwise noted)

Quiescent Current vs Supply Voltage

(VCON = 0.267V, FB = 2V, No Switching, LDO Disabled)

20181904

Quiescent Current vs Supply Voltage

(VCON = 0.267V, FB = 2V, No Switching, LDO Enabled)

20181905

Shutdown Current vs Temperature

(all EN = BYPOUT = VCON = SW = FB = 0V)

20181906

LDO Line Transient Response

(RLOAD = 270Ω, COUT = 1µF)

20181944

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LM3280

LDO Turn ON

(ENLDO = Low to High)

20181940

LDO Turn ON

(ENBUCK = ENLDO = Low to High)

20181941

LDO Turn OFF

(ENLDO = High to Low)

20181942

LDO Load Transient Response

(COUT = 1µF)

20181943

LDO Voltage vs Supply Voltage

20181936

LDO Voltage vs Temperature

20181937

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LM3280

LDO Dropout Voltage vs Output Current

20181938

LDO Voltage vs Output Current

(VIN = 3.6V)

20181939

PWM Startup

(VCON = 1.13V)

20181926

PWM Shutdown Response

(VCON = 1.08V)

20181927

Automatic Bypass Operation

(VIN = 4.2V to 3.0V)

20181928

Forced Bypass Operation

(VIN = 3.0V)

20181929

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LM3280

Line Transient Response

(VIN = 3.0V to 3.6V)

20181930

Load Transient Response

(VCON = 0.5V)

20181924

VCON Voltage Response

(VIN = 4.2V, VCON = 0.5V / 1.1V)

20181931

Timed Current Limit Response

(Normal Operation to Short Circuit)

20181932

Output Voltage Ripple

(VOUT = 1.5V)

20181933

Output Voltage Ripple in Dropout

(VIN = 3.75V, VOUT = 3.25V, IOUT = 200mA)

20181934

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LM3280

Switching Frequency Variation vs Temperature

(VOUT = 1.5V)

20181908

RDSON vs Temperature

(Bypass FET)

20181922

RDSON vs Temperature

(P-FET)

20181920

RDSON vs Temperature

(N-FET)

20181921

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LM3280

PWM Output Voltage vs Supply Voltage

(VOUT = 1.5V)

20181909

PWM Output Voltage vs Temperature

(VOUT = 1.5V)

20181910

Open/Closed Loop Current Limit vs Temperature

(PWM mode)

20181912

Dropout Voltage vs Output Current

(Bypass mode, VIN = BYP = 3.6V)

20181913

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LM3280

VCON Voltage vs PWM Output Voltage

(IOUT = 200mA)

20181914

Low VCON Voltage vs Output Voltage

(RLOAD = 15Ω)

20181915

Efficiency vs Output Voltage

(VIN = 3.9V)

20181917

Efficiency vs Output Current

(VOUT = 1.5V)

20181918

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LM3280

Efficiency vs Output Current

(VOUT = 3.25V)

20181919

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LM3280

Block Diagram

20181935

FIGURE 2. Functional Block Diagram

Device Information

The LM3280 a multi-functional Power Management Unit, op-

timized for low-power handheld applications such as Cellular

Phones. It incorporates one adjustable voltage PWM DC-DC

converter with an internal Bypass FET and three LDOs. It also

provides a separate enable pin for each output. The buck

converter output voltage can be programmed from 0.8V to

3.6V in PWM mode. The buck converter is designed for a

maximum load capability of 300mA in PWM mode and 500mA

in Bypass mode. Maximum load range may vary from this

depending on input voltage, output voltage and the inductor

chosen. The LDO operates a nominal output voltage of 2.85V

and maximum load current capability of 20mA.

The buck converter is designed to allow the RF PA (Power

Amplifier) to operate at maximum efficiency over a wide range

of power levels from a single Li-Ion battery cell. It is based on

current-mode buck architecture, with synchronous rectifica-

tion for high efficiency. It has three of pin-selectable operating

modes. Fixed-frequency PWM operation offers regulated out-

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LM3280

put at high efficiency while minimizing interference with sen-

sitive IF and data acquisition circuits. Bypass mode (Forced

or Automatic) turns on an internal FET bypass switch to power

the PA directly from the battery. This helps the RF PA main-

tain its operating power during low battery conditions by re-

ducing the dropout voltage across the buck converter.

Shutdown mode turns the device off and reduces battery con-

sumption to 0.1µA (typ.).

DC PWM mode output voltage precision is +/-2% for

3.6VOUT. Efficiency is typically around 96% for a 120mA load

with 3.2V output, 3.6V input. PWM mode quiescent current is

0.72mA typ. The output voltage is dynamically programmable

from 0.8V to 3.6V by adjusting the voltage on the control pin

(VCON) without the need for external feedback resistors.

An LDO is used to provide a regulated 2.85V reference volt-

age supply to each RF PA. Since each LDO has its own

enable pin, it can be used to enable or disable its respective

PA. The LDO can be enabled only after the buck converter is

activated. The LDO will automatically be disabled whenever

the ENBUCK or ENLDOx is disabled. Single LDO must be turned

on at the same time. Each LDO provides an active charge

circuit. The LDO output is pulled to ground potential via an

internal resistor when the ENBUCK or ENLDOx pin is low.

Additional features include current overload protection and

thermal shutdown. The buck converter also provides over

voltage protection.

The LM3280 is constructed using a chip-scale 16-pin micro

SMD package. This package offers the smallest possible

size, for space-critical applications such as cell phones,

where board area is an important design consideration. Use

of a micro SMD package requires special design considera-

tions for implementation. (See Micro SMD Package Assembly

and use in the Applications Information section.) Its fine

bump-pitch requires careful board design and precision as-

sembly equipment. Use of this package is best suited for

opaque-case applications, where its edges are not subject to

high-intensity ambient red or infrared light. Also, the system

controller should set ENBUCK low during power-up and other

low supply voltage conditions. (See Shutdown Mode in the

Device Information section.)

Buck Converter

CIRCUIT OPERATION

Referring to Figure 1 and Figure 2, the buck converter oper-

ates as follows. During the first part of each switching cycle,

the control block in the buck converter turns on the internal

PFET (P-channel MOSFET) switch. This allows current to

flow from the input through the inductor to the output filter ca-

pacitor and load. The inductor limits the current to a ramp with

a slope of around (VIN - VOUT) / L, by storing energy in a mag-

netic field. During the second part of each cycle, the controller

turns the PFET switch off, blocking current flow from the input,

and then turns the NFET (N-channel MOSFET) synchronous

rectifier on. In response, the inductor’s magnetic field collaps-

es, generating a voltage that forces current from ground

through the synchronous rectifier to the output filter capacitor

and load. As the stored energy is transferred back into the

circuit and depleted, the inductor current ramps down with a

slope around VOUT / L. The output filter capacitor stores

charge when the inductor current is going high, and releases

it when inductor current is going low, smoothing the voltage

across the load.

The output voltage is regulated by modulating the PFET

switch on time to control the average current sent to the load.

The effect is identical to sending a duty-cycle modulated rect-

angular wave formed by the switch and synchronous rectifier

at SW to a low-pass filter formed by the inductor and output

filter capacitor. The output voltage is equal to the average

voltage at the SW pin.

PWM MODE

While in PWM (Pulse Width Modulation) mode, the output

voltage is regulated by switching at a constant frequency

(2MHz typ.) and then modulating the energy per cycle to con-

trol power to the load. Energy per cycle is set by modulating

the PFET switch on-time pulse width to control the peak in-

ductor current. This is done by comparing the PFET drain

current to a slope-compensated reference current generated

by the error amplifier. At the beginning of each cycle, the clock

turns on the PFET switch, causing the inductor current to

ramp up. When the current sense signal ramps past the error

amplifier signal, the PWM comparator turns off the PFET

switch and turns on the NFET synchronous rectifier, ending

the first part of the cycle. If an increase in load pulls the output

down, the error amplifier output increases, which allows the

inductor current to ramp higher before the comparator turns

off the PFET. This increases the average current sent to the

output and adjusts for the increase in the load. The minimum

on-time of PFET in PWM mode is 50ns (typ.).

BYPASS MODE

The buck converter contains an internal PFET switch for by-

passing the PWM DC-DC converter during Bypass mode. In

Bypass mode, this PFET is turned on to power the PA directly

from the battery for maximum RF output power. Bypass mode

is more efficient than operating in PWM mode at 100% duty

cycle because the resistance of the bypass PFET is less than

the series resistance of the PWM PFET and inductor. This

translates into higher voltage available on the output in By-

pass mode, for a given battery voltage. The part can be placed

in bypass mode by sending BYP pin high. This is called

Forced Bypass Mode and it remains in bypass mode until

BYP pin goes low.

Alternatively the part can go into Bypass mode automatically.

This is called Auto-bypass mode or Automatic Bypass mode.

The bypass switch turns on when the difference between the

input voltage and programmed output voltage is less than

250mV (typ.) for more than the bypass delay time of 15µs

(typ.). The bypass switch turns off when the input voltage is

higher than the programmed output voltage by 450mV (typ.)

for longer than the bypass delay time. The bypass delay time

is provided to prevent false triggering into Automatic Bypass

mode by either spikes or dips in VIN. This method is very sys-

tem resource friendly in that the Bypass PFET is turned on

automatically when the input voltage gets close to the output

voltage, typical scenario of a discharging battery. It is also

turned off automatically when the input voltage rises, typical

scenario of a charger connected. Another scenario could be

changes made to VCON voltage causing Bypass PFET to turn

on and off automatically. It is recommended to connect BY-

POUT pin directly to the output capacitor with a separate trace

and not to the FB pin.

OPERATING MODE SELECTION CONTROL

The BYP digital input pin is used to select between PWM/

Auto-bypass and Bypass operating mode. Setting BYP pin

high (>1.2V) places the device in Forced Bypass mode. Set-

ting BYP pin low (<0.4V) or leaving it floating places the

device in PWM/Auto-bypass mode.

Bypass and PWM operation overlap during the transition be-

tween the two modes. This transition time is approximately

31µs when changing from PWM to Bypass mode, and 15µs

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LM3280

when changing from Bypass to PWM mode. This helps pre-

vent under or overshoots during the transition period between

PWM and Bypass modes.

DYNAMICALLY ADJUSTABLE OUTPUT VOLTAGE

The LM3280 buck converter features dynamically adjustable

output voltage to eliminate the need for external feedback re-

sistors. The output can be set from 0.8V to 3.6V by changing

the voltage on the analog VCON pin. This feature is useful in

PA applications where peak power is needed only when the

handset is far away from the base station or when data is

being transmitted. In other instances, the transmitting power

can be reduced. Hence the supply voltage to the PA can be

reduced, promoting longer battery life. See Setting the Output

Voltage in the Application Information section for further de-

tails.

OVER VOLTAGE PROTECTION

The buck converter has an over voltage comparator that pre-

vents the output voltage from rising too high, when the device

is left in PWM mode under light-load conditions, during output

voltage steps, or during startup. When the output voltage rises

to 330mV over its target, the OVP comparator inhibits PWM

operation to skip pulses until the output voltage returns to the

target. During the over voltage protection mode, both the

PWM PFET and the NFET synchronous rectifier are off.

When the part comes out of the over voltage protection mode,

the NFET synchronous rectifier remains off for approximately

3.5µs to avoid inductor current going negative.

INTERNAL SYNCHRONOUS RECTIFICATION

While in PWM mode, the buck converter uses an internal

NFET as a synchronous rectifier to reduce rectifier forward

voltage drop and associated power loss. Synchronous recti-

fication provides a significant improvement in efficiency

whenever the output voltage is relatively low compared to the

voltage drop across an ordinary rectifier diode.

With medium and heavy loads, the internal NFET syn-

chronous rectifier is turned on during the inductor current

down slope in the second part of each cycle. The synchronous

rectifier is turned off prior to the next cycle. There is no zero

cross detect, which means that the NFET can conduct current

in both directions and inductor current is always continuous.

The advantage of this method is that the part remains in PWM

mode at light loads or no load conditions. The NFET has a

current limit. The NFET is designed to conduct through its in-

trinsic body diode during transient intervals before it turns on,

eliminating the need for an external diode.

CURRENT LIMITING

A current limit feature allows the buck converter to protect it-

self and external components during overload conditions. In

PWM mode, a 940mA (max.) cycle-by-cycle current limit is

normally used. If an excessive load pulls the output voltage

down to below approximately 0.375V, indicating a possible

short to ground, then the device switches to a timed current

limit mode. In timed current limit mode, the internal PFET

switch is turned off after the current comparator trips, and the

beginning of the next cycle is inhibited for 3.5µs to force the

instantaneous inductor current to ramp down to a safe value.

After the 3.5µs interval, the internal PFET is turned on again.

This cycle is repeated until the load is reduced and the output

voltage exceeds approximately 0.375V. Therefore, the device

may not startup if an excessive load is connected to the output

when the device is enabled. The synchronous rectifier is off

in the timed current limit mode. Timed current limit prevents

the loss of current control seen in some products when the

output voltage is pulled low in serious overload conditions.

A current limit is also provided for the NFET. This is approxi-

mately −500mA. Both the NFET and the PFET are turned off

in negative current limit until the PFET is turned on again at

the beginning of the next cycle. The negative current limit in-

hibits buildup of excessive negative inductor current.

In the Bypass mode, the bypass current limit is 1000mA (typ.).

The output voltage drops when the bypass current limit kicks

in.

LDO

LDO OPERATION

The LDO provides a nominal output voltage of 2.85V. Each

LDO can be enabled when the respective enable pin is set

high (>1.2V) after the buck converter has been enabled. The

LDO will automatically be disabled whenever the ENBUCK or

ENLDOx is disabled. Only one LDO may be enabled on at a

time. A 2µs period of time needs to occur between disabled

one LDO and enabling another. Otherwise, all LDOs are dis-

abled.

CHARGE AND DISCHARGE

Each LDO includes an active charge circuit. 7.5us (typ.) after

the LDO is enabled, the current limit of the LDO is set to 60-

mA. A 1µF load capacitor will be charged to 90% of the

nominal output voltage in approximately 50us (typ.). (Note:

This number is based on the assumption that the PWM loop

has been enabled and given time to stabilize before the LDO

is enabled.) The current limit is then reduced to 40mA.

An internal pull-down resistor is also included in each LDO.

The LDO discharges the output capacitor through the pull-

down resistor when LDO is disabled.

Shutdown Mode

Setting the ENBUCK digital pin low (<0.4V) places the LM3280

in a 0.1µA (typ.) Shutdown mode. During shutdown, the PFET

switch, NFET synchronous rectifier, reference voltage

source, control and bias circuitry of the LM3280 are turned

off. Setting ENBUCK high (>1.2V) enables normal operation.

ENBUCK should be set low to turn off the LM3280 during pow-

er-up and under voltage conditions when the power supply is

less than the 2.7V minimum operating voltage. The LM3280

is designed for compact portable applications, such as cellu-

lar phones. In such applications, the system controller deter-

mines power supply sequencing and requirements for small

package size outweigh the benefit of including UVLO (Under

Voltage Lock-Out) circuitry.

Thermal Overload Protection

The LM3280 has a thermal overload protection function to

protect the device from short-term misuse and overload con-

ditions. When the junction temperature exceeds around 150°

C, the device inhibits operation. Both the PFET and the NFET

are turned off in PWM mode, and the Bypass PFET is turned

off in Bypass mode. The LDO is also turned off. When the

temperature drops below 125°C, normal operation resumes.

Prolonged operation in thermal overload conditions may dam-

age the device.

www.national.com 18

LM3280

Application Information

BUCK CONVERTER SETTING THE OUTPUT VOLTAGE

The buck converter features a pin-controlled variable output

voltage to eliminate the need for external feedback resistors.

It can be programmed for an output voltage from 0.8V to 3.6V

by setting the voltage on the VCON pin, as in the following for-

mula:

VOUT = 3 x VCON

When VCON is between 0.267V and 1.20V, the output voltage

will follow proportionally by 3 times of VCON.

If VCON is over 1.20V (VOUT = 3.6V), sub-harmonic oscillation

may occur because of insufficient slope compensation.

If VCON voltage is less than 0.267V (VOUT = 0.8V), the output

voltage may not be regulated due to the required on-time be-

ing less than the minimum on-time (50ns). The output voltage

can go lower than 0.8V providing a limited VIN range is used.

Refer to datasheet curve (Low VCON Voltage vs. Output Volt-

age) for details. This curve is for a typical part and there could

be part to part variation for output voltages less than 0.8V over

the limited VIN range. In addition, if the VCON is less than ap-

proximately 0.15V, the PWM mode output is turned off, but

the internal bias circuits are still active.

INDUCTOR SELECTION

A 2.2μH inductor with saturation current rating over 940mA is

recommended for almost all applications. The inductor resis-

tance should be less than 0.2Ω for better efficiency. Table 1

lists suggested inductors and suppliers.

TABLE 1. Suggested Inductors and Their Suppliers

Model Size (WxLxH) [mm] Vendor

DO3314-222MX 3.3 x 3.3 x 1.4 Coilcraft

LPS3010-222MLC 3.1 x 3.1 x 1.0 Coilcraft

LPS3008-222MLC 3.1 x 3.1 x 0.8 Coilcraft

MIPSA2520D2R2** 2.5 x 2.0 x 1.2 FDK

KSLI252010AG2R2* 2.5 x 2.0 x 1.0 Hitachi-

Metal

VLF3010AT-2R2M1R0 2.6 x 2.8 x 1.0 TDK

NR3010T2R2M 3.0 x 3.0 x 1.0 Taiyo-

Yuden

NR3012T2R2M 3.0 x 3.0 x 1.2 Taiyo-

Yuden

1117AS-2R2M

(DE2810C)

2.8 x 3.0 x 1.0 Toko

Note *:Mass production in April 2007. Contact vendor for further information.

**:Mass production in Feb. 2007. Contact vendor for futher information.

If a higher value inductor is used the LM3280 may become

unstable and exhibit large under or over shoot during line,

load and VCON transients. If smaller inductance value is used,

slope compensation maybe insufficient causing sub-harmon-

ic oscillations. The device has been tested with inductor val-

ues in the range 1.55μH to 3.1μH to account for inductor

tolerances.

For low-cost applications, an un-shielded bobbin inductor can

be used. For noise-critical applications, an un-shielded or

shielded-bobbin inductor should be used. A good practice is

to layout the board with footprints accommodating both types

for design flexibility. This allows substitution of an un-shielded

inductor, in the event that noise from low-cost bobbin models

is unacceptable. Saturation occurs when the magnetic flux

density from current through the windings of the inductor ex-

ceeds what the inductor’s core material can support with a

corresponding magnetic field. This can cause poor efficiency,

regulation errors or stress to a DC-DC converter like the

LM3280.

CAPACITOR SELECTION

The LM3280 is designed to be used with ceramic capacitors.

Use a 10µF ceramic capacitor for the power input, a 4.7µF

ceramic capacitor for the buck converter output, and a 1µF

ceramic capacitor for the LDO and the signal input. Ceramic

capacitors such as X5R, X7R and B are recommended for

both filters. These provide an optimal balance between small

size, cost, reliability and performance for cell phones and

similar applications. Table 2 lists suggested capacitors and

suppliers.

TABLE 2. Suggested Capacitors and Their Suppliers

Model Size (EIA) Vendor

C1608X5R0J475M 1608 (0603) TDK

C2012X5R0J106M 2012 (0805) TDK

GRM188B10J105KA01 1608 (0603) Murata

LMK107BJ105KA 1608 (0603) Taiyo-Yuden

C1608JB1C105K 1608 (0603) TDK

The DC bias characteristics of the capacitor must be consid-

ered when making the selection. If smaller case size such as

1608 (0603) is selected, the DC bias could reduce the cap

value by as much as 40%, in addition to the 20% tolerances

and 15% temperature coefficients. Request DC bias curves

from manufacturer when making selection. The buck con-

verter has been designed to be stable with output capacitors

as low as 3μF to account for capacitor tolerances. The LDO

has been done with output capacitors as low as 0.5µF. These

values include DC bias reduction, manufacturing tolerances

and temp coefficients.

The input filter capacitor supplies AC current drawn by the

PFET switch of the LM3280 in the first part of each cycle and

reduces the voltage ripple imposed on the input power

source. A 1µF capacitor is also recommended close to SVIN

pin. The output filter capacitor absorbs the AC inductor cur-

rent, helps maintain a steady output voltage during transient

load changes and reduces output voltage ripple. These ca-

pacitors must be selected with sufficient capacitance and

sufficiently low ESR (Equivalent Series Resistance) to per-

form these functions. The ESR of the filter capacitors is

generally a major factor in voltage ripple.

MICRO SMD PACKAGE ASSEMBLY AND USE

Use of the Micro SMD package requires specialized board

layout, precision mounting and careful re-flow techniques, as

detailed in National Semiconductor Application Note 1112.

Refer to the section Surface Mount Technology (SMD) As-

sembly Considerations. For best results in assembly, align-

ment ordinals on the PC board should be used to facilitate

placement of the device. The pad style used with Micro SMD

package must be the NSMD (non-solder mask defined) type.

This means that the solder-mask opening is larger than the

pad size. This prevents a lip that otherwise forms if the solder-

mask and pad overlap, from holding the device off the surface

of the board and interfering with mounting. See Application

Note 1112 for specific instructions how to do this. The 16-

Bump package used for the LM3280 has 300 micron solder

balls and requires 10.82 mil pads for mounting on the circuit

board. The trace to each pad should enter the pad with a 90°

entry angle to prevent debris from being caught in deep cor-

19 www.national.com

LM3280

ners. Initially, the trace to each pad should be 6-7 mil wide,

for a section approximately 6 mil long or longer, as a thermal

relief. Then each trace should neck up or down to its optimal

width. The important criterion is symmetry. This ensures the

solder bumps on the LM3280 re-flow evenly and that the de-

vice solders level to the board. In particular, special attention

must be paid to the pads for bumps B4, C4 and D4. Because

PVIN and PGND are typically connected to large copper

planes, inadequate thermal relief can result in inadequate re-

flow of these bumps.

The Micro SMD package is optimized for the smallest possi-

ble size in applications with red or infrared opaque cases.

Because the Micro SMD package lacks the plastic encapsu-

lation characteristic of larger devices, it is vulnerable to light.

Backside metallization and/or epoxy coating, along with front-

side shading by the printed circuit board, reduce this sensi-

tivity. However, the package has exposed die edges. In

particular, Micro SMD devices are sensitive to light, in the red

and infrared range, shining on the package’s exposed die

edges.

Do not use or power-up the LM3280 while subjecting it to high

intensity red or infrared light; otherwise degraded, unpre-

dictable or erratic operation may result. Examples of light

sources with high red or infrared content include the sun and

halogen lamps. Place the device in a case opaque to red or

infrared light.

BOARD LAYOUT CONSIDERATIONS

PC board layout is an important part of DC-DC converter de-

sign. Poor board layout can disrupt the performance of a DC-

DC converter and surrounding circuitry by contributing to EMI,

ground bounce, and resistive voltage loss in the traces. These

can send erroneous signals to the DC-DC converter, resulting

in poor regulation or instability. Poor layout can also result in

re-flow problems leading to poor solder joints between the

Micro SMD package and board pads. Poor solder joints can

result in erratic or degraded performance. Good layout for the

LM3280 can by implemented by following a few simple design

rules.

1. Place the LM3280 on 10.82 mil pads. As a thermal relief,

connect to each pad with a 7 mil wide, approximately 7

mil long traces, and when incrementally increase each

trace to its optimal width. The important criterion is

symmetry to ensure the solder bumps on the LM3280 re-

flow evenly (see Micro SMD Package Assembly and

Use).

2. Place the LM3280, inductor and filter capacitors close

together and make the trace short. The traces between

these components carry relatively high switching

currents and act as antennas. Following this rule reduces

radiated noise. Place the capacitors and inductor close

to the LM3280. The input capacitor should be placed right

next to the device between PVIN and PGND pin.

3. Arrange the components so that the switching current

loops curl in the same direction. During the first half of

each cycle, current flows from the input filter capacitor,

through the LM3280 and inductor to the output filter

capacitor and back through ground, forming a current

loop. In the second half of each cycle, current is pulled

up from ground, through the LM3280 by the inductor, to

the output filter capacitor and then back through ground,

forming a second current loop. Routing these loops so

the current curls in the same direction, prevents magnetic

field reversal between the two half-cycles and reduces

radiated noise.

4. Connect the ground pins of the LM3280, and filter

capacitors together using generous component side

copper fill as a pseudo-ground plane. Then connect this

to the ground-plane (if one is used) with several vias. This

reduces ground plane noise by preventing the switching

currents from circulating through the ground plane. It also

reduces ground bounce at the LM3280 by giving it a low

impedance ground connection.

5. Use wide traces between the power components and for

power connections to the DC-DC converter circuit. This

reduces voltage errors caused by resistive losses across

the traces.

6. Route noise sensitive traces, such as the voltage

feedback trace, away from noisy traces and components.

The voltage feedback trace must remain close to the

LM3280 circuit and should be routed directly from FB pin

to VOUT at the output capacitor. A good approach is to

route the feedback trace on another layer and to have a

ground plane between the top layer and the layer on

which the feedback trace is routed. This reduces EMI

radiation on to the DC-DC converter’s own voltage

feedback trace.

7. It is recommended to connect BYPOUT pin to VOUT at the

output capacitor using a separate trace, instead of

connecting it directly to the FB pin for better noise

immunity.

www.national.com 20

LM3280

Physical Dimensions inches (millimeters) unless otherwise noted

16-Bump Thin Micro SMD, Large Bump

X1 = 2.352mm ± 0.030mm

X2 = 2.352mm ± 0.030mm

X3 = 0.600mm ± 0.075mm

NS Package Number TLA16QQA

21 www.national.com

LM3280

Notes

LM3280 Adjustable Step-Down DC-DC Converter and 3 LDOs for RF Power Management

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