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DS1806

Digital Sextet Potentiometer

DS1806

062097 1/8

FEATURES

•Six digitally controlled 64–position potentiometers

•3–Wire Serial Port provides for reading and setting

each potentiometer

•Devices can be cascaded for single processor multi–

device control

•Standard Resistance Values

– DS1806–010 – 10K ohm

– DS1806–050 – 50K ohm

– DS1806–100 – 100K ohm

•Temperature:

– Industrial: –40°C to +85° C

PIN ASSIGNMENT

VCC

DIN

COUT

L1-3

L4-6

RST

CLK

GND

DS1806 20–PIN DIP (300 MIL)

DS1806S 20–PIN SOIC (300 MIL)

DS1806E 20–PIN TSSOP (173 MIL)

See Mech. Drawings

Section

PIN DESCRIPTION

VCC – 3V or 5V Supply

RST – Serial Port Reset Input

DIN – Serial Port Data Input

CLK – Serial Port Clock Input

COUT – Cascade Data Output

H1 – H6 – High End Terminal of Pot

W1 – W6 – Wiper Terminal of Pot

GND – Ground

L1–3 – Low Terminal Pots 1 thru 3

L4–6 – Low Terminal Pots 4 thru 6

DESCRIPTION

The DS1806 is a six–channel digitally controlled solid–

state linear potentiometer. Each potentiometer is com-

prised of 63 equiresistive sections as illustrated in the

block diagram of Figure 1. Each potentiometer has

three terminals accessible to the user. These include

the high side terminals, HX, the wiper terminals, WX, and

the low–end terminals, L1–3 and L4–6. Potentiometers

1 through 3 share the same low–end terminal L1–3. And

likewise, potentiometers 4 through 6 share the low–end

terminal L4–6.

Each wiper ’s position is selected via an 8–bit register

value. Communication and control of the device is ac-

complished via a 3–wire serial port interface. This inter-

face in conjunction with a cascade output allows the val-

ue of the device wiper settings to be read.

For multiple device and single processor environments,

the DS1806 can be cascaded or daisy chained. This

feature allows a single processor to control multiple de-

vices.

The DS1806 is available in 10K, 50K and 100K ohm ver-

sions and is specified over the industrial temperature

range. Packages for the device include 20–lead DIPs,

SOICs, and TSSOPs.

DS1806

062097 2/8

OPERATION

A block diagram of the device is provided in Figure 1. As

shown, the DS1806 contains six 64–position potentiom-

eters whose wiper positions are set by an 8–bit value.

The DS1806 contains a 48–bit I/O shift register which is

used to store the respective wiper position data for each

of the six potentiometers.

Each potentiometer has three terminals accessible to

the user . These include the high side terminals, HX, the

wiper terminals, WX, and the low–end terminals, L1–3

and L4–6. Potentiometers 1 through 3 share the same

low–end terminal L1–3. And likewise, potentiometers 4

through 6 share the low–end terminal L4–6.

Control of the DS1806 is accomplished via a 3–wire se-

rial communication interface which allows the user to

set the wiper position value for each potentiometer. The

3–wire serial interface consists of the control signals

RST, DIN, and CLK. On power–up, the wiper positions of

each potentiometer are set to the low–end terminal LX

(00000000).

The RST control signal is used to enable 3–wire serial

port operation. The RST signal (3–wire serial port) is ac-

tive when in a high state. Any communication intended

to change wiper settings must begin with the transition

of the RST from the low–state to the high–state.

The CLK signal input is used to provide timing synchro-

nization for data input and output. Wiper position data is

loaded into the DS1806 through the DIN input terminal.

This data is shifted one bit at a time into the 48–bit I/O

shift register of the part, LSB first. Figure 3 provides an

illustration of the 48–bit shift register.

Figure 4 provides 3–wire serial port protocol and timing

diagrams. As shown, the 3–wire port is inactive when

the RST signal input is low . Once RST has transitioned

from the low to the high state, the serial port becomes

active. When active, data is loaded into the I/O shift reg-

ister on the low–to–high transition of the CLK.

Data is transmitted in order of LSB first. Potentiometers

are designated from 1 through 6 and the value for poten-

tiometer–1 will be the first data entered into the shift reg-

ister, followed by that of potentiometer–2 and so forth.

Each wiper has an 8–bit register which is used for set-

ting the position of the wiper on the resistor array. Be-

cause the DS1806 is a 64–position potentiometer, only

six bits of information are needed to set wiper position.

The remaining two bits of information are used to pro-

vide a “don’t change” feature. Wiper position is con-

trolled by bit positions 0 through 5 of each register . The

“don’t change” feature is controlled by bits 6 and 7 of

each register. When bits 6 and 7 have value “11 xxxxxx”,

wiper position will not change regardless of the states of

bits 0 through 5. If bits 6 and 7 are set to any other value,

bits 0 through 5 will be used as the new wiper position.

The “don’t change” feature allows the user to change

the value of any potentiometer of the DS1806 without af-

fecting or having to remember the remaining positions

of the potentiometer wipers. Figure 2 provides the for-

mat for a wiper’s register.

Wiper placement for each potentiometer is such that

position–63 corresponds to the HX terminal of the de-

vice while position–0 corresponds to the ground termi-

nal. For example, to set a potentiometer’s wiper position

to 15 (decimal), the binary value shifted into the wiper

tap at the 15th step above the low end terminal, LX.

All communication transactions should provide the total

48 bits of information when writing or reading from the

part. This is especially true for applications using all six

potentiometers. If a complete set of 48 bits is not trans-

mitted to the part, undesired wiper position settings may

occur.

DS1806

062097 3/8

DS1806 BLOCK DIAGRAM Figure 1

64–TO–1 MULTIPLEXER

L46

POTENTIOMETER–6 W6 H5

64–TO–1 MULTIPLEXER

POTENTIOMETER–5 W5 H1

64–TO–1 MULTIPLEXER

POTENTIOMETER–1 W1

L13

. . . . . . . . . . . .

WIPER–6 (8 BITS) WIPER–5 (8–BITS) WIPER–1 (8–BITS)

48–BIT SHIFT REGISTER

DIN

RST

CLK

COUT

3–WIRE SERIAL

INTERFACE

CONTROL LOGIC

WIPER REGISTER CONFIGURATION Figure 2

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

MSB LSB

LOAD/NO LOAD WIPER POSITION VALUE

Bits 6 and 7 Functionality

11 – Do not load wiper value

10 – Load wiper value

01 – Load wiper value

00 – Load wiper value

48–BIT I/O SHIFT REGISTER Figure 3

B0 POT 1 B7 B0 POT 2 B7 B0 POT 3 B7 B0 POT 4 B7 B0 POT 5 B7 B0 POT 6 B7

MSBLSB MSBLSB MSBLSB MSBLSB MSBLSB MSBLSB

Data entered LSB first, starting with potentiometer–1.

DS1806

062097 4/8

3–WIRE SERIAL PORT TIMING Figure 4

•••

RST

CLK

DIN

COUT

LSB

POT 1

tCC tCH

tRLT

tHLT

tCDH

tDC

CASCADE OPERATION

A feature of the DS1806 is the ability to control multiple

devices from a single processor . Multiple DS1806s can

be linked or daisy chained as shown in Figure 5. As a

data bit is entered into the I/O shift register of the

DS1806, a bit will appear at the COUT terminal before a

maximum delay of 50 nanoseconds. The LSB of poten-

tiometer–1 will always be the first out of the part at the

beginning of a transaction. Additionally , the COUT termi-

nal is always active regardless of the state RST . Howev-

er, DIN and CLK inputs are ignored when RST is in the

low state.

The COUT output of the DS1806 can be used to drive the

DIN input of another DS1806. When cascading multiple

devices, the total number of bits transmitted is always

48 multiplied by the total number of DS1806s being cas-

caded.

An optional feedback resistor can be placed between

the COUT terminal of the last device and the first DS1806

DIN input, which allows the controlling processor to

read, as well as, write data, or circularly clock data

through the daisy chain. The value of the feedback or

isolation resistor should be in the range from 1KΩ to

10KΩ.

To read data, the reading device configures itself as an

input and monitors the state of the DIN line, which is driv-

en by COUT through the isolation resistor . When RST is

driven high, bit 48 is present on the COUT pin, which is

fed back to the input DIN pin through the isolation resis-

tor . When the CLK input transitions low to high, bit 48 is

loaded into the first position of the I/O shift register and

bit 47 becomes present on COUT and DIN of the next de-

vice. After 48 bits (or 48 times the number of the

DS1806s in the daisy chain), the data has shifted com-

pletely around and back to its original position. When

RST transitions to the low state to end data transfer , the

value (the same as before the read occurred) is loaded

in the shift register.

ABSOLUTE AND RELATIVE LINEARITY

Absolute linearity is defined as the difference between

the actual measured output voltage and the expected

output voltage. Absolute linearity is given in terms of a

minimum increment or expected output when the wiper

is moved one position. The DS1806 is specified to have

an absolute linearity of ±0.50 LSB.

Relative linearity is a measure of error between two ad-

jacent wiper position points. The DS1806 is specified to

have a relative linearity of ±0.25 LSB.

TYPICAL APPLICATION CONFIGURATIONS

Figure 6 shows the typical application configuration of

the DS1806 as a fixed gain attenuator . In this configura-

tion, the DS1806 adjusts the attenuation level of the in-

coming signal. Variations in wiper resistance are mini-

mized by connecting the wiper terminal of the part to a

high impedance load. Depending on voltage across the

wiper, its resistance may vary from 400 ohms to

1000 ohms. Note that the resistance R1 in Figure 6

should be chosen to be much greater than the wiper re-

sistance RW.

DS1806

062097 5/8

CASCADING MULTIPLE DEVICES Figure 5

DS1806

COUT

DIN DIN DIN

ISOLATION RESISTOR

FOR READING REGISTER DATA

1KΩ–10KΩ

FIXED GAIN ATTENUATOR Figure 6

–

DS1806

062097 6/8

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground –0.5V to +7.0V

Operating Temperature –40°C to +85°C; industrial

Storage Temperature –55°C to +125°C

Soldering Temperature 260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (-40°C to +85°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Supply Voltage VCC +2.7 5.5 V 1

DC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCC = 2.7 to 5.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Supply Current Active ICC 1.3 2 mA

Input Leakage IIL –1 +1 µA

Wiper Resistance RW400 1000 Ω

Wiper Current IW1 mA

Input Logic 1 VIH 2.0 VCC+0.5 V 1

Input Logic 0 VIL –0.5 +0.8

+0.6 V1, 6

Logic 1 Output @ 2.4 Volts IOH –1 mA

Logic 0 Output @ 0.4 Volt IOL 4mA 6

Standby Current: 3 Volts

5 Volts ISTBY 12

20 40 µA

µA9

Resistor Inputs HX, LX,

WXGND –0.5 VCC +0.5 µA 2

ANALOG RESISTOR CHARACTERISTICS (–40°C to +85°C; VCC = 2.7 to 5.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

End–to–End Resistor Tolerance –20 +20 %

Absolute Linearity –0.5 +0.5 LSB 7

Relative Linearity –0.25 +0.25 LSB 8

–3 dB Cutoff Frequency Icutoff Hz 4

Temperature Coefficient 650 PPM/°C

DS1806

062097 7/8

CAPACITANCE (tA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance CIN 5pF 3

Output Capacitance COUT 7 pF 3

AC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCC = 2.7 to 5.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Clock Frequency fCLK DC 10 MHZ 5

Width of CLK Pulse tCH 50 ns 5

Data Setup T ime tDC 30 ns 5

Data Hold T ime tCDH 0ns 5

Propagation Delay T ime Low to

High Level Clock to Output tPLH 50 ns 5

RST High to Clock Input High tCC 50 ns 5

RST Low from lock Input High tHLT 50 ns 5

RST Inactive tRLT 125 ns 5

CLK Rise T ime, CLK Fall Time tCR 50 ns 5

NOTES:

1. All voltages are referenced to ground.

2. Resistor inputs cannot go below GND by more than 0.5 volts or above VCC by 0.5 volts in the positive direction.

3. Capacitance values apply at 25°C.

4. –3 dB cutoff frequency characteristics for the DS1806 depend on potentiometer total resistance: DS1806–010;

1 MHz; DS1806–050; 200 KHz, DS1806–100; 100 KHz.

5. See Figure 4.

6. For VCC = 5V ±10% maximum VIL = +0.8V. For VCC = 3.0 ± 10% VIL = +0.6V.

7. Absolute Linearity is to used measure expected wiper voltage versus measured wiper voltage as determined by

wiper position. The DS1806 is specified to provide an Absolute Linearity of +0.5 LSB.

8. Relative Linearity is used to determine the change in wiper voltage between two adjacent wiper positions. The

DS1806 is specified to provide a relative linearity of +0.25 LSB.

9. Standby current levels apply when all inputs are driven to appropriate supply levels.

DS1806

062097 8/8

DS1806 ORDERING INFORMATION

ORDERING NUMBER PACKAGE OPERATING

TEMPERATURE VERSION

DS1806–010 20L DIP –40°C TO +85°C 10KΩ

DS1806–050 20L DIP –40°C TO +85°C 50KΩ

DS1806–100 20L DIP –40°C TO +85°C 100KΩ

DS1806E–010 20L TSSOP (173 MIL) –40°C TO +85°C 10KΩ

DS1806E–050 20L TSSOP (173 MIL) –40°C TO +85°C 50KΩ

DS1806E–100 20L TSSOP (173 MIL) –40°C TO +85°C 100KΩ

DS1806S–010 20L SOIC (300 MIL) –40°C TO +85°C 10KΩ

DS1806S–050 20L SOIC (300 MIL) –40°C TO +85°C 50KΩ

DS1806S–100 20L SOIC (300 MIL) –40°C TO +85°C 100KΩ