HYB18RL28818AC HYB18RL28836AC Graphics & Speciality DRAMs 288 Mbit DDR Reduced Latency DRAM Version 1.60 July 2003 HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM Edition July 2003 This edition was realized using the software system FrameMaker. Published by Infineon Technologies, Marketing-Kommunikation, Balanstrae 73, 81541 Munchen (c) Infineon Technologies 4/01/03. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of Infineon Technologies, may only be used in life-support devices or systems2 with the express written approval of Infineon Technologies. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. HYB18RL28818/36AC Revision History: Current Version 1.60 Subjects (major changes since last revision) Previous Version: 1.51 frontpage frontpage fixed part number HYB18RL28809AC -> HYB18RL28890AC all all removed confidential 48 48 x36 configuration table, swapped pins F12 and E12 11 11 Ball Description table - ZQ - added `...connected to GND, then minimum DQ output impedance is set.' 46,47,48 46,47,48 Re-numbered scan registers order, starting with 0 to 112 52 52 Removed the word "Isolated" from the Vddq power supply description in table 18 52 52 Added note 7 for Vtt. A power supply should be used for Vtt generation, not a voltage divider. 19 19 Changed the value of tMRSC from 6 to 12 clocks 49 49 Figure 40, Tap Block Diagram. Added numbering to scan chain order. 16 16 Added tCKvar, added notes 4 and 5. (jitter parameter) 11 11 Add to ZQ, QVLD, DQ, QK that the output impedance of QVLD, DQ, and QKx is controlled via ZQ 20,21,25 20,21,25 Comment that states each RD/WR is a row access, wait tRC before next RD/WR to same bank. 32 32 added: (8k refresh per bank, 64k total refresh cycles each 32ms) 19 19 Idle means all commands complete, no more burst or refresh occuring 54 54 Added power estimates. 5,52 5,52 Remove 1.5v VDDQ option all all Removed x9 option Version 1.60 Page 2 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 1.2.1 1.3 1.4 1.4.1 2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.1.1 2.5.1.2 2.5.1.3 2.5.1.4 2.6 2.6.1 2.6.1.1 2.6.1.2 2.6.2 2.7 2.7.1 2.7.2 2.8 3 15 16 17 18 19 19 21 21 22 22 23 23 25 25 26 27 27 28 30 Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Set command in multiplexed address mode . . . . . . . . . . . . Ball Configuration of RLDRAM in multiplexed address mode . . . . . . . . . . . Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 33 34 37 37 39 IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . . . . . . 40 4.0.1 4.0.2 4.0.3 4.0.4 4.0.5 4.0.6 4.0.7 4.0.8 4.1 4.2 4.2.1 4.2.2 4.3 4.4 5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Impedance Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Set Command (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writes (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reads (RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On Die Termination Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Refresh Command (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation with multiplexed addresses . . . . . . . . . . . . . . . . . . . . . . 31 3.1 3.2 3.3 3.4 3.4.1 3.4.2 4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package and Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Data-In (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Data-Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Exit Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x18 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x36 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TAP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 40 40 40 41 41 42 43 43 44 45 47 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.1 Version 1.60 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Page 3 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 1 Overview 1.1 Features z z z z z z z z z z z z z z z z z z z z z z z 288 Megabit (288M) 400MHz DDR operation (800Mb/pin/sec) Organization 8Mx36, 16Mx18 and 32Mx9 in 8 banks Cyclic bank switching for maximum bandwidth Reduced row cycle time (20ns at 200/300/400MHz) Non multiplexed addresses, address multiplexing optionally available for Burst Length of 4 and 8. SRAM type interface Read latency, row cycle time and burst sequence length programmable Balanced Read and Write latencies to optimise data bus utilisation Data mask for write commands Differential input clocks (CK, CK#) 2 pairs of differential write clocks in x36 , 1pair in x18/x9 (DKx, DKx#) 2 pairs of differential read clocks (QKx, QKx#) On chip DLL to generate CK edge aligned data and data strobe signals. Data valid signal 32ms Refresh (8k refresh per bank, 64k total refresh cycles each 32ms) 144 pin P-TFBGA package 1.8V, 25 Ohm - 60 Ohm Matched Impedance IO IEEE 1149.1 compliant JTAG boundary scan interface 1.8V VDDQ IO voltage 1.8V VDD, 2.5V VEXT core voltages On-die termination RTT 0.11m technology Table 1 Key timing parameters (Configuration Example x36, x18 device) Speed Sort -2.5 -3.3 -5.0 Units Frequency 400 300 200 MHz 20 20 20 ns 8 6 4 cycles 8 6 4 cyles tRC Read latency Version 1.60 Page 4 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 1.2 General Description The Infineon 288 Mbit DDR Reduced Latency DRAM is a high speed memory device, designed for high bandwidth communication data storages like transmit or receive buffers in telecommunication systems as well as data or instruction cache applications requiring large amounts of memory. The chip's 8 bank architecture is optimized for high speed and achieves a peak bandwidth of 3.2 GBytes/s using a 36 bit interface and a maximum system clock of 400 MHz. The double data rate (DDR) interface transfers 36, or 18 wide data words per clock edge at the I/O pins. An on chip DLL aligns the output data with the incoming clock (CK). Commands, addresses and control signals are registered at every positive edge of the differential input clock, while input data are registered at both, positive and negative edge, of one (x18) or two (x36) separate differential write clocks. Read and write accesses to the RLDRAM are burst oriented. The burst length is programmable to 2, 4 and 8 (BL=8 is available on x18 device only) by setting the mode register. The device is supplied with 2.5V and 1.8V for the core and 1.8V for the output drivers. Bank scheduled refresh is supported whereby the row address will be generated internally. A standard P-TFBGA 144-ball package is used which enables ultra high speed data transfer rates and a simple upgrade path from former products. The chip is fabricated in Infineon advanced 0.11m process technology. Version 1.60 Page 5 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 1.3 Package and Ball Assignment Figure 1 P-TFBGA 144 package SIDE VIEW BOTTOM VIEW 1.20 max 12 11 10 9 8 7 6 5 4 3 2 1 A 1 D E O 0.51 typ B C F G J 17 18.5 H K L M N P R T U V 4 0.8 8.8 11 Note: 1. All dimensions in millimeters. Version 1.60 Page 6 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM Figure 2 8M x 36 Ball assignment (Top view) 144 P-TFBGA package 1 2 3 4 A VREF VSS VEXT B VDD DQ8 C VTT D (A22) 9 10 11 12 VSS VSS VEXT TMS TCK DQ9 VSSQ VSSQ DQ1 DQ0 VDD DQ10 DQ11 VDDQ VDDQ DQ3 DQ2 VTT DQ12 DQ13 VSSQ VSSQ QK0# QK0 VSS E (A21) DQ14 DQ15 VDDQ VDDQ DQ5 DQ4 (A20) F A5 DQ16 DQ17 VSSQ VSSQ DQ7 DQ6 QVLD G A8 A6 A7 VDD VDD A2 A1 A0 H B2 A9 VSS VSS VSS VSS A4 A3 J DK0 DK0# VDD VDD VDD VDD B0 CK K DK1 DK1# VDD VDD VDD VDD B1 CK# L REF# CS# VSS VSS VSS VSS A14 A13 M WE# A16 A17 VDD VDD A12 A11 A10 N A18 DQ24 DQ25 VSSQ VSSQ DQ35 DQ34 (A19) P A15 DQ22 DQ23 VDDQ VDDQ DQ33 DQ32 DM R VSS QK1 QK1# VSSQ VSSQ DQ31 DQ30 VSS T VTT DQ20 DQ21 VDDQ VDDQ DQ29 DQ28 VTT U VDD DQ18 DQ19 VSSQ VSSQ DQ27 DQ26 VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI 1 1 5 6 7 8 2 2 Note: 1. Reserved for future use. May optionaly be connected to GND for improved heat dissipation. Note: 2. Reserved for future use. This signal has parasitic characteristics of an address input. May optionaly be connected to GND for improved heat dissipation. Version 1.60 Page 7 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM Figure 3 16M x 18 Ball assignment (Top view) 144 P-TFBGA package 1 2 3 4 A VREF VSS VEXT B VDD DNU 9 10 11 12 VSS VSS VEXT TMS TCK DQ4 VSSQ VSSQ DQ0 DNU C VTT DNU DQ5 VDDQ VDDQ DQ1 DNU VTT D (A22) DNU DQ6 VSSQ VSSQ QK0# QK0 VSS E (A21) 1 DNU DQ7 VDDQ VDDQ DQ2 DNU F A5 DNU DQ8 VSSQ VSSQ DQ3 DNU QVLD G A8 A6 A7 VDD VDD A2 A1 A0 H B2 A9 VSS VSS VSS VSS A4 A3 J NC NC VDD VDD VDD VDD B0 CK K DK DK# VDD VDD VDD VDD B1 CK# L REF# CS# VSS VSS VSS VSS A14 A13 M WE# A16 A17 VDD VDD A12 A11 A10 N A18 DNU DQ14 VSSQ VSSQ DQ9 DNU P A15 DNU DQ15 VDDQ VDDQ DQ10 DNU R VSS QK1 QK1# VSSQ VSSQ DQ11 DNU T VTT DNU DQ16 VDDQ VDDQ DQ12 DNU U VDD DNU DQ17 VSSQ VSSQ DQ13 DNU VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI 4 4 1 3 4 4 4 3 4 4 4 4 5 6 7 8 4 4 4 4 4 4 4 4 4 VDD 2 (A20) A19 DM VSS VTT Note: 1. Reserved for future use. May optionaly be connected to GND for improved heat dissipation. Note: 2. Reserved for future use. This signal has parasitic characteristics of an address input. May optionaly be connected to GND for improved heat dissipation. Note: 3. Do not connect. This signal has parasitic characteristics of a clock input Note: 4. Do not use. This signal has parasitics characteristics of an IO. May optionaly be connected to GND for improved heat dissipation. Version 1.60 Page 8 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 1.3.1 Ball Description Table 2 Ball description Ball Type Detailed Function CK, CK# Input Input Clock: CK and CK# are differential clock inputs. Addresses and commands are latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK. CS# Input Chip Select: CS# enables the command decoder when low and disables it when high. When the command decoder is disabled new commands are ignored, but internal operations continue. WE#, REF# Input Command Inputs: Sampled at the positive edge of CK, WE# and REF# define (together with CS#) the command to be executed. A[0:20] Input Address Inputs: A<0:20> define the row and column addresses for READ and WRITE operations. During an MODE REGISTER SET the address inputs define the register settings. They are sampled at the rising edge of CK. In the x36 configuration A[20:19] are reserved for address expansion. In the x18 configuration A[20] is reserved for address expansion. These expansion addresses can be treated as address inputs but do not affect the operation of the device. A[21:22] - BA[0:2] Input DQ0-DQ35 I/O Reserved. Do not use. Bank Address Inputs: Select to which internal bank a command is being applied. Data Input/Output: The DQ signals form the 36 bit data bus. During READ commands the data is referenced to both edges of QKx. During WRITE commands the data is sampled at both edges of DKx. DQ output impedance is controlled by ZQ. QKx,QKx# Output Data Clock: QKx and QKx# are the differential output data clocks. During READs Output they are transmitted by the RLDRAM and edge-aligned with data. QKx# is ideally 180 out of phase with QKx. QKx output impedance is controlled by ZQ. DKx,DKx# Input Input Data Clock: DKx and DKx# are the differential input data clocks. All input data is referenced to both edges of DKx and is center aligned with these edges. DKx# is ideally 180 out of phase with DKx. For the x36 device, DQ0-DQ17 are referenced to DK0 and DK0# and DQ18-DQ35 are referenced to DK1 and DK1#. For the x18 devices, all the DQs are referenced to DK and DK#. DM Input Input Data Mask: The DM signal is the input mask signal for WRITE data. Input data is masked when DM is sampled HIGH along with the WRITE input data. DM is sampled on both edges of DK. For the x36 device, DM is referenced to DK1 and DK1#. For the x18 devices, DM is referenced to DK and DK#. QVLD Output Data Valid: The QVLD indicates valid output data. QVLD is edge-aligned with QK0, QK0#. QVLD output impedance is controlled by ZQ. TCK Input IEEE 1149.1 Clock Input: JEDEC-standard 1.x V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the circuit. TMS TDI Input IEEE 1149.1 Test Input: JEDEC-standard 1.x V I/O levels. These pins may be left Not Connected if the JTAG function is not used in the circuit. TDO ZQ Version 1.60 Output IEEE 1149.1 Test Output: JEDEC-standard 1.x V I/O levels. I/O External Impedance: This signal is used to tune the device outputs (DQ, QVLD, QK, QK#) to the system data bus impedance. Output impedance is set to 0.2 x RQ, where RQ is a resistor from the signal to ground. Refer to the Mode Register Bitmap to activate this function. If the MRS mode is set to "Internal resistor", then the ZQ pin may be connected to GND, then minimum output impedance is set. If the MRS mode is set to "External resistor" and no resistor is connected, then the maximum output impedance will be set. Page 9 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM Table 2 Ball description Ball Type Detailed Function VREF Input Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. VEXT Supply Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions for range. (section 5 on page 48) VDD Supply Power Supply: 1.8V nominal.See DC Electrical Characteristics and Operating Conditions for range. (section 5 on page 48 ) VDDQ Supply Power Supply: Isolated Ouput Buffer Supply. Nominally 1.8V. See DC Electrical Characteristics and Operating Conditions for range. VSS VSSQ Supply Power Supply: GND Supply Power Supply: Isolated Output Buffer Supply. GND Power Supply: Isolated Termination Supply. Nominally VDDQ/2. See DC Electrical Characteristics and Operating Conditions for range. VTT Supply NC - No Connect. DNU - Do Not Use. May optionaly be connected to GND for improved heat dissipation. Version 1.60 Page 10 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 1.4 Functional Block Diagram Figure 4 Functional Block Diagram A0-A20, B0, B1, B2 Column Address Buffer Refresh Counter Memory Array Column Decoder Memory Array Bank 1 Bank 2 Sense Amp and Data Bus Memory Array Bank 0 Column Decoder Memory Array Sense Amp and Data Bus Row Decoder Column Decoder Row Decoder Sense Amp and Data Bus Row Decoder Bank 3 Memory Array Memory Array Memory Array Page 11 VREF DM REF# CS# WE# DQ0-DQ35 Bank 7 Control Logic and Timing Generators DK [1:0] QK[1:0], QK#[1:0] Output Buffers DK# [1:0] QVLD Input Buffers Bank 6 CK Output Data Clock Bank 5 CK# Bank 4 Column Decoder Memory Array Sense Amp and Data Bus Row Decoder Column Decoder Row Decoder Sense Amp and Data Bus Row Decoder Column Decoder Row Decoder Output Data Valid Version 1.60 Row Address Buffer Row Decoder Sense Amp and Data Bus Column Decoder Column Decoder Sense Amp and Data Bus Sense Amp and Data Bus Column Address Counter Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 1.5 Commands 1.5.1 Command Table According to the functional signal description, the following command sequences are possible. All input states or sequences not shown are illegal or reserved. All command and address inputs must meet setup and hold times around the rising edge of CK. Table 3 Command Overview Operation Code CS# Device Deselect / No Operation DESEL / NOP H Mode Register Set MRS L Read READ L Write WRITE L Auto Refresh AREF L WE# REF# A<20:0> BA<2:0> Note X X X X 4 L L H H OPCODE X 2 A BA 3 L H A BA 3 H L X BA Note: 1: X represents "Don't Care", H represents a logic HIGH, L represents a logic LOW, A represents a Valid Address, BA represents a Valid Bank Address Note: 2: Only A[17:0] are used for the MRS command. Note: 3: See table Table 4 Note: 4: When the chip is deselected, no commands are accepted from outside, but internally NOP commands are generated. Table 4 Address Widths at Different Burst Lengths Data Width Burst Length 36 18 BL 2 18:0 19:0 BL 4 17:0 18:0 BL 8 N.A 17:0 Version 1.60 Page 12 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 1.5.2 Description of Commands Table 5 Description of Commands Command Description DESEL / NOP The NOP command is used to perform a no operation to the RLDRAM, this is equal to deselecting the chip. Use NOP command to prevent unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Output values depend on command history. MRS The Mode Register is set via the address inputs A[17:0]. See the mode register description in the register description section. The MRS command can only be issued when all banks are idle and no bursts are in progress. READ The READ command is used to initiate a burst read access to a bank. The value on the BA[2:0] inputs selects the bank, and the address provided on inputs A[20:0] selects the data location within the bank. WRITE The WRITE command is used to initiate a burst write access to a bank. The value on the BA[2:0] inputs selects the bank, and the address provided on inputs A[20:0] selects the data location within the bank. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If the DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored ie. this part of the data word will not be written. AREF The AREF is used during normal operation of the RLDRAM to refresh the memory content of a bank. The command is non persistent, so it must be issued each time a refresh is required. The value on the BA[2:0] inputs selects the bank. The refresh address is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AREF command. The RLDRAM requires 64k cycles at an average periodic interval of 0.49s1 (maximum). To improve efficiency a burst of eight AREF commands (One AREF for each bank) can be posted to the RLDRAM at an average periodic interval of 3.9s2. Note: 1: Actual refresh is 32ms/8K/8 = 0.488 s. Note: 2: Actual refresh is 32ms/8K = 3.90 s. Version 1.60 Page 13 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2 Functional Description 2.1 Clocks, Commands and Addresses Figure 5 Clock/Write clock Command/Address Timings tCKH tCK tCKL CK# CK CMD, ADDR Valid Valid tCKDK Valid tCKDK tAS,tCS DKx# tAH,tCH DKx tCK tDKL tDKH Don't Care Table 6 General Timing Parameters for -2.5, -3.3 and -5.0 ns speed sorts -2.5 Parameter Symbol min -3.3 -5.0 max min max min max Units Notes Clock Clock Cycle Time tCK 2.5 5.7 3.3 5.7 5.0 5.7 ns tCKvar -0.05 0.05 -0.05 0.05 -0.05 0.05 tCK System frequency fCK 175 400 175 300 175 200 MHz Clock HIGH time tCKH, tDKH 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock LOW time tCKL, tDKL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCKDK -0.3 0.3 -0.3 0.3 -0.3 0.3 ns tAS, tCS 0.4 tAH, tCH 0.4 Clock Jitter Clock to Write Clock 4,5 Setup Times Address and Command input setup time 0.5 0.8 ns Hold Times Address and Command input hold time - 0.5 - 0.8 - ns Note: 1. All timings are measured relatively to the crossing point of CK/CK#, and to the crossing point with VREF of the Command and Address signals. Note: 2. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; The input reference level for signals other than CK/CK# is VREF. Note: 3. The signal input slew rate must be 2V/ns. Note: 4. The clock phase jitter of +/- tCKvar is the maximum variance the clock cycle can have from the expected or ideal clock. Note: 5. Cycle to Cycle maximum jitter is +/-tCKvar, the change in cycle time from one clock cycle to the next can not differ greater than tCKvar from the previous cycle. Version 1.60 Page 14 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.2 Initialization The RLDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation or permanent damage to the device. The following sequence is used for Power-Up: 1. Apply power (VEXT, VDD, VDDQ, VTT, VREF) and start clock as soon as the supply voltages are stable. Apply VDD and VEXT before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF and VTT. There is no timing relation between VEXT and VDD, the chip starts the power up sequence only when both voltages are at their nominal level. However, the pad supply must not be applied before the core supplies. Maintain all pins in NOP conditions. 2. Maintain stable conditions for 200 s (minimum). 3. Issue three Mode Register Set commands - 2 dummies plus 1 valid MRS. (Figure 6) 4. After tMRSC issue 8 Auto Refresh commands, one on each bank and separated by 2048 cycles.Initial bank refresh order does not matter. 5. After tRC the chip is ready for normal operation. Figure 6 Power Up Sequence VEXT VDD VDDQ VTT VREF CK# CK Com MRS MRS MRS Add min. 200 s min. 1 cycle min. 1 cycle tMRSC RF RF RF BA0 BA1 BA7 tRC min. 2048 6 x 2048 cycles cycles MRS: RF: A.C.: A.C. MRS command REFRESH Any command Don't Care Version 1.60 Page 15 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.3 Programmable Impedance Output Buffer The RLDRAM is equipped with programmable impedance output buffers. This allows a user to match the driver impedance to the system data bus impedance. To adjust the impedance, an external precision resitance (RQ) is connected between the ZQ pin and VSS. The value of the resistor must be five times the desired impedance. For example, a 250 resitor is required for an output impedance of 50. To ensure that the output impedance is one fifth of the value of RQ (within 15 percent), the range of RQ is 125 to 300. Output impedance updates may be required because, over time, variations may occur in supply voltage and temperature. The device samples the value of RQ. The impedance update is transparent to the system. Impedance updates do not affect the device operation, and all data sheet timing and current specifications are met during an update. Table 7 Driver Strength of Output Buffers Ball Description DQ0 .. DQ35, QK, QK#, QVLD Driver Strength Adjustable ( MRS / External RES) TDO Version 1.60 CMOS Page 16 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.4 Mode Register Set Command (MRS) The mode register stores the data for controlling the operating modes of the memory. It programs the RLDRAM configuration, burst length, test mode and IO options. During a Mode Register Set command the address inputs A<17:0> are sampled and stored in the mode register. tMRSC must be met before any command can be issued to the RLDRAM. The Mode Register content can only be set or changed when the RLDRAM is in idle state, all commands must be completed, no persistent commands. Figure 8 Figure 7 Mode Register Set CK# CK CS# Mode Register Set Timing WE# CK# CK REF# Command MRS NOP NOP A.C. COD A<17:0> tMRSC MRS: command MRS A.C.: Any command A<20:18> Don't Care BA<2:0> COD: Code to be loaded into the register Don't Care Table 8 Timing Parameters MRS for -2.5, -3.3 and -5.0 ns speed sorts -2.5 Parameter Symbol Mode Register Set timing Figure 9 -3.3 min max min max min max 12 tMRSC - A10 A9 A8 A7 A6 A5 Reserved1 Test Mode On-die Termination Calibration DLL Reset Unused Address Mux Test Mode 0 default 1 test mode 1 12 - 12 - Units Notes tCK Mode Register Bitmap A<17:11> A10 -5.0 A4 A3 A2 Burst Length A0 RLDRAM configuration 0 0 1 (default) 0 1 1 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved Termination A7 DLL Reset A4 A3 BL 0 Disabled (default) 0 Reset (default) 0 0 2 (default) 0 1 Enabled 1 Enable 0 1 4 0 1 0 8 0 1 1 not valid Resistor A5 Addresss Mux 0 internal (50 ) (default) 0 non-multiplexed (default) 1 external 1 address multiplexed A0 Configuration A9 A8 A1 A2 A1 Bits A<17:11> MUST be set to zero Version 1.60 Page 17 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.5 Configuration Table The following table shows, for different operating frequencies, the different RLDRAM configurations that can be programmed into the Mode Register. The Row Cycle time (tRC), the Read Latency (tRL) and the Write Latency (tWL) are shown in clock cycles as well as in nanoseconds. Each WR and RD command is a page access which requires a wait of tRC between the next WR or RD to the same bank. The shaded areas correspond to configurations that are not allowed. Table 9 RLDRAM Configuration table Configuration Frequency Parameter 400MHz (-2.5) 300MHz (-3.3) 1* 2 3 Unit tRC tRL 4 6 8 cycles 4 6 8 cycles tWL 5 7 9 cycles tRC 20 ns tRL tWL 20 ns 22.5 ns tRC 20 26.7 ns tRL 20 26.7 ns 23.3 30 ns tRC 20 30 40 ns tRL 20 30 40 ns tWL 25 35 45 ns tWL 200MHz (-5.0) Note: BL=8 is not available in configuration 1 Version 1.60 Page 18 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.6 Writes (WR) 2.6.1 Write - Basic Information Figure 10 Write command Write accesses are initiated with a WR command, as shown in Figure 10. Row and bank addresses are provided together with the WR command. Each WR command is a page access which requires a wait of tRC between the next WR or RD to the same bank. During WR commands, data will be registered at both edges of DK according to the programmed burst length BL. There is a write latency WL which is equal to the programmed read latency RL+1. The first valid data is registered with the first rising DK edge WL cycles after the WRITE command. Any WRITE burst may be followed by a subsequent READ command. Figure 14 shows the timing requirements for a WRITE followed by a READ. Setup and hold time for incoming DQs relative to the DK edges are specified as tDS and tDH. The input data is masked if the corresponding DM signal is high, setup and hold times for data mask is also tDS and tDH. CK# CK CS# WE# REF# A<20:0> A BA<2:0> BA A: BA: Address Bank Address Don't Care Figure 11 Basic Write Burst / DM Timing CK# CK tCKDK DKx# DKx Write Latency tDS DQ D0 D1 tDH D2 D3 DM Data masked tDS tDH Data masked Don't Care Version 1.60 Page 19 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM Table 10 WRITE Timing Parameters for -2.5, -3.3 and -5.0 speed sorts -2.5 Parameter Symbol -3.3 -5.0 min max min max min max Units Data-in to DK Setup Time tDS 0.25 - 0.3 - 0.4 - ns Data-in to DK Hold Time tDH 0.25 - 0.3 - 0.4 - ns tCKDK -0.30 0.30 -0.30 0.30 -0.30 0.30 ns Clock to Write Clock Time Note: 1. All timings are measured relatively to the crossing point of CK/CK#, DK/DK# and to the crossing point with VREF of the Command, Address and data signals. Note: 2. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross Note: 3. The DK/DK# input reference level (for timing referenced to DK/DK#) is the point at which DK and DK# cross Note: 4. The input reference level for signals other than CK/CK# , DK/DK# is VREF. Note: 5. The signal input slew rate must be 2V/ns. Version 1.60 Page 20 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.6.2 Write - Cyclic Bank Access 2.6.2.1 Burst Length (BL) = 2 Figure 12 Write Burst Basic Sequence, BL = 2, RL = 4, WL = 5 0 1 2 3 4 5 6 7 8 Com . WR WR WR WR WR WR WR WR WR Addr. A BA0 A BA1 A BA2 A BA3 A BA0 A BA4 A BA5 A BA6 A BA7 CK# C K RC = 4 WL = 5 DKx# DKx DQ D0a D0b D1a D1b D0d D2a D2b D3a D3b A/BAx: WR: Dxy: address A of bank x WRITE Data y to bank x WL: RC: Write Latency Row cycle time Don't Care 2.6.2.2 Burst Length (BL) = 4 Figure 13 Write Burst Basic Sequence, BL = 4, RL = 4, WL = 5 0 1 2 3 4 5 6 7 8 Com . WR NOP WR NOP WR NOP WR NOP WR Addr. A BA0 CK# CK A BA1 A BA0 A BA2 A BA0 RC = 4 WL = 5 DKx# DKx DQ D0a D0b D0c D0d A / BAx: WR: Dxy: WL: RC: D1a D1b D1c D1d address A of bank x WRITE Data y to bank x Write Latency Row Cycle time Don't Care Version 1.60 Page 21 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.6.3 Write followed by Read 2.6.3.3 Burst Length (BL) = 2 Figure 14 Write followed by Read BL = 2, RL = 4, WL = 5 0 1 2 3 4 5 6 7 8 9 Com . WR NOP RD RD NOP NOP NOP NOP NOP NOP Addr. A BA0 A BA1 A BA2 CK# CK RL = 4 WL = 5 DKx# DKx DQ D0a D0b Q1a Q1b Q2a Q2b QKx# QKx A/BAx: WR: Dxy: WL: RD: Qxy: RL: address A of bank x WRITE Data y to bank x Write Latency READ Data y to bank x Read Latency Don't Care 2.6.3.4 Burst Length (BL) = 4 Figure 15 Write followed by Read BL = 4, RL = 4, WL = 5 0 1 2 3 4 5 6 7 8 9 Com. WR NOP NOP RD NOP RD NOP NOP NOP NOP Addr. A BA0 CK# CK A BA1 A BA2 RL = 4 WL = 5 DKx# DKx DQ D0a D0b D0c D0d Q1a Q1b Q1c Q1d Q2a QKx# QKx A/BAx: WR: Dxy: WL: RD: Qxy: RL: address A of bank x WRITE Data y to bank x Write Latency READ Data y to bank x Read Latency Don't Care Version 1.60 Page 22 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.7 Reads (RD) 2.7.1 Read - Basic Information Figure 16 READ command Read accesses are initiated with a RD command, as shown in Figure 16. Row and bank addresses are provided with the RD command. Each RD command is a page access which requires a wait of tRC between the next WR or RD to the same bank. During READ bursts the memory device drives the read data edge aligned with the QK clock. After a programmable read latency, data is available at the outputs. The data valid signal indicates that data will be present on the bus after 0.5 clock cycles. CK# CK CS# WE# The skew between QK and CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last (tQKQ0max) or first (tQKQ0min) valid data edge considered over all the data generated at DQ0-DQ17 (x36) or at DQ0-DQ8 (x18). tQKQ1 is the skew between QK1 and the last (tQKQ1max) or first (tQKQ1min) valid data edge considered over all the data generated at DQ18-DQ35 (x36) or at DQ9-DQ17 (x18). tQKQx is derived at each QKx clock edge and is not cumulative over time. tQKQ is the maximum skew between one of the QKx and the last (tQKQmax) or first (tQKQmin) valid data edge considered over all the data generated at the DQ balls. All the data pins are valid after tQKQmax from the current QKx clock until tQKQmin before the next QKx clock edge. REF# A<20:0> A BA<2:0> BA A: BA: Address Bank Address Don't Care After completion of a burst, assuming no other commands have been initiated, output data (DQ) will go High-Z. Back to back RD commands are possible, producing a continuous flow of output data. The data valid window is derived from each QK transistion and is defined as : min( tQKH, tQKL) - 2* tQKQmax. Any READ burst may be followed by a subsequent WRITE command. Figure 20 shows the corresponding timing requirements. A READ to WRITE delay has to be built in in order to prevent bus contention. Some systems having long line lengths or severe skews may need additional idle cycles inserted. Version 1.60 Page 23 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM Figure 17 Basic Read Burst Timing tCKH tCKL tCK CK# CK tCKQK tQKH tQKL QKx QKx# tQKVLD tQKVLD QVLD DQ D0 D1 tQKQ D2 tQKQ D3 tQKQ tQKQ data valid window Don't Care Table 11 READ Timing Parameters for -2.5, -3-3 and -5.0 speed sorts -2.5 Parameter Symbol Conf -3.3 -5.0 min max min max min max Units Note Output Data Clock High Time tQKH 0.9 1.1 0.9 1.1 0.9 1.1 tCKH Output Data Clock Low Time tQKL 0.9 1.1 0.9 1.1 0.9 1.1 tCKL -0.25 0.25 -0.3 0.3 Clock to Output Data Clock tCKQK QK edge to Output Data edge tQKQ0, tQKQ1 x18 x36 -0.5 0.5 ns -0.2 0.2 -0.25 0.25 -0.3 0.3 ns 4 -0.3 0.3 -0.35 0.35 -0.4 0.4 ns 5 x9 QK edge to Output Data edge tQKQ x18 x36 QK edge to QVLD edge tQKVLD -0.3 0.3 -0.35 0.35 -0.4 0.4 ns Note: 1. All timings are measured relatively to the crossing point of CK/CK# (QK/QK#), and to the crossing point with VREF of the Command and Address signals. Note: 2. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; The input reference level for signals other than CK/CK# is VREF. Note: 3. The signal input slew rate must be 2V/ns. Note: 4. tQKQ0 is referenced to DQ0-DQ17 in x36 and to DQ0-DQ8 in x18. tQKQ1 is referenced to DQ18-DQ35 in x36 and to DQ9-DQ17 in x18. Note: 5. tQKQ takes into account the skew between any QKx and any DQ. Version 1.60 Page 24 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.7.2 Read - Cyclic Bank Access 2.7.2.1 Burst Length (BL) = 2 Figure 18 Read Burst, BL = 2, RL = 4 0 1 2 3 4 5 6 7 8 Com . RD RD RD RD RD RD RD RD RD Addr. A BA0 A BA1 A BA2 A BA3 A BA4 A BA5 A BA6 A BA7 A BA0 CK# CK RL = 4 QKx# QKx QVLD DQ Q0a Q0b Q1a Q1b Q2a Q2b Q3a A / BAx: RD: Qxy: RL: Q3b Q4a address A of bank x READ Data y to bank x Read Latency Don't Care 2.7.2.2 Burst Length (BL) = 4 Figure 19 Read Burst, BL = 4, RL = 4 0 1 2 3 4 5 6 7 8 Com . RD NOP RD NOP RD NOP RD NOP RD Addr. A BA0 CK# CK A BA1 A BA0 A BA2 A BA3 RC = RL = 4 QKx# QKx QVLD DQ Q0a Q0b Q0c Q0d Q1a Q1b Q1c Q1d Q0a A / BAx: address A of bank x RD: Qxy: RL: RC: READ Data part y from bank x Read Latency Row Cycle time Don't Care Version 1.60 Page 25 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.7.3 Read followed by Write Figure 20 Read followed by Write, BL=2, RL = 4, WL = 5 0 1 2 3 4 5 6 7 Com . RD WR WR NOP NOP NOP NOP NOP Addr. A BA0 A BA1 A BA2 CK# CK RL = 4 WL = 5 DKx# DKx DQ Q0a Q0b D1a D1b D2a D2b QKx# QKx A/BAx: WR: Dxy: WL: RD: Qxy: RL: address A of bank x WRITE Data y to bank x Write Latency READ Data y from bank x Read Latency Don't Care Figure 21 Read followed by Write, BL=4, RL = 4, WL = 5 0 1 2 3 4 5 6 7 Com. RD NOP WR NOP NOP NOP NOP NOP Addr. A BA0 CK# CK NOP A BA1 WL = 5 RL = 4 DKx# DKx DQ Q0a Q0b Q0c Q0d D1a D1b D1c D1d QKx# QKx A/BAx: WR: Dxy: WL: RD: Qxy: RL: address A of bank x WRITE Data y to bank x Write Latency READ Data y from bank x Read Latency Don't Care Version 1.60 Page 26 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.8 On Die Termination 2.8.1 Description On Die Termination is enabled by setting A9 to one during a Mode Register Set (MRS) command. With On Die Termination on, all the DQs as well as DM are terminated to VTT with a resistance RTT. The Commands, Addresses and clock signals are not terminated. Figure 22 shows the equivalent circuit of a DQ receiver with On Die Termination. The On Die Terminations are dynamically switched off during Read commands. Figure 22 On Die Termination Equivalent Circuit VTT sw RTT DQ Receiver Table 12 Activation of On Die Termination Ball Description (Input) Termination CK, CK# , DK0, DK0#, DK1, DK1# Activation Type No CS#, WE#, REF#, A[0:20], BA[0:2], DM No DQ0 .. DQ35 Yes TCK No ZQ No Desactivated for READs Table 13 On Die Termination DC Parameters Description Conditions Symbol Min. Max. Unit Notes Termination Voltage VTT 0.95 * VREF 1.05 * VREF V 1 On-die Termination RTT 135 165 2 Note: 1. All voltages referenced to VSS (GND) Note: 2. The RTT value is measured at 70C Version 1.60 Page 27 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.8.2 On Die Termination Timing During a Read command, the On Die Termination is switched off at the same time the data appears on the DQ bus and switched on again after the last data has been issued. The switching is conincident with the falling edge of QKx. Figure 23 Read Burst with ODT , BL=2 0 1 2 3 4 5 6 7 8 Com . RD RD RD NOP NOP NOP NOP NOP NOP Addr. A BA0 A BA1 A BA2 CK# CK RL = 4 QKx# QKx QVLD DQ Q0a ODT Q0b Q1a ODT ON Q1b Q2a Q2b ODT OFF ODT ON A / BAx: RD: Qxy: RL: Don't Care Termination Switching address A of bank x READ Data y to bank x Read Latency Note: It is ensured by design that the ODT is switched off prior the DQs are activated and on after the last data has been issued. Figure 24 Read NOP Read with ODT, BL=2 0 1 2 3 4 5 6 7 8 Com . RD NOP RD NOP NOP NOP NOP NOP NOP Addr. A BA0 CK# CK A BA2 RL = 4 QKx# QKx QVLD DQ ODT Q0a ODT ON Q0b ODT OFF Don't Care Termination Switching Q2a Q2b ODT OFF ODT ON A / BAx: address A of bank x RD: Qxy: RL: READ Data y to bank x Read Latency Note: It is ensured by design that the ODT is switched off prior the DQs are activated and on after the last data has been issued. Version 1.60 Page 28 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM Figure 25 Read followed by Write with ODT, BL=2 0 1 2 3 4 5 6 7 8 Com . RD WR WR NOP NOP NOP NOP NOP NOP Addr. A BA0 A BA1 A BA2 CK# CK RL = 4 WL = 5 DKx# DKx DQ Q0a Q0b D1a D1b D2a D2b QKx# QKx ODT ON ODT ODT OFF RD: Qxy: RL: Don't Care Termination Switching ODT ON A/BAx: WR: Dxy: WL: READ Data y from bank x Read Latency address A of bank x WRITE Data y to bank x Write Latency Note: It is ensured by design that the ODT is switched off prior the DQs are activated and on after the last data has been issued. Figure 26 Write followed by Read with ODT, BL=2 0 1 2 3 4 Com . WR NOP NOP RD RD Addr. A BA0 A BA1 A BA2 5 6 7 8 9 10 NOP NOP NOP NOP NOP NOP CK# CK RL = 4 WL = 5 DKx# DKx DQ D0a D0b Q1a Q1b Q2a Q2b QKx# QKx ODT ODT ON ODT OFF Don't Care Termination Switching RD: Qxy: RL: READ Data y to bank x Read Latency A/BAx: WR: Dxy: WL: ODT ON address A of bank x WRITE Data y to bank x Write Latency Note: It is ensured by design that the ODT is switched off prior the DQs are activated and on after the last data has been issued. Version 1.60 Page 29 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 2.9 Auto Refresh Command (AREF) Figure 27 Auto Refresh Command AREF is used to do a refresh cycle on one row in a specific bank. The row addresses are generated by an internal refresh counter for each bank; external address pins are "DON'T CARE". The delay between the AREF command and a subsequent command on the same bank must be at least tRC. Within a period of tREF=32ms the whole memory has to be refreshed (8k refresh per bank, 64k total refresh cycles each 32ms). Figure 28 shows an example of a continuous refresh sequence. Other refresh strategies such as burst refresh are also possible. CLK# CLK CS# WE# REF# A<20:0> BA<2:0> BA BA: Bank Address Don't Care Figure 28 Auto Refresh Cycle CLK# CLK Command ARFx ACy ACx ACy ARFx ACy tRC ACx.: Any Command on bank x ARFx: Auto Refresh bank x ACy.: Any Command on different bank Don't Care Version 1.60 Page 30 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 3 Operation with multiplexed addresses 3.1 Description In multiplexed address mode, the address can be provided to the RLDRAM in two parts that are latched into the memory with two consecutive rising clock edges. This provides the advantage that only 11 addresses are required to control the RLDRAM, reducing the number of pins on the controller side. The address mapping is represented in Table 14. The command is internally executed with the second clock rising edge, when the Ay address part is made available to the memory. For this reason, the effective Read and Write latencies are increased by 1 clock cycle in the multiplexed address mode of operation, whereas tRC remains unaffected. The data bus efficiency in continuous burst mode is not affected for BL4 and BL8 since at least two clocks are required to read the data out of the memory. The bank addresses are delivered to the RLDRAM at the same time as the READ or WRITE command and the first address part Ax. This option is available by setting bit A5 to 1 in the Mode Register. Once this bit set, the READ, WRITE and MRS commands follow the format described in Figure 29. An alternative address mapping using a different address ballout and the numbering A[10:0] is available in a separate application note. Figure 29: Command description in multiplexed address mode Read Write MRS NOP AREF CK CK# CS# WE# REF# A<20:0> Ax BA<2:0> BA Ay Ax Ay Ax Ay BA BA Ax, Ay: BA: Address Bank Address Don't Care Note: The minimum setup and hold times of the two address parts are defined tAS and tAH. Version 1.60 Page 31 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 3.2 Address mapping In the address multiplexing mode, the RLDRAM concatenates the addresses Ax and Ay received at the balls [A0, A3, A4, A5, A8, A9, A10, A13, A14, A17, A18] and builds an internal address a[19..0] that is processed as if the RLDRAM were in the default mode of operation. The address mapping is described in table 11 as a function of burst length and data width. The external addresses Ax are translated to the internal addresses a[19..0] according to the table below. Table 14 Address mapping in multiplexed address mode Data Width Burst Length BL2 x36 BL 4 BL2 x18 BL 4 BL 8 Addresses Add pin A0 A3 A4 A5 Ax a0 a3 a4 a5 a1 a2 a3 a4 a1 a2 a0 a3 a4 a1 a2 a0 a3 a4 a1 a2 a0 a3 a4 a1 a2 Ay Ax a0 Ay Ax Ay Ax Ay Ax Ay 2 A8 A9 A10 A13 A14 A17 A18 a8 a9 a10 a13 a14 a17 a18 a6 a7 a11 a12 a16 a15 a8 a9 a13 a14 a17 a6 a7 a11 a12 a16 a15 a5 a8 a9 a13 a14 a17 a18 a6 a7 a19 a11 a12 a16 a15 a5 a8 a9 a10 a13 a14 a17 a18 a6 a7 a11 a12 a16 a15 a5 a8 a9 a10 a13 a14 a17 a6 a7 a11 a12 a16 a5 a10 a10 a15 Note: 1. Don't Care Note: 2. Reserved for A21 expansion in multiplexed mode Version 1.60 Page 32 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 3.3 Mode Register Set command in multiplexed address mode The addresses A0, A3, A4, A5, A8, A9, A10 have to be set as follows in order to activate the Mode Register in the muxed address mode. Ax A10 A9 A8 A5 Ay Test Mode A10x Test Mode 0 default 1 test mode On-die Termination Calibration A4 A0 A3 A4 A9 A8 DLL Reset Unused Address Mux Burst Length A3y A0x RLDRAM configuration 2 (default) 0 0 0 1 (default) 4 0 0 1 1 0 8 0 1 0 2 1 not valid 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved Termination A9y DLL Reset A4x A3x 0 Disabled (default) 0 Reset (default) 0 0 1 Enabled 1 Enable 0 1 1 1 Resistor A5x Addresss Mux 0 internal (50 ) (default) 0 non-multiplexed (default) 1 external 1 address multiplexed Configuration A4y A9x A8x A3 BL All non used bits MUST be set to zero 3.4 Power up sequence for multiplexed address mode The following sequence has to be respected in order to power up the RLDRAM in the multiplexed address mode. Figure 30 Power up sequence in multiplexed address mode VEXT VDD VDDQ VTT VREF CK# CK Com MRS MRS MRS MRS A1) Ax Add min. 200 s min. 1 cycle min. 1 cycle 2) tMRSC RF0 RF1 RF7 A.C. Ay tMRSC min. 2048 6 x 2048 cycles cycles MRS: RFx: A.C.: tRC MRS command REFRESH Bank x Any command Don't Care Note: 1) Address A5 must be set HIGH (Muxed address mode setting when RLDRAM in normal mode of operation) Note: 2) Address A5x must be set HIGH (Muxed address mode setting when RLDRAM already in muxed address mode) Version 1.60 Page 33 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 3.5 Ball Configuration of RLDRAM in multiplexed address mode Figure 31 8M x 36 Ball assignment in multiplexed address mode ( Top view) 144 P-TFBGA package 1 2 3 4 A VREF VSS VEXT B VDD DQ8 C VTT D DNU 9 10 11 12 VSS VSS VEXT TMS TCK DQ9 VSSQ VSSQ DQ1 DQ0 VDD DQ10 DQ11 VDDQ VDDQ DQ3 DQ2 VTT DQ12 DQ13 VSSQ VSSQ QK0# QK0 VSS E DNU DQ14 DQ15 VDDQ VDDQ DQ5 DQ4 DNU F A5 DQ16 DQ17 VSSQ VSSQ DQ7 DQ6 QVLD G A8 DNU DNU VDD VDD DNU DNU A0 H B2 A9 VSS VSS VSS VSS A4 A3 J DK0 DK0# VDD VDD VDD VDD B0 CK K DK1 DK1# VDD VDD VDD VDD B1 CK# L REF# CS# VSS VSS VSS VSS A14 A13 M WE# DNU A17 VDD VDD DNU DNU A10 N A18 DQ24 DQ25 VSSQ VSSQ DQ35 DQ34 DNU P DNU DQ22 DQ23 VDDQ VDDQ DQ33 DQ32 DM R VSS QK1 QK1# VSSQ VSSQ DQ31 DQ30 VSS T VTT DQ20 DQ21 VDDQ VDDQ DQ29 DQ28 VTT U VDD DQ18 DQ19 VSSQ VSSQ DQ27 DQ26 VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI 1 1 2 2 2 2 5 6 7 8 2 2 2 2 2 2 Note: 1. Reserved for future use. May optionaly be connected to GND for improved heat dissipation. Note: 2. Do not use. This signal has parasitic characteristics of an address input. May optionally be connected to GND in order to improve heat dissipation. Version 1.60 Page 34 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM Figure 32 16M x 18 Ball assignment in multiplexed address mode ( Top view) 144 P-TFBGA package 1 2 3 4 A VREF VSS VEXT B VDD DNU 9 10 11 12 VSS VSS VEXT TMS TCK DQ9 VSSQ VSSQ DQ0 DNU C VTT DNU DQ10 VDDQ VDDQ DQ1 DNU VTT D DNU DQ11 VSSQ VSSQ QK0# QK0 VSS E DNU DNU DQ12 VDDQ VDDQ DQ2 DNU F A5 DNU DQ13 VSSQ VSSQ DQ3 DNU G A8 DNU DNU VDD VDD DNU DNU A0 H B2 A9 VSS VSS VSS VSS A4 A3 J NC NC VDD VDD VDD VDD B0 CK K DK DK# VDD VDD VDD VDD B1 CK# L REF# CS# VSS VSS VSS VSS A14 A13 M WE# DNU A17 VDD VDD DNU DNU N A18 DNU DQ14 VSSQ VSSQ DQ4 DNU P DNU DNU DQ15 VDDQ VDDQ DQ5 DNU R VSS QK1 QK1# VSSQ VSSQ DQ6 DNU T VTT DNU DQ16 VDDQ VDDQ DQ7 DNU U VDD DNU DQ17 VSSQ VSSQ DQ8 DNU VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI 4 4 1 1 4 DNU 4 4 3 2 2 3 4 3 4 4 4 3 5 6 7 8 3 3 4 4 4 4 3 3 4 4 4 4 4 VDD 3 DNU QVLD A10 DNU DM VSS VTT Note: 1. Reserved for future use. May optionaly be connected to GND for improved heat dissipation. Note: 2. Do not connect. This signal has parasitic characteristics of a clock input Note: 3. Do not use This signal has parasitic characteristics of an address input. May optionally be connected to GND in order to improve heat dissipation. Note: 4. Do not use This signal has parasitic characteristics of an IO. May optionally be connected to GND in order to improve heat dissipation. Version 1.60 Page 35 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 3.6 Configuration table In this mode, the Read and Write latencies are increased of one clock cycle. The RLDRAM cycle time remains the same as described in table 12. Table 15 RLDRAM Configuration table in multiplexed address mode Configuration Frequency 400MHz 300MHz 200MHz 11 2 3 Unit tRC tRL 4 6 8 cycles 5 7 9 cycles tWL 6 8 10 cycles Parameter tRC tRL 20 ns 22.5 ns tWL 25 ns 26.7 ns 20 tRC tRL 23.3 30 ns tWL 26.7 33.3 ns tRC tRL 20 30 40 ns 25 35 45 ns tWL 30 40 50 ns Note: 1: BL=8 is not available in configuration 1 Version 1.60 Page 36 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 3.7 Timing diagrams 3.7.1 Write Command The basic WRITE timing is identical for the default mode and the multiplexed address mode, except for the latency. In particular, the DM signal is handled in the same way as in the default mode of operation. Please refer to chapter 2.6 for more details. Figure 33 Write burst basic sequence BL4 with multiplexed addresses, config. 1, WL = 6 0 1 2 3 4 5 6 7 8 Com. WR NOP WR NOP WR NOP WR NOP WR Addr. Ax/ BA0 Ay Ax/ BA1 Ay Ax/ BA2 Ay Ax/ BA3 Ay Ax/ BA0 CK# CK WL = 6 DK# DK DQ D0a D0b D0c D0d D1a D1b Ax/BAk: Ay: WR: Dik: address Ax of bank k address Ay of bank k WRITE Data part i to bank k WL: Write Latency Don't Care Figure 34 Write followed by Read with multiplexed addresses, BL=4, RL=5, WL=6 0 1 Com. WR Addr. Ax/ BA0 2 3 4 5 6 7 8 9 NOP RD NOP RD NOP NOP NOP NOP Ay Ax/ BA1 Ay Ax/ BA2 Ay CK# CK RL = 5 WL = 6 DKx# DKx DQ D0a D0b D0c D0d Q1a Q1b Q1c QKx# QKx Ax/BAk: Ay: WR: Dxy: WL: Version 1.60 Page 37 address Ax of bank k address Ay WRITE Data y to bank x Write Latency RD: Qxy: RL: READ Data y to bank x Read Latency Don't Care Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 3.7.2 Read Command The basic READ timing is identical for the default mode and the multiplexed address mode, except for the latency. In particular, the QVLD signal will be generated in the same manner as in the default mode of operation. Please refer to chapter 2.7 for more details. Figure 35 Read burst basic sequence BL4 with multiplexed addresses, config. 1, RL = 5 0 1 2 3 4 5 6 7 8 Com. RD NOP RD NOP RD NOP RD NOP RD Addr. Ax/ BA0 Ay Ax/ BA1 Ay Ax/ BA2 Ay Ax/ BA0 Ay Ax/ BA1 CK# CK RL = 5 QKx# QKx QVLD DQ Q0a Q0b Q0c Q0d Q1a Q1b Q1c Ax/BAk: Ay: address Ax of bank k address Ay RD: Qik: RL: READ Data part i from bank k Read Latency Don't Care Figure 36 Read followed by Write with multiplexed addresses, BL=4, RL=5, WL=6 0 1 2 3 4 5 6 7 8 9 Com. RD NOP WR NOP NOP NOP NOP NOP NOP NOP Addr. Ax/ BA0 Ay Ax/ BA1 Ay CK# CK WL = 6 RL = 5 DKx# DKx DQ Q0a Q0b Q0c Q0d D1a D1b D1c D1d QKx# QKx Ax/BAk: Ay: WR: Dxy: WL: Version 1.60 Page 38 address Ax of bank k address Ay WRITE Data y to bank x Write Latency RD: Qxy: RL: READ Data y to bank x Read Latency Don't Care Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 3.7.3 Refresh command In the multiplexed address mode the refresh command is, like the other commands, executed on the next rising clock edge. However, since no second address part is required, the next AREF command can already be applied. No NOP operation is required either between an AREF command and any other valid command as represented on Figure 37. Figure 37 Burst refresh operation 0 1 2 3 4 5 6 7 8 9 10 Com. AC NOP AREF AREF AREF AREF AREF AREF AREF AREF AC Addr. Ax Ay BAdd. BAk 11 CK# CK Ax BA0 BA1 BA2 BA3 BA4 BA5 AREF: AC : Version 1.60 Page 39 BA6 Autorefresh Any command BA7 Ax: Ay: BAk: Ay BAk First part Ax of address Second part Ay of address Bank k. k is chosen so that tRC is met Don't Care Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 4 IEEE 1149.1 Serial Boundary Scan (JTAG) The RLDRAM incorporates a serial boundary scan Test Access Port (TAP). This port operates fully complient with IEEE Standard 1149.1-1990. It contains a TAP controller, instruction register, boundary scan register, bypass register, and ID code register. It is possible to operate the RLDRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied low while TDI, TMS and TDO may be left unconnected. Upon power-up, the TAP will come up in a reset state which will not interfere with the normal operation of the device. 4.1 Test Access Port (TAP) 4.1.1 Test Clock (TCK) The test clock is used only with the TAP controller. The pin must be tied low if the TAP is not used. 4.1.2 Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. 4.1.3 Test Data-In (TDI) The TDI pin is used to serially input information into the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is connected to the most significant bit (MSB) of any register (see Figure 38). This pin may be left unconnected if the TAP is not used. 4.1.4 Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Figure 39). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register (see Figure 38). This pin may be left unconnected if the TAP is not used. 4.2 TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and shifted out of the RLDRAM test circuitry (see Figure 38). Only one register is selected at a time through the instruction register. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. 4.2.1 Instruction Register Eight-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in Figure 38. Upon power-up, the instruction register is internally preloaded with the IDCODE instruction. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. 4.2.2 Bypass Register The bypass register is a single-bit register that can be placed between the TDI and TDO pins. This allows data to be shifted through the RLDRAM with minimal delay. The bypass register is set LOW during the Capture-DR state when the BYPASS instruction is loaded in the instruction register. Version 1.60 Page 40 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 4.2.3 Boundary Scan Register The boundary scan register is connected to all the IO pins on the RLDRAM. It allows to observe and control the data flowing into and out of the device, depending on the instruction being loaded in the instruction register. The boundary scan register is 113 bits long. The register is the same for the x18 and x36 configurations of the RLDRAM. Pins not used in x18 configuration read a LOW into the boundary scan register in the CaptureDR controller state. Differential inputs (CK/CK#, DKx/DKx#) and outputs (QKx/QKx#) are equipped with two boundary scan cells each. Thus, the differential nature of these pins is not visible to the test circuitry. However, it is recommended that during testing differential signals are always applied to these pin pairs. 4.2.4 Identification (ID) Register The ID register is loaded with a hardwired, vendor-specific, 32-bit code during the Capture-DR state when the IDCODE instruction is loaded in the instruction register. The code can be shifted out when the TAP controller is in the Shift-DR state. Two different codes are implemented for the x18 and x36 configurations of the RLDRAM (see Table 16). . Table 16 ID Register Definition Revision Number Part Number Infineon JEDEC Code L S B Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x18 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 x36 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 Version 1.60 Page 41 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 4.3 TAP Instructions The TAP implements the 6 instructions BYPASS, EXTEST, SAMPLE/PRELOAD, IDCODE, HIGHZ and CLAMP for user access (see Table 17). The implementation of these instructions fully complies with the IEEE standard. All other instructions are reserved and should not be used. Table 17 JTAG Instruction Register Instruction Register Code Instruction Description Hex x7 .. x0 00 0000 0000 EXTEST Selects the boundary scan register to be connected between TDI and TDO. Data received at input pins are sampled and loaded into the boundary scan register. Data driven by output pins are determined from values contained in the boundary scan register. 03 0000 0011 HIGHZ Selects the bypass register to be connected between TDI and TDO. All ouputs are forced into high impedance state. 05 0000 0101 07 0000 0111 CLAMP Selects the bypass register to be connected between TDI and TDO. Data driven by output pins are determined from values held in the boundary scan regsiter. 21 0010 0001 IDCODE Selects the ID code register to be connected to TDI and TDO. Instructin does not interfere with the normal operation of the device. E0-EF 1110 0000 1110 1111 RESERVED FF 1111 1111 BYPASS Version 1.60 SAMPLE / PRELOAD Selects the boundary scan register to be connected between TDI and TDO. Data receivedat input pins are sampled and loaded int the boundary scan register. initial ouput data are shifted into the boundary scan register prior to an EXTEST intruction. Instruction does not interfere with the normal operation of the device. Do not use. Selects the bypass register to be connected between TDI and TDO. Instruction does not interfere with the normal operation of the device. Page 42 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 4.4 Boundary Scan Exit Order 4.4.1 x18 Configuration Note: Note: Note: Note: Note: Pin Descr . Pin Name Ball # Ball # Pin Name Pin Descr . Reg Content Scan Reg # I/O DQ0 B10 B3 DQ4 I/O Enb Data 84 85 I/O DNU B11 B2 DNU I/O I/O DQ1 C10 C3 DQ5 I/O I/O DNU C11 C2 DNU I/O Enb Data Enb Data Enb Data 86 87 88 89 90 91 Data O QK0# D10 D3 DQ6 I/O 74 Data O QK0 D11 D2 DNU I/O 73 72 71 70 Data Enb Data Enb I/O DNU E11 E2 DNU I/O Enb Data Enb Data Enb Data 92 93 94 95 96 97 I/O DQ2 E10 E3 DQ7 I/O 69 68 67 66 Data Enb Data Enb I/O DNU F11 F2 DNU I/O Enb Data Enb Data 98 99 100 101 I/O DQ3 F10 F3 DQ8 I/O 65 64 Data Data O I QVLD (A20) F12 E12 E1 (A21) I Enb Data Data 102 103 104 63 62 61 60 59 58 57 Data Data Data Data Data Data Data I I I I I I I A1 A2 A0 A3 A4 B0 CK G11 G10 G12 H12 H11 J11 J12 F1 G2 G3 G1 H1 H2 J2 J1 A5 A6 A7 A8 B2 A9 NC NC I I I I I I I I Data Data Data Data Data Data Data Data 105 106 107 108 109 110 111 112 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 Data Data Data Data Data Data Data Data Data Data Enb Data Enb Data Enb I I I I I I I I I CK# B1 A14 A13 A10 A12 A11 A19 DM K12 K11 L11 L12 M12 M10 M11 N12 P12 K1 K2 L2 L1 M1 M3 M2 N1 P1 DK DK# CS# REF# WE# A17 A16 A18 A15 I I I I I I I I I I/O DQ9 N10 N3 DQ14 I/O I/O DNU N11 N2 DNU I/O Data Data Data Data Data Data Data Data Data Enb Data Enb Data 0 1 2 3 4 5 6 7 8 9 10 11 12 I/O DQ10 P10 P3 DQ15 I/O 41 40 39 38 37 36 Data Enb Data Enb Data Enb I/O DNU P11 P2 DNU I/O Enb Data Enb Data 13 14 15 16 I/O DNU R11 R2 QK1 O Data 17 I/O DQ11 R10 R3 QK1# O Data 18 35 34 33 32 31 30 Data Enb Data Enb Data Enb I/O DNU T11 T2 DNU I/O I/O DQ12 T10 T3 DQ16 I/O Enb Data Enb Data 19 20 21 22 I/O DNU U11 U2 DNU I/O 29 28 Data Enb I/O DQ13 U10 U3 DQ17 I/O Enb Data Enb Data 23 24 25 26 V2 ZQ I Data 27 Scan Reg# Reg Content 83 82 81 80 Data Enb Data Enb 79 78 77 76 Data Enb Data Enb 75 1: Input pins are connected to Observe-Only Boundary Scan Register Cells. 2: Output pins are connected to Force-Only Boundary Scan Register Cells. 3: IO pins are connected to Force-and-Observe Boundary Scan Register Cells. 4 : Enb should be set to 0 for DNU pins, if they are connected to GND 5: Any unused pins that are in the order will read as the logic level applied to the ball site. If the ball is unconnected a logic level "LOW" will be read. Version 1.60 Page 43 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 4.4.2 Note: Note: Note: Note: Note: x36 Configuration Pin Descr . Pin Name Ball # Ball # Pin Name Pin Descr . I/O DQ1 B10 B3 DQ9 I/O I/O DQ0 B11 B2 DQ8 I/O I/O DQ3 C10 C3 DQ11 I/O I/O DQ2 C11 C2 DQ10 I/O Data O QK0# D10 D3 DQ13 I/O 74 Data O QK0 D11 D2 DQ12 I/O 73 72 Data Enb I/O DQ4 E11 E2 DQ14 I/O 71 70 69 68 Data Enb Data Enb I/O DQ5 E10 E3 DQ15 I/O I/O DQ6 F11 F2 DQ16 I/O 67 66 Data Enb I/O DQ7 F10 F3 DQ17 I/O 65 64 63 62 61 60 59 58 57 Data Data Data Data Data Data Data Data Data O I I I I I I I I QVLD (A20) A1 A2 A0 A3 A4 B0 CK F12 E12 G11 G10 G12 H12 H11 J11 J12 E1 F1 G2 G3 G1 H1 H2 J2 J1 (A21) A5 A6 A7 A8 B2 A9 DK0# DK0 I I I I I I I I I 56 55 54 53 52 51 50 49 48 47 46 45 44 Data Data Data Data Data Data Data Data Data Data Enb Data Enb I I I I I I I I I CK# B1 A14 A13 A10 A12 A11 (A19) DM K12 K11 L11 L12 M12 M10 M11 N12 P12 K1 K2 L2 L1 M1 M3 M2 N1 P1 DK1 DK1# CS# REF# WE# A17 A16 A18 A15 I I I I I I I I I I/O DQ35 N10 N3 DQ25 I/O I/O DQ34 N11 N2 DQ24 I/O 43 42 41 40 39 38 Data Enb Data Enb Data Enb I/O DQ33 P10 P3 DQ23 I/O I/O DQ32 P11 P2 DQ22 I/O I/O DQ30 R11 R2 QK1 37 36 35 34 33 32 Data Enb Data Enb Data Enb I/O DQ31 R10 R3 I/O DQ28 T11 I/O DQ29 31 30 29 28 Data Enb Data Enb I/O I/O Scan Reg# Reg Content 83 82 81 80 79 78 77 76 Data Enb Data Enb Data Enb Data Enb 75 Reg Content Scan Reg # Enb Data Enb Data Enb Data 84 85 86 87 88 89 Enb Data Enb Data Enb Data 90 91 92 93 94 95 Enb Data Enb Data 96 97 98 99 Enb Data 100 101 Enb Data Data Data Data Data Data Data Data Data Data 102 103 104 105 106 107 108 109 110 111 112 Data Data Data Data Data Data Data Data Data Enb Data Enb Data Enb Data Enb Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 O Data 17 QK1# O Data 18 T2 DQ20 I/O Enb Data 19 20 T10 T3 DQ21 I/O DQ26 U11 U2 DQ18 I/O DQ27 U10 U3 DQ19 I/O V2 ZQ I Enb Data Enb Data Enb Data Data 21 22 23 24 25 26 27 1: Input pins are connected to Observe-Only Boundary Scan Register Cells. 2: Output pins are connected to Force-Only Boundary Scan Register Cells. 3: IO pins are connected to Force-and-Observe Boundary Scan Register Cells. 4 : Enb should be set to 0 for DNU pins, if they are connected to GND 5: Any unused pins that are in the order will read as the logic level applied to the ball site. If the ball is unconnected a logic level "LOW" will be read. Version 1.60 Page 44 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 4.5 TAP Operation The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while the RLDRAM clock operates much faster. As a consequence, it is possible that an input or output will undergo a transition right at the moment when the TAP takes the snapshot in the Capture-DR state of EXTEST or SAMPLE/PRELOAD instructions. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. To guarantee that the boundary scan register will capture the correct value of a signal, the signal must meet the TAP's setup and hold time ( tCS plus tCH) around the rising edge of TCK. 4.6 JTAG TAP Block Diagram Figure 38 TAP Block Diagram TMS TCK Test Access Port (TAP) Controller 0 Bypass Register TDI 7 6 5 4 3 2 1 TDO 0 Instruction Register 31 30 1 0 ID Code Register Version 1.60 113 0 112 1 Page 45 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 4.7 JTAG TAP Controller State Diagram Figure 39 TAP Controller State Diagram Test Logic Reset 1 0 Run Test Idle 1 0 1 1 Select DR 0 Capture DR 1 0 Shift IR 0 1 Exit DR 1 0 Exit IR 0 0 Pause DR Pause IR 0 1 0 Exit2 DR 1 1 Exit2 IR 0 0 1 0 Update DR 1 4.8 1 0 Shift DR 1 Select IR 0 Capture IR Update IR 0 1 JTAG DC Operating Conditons (0C Tj 100C; 1.7V VDD 1.9V unless otherwise noted) Parameter Symbol Limit Values Unit Notes min. typ. max. Input logic high voltage, VTIH DC VREF + 0.15 - VDDQ + 0.3 V Input logic low voltage, DC VSSQ -0.3 - VREF - 0.15 V Output logic high VTOH voltage (IOH = -tbd mA) VREF + tbd - - V Output logic low voltage VTOL (IOL = tbd mA) - - VREF - tbd V Version 1.60 VTIL Page 46 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 4.9 JTAG AC Operating Conditions (0C Tj 100C; 1.7V VDD 1.9V unless otherwise noted) Parameter Symbol Limit Values Unit min. typ. max. Input logic high voltage, VTIH AC VREF + 0.3 - VDDQ + 0.3 V Input logic low voltage, AC VSSQ - 0.3 - VREF - 0.3 V - - V/ns VTIL Input Slew Rate TTSL Input and Output Timing VREF Reference Level 4.10 1.0 VDDQ /2 Notes V JTAG AC Electrical Characteristics (0C Tj 100C; 1.7V VDD 1.9V unless otherwise noted) Parameter Symbol Limit Values Unit Notes min. typ. max. TTCK TTCKH 20 - - ns 10 - - ns TTCKL TTCKDO 10 - - ns TCK Low to TDO Valid - - 10 ns TDI Set Up Time TTDIS 5 - - ns TMS Set Up Time TTMSS TTDIH 5 - - ns TDI Hold Time 5 - - ns TMS Hold Time TTMSH 5 - - ns TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width 4.11 JTAG Timing Diagram TTCK TTCKH TTCKL TCK TTMSH TTMSS TTDIH TTDIS TMS TDI TTCKDO TDO Version 1.60 Page 47 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 5 Electrical Characteristics 5.1 Absolute Maximum Ratings z z z z z z Storage temperature range............................................- 55 to + 150 C I/O voltage .......................................................... - 0.3 to +VDDQ + 0.3V Power supply voltage VEXT ............................................. - 0.3 to + 2.8V Power supply voltage VDD ....................................................- 0.3 to + 2.1V Power supply voltage VDDQ ............................................ - 0.3 to + 2.1V Junction Temperature......................................................... 0C to 100C Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5.2 Recommended Power & DC Operation Ratings All values are recommended operating conditions unless otherwise noted. Table 18 Power & DC Operating Conditions (0C Tj 100C; 1.7V VDD 1.9V unless otherwise noted) Description Conditions Symbol Min. Max. VEXT 2.38 2.63 V 1 VDD 1.7 1.9 V 1 VDDQ VTT 1.7 VDD V 1,2 0.95*VREF 1.05*VREF V 1,7 Reference Voltage Vref 0.49*VDDQ 0.51*VDDQ V 1,3,4 External Resistor RQ 125 250 On-die Termination RTT 135 165 5 Input HIGH (Logic 1) voltage VIH Vref + 0.1 V 1 Input LOW (Logic 0) voltage VIL VDDQ + 0.3 VSSQ - 0.3 Vref - 0.1 V 1 Output high current IOH (VDDQ/2) (1.15xRQ/5) (VDDQ/2) (0.85xRQ/5) A 6 IOL (VDDQ/2) (1.15xRQ/5) (VDDQ/2) (0.85xRQ/5) A 6 ILI -5 +5 A ILCI ILO -5 +5 A -5 +5 A IREF -5 +5 A Supply Voltage IO Supply Voltage Termination Voltage Output low current VOUT = VDDQ/2 Input leakage current CLK Input leakage current Output leakage current VREF Current 0V< VIN < VDDQ Unit Notes Note: Note: Note: Note: 1. All voltages referenced to VSS (GND) 2. VDDQmax = 1.8V or VDD which ever is lower. 3. Typically the value of Vref is expected to be VDDQ/2 of the transmitting device. Vref is expected to track variations in VDDQ 4. Peak to peak AC noise on Vref may not exceed 2% Vref (DC). Thus, from VDDQ/2, VREF is allowed 2% for DC error and 2% for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. Note: 5. The RTT value is measured at 70C Note: 6. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the device, IOL flows into the device. Note: 7. A power supply should be used for the generation of Vtt to sink and source the transiant currents. A 1k voltage divider will not work. Version 1.60 Page 48 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 5.3 AC Operation Ratings Table 19 AC Operation Conditions (0C Tj 100C; 1.7V VDD 1.9V unless otherwise noted) DESCRIPTION CONDITIONS Symbol min. max. Unit Notes Input HIGH (Logic 1) Voltage VIH Vref + 0.2 VDDQ + 0.3 V Input LOW (Logic 0) Voltage VIL VSSQ - 0.3 Vref - 0.2 V Note: 1. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; The input reference level for signals other than CK/CK# is VREF. Note: 2. The signal input slew rate must be 2V/ns. 5.4 Clock Input Operation Ratings Table 20 Clock Input Operating Conditions DESCRIPTION Symbol min. max. VIN(DC) DC Clock Input Differential Voltage (CK / CK#) VID(DC) -0.3 VDDQ + 0.3 V 0.2 VDDQ + 0.6 V 3 AC Clock Input Differential Voltage (CK / CK#) VID(AC) 0.4 VDDQ + 0.6 V 3 VDDQ/2 -0.15 VDDQ/2 +0.15 V 4 Clock Input Voltage Levels (CK / CK#) Clock Input Crossing Point Voltage (CK/ CK#) VIX(AC) Unit Notes Note: 1. DKx and DKx# have the same requirements as CK and CK# Note: 2. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; The input reference level for signals other than CK/CK# is VREF. Note: 3. VID is the magnitude of the difference between the input level on CK and the input level on CK#. Note: 4. The value if VIX is expected to equal VDDQ/2 of the transmitting device and must track variations of the DC value of the same. 5.5 Output Test Conditions Figure 40 Output Test Circuits + Vtt = 0.5 x V DDQ 50 Ohm DQ Test point 10 pF Note:VDDQ=1.8V 0.1V, TJ = 0 C to 100 C Version 1.60 Page 49 Infineon Technologies This specification is preliminary and subject to change without notice HYB18RL28818/36AC 288 Mbit DDR Reduced Latency DRAM 5.6 Pin Capacitances Table 21 Pin Capacitances Pin Conditions Symbol Min Max Unit CI CO CCK 1.5 2.5 pF TA = 25C; f = 1MHz 3.0 4.0 pF 2.0 3.0 pF A<20:0>, BA<2:0>, CS#, AREF#, WE# DQ<35:0>, QKx, QKx#, QVLD, DM CK, CK#, DKx, DKx# 5.7 Operating Currents Table 22 IDD Specifications and Conditions Parameter Limit Values (max.) Freq IDD1 (*) Operating Current (Average Power Supply Current) IDD4R (*) Operating Current (Average Power Supply Current) IDD8 (*) Operating Current (Average Power Supply Current) x36 Unit Notes Burst Length = 2 tCK=min, tRC=min, 1 bank active, Address change one time during min tRC, Read/Write command cycling Burst Length = 4 tCK=min, tRC=min, 4 banks interleave, address change with each bank activation, continuous read operation 1.) Burst Length = 2 tCK=min, tRC=min, up to 8banks interleave, address change with each bank activation, continuous read operation 2.) 400MHz VDD VEXT 260 55 260 55 mA mA 300MHz VDD VEXT 240 55 240 55 mA mA 200MHz VDD VEXT 215 55 215 55 mA mA 400MHz VDD VEXT 340 65 390 65 mA mA 300MHz VDD VEXT 315 65 360 65 mA mA 200MHz VDD VEXT 295 65 340 65 mA mA 400MHz VDD VEXT 505 90 505 90 mA mA 300MHz VDD VEXT 475 90 565 90 mA mA 200MHz VDD VEXT 445 90 535 90 mA mA 400MHz VDD VEXT 175 45 175 45 mA mA 300MHz VDD VEXT 160 45 160 45 mA mA 200MHz VDD VEXT 140 45 140 45 mA mA Standby Current Version 1.60 x18 Page 50 tCK=min All banks idle, CS=1 Command toggling Infineon Technologies This specification is preliminary and subject to change without notice