Graphics & Speciality DRAMs
288 Mbit DDR Reduced Latency DRAM
Version 1.60
July 2003
HYB18RL28818AC
HYB18RL28836AC
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 2 Infineon Technologies
This specification is preliminary and subject to change without notice
Edition July 2003
This edition was realized using the software system FrameMaker.
Published by Infineon Technologies,
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Balanstraße 73,
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© Infineon Technologies 4/01/03.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits imple-
mented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies
and Representatives worldwide (see address list).
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fineon Technologies Office.
Infineon Technologies is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing
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Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of Infineon Technologies, may only be used in life-support devices or systems2 with the express written approval of Infineon Tech-
nologies.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-
support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they
fail, it is reasonable to assume that the health of the user may be endangered.
HYB18RL28818/36AC
Revision History: Current Version 1.60
Subjects (major changes since last revision)
Previous Version: 1.51
frontpage frontpage fixed part number HYB18RL28809AC -> HYB18RL28890AC
all all removed confidential
48 48 x36 configuration table, swapped pins F12 and E12
11 11 Ball Description table - ZQ - added ‘...connected to GND, then minimum DQ output impedance is set.’
46,47,48 46,47,48 Re-numbered scan registers order, starting with 0 to 112
52 52 Removed the word “Isolated” from the Vddq power supply description in table 18
52 52 Added note 7 for Vtt. A power supply should be used for Vtt generation, not a voltage divider.
19 19 Changed the value of tMRSC from 6 to 12 clocks
49 49 Figure 40, Tap Block Diagram. Added numbering to scan chain order.
16 16 Added tCKvar, added notes 4 and 5. (jitter parameter)
11 11 Add to ZQ, QVLD, DQ, QK that the output impedance of QVLD, DQ, and QKx is controlled via ZQ
20,21,25 20,21,25 Comment that states each RD/WR is a row access, wait tRC before next RD/WR to same bank.
32 32 added: (8k refresh per bank, 64k total refresh cycles each 32ms)
19 19 Idle means all commands complete, no more burst or refresh occuring
54 54 Added power estimates.
5,52 5,52 Remove 1.5v VDDQ option
all all Removed x9 option
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 3 Infineon Technologies
This specification is preliminary and subject to change without notice
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Package and Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.1 Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4.1 Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Programmable Impedance Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Mode Register Set Command (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4 Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Writes (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.1 Write - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.1.1 Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5.1.2 Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5.1.3 Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5.1.4 Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6 Reads (RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.6.1 Read - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.6.1.1 Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.6.1.2 Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.6.2 Read followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.7 On Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.7.2 On Die Termination Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.8 Auto Refresh Command (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3 Operation with multiplexed addresses . . . . . . . . . . . . . . . . . . . . . .31
3.1 Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2 Mode Register Set command in multiplexed address mode . . . . . . . . . . . . 33
3.3 Ball Configuration of RLDRAM in multiplexed address mode . . . . . . . . . . . 34
3.4 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.2 Refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4 IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . . . . . .40
4.0.1 Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.0.2 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.0.3 Test Data-In (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.0.4 Test Data-Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.0.5 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.0.6 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.0.7 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.0.8 Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1 TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2 Boundary Scan Exit Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.1 x18 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.2 x36 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3 TAP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4 JTAG AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
5.1 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 4 Infineon Technologies
This specification is preliminary and subject to change without notice
1Overview
1.1 Features
z288 Megabit (288M)
z400MHz DDR operation (800Mb/pin/sec)
zOrganization 8Mx36, 16Mx18 and 32Mx9 in 8 banks
zCyclic bank switching for maximum bandwidth
zReduced row cycle time (20ns at 200/300/400MHz)
zNon multiplexed addresses, address multiplexing optionally available for Burst Length of 4 and 8.
zSRAM type interface
zRead latency, row cycle time and burst sequence length programmable
zBalanced Read and Write latencies to optimise data bus utilisation
zData mask for write commands
zDifferential input clocks (CK, CK#)
z2 pairs of differential write clocks in x36 , 1pair in x18/x9 (DKx, DKx#)
z2 pairs of differential read clocks (QKx, QKx#)
zOn chip DLL to generate CK edge aligned data and data strobe signals.
zData valid signal
z32ms Refresh (8k refresh per bank, 64k total refresh cycles each 32ms)
z144 pin P-TFBGA package
z1.8V, 25 Ohm - 60 Ohm Matched Impedance IO
zIEEE 1149.1 compliant JTAG boundary scan interface
z1.8V VDDQ IO voltage
z1.8V VDD, 2.5V VEXT core voltages
zOn-die termination RTT
z0.11µm technology
Table 1
Key timing parameters (Configuration Example x36, x18 device)
Speed Sort -2.5 -3.3 -5.0 Units
Frequency 400 300 200 MHz
tRC
20 20 20 ns
864cycles
Read latency 8 6 4 cyles
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 5 Infineon Technologies
This specification is preliminary and subject to change without notice
1.2 General Description
The Infineon 288 Mbit DDR Reduced Latency DRAM is a high speed memory device, designed for high
bandwidth communication data storages like transmit or receive buffers in telecommunication systems as
well as data or instruction cache applications requiring large amounts of memory. The chip’s 8 bank
architecture is optimized for high speed and achieves a peak bandwidth of 3.2 GBytes/s using a 36 bit
interface and a maximum system clock of 400 MHz.
The double data rate (DDR) interface transfers 36, or 18 wide data words per clock edge at the I/O pins. An
on chip DLL aligns the output data with the incoming clock (CK).
Commands, addresses and control signals are registered at every positive edge of the differential input
clock, while input data are registered at both, positive and negative edge, of one (x18) or two (x36) separate
differential write clocks.
Read and write accesses to the RLDRAM are burst oriented. The burst length is programmable to 2, 4 and
8 (BL=8 is available on x18 device only) by setting the mode register.
The device is supplied with 2.5V and 1.8V for the core and 1.8V for the output drivers.
Bank scheduled refresh is supported whereby the row address will be generated internally.
A standard P-TFBGA 144-ball package is used which enables ultra high speed data transfer rates and a
simple upgrade path from former products.
The chip is fabricated in Infineon advanced 0.11µm process technology.
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 6 Infineon Technologies
This specification is preliminary and subject to change without notice
1.3 Package and Ball Assignment
Figure 1 P-TFBGA 144 package
Note: 1. All dimensions in millimeters.
3
BOTTOM VIEW
4
0.8
8.8
11
17
18.5
1
12 11 10 9 8 7 654 21
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
Ø 0.51 typ
1.20 max
SIDE VIEW
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 7 Infineon Technologies
This specification is preliminary and subject to change without notice
Figure 2 8M x 36 Ball assignment (Top view) 144 P-TFBGA package
Note: 1. Reserved for future use. May optionaly be connected to GND for improved heat dissipation.
Note: 2. Reserved for future use. This signal has parasitic characteristics of an address input. May optionaly be connected to GND
for improved heat dissipation.
VREF VEXT
VDD
VSSVSS
DQ10
DQ9 VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
DQ12
DQ11VTT
(A22)
DQ17
(A21)
DQ13
DQ15DQ14
DQ16A5
VDD
VSS
VDD
VSS
VDD
VSSQ
VDDQ
A8 A6 A7
B2 A9 VSS
DK0 DK0# VDD
DK1 DK1# VDDVDD
REF# CS# VSS
A18
A16 A17
A15
WE#
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
VTT
ZQVREF
VSSQ
VSS
VDDQ
VSSQ
DQ18VDD
VEXT
DQ19
DQ20 DQ21
DQ26
DQ22
DQ24
DQ23
DQ25
VSS VEXT
VDD
TCK
VSS
DQ1 DQ0VSSQ
VTTVDDQ DQ2
VSSQ
DQ3
DQ8
TMS
DQ5VDDQ DQ4
VSSQ DQ7 DQ6
A0A1A2VDD
VSS VSS A4 A3
VDD VDD B0 CK
VDD VDD B1 CK#
VSSVSS A14 A13
VDD A12 A11 A10
VSSQ
DQ33VDDQ
VSSQ
VSS
VDDQ
VSSQ
VEXT
VDD
TDITDO
VSS
VTT
DQ32
DQ34
DQ30
DQ28
DQ27
DQ29
DQ35
DQ31
DM
1234 910111256 7 8
(A19)
QK1 QK1#
QVLD
(A20)
QK0QK0#
1
1 2
2
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 8 Infineon Technologies
This specification is preliminary and subject to change without notice
Figure 3 16M x 18 Ball assignment (Top view) 144 P-TFBGA package
Note: 1. Reserved for future use. May optionaly be connected to GND for improved heat dissipation.
Note: 2. Reserved for future use. This signal has parasitic characteristics of an address input. May optionaly be connected to GND
for improved heat dissipation.
Note: 3. Do not connect. This signal has parasitic characteristics of a clock input
Note: 4. Do not use. This signal has parasitics characteristics of an IO. May optionaly be connected to GND for improved heat
dissipation.
VREF VEXT
VDD
VSSVSS
DNU
DQ4 VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
DNU
DQ5VTT
(A22)
DQ8
(A21)
DQ6
DQ7DNU
DNUA5
VDD
VSS
VDD
VSS
VDD
VSSQ
VDDQ
A8 A6 A7
B2 A9 VSS
DK DK#
VDD
VDDVDD
REF# CS# VSS
A18
A16 A17
A15
WE#
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
VTT
ZQVREF
VSSQ
VSS
VDDQ
VSSQ
DNUVDD
VEXT
DQ17
DNU DQ16
DNU
DNU
DNU
DQ15
DQ14
VSS VEXT
VDD
TCK
VSS
DQ0 DNUVSSQ
VTTVDDQ DNU
VSSQ
DQ1
DNU
TMS
DQ2VDDQ DNU
VSSQ DQ3 DNU
A0A1A2VDD
VSS VSS A4 A3
VDD VDD B0 CK
VDD VDD B1 CK#
VSSVSS A14 A13
VDD A12 A11 A10
VSSQ
DQ10VDDQ
VSSQ
VSS
VDDQ
VSSQ
VEXT
VDD
TDITDO
VSS
VTT
DNU
DNU
DNU
DNU
DQ13
DQ12
DQ9
DQ11
DM
1234 91011125678
A19
QK1 QK1#
QVLD
(A20)
QK0QK0#
1
12
NC
3
NC
3
4
4
4
4
4
4
4
4
4 4
4
4
4
4
4
4
4
4
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 9 Infineon Technologies
This specification is preliminary and subject to change without notice
1.3.1 Ball Description
Table 2 Ball description
Ball Type Detailed Function
CK, CK# Input Input Clock: CK and CK# are differential clock inputs. Addresses and commands are
latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
CS# Input
Chip Select: CS# enables the command decoder when low and disables it when high.
When the command decoder is disabled new commands are ignored, but internal
operations continue.
WE#, REF# Input Command Inputs: Sampled at the positive edge of CK, WE# and REF# define (together
with CS#) the command to be executed.
A[0:20] Input
Address Inputs: A<0:20> define the row and column addresses for READ and WRITE
operations. During an MODE REGISTER SET the address inputs define the register
settings. They are sampled at the rising edge of CK. In the x36 configuration A[20:19] are
reserved for address expansion. In the x18 configuration A[20] is reserved for address
expansion. These expansion addresses can be treated as address inputs but do not affect
the operation of the device.
A[21:22] - Reserved. Do not use.
BA[0:2] Input Bank Address Inputs: Select to which internal bank a command is being applied.
DQ0-DQ35 I/O
Data Input/Output: The DQ signals form the 36 bit data bus. During READ commands the
data is referenced to both edges of QKx. During WRITE commands the data is sampled at
both edges of DKx. DQ output impedance is controlled by ZQ.
QKx,QKx# Output
Output Data Clock: QKx and QKx# are the differential output data clocks. During READs
they are transmitted by the RLDRAM and edge-aligned with data. QKx# is ideally 180° out
of phase with QKx. QKx output impedance is controlled by ZQ.
DKx,DKx# Input
Input Data Clock: DKx and DKx# are the differential input data clocks. All input data is
referenced to both edges of DKx and is center aligned with these edges. DKx# is ideally
180° out of phase with DKx. For the x36 device, DQ0-DQ17 are referenced to DK0 and
DK0# and DQ18-DQ35 are referenced to DK1 and DK1#. For the x18 devices, all the DQs
are referenced to DK and DK#.
DM Input
Input Data Mask: The DM signal is the input mask signal for WRITE data. Input data is
masked when DM is sampled HIGH along with the WRITE input data. DM is sampled on
both edges of DK. For the x36 device, DM is referenced to DK1 and DK1#. For the x18
devices, DM is referenced to DK and DK#.
QVLD Output Data Valid: The QVLD indicates valid output data. QVLD is edge-aligned with QK0, QK0#.
QVLD output impedance is controlled by ZQ.
TCK Input IEEE 1149.1 Clock Input: JEDEC-standard 1.x V I/O levels. This pin must be tied to VSS
if the JTAG function is not used in the circuit.
TMS
TDI Input IEEE 1149.1 Test Input: JEDEC-standard 1.x V I/O levels. These pins may be left Not
Connected if the JTAG function is not used in the circuit.
TDO Output IEEE 1149.1 Test Output: JEDEC-standard 1.x V I/O levels.
ZQ I/O
External Impedance: This signal is used to tune the device outputs (DQ, QVLD, QK, QK#)
to the system data bus impedance. Output impedance is set to 0.2 x RQ, where RQ is a
resistor from the signal to ground. Refer to the Mode Register Bitmap to activate this
function.
If the MRS mode is set to "Internal resistor", then the ZQ pin may be connected to GND,
then minimum output impedance is set.
If the MRS mode is set to "External resistor" and no resistor is connected, then the
maximum output impedance will be set.
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 10 Infineon Technologies
This specification is preliminary and subject to change without notice
VREF Input Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input
buffers.
VEXT Supply Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions
for range. (section 5 on page 48)
VDD Supply Power Supply: 1.8V nominal.See DC Electrical Characteristics and Operating Conditions
for range. (section 5 on page 48 )
VDDQ Supply Power Supply: Isolated Ouput Buffer Supply. Nominally 1.8V. See DC Electrical
Characteristics and Operating Conditions for range.
VSS Supply Power Supply: GND
VSSQ Supply Power Supply: Isolated Output Buffer Supply. GND
VTT Supply Power Supply: Isolated Termination Supply. Nominally VDDQ/2. See DC Electrical
Characteristics and Operating Conditions for range.
NC - No Connect.
DNU - Do Not Use. May optionaly be connected to GND for improved heat dissipation.
Table 2 Ball description
Ball Type Detailed Function
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 11 Infineon Technologies
This specification is preliminary and subject to change without notice
1.4 Functional Block Diagram
Figure 4 Functional Block Diagram
A0-A20, B0, B1, B2
Column Address
Counter Column Address Buffer Row Address Buffer Refresh Counter
Input Buffers
Row Decoder
Memory Array
Bank 0
Sense Amp and Data Bus
Column Decoder
Row Decoder
Memory Array
Bank 1
Sense Amp and Data Bus
Column Decoder
Row Decoder
Memory Array
Bank 2
Sense Amp and Data Bus
Column Decoder
Row Decoder
Memory Array
Bank 3
Sense Amp and Data Bus
Column Decoder
Row Decoder
Memory Array
Bank 7
Sense Amp and Data Bus
Column Decoder
Row Decoder
Memory Array
Bank 6
Sense Amp and Data Bus
Column Decoder
Row Decoder
Memory Array
Bank 5
Sense Amp and Data Bus
Column Decoder
Row Decoder
Memory Array
Bank 4
Sense Amp and Data Bus
Column Decoder
Output BuffersOutput Data ClockOutput Data Valid Control Logic and Timing Generators
QVLD QK[1:0], QK#[1:0] DQ0-DQ35
CK
CK#
DK [1:0]
DK# [1:0]
WE#
CS#
REF#
DM
VREF
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 12 Infineon Technologies
This specification is preliminary and subject to change without notice
1.5 Commands
1.5.1 Command Table
According to the functional signal description, the following command sequences are possible. All input
states or sequences not shown are illegal or reserved. All command and address inputs must meet setup
and hold times around the rising edge of CK.
Table 3 Command Overview
Note: 1: X represents “Don’t Care”, H represents a logic HIGH, L represents a logic LOW, A represents a Valid Address, BA represents
a Valid Bank Address
Note: 2: Only A[17:0] are used for the MRS command.
Note: 3: See table Table 4
Note: 4: When the chip is deselected, no commands are accepted from outside, but internally NOP commands are generated.
Table 4 Address Widths at Different Burst Lengths
Operation Code CS# WE# REF# A<20:0> BA<2:0> Note
Device Deselect / No Operation DESEL / NOP H X X X X 4
Mode Register Set MRS L L L OPCODE X 2
Read READ L H H A BA 3
Write WRITE L L H A BA 3
Auto Refresh AREF L H L X BA
Data Width
Burst Length 36 18
BL 2 18:0 19:0
BL 4 17:0 18:0
BL 8 N.A 17:0
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 13 Infineon Technologies
This specification is preliminary and subject to change without notice
1.5.2 Description of Commands
Table 5 Description of Commands
Note: 1: Actual refresh is 32ms/8K/8 = 0.488 µs.
Note: 2: Actual refresh is 32ms/8K = 3.90 µs.
Command Description
DESEL /
NOP
The NOP command is used to perform a no operation to the RLDRAM, this is equal to deselecting the
chip. Use NOP command to prevent unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected. Output values depend on command history.
MRS
The Mode Register is set via the address inputs A[17:0]. See the mode register description in the
register description section. The MRS command can only be issued when all banks are idle and no
bursts are in progress.
READ The READ command is used to initiate a burst read access to a bank. The value on the BA[2:0] inputs
selects the bank, and the address provided on inputs A[20:0] selects the data location within the bank.
WRITE
The WRITE command is used to initiate a burst write access to a bank. The value on the BA[2:0]
inputs selects the bank, and the address provided on inputs A[20:0] selects the data location within
the bank. Input data appearing on the DQs is written to the memory array subject to the DM input logic
level appearing coincident with the data. If the DM signal is registered LOW, the corresponding data
will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be
ignored ie. this part of the data word will not be written.
AREF
The AREF is used during normal operation of the RLDRAM to refresh the memory content of a bank.
The command is non persistent, so it must be issued each time a refresh is required. The value on
the BA[2:0] inputs selects the bank. The refresh address is generated by the internal refresh controller.
This makes the address bits “Don’t Care” during an AREF command. The RLDRAM requires 64k
cycles at an average periodic interval of 0.49µs1 (maximum). To improve efficiency a burst of eight
AREF commands (One AREF for each bank) can be posted to the RLDRAM at an average periodic
interval of 3.9µs2.
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 14 Infineon Technologies
This specification is preliminary and subject to change without notice
2 Functional Description
2.1 Clocks, Commands and Addresses
Figure 5 Clock/Write clock Command/Address Timings
Table 6 General Timing Parameters for -2.5, -3.3 and -5.0 ns speed sorts
Note: 1. All timings are measured relatively to the crossing point of CK/CK#, and to the crossing point with VREF of the Command and
Address signals.
Note: 2. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; The input
reference level for signals other than CK/CK# is VREF.
Note: 3. The signal input slew rate must be ≥ 2V/ns.
Note: 4. The clock phase jitter of +/- tCKvar is the maximum variance the clock cycle can have from the expected or ideal clock.
Note: 5. Cycle to Cycle maximum jitter is +/-tCKvar, the change in cycle time from one clock cycle to the next can not differ greater
than tCKvar from the previous cycle.
Parameter Symbol
-2.5 -3.3 -5.0
Units Notes
min max min max min max
Clock
Clock Cycle Time tCK 2.5 5.7 3.3 5.7 5.0 5.7 ns
Clock Jitter tCKvar -0.05 0.05 -0.05 0.05 -0.05 0.05 tCK 4,5
System frequency fCK 175 400 175 300 175 200 MHz
Clock HIGH time tCKH, tDKH 0.45 0.55 0.45 0.55 0.45 0.55 tCK
Clock LOW time tCKL, tDKL 0.45 0.55 0.45 0.55 0.45 0.55 tCK
Clock to Write Clock tCKDK -0.3 0.3 -0.3 0.3 -0.3 0.3 ns
Setup Times
Address and Command input setup time tAS, tCS 0.4 0.5 0.8 ns
Hold Times
Address and Command input hold time tAH, tCH 0.4 –0.5–0.8– ns
Don't Care
CK#
CK
t
CKH
t
CKL
t
AS
,t
CS
t
CK
CMD,
ADDR
t
DKH
t
DKL
t
CK
ValidValid Valid
DKx#
DKx
t
CKDK
t
CKDK
t
AH
,t
CH
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 15 Infineon Technologies
This specification is preliminary and subject to change without notice
2.2 Initialization
The RLDRAM must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation or permanent damage to the device.
The following sequence is used for Power-Up:
1. Apply power (VEXT, VDD, VDDQ, VTT, VREF) and start clock as soon as the supply voltages are stable.
Apply VDD and VEXT before or at the same time as VDDQ, apply VDDQ before or at the same time as
VREF and VTT. There is no timing relation between VEXT and VDD, the chip starts the power up
sequence only when both voltages are at their nominal level. However, the pad supply must not be applied
before the core supplies. Maintain all pins in NOP conditions.
2. Maintain stable conditions for 200 µs (minimum).
3. Issue three Mode Register Set commands - 2 dummies plus 1 valid MRS. (Figure 6)
4. After tMRSC issue 8 Auto Refresh commands, one on each bank and separated by 2048 cycles.Initial
bank refresh order does not matter.
5. After tRC the chip is ready for normal operation.
Figure 6 Power Up Sequence
Don't Care
MRS: MRS command
A.C.: Any command
RF: REFRESH
CK
MRS
t
MRSC
MRSMRS
min. 200 µs
Com
VDD
VDDQ
VTT
CK#
VEXT
min. 2048
cycles
RF A.C.RF RF
6 x 2048
cycles
t
RC
VREF
Add BA0 BA1 BA7
min.
1 cycle
min.
1 cycle
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 16 Infineon Technologies
This specification is preliminary and subject to change without notice
2.3 Programmable Impedance Output Buffer
The RLDRAM is equipped with programmable impedance output buffers. This allows a user to match the
driver impedance to the system data bus impedance. To adjust the impedance, an external precision
resitance (RQ) is connected between the ZQ pin and VSS. The value of the resistor must be five times the
desired impedance. For example, a 250Ω resitor is required for an output impedance of 50Ω. To ensure that
the output impedance is one fifth of the value of RQ (within 15 percent), the range of RQ is 125Ω to 300Ω.
Output impedance updates may be required because, over time, variations may occur in supply voltage and
temperature. The device samples the value of RQ. The impedance update is transparent to the system.
Impedance updates do not affect the device operation, and all data sheet timing and current specifications
are met during an update.
Table 7 Driver Strength of Output Buffers
Ball Description Driver Strength
DQ0 .. DQ35, QK, QK#, QVLD Adjustable ( MRS / External RES)
TDO CMOS
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 17 Infineon Technologies
This specification is preliminary and subject to change without notice
2.4 Mode Register Set Command (MRS)
The mode register stores the data for controlling the operating modes of
the memory. It programs the RLDRAM configuration, burst length, test
mode and IO options. During a Mode Register Set command the address
inputs A<17:0> are sampled and stored in the mode register. tMRSC
must be met before any command can be issued to the RLDRAM. The
Mode Register content can only be set or changed when the RLDRAM is
in idle state, all commands must be completed, no persistent commands.
Figure 8 Mode Register Set Timing
Table 8 Timing Parameters MRS for -2.5, -3.3 and -5.0 ns speed sorts
Figure 9 Mode Register Bitmap
Parameter Symbol
-2.5 -3.3 -5.0
Units Notes
min max min max min max
Mode Register Set timing tMRSC 12 – 12 – 12 – tCK
CK#
CK
WE#
REF#
A<17:0>
Don't Care
COD: Code to be loaded into
the register
CS#
COD
A<20:18>
BA<2:0>
Figure 7
Mode Register Set
CK#
CK
Don't Care
t
MRSC
Command
MRS: MRS
command
A.C.: Any command
MRS NOP A.C.NOP
Configuration
A2
A4A5A10 A3
Unused Burst Length
Address
Mux
Test ModeReserved
1
A1 A0
1
Bits A<17:11> MUST be set to zero
A6A7
A3
0
1
BL
2 (default)
4
A4
0
1
8
not valid
0
0
1
1
A<17:11>
On-die
Termination
A9
Calibration
A8
RLDRAM
configuration
A2 A1 A0
reserved110
100
reserved101
3011
1001
2010
1 (default)000
reserved111
DLL Reset
A8
1
0
Resistor
external
internal (50
Ω
)
(default)
A10
0
1
Test Mode
default
test mode
A7
0
1
DLL Reset
Reset (default)
Enable
reserved
Termination
A9
0
1
Disabled (default)
Enabled
Addresss MuxA5
0
1
non-multiplexed
(default)
address multiplexed
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 18 Infineon Technologies
This specification is preliminary and subject to change without notice
2.5 Configuration Table
The following table shows, for different operating frequencies, the different RLDRAM configurations that can
be programmed into the Mode Register. The Row Cycle time (tRC), the Read Latency (tRL) and the Write
Latency (tWL) are shown in clock cycles as well as in nanoseconds. Each WR and RD command is a page
access which requires a wait of tRC between the next WR or RD to the same bank.
The shaded areas correspond to configurations that are not allowed.
Table 9 RLDRAM Configuration table
Note: BL=8 is not available in configuration 1
Configuration
Frequency Parameter 1* 23Unit
tRC 4 6 8 cycles
tRL 4 6 8 cycles
tWL 5 7 9 cycles
400MHz (-2.5) tRC 20 ns
tRL 20 ns
tWL 22.5 ns
300MHz (-3.3) tRC 20 26.7 ns
tRL 20 26.7 ns
tWL 23.3 30 ns
200MHz (-5.0) tRC 20 30 40 ns
tRL 20 30 40 ns
tWL 25 35 45 ns
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 19 Infineon Technologies
This specification is preliminary and subject to change without notice
2.6 Writes (WR)
2.6.1 Write - Basic Information
Write accesses are initiated with a WR command, as shown in Figure
10. Row and bank addresses are provided together with the WR
command. Each WR command is a page access which requires a wait
of tRC between the next WR or RD to the same bank.
During WR commands, data will be registered at both edges of DK
according to the programmed burst length BL. There is a write latency
WL which is equal to the programmed read latency RL+1. The first valid
data is registered with the first rising DK edge WL cycles after the
WRITE command.
Any WRITE burst may be followed by a subsequent READ command.
Figure 14 shows the timing requirements for a WRITE followed by a
READ.
Setup and hold time for incoming DQs relative to the DK edges are
specified as tDS and tDH. The input data is masked if the
corresponding DM signal is high, setup and hold times for data mask is
also tDS and tDH.
Figure 11 Basic Write Burst / DM Timing
CK#
CK
BA<2:0>
A
BA
A: Address
BA: Bank Address
Don't Care
CS#
WE#
REF#
A<20:0>
Figure 10
Write command
DQ
DM
Don't Care
Data masked Data masked
D0 D1 D2 D3
CK#
CK
Write Latency
t
DH
t
DS
DKx#
DKx
t
CKDK
t
DH
t
DS
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 20 Infineon Technologies
This specification is preliminary and subject to change without notice
Table 10 WRITE Timing Parameters for -2.5, -3.3 and -5.0 speed sorts
Note: 1. All timings are measured relatively to the crossing point of CK/CK#, DK/DK# and to the crossing point with VREF of the
Command, Address and data signals.
Note: 2. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross
Note: 3. The DK/DK# input reference level (for timing referenced to DK/DK#) is the point at which DK and DK# cross
Note: 4. The input reference level for signals other than CK/CK# , DK/DK# is VREF.
Note: 5. The signal input slew rate must be ≥ 2V/ns.
Parameter Symbol
-2.5 -3.3 -5.0
Units
min max min max min max
Data-in to DK Setup Time tDS 0.25–0.3–0.4– ns
Data-in to DK Hold Time tDH 0.25–0.3–0.4– ns
Clock to Write Clock Time tCKDK -0.30 0.30 -0.30 0.30 -0.30 0.30 ns
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 21 Infineon Technologies
This specification is preliminary and subject to change without notice
2.6.2 Write - Cyclic Bank Access
2.6.2.1 Burst Length (BL) = 2
Figure 12 Write Burst Basic Sequence, BL = 2, RL = 4, WL = 5
2.6.2.2 Burst Length (BL) = 4
Figure 13 Write Burst Basic Sequence, BL = 4, RL = 4, WL = 5
CK#
C
K
Com
.
012345678
Addr.
WL = 5
DQ D0a D0dD1aD0b D1b D2a D2b D3a D3b
WR
A
BA0
A
BA1
A
BA2
A
BA3
A
BA0
A
BA4
A
BA5
A
BA6
A
BA7
WR WR WR WR WR WR WR WR
Don't Care
WR: WRITE
Dxy: Data y to bank x
A/BAx: address A of bank x
WL: Write Latency
DKx#
DKx
RC = 4
RC: Row cycle time
CK#
CK
Com
.
012345678
Addr.
WL = 5
DQ D0a D0dD0cD0b D0d D1a D1b D1c D1d
WR
A
BA0
A
BA1
NOP WR WR WR WRNOP NOP NOP
A
BA2
A
BA0
A
BA0
Don't Care
WR: WRITE
Dxy: Data y to bank x
A / BAx: address A of bank x
WL: Write Latency
DKx#
DKx
RC = 4
RC: Row Cycle time
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 22 Infineon Technologies
This specification is preliminary and subject to change without notice
2.6.3 Write followed by Read
2.6.3.3 Burst Length (BL) = 2
Figure 14 Write followed by Read BL = 2, RL = 4, WL = 5
2.6.3.4 Burst Length (BL) = 4
Figure 15 Write followed by Read BL = 4, RL = 4, WL = 5
Com
.
Addr.
WL = 5
Q1a Q2bQ2aQ1bD0a D0b
RL = 4
Don't Care
WR: WRITE
Dxy: Data y to bank x
A/BAx: address A of bank x
WL: Write Latency
RD: READ
RL: Read Latency
Qxy: Data y to bank x
DQ
0123456789
WR NOP RD NOP NOP NOPRD NOP NOPNOP
A
BA0
A
BA1
A
BA2
QKx
QKx#
CK#
CK
DKx#
DKx
Com.
Addr.
D0a
RL = 4
Don't Care
WR: WRITE
Dxy: Data y to bank x
A/BAx: address A of bank x
WL: Write Latency
RD: READ
RL: Read Latency
Qxy: Data y to bank x
D0b D0c D0dDQ
012345678
WL = 5
9
WR NOP RDNOP NOP NOPRD NOP NOPNOP
A
BA0
A
BA1
A
BA2
QKx
QKx#
CK#
CK
DKx#
DKx
Q1a Q1b Q1c Q1d Q2a
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 23 Infineon Technologies
This specification is preliminary and subject to change without notice
2.7 Reads (RD)
2.7.1 Read - Basic Information
Read accesses are initiated with a RD command, as shown in Figure
16. Row and bank addresses are provided with the RD command.
Each RD command is a page access which requires a wait of tRC
between the next WR or RD to the same bank.
During READ bursts the memory device drives the read data edge
aligned with the QK clock. After a programmable read latency, data is
available at the outputs. The data valid signal indicates that data will be
present on the bus after 0.5 clock cycles.
The skew between QK and CK is specified as tCKQK.
tQKQ0 is the skew between QK0 and the last (tQKQ0max) or first
(tQKQ0min) valid data edge considered over all the data generated at
DQ0-DQ17 (x36) or at DQ0-DQ8 (x18). tQKQ1 is the skew between
QK1 and the last (tQKQ1max) or first (tQKQ1min) valid data edge
considered over all the data generated at DQ18-DQ35 (x36) or at
DQ9-DQ17 (x18). tQKQx is derived at each QKx clock edge and is not
cumulative over time.
tQKQ is the maximum skew between one of the QKx and the last
(tQKQmax) or first (tQKQmin) valid data edge considered over all the
data generated at the DQ balls. All the data pins are valid after
tQKQmax from the current QKx clock until tQKQmin before the next
QKx clock edge.
After completion of a burst, assuming no other commands have been
initiated, output data (DQ) will go High-Z. Back to back RD commands
are possible, producing a continuous flow of output data.
The data valid window is derived from each QK transistion and is
defined as : min( tQKH, tQKL) - 2* tQKQmax.
Any READ burst may be followed by a subsequent WRITE command. Figure 20 shows the corresponding
timing requirements. A READ to WRITE delay has to be built in in order to prevent bus contention. Some
systems having long line lengths or severe skews may need additional idle cycles inserted.
CK#
CK
WE#
CS#
REF#
BA<2:0>
A
BA
A: Address
BA: Bank Address
Don't Care
A<20:0>
Figure 16
READ command
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 24 Infineon Technologies
This specification is preliminary and subject to change without notice
Figure 17 Basic Read Burst Timing
Table 11 READ Timing Parameters for -2.5, -3-3 and -5.0 speed sorts
Note: 1. All timings are measured relatively to the crossing point of CK/CK# (QK/QK#), and to the crossing point with VREF of the
Command and Address signals.
Note: 2. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; The input
reference level for signals other than CK/CK# is VREF.
Note: 3. The signal input slew rate must be ≥ 2V/ns.
Note: 4. tQKQ0 is referenced to DQ0-DQ17 in x36 and to DQ0-DQ8 in x18.
tQKQ1 is referenced to DQ18-DQ35 in x36 and to DQ9-DQ17 in x18.
Note: 5. tQKQ takes into account the skew between any QKx and any DQ.
Parameter Symbol Conf
-2.5 -3.3 -5.0
Units Note
min max min max min max
Output Data Clock High Time tQKH 0.9 1.1 0.9 1.1 0.9 1.1 tCKH
Output Data Clock Low Time tQKL 0.9 1.1 0.9 1.1 0.9 1.1 tCKL
Clock to Output Data Clock tCKQK -0.25 0.25 -0.3 0.3 -0.5 0.5 ns
QK edge to Output Data edge tQKQ0,
tQKQ1
x18
-0.2 0.2 -0.25 0.25 -0.3 0.3 ns 4
x36
QK edge to Output Data edge tQKQ
x9
-0.3 0.3 -0.35 0.35 -0.4 0.4 ns 5x18
x36
QK edge to QVLD edge tQKVLD -0.3 0.3 -0.35 0.35 -0.4 0.4 ns
D0 D1 D2 D3
t
CKQK
t
CK
t
QKVLD
t
QKVLD
Don't Care
t
QKQ
data valid
window
QKx
CK#
CK
QKx#
QVLD
DQ
t
CKH
t
CKL
t
QKH
t
QKL
t
QKQ
t
QKQ
t
QKQ
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 25 Infineon Technologies
This specification is preliminary and subject to change without notice
2.7.2 Read - Cyclic Bank Access
2.7.2.1 Burst Length (BL) = 2
Figure 18 Read Burst, BL = 2, RL = 4
2.7.2.2 Burst Length (BL) = 4
Figure 19 Read Burst, BL = 4, RL = 4
CK#
CK
Com
.
012345678
Addr.
RL = 4
QKx
QKx#
DQ
RD
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA5
A
BA6
A
BA7
A
BA0
RD RD RD RD RD RD RD RD
Don't Care
A / BAx: address A of bank x
RD: READ
Qxy: Data y to bank x
RL: Read Latency
Q0a Q1aQ0b Q1b Q2a Q2b Q3a Q3b Q4a
QVLD
CK#
CK
Com
.
012345678
Addr.
RC = RL = 4
QKx
QKx#
DQ
RD RD RD RD RDNOP NOP NOP NOP
A
BA0
A
BA1
A
BA2
A
BA3
A
BA0
Q0a Q0cQ0b Q0d Q1a Q1b Q1c Q1d Q0a
Don't Care
A / BAx: address A of bank x
RD: READ
Qxy: Data part y from bank x
RL: Read Latency
RC: Row Cycle time
QVLD
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 26 Infineon Technologies
This specification is preliminary and subject to change without notice
2.7.3 Read followed by Write
Figure 20 Read followed by Write, BL=2, RL = 4, WL = 5
Figure 21 Read followed by Write, BL=4, RL = 4, WL = 5
Com
.
Addr.
RL = 4
DQ D1a D2bD2aD1bQ0a Q0b
QKx
Don't Care
WR: WRITE
Dxy: Data y to bank x
A/BAx: address A of bank x
WL: Write Latency
RD: READ
Qxy: Data y from bank x
RL: Read Latency
CK#
CK
01234567
WL = 5
WR NOPRD NOP NOP NOPNOPWR
A
BA0
A
BA1
A
BA2
QKx#
DKx
DKx#
Com.
Addr.
RL = 4
DQ D1a D1dD1cD1b
QKx
WL = 5
Don't Care
WR: WRITE
Dxy: Data y to bank x
A/BAx: address A of bank x
WL: Write Latency
RD: READ
Qxy: Data y from bank x
RL: Read Latency
Q0a
Q0dQ0c
Q0b
01234567
NOPRD NOP NOP NOPNOPWR
A
BA0
A
BA1
NOP
QKx#
NOP
CK#
CK
DKx#
DKx
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 27 Infineon Technologies
This specification is preliminary and subject to change without notice
2.8 On Die Termination
2.8.1 Description
On Die Termination is enabled by setting A9 to one during a Mode Register Set (MRS) command. With On
Die Termination on, all the DQs as well as DM are terminated to VTT with a resistance RTT. The Commands,
Addresses and clock signals are not terminated. Figure 22 shows the equivalent circuit of a DQ receiver with
On Die Termination. The On Die Terminations are dynamically switched off during Read commands.
Figure 22 On Die Termination Equivalent Circuit
Table 12 Activation of On Die Termination
Table 13 On Die Termination DC Parameters
Note: 1. All voltages referenced to VSS (GND)
Note: 2. The RTT value is measured at 70°C
Ball Description (Input) Termination Activation Type
CK, CK# , DK0, DK0#, DK1, DK1# No
CS#, WE#, REF#, A[0:20], BA[0:2], DM No
DQ0 .. DQ35 Yes Desactivated for READs
TCK No
ZQ No
Description Conditions Symbol Min. Max. Unit Notes
Termination Voltage VTT 0.95 * VREF 1.05 * VREF V1
On-die Termination RTT 135 165 Ω2
VTT
RTT
sw
Receiver
DQ
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 28 Infineon Technologies
This specification is preliminary and subject to change without notice
2.8.2 On Die Termination Timing
During a Read command, the On Die Termination is switched off at the same time the data appears on the
DQ bus and switched on again after the last data has been issued. The switching is conincident with the
falling edge of QKx.
Figure 23 Read Burst with ODT , BL=2
Note: It is ensured by design that the ODT is switched off prior the DQs are activated and on after the last data has been issued.
Figure 24 Read NOP Read with ODT, BL=2
Note: It is ensured by design that the ODT is switched off prior the DQs are activated and on after the last data has been issued.
CK#
CK
Com
.
012345678
Addr.
RL = 4
QKx
QKx#
DQ
RD
A
BA0
A
BA1
A
BA2
RD RD
A / BAx: address A of bank x
RD: READ
Qxy: Data y to bank x
RL: Read Latency
Q0a Q1aQ0b Q1b Q2a
QVLD
Q2b
ODT ODT ON ODT ONODT OFF
NOP NOP NOP NOP NOP NOP
Don't Care
Termination Switching
CK#
CK
Com
.
012345678
Addr.
RL = 4
QKx
QKx#
DQ
RD
A
BA0
A
BA2
RD
A / BAx: address A of bank x
RD: READ
Qxy: Data y to bank x
RL: Read Latency
Q0a
QVLD
Q2b
ODT ODT ON ODT ON
NOP NOP NOP NOP NOP NOP NOP
Q0b Q2a
ODT OFFODT OFF
Don't Care
Termination Switching
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 29 Infineon Technologies
This specification is preliminary and subject to change without notice
Figure 25 Read followed by Write with ODT, BL=2
Note: It is ensured by design that the ODT is switched off prior the DQs are activated and on after the last data has been issued.
Figure 26 Write followed by Read with ODT, BL=2
Note: It is ensured by design that the ODT is switched off prior the DQs are activated and on after the last data has been issued.
Com
.
Addr.
RL = 4
DQ D1a D2bD2aD1bQ0a Q0b
QKx
CK#
CK
01234567
WL = 5
WR NOPRD NOP NOP NOPNOPWR
A
BA0
A
BA1
A
BA2
QKx#
DKx
DKx#
ODT ODT ON ODT OFF ODT ON
NOP
8
RD: READ
Qxy: Data y from bank x
RL: Read Latency
WR: WRITE
Dxy: Data y to bank x
A/BAx: address A of bank x
WL: Write Latency
Don't Care
Termination Switching
Com
.
Addr.
WL = 5
D0a D0b
RL = 4
DQ
0123456789
WR NOP RDNOP NOP NOPRD NOP NOPNOP
A
BA0
A
BA1
A
BA2
QKx
QKx#
CK#
CK
DKx#
DKx
Q1a Q2bQ2aQ1b
RD: READ
RL: Read Latency
Qxy: Data y to bank x WR: WRITE
Dxy: Data y to bank x
A/BAx: address A of bank x
WL: Write Latency
ODT ODT OFF ODT ONODT ON
NOP
10
Don't Care
Termination Switching
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 30 Infineon Technologies
This specification is preliminary and subject to change without notice
2.9 Auto Refresh Command (AREF)
AREF is used to do a refresh cycle on one row in a specific bank. The
row addresses are generated by an internal refresh counter for each
bank; external address pins are “DON’T CARE”. The delay between
the AREF command and a subsequent command on the same bank
must be at least tRC.
Within a period of tREF=32ms the whole memory has to be refreshed
(8k refresh per bank, 64k total refresh cycles each 32ms). Figure 28
shows an example of a continuous refresh sequence. Other refresh
strategies such as burst refresh are also possible.
Figure 28 Auto Refresh Cycle
CLK#
CLK
WE#
BA: Bank Address
Don't Care
CS#
REF#
A<20:0>
BA<2:0> BA
Figure 27
Auto Refresh Command
CLK#
CLK
t
RC
Command ARFx ACy ACx ACy ARFx ACy
Don't Care
ARFx: Auto Refresh bank x
ACx.: Any Command on bank x
ACy.: Any Command on different bank
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 31 Infineon Technologies
This specification is preliminary and subject to change without notice
3 Operation with multiplexed addresses
3.1 Description
In multiplexed address mode, the address can be provided to the RLDRAM in two parts that are latched into
the memory with two consecutive rising clock edges. This provides the advantage that only 11 addresses
are required to control the RLDRAM, reducing the number of pins on the controller side. The address
mapping is represented in Table 14.
The command is internally executed with the second clock rising edge, when the Ay address part is made
available to the memory. For this reason, the effective Read and Write latencies are increased by 1 clock
cycle in the multiplexed address mode of operation, whereas tRC remains unaffected.
The data bus efficiency in continuous burst mode is not affected for BL4 and BL8 since at least two clocks
are required to read the data out of the memory. The bank addresses are delivered to the RLDRAM at the
same time as the READ or WRITE command and the first address part Ax.
This option is available by setting bit A5 to 1 in the Mode Register. Once this bit set, the READ, WRITE and
MRS commands follow the format described in Figure 29.
An alternative address mapping using a different address ballout and the numbering A[10:0] is available in
a separate application note.
Figure 29: Command description in multiplexed address mode
Note: The minimum setup and hold times of the two address parts are defined tAS and tAH.
BA<2:0>
CK#
CK
WE#
CS#
REF#
Ax
BA
A<20:0> Ay
Read
Ax
BA
Ay
Write
Ax Ay
MRS NOP
Ax, Ay: Address
BA: Bank Address
Don't Care
AREF
BA
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 32 Infineon Technologies
This specification is preliminary and subject to change without notice
3.2 Address mapping
In the address multiplexing mode, the RLDRAM concatenates the addresses Ax and Ay received at the balls
[A0, A3, A4, A5, A8, A9, A10, A13, A14, A17, A18] and builds an internal address a[19..0] that is processed
as if the RLDRAM were in the default mode of operation.
The address mapping is described in table 11 as a function of burst length and data width. The external
addresses Ax are translated to the internal addresses a[19..0] according to the table below.
Table 14 Address mapping in multiplexed address mode
Note: 1. Don’t Care
Note: 2. Reserved for A21 expansion in multiplexed mode
Data Width Burst
Length
Addresses
Add
pin A0 A3 A4 A52A8 A9 A10 A13 A14 A17 A18
x36
BL2 Ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18
Ay a1 a2 a6 a7 a11 a12 a16 a15
BL 4 Ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17
Ay a1 a2 a6 a7 a11 a12 a16 a15
x18
BL2 Ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18
Ay a1 a2 a6 a7 a19 a11 a12 a16 a15
BL 4 Ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18
Ay a1 a2 a6 a7 a11 a12 a16 a15
BL 8 Ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17
Ay a1 a2 a6 a7 a11 a12 a16 a15
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 33 Infineon Technologies
This specification is preliminary and subject to change without notice
3.3 Mode Register Set command in multiplexed address mode
The addresses A0, A3, A4, A5, A8, A9, A10 have to be set as follows in order to activate the Mode Register
in the muxed address mode.
3.4 Power up sequence for multiplexed address mode
The following sequence has to be respected in order to power up the RLDRAM in the multiplexed address
mode.
Figure 30 Power up sequence in multiplexed address mode
Note: 1) Address A5 must be set HIGH (Muxed address mode setting when RLDRAM in normal mode of operation)
Note: 2) Address A5x must be set HIGH (Muxed address mode setting when RLDRAM already in muxed address mode)
Configuration
A4
Unused Burst Length
Address
Mux
Test Mode
A3
All non used bits MUST be set to zero
A8A9
A3x
0
1
BL
2 (default)
4
A4x
0
1
8
not valid
0
0
1
1
On-die
Termination
Calibration
RLDRAM
configuration
A4y A3y A0x
reserved11 0
100
reserved101
3011
1001
2010
1 (default)00 0
reserved111
DLL Reset
A8x
1
0
Resistor
external
internal (50
Ω
)
(default)
A10x
0
1
Test Mode
default
test mode
A9y
0
1
DLL Reset
Reset (default)
Enable
reserved
Termination
A9x
0
1
Disabled (default)
Enabled
Addresss MuxA5x
0
1
non-multiplexed
(default)
address multiplexed
A4A5A10 A3 A0
A9 A8
Ax
Ay
Don't Care
MRS: MRS command
A.C.: Any command
RFx: REFRESH Bank x
CK
MRS
t
MRSC
MRSMRS
min. 200 µs
Com
VDD
VDDQ
VTT
CK#
VEXT
min. 2048
cycles
RF0 A.C.RF1 RF7
6 x 2048
cycles
t
RC
VREF
MRS
Add Ax Ay
t
MRSC
A
1) 2)
min.
1 cycle
min.
1 cycle
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 34 Infineon Technologies
This specification is preliminary and subject to change without notice
3.5 Ball Configuration of RLDRAM in multiplexed address mode
Figure 31 8M x 36 Ball assignment in multiplexed address mode ( Top view) 144 P-TFBGA package
Note: 1. Reserved for future use. May optionaly be connected to GND for improved heat dissipation.
Note: 2. Do not use. This signal has parasitic characteristics of an address input. May optionally be connected to GND in order to
improve heat dissipation.
VREF VEXT
VDD
VSSVSS
DQ10
DQ9 VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
DQ12
DQ11VTT
DNU
DQ17
DNU
DQ13
DQ15DQ14
DQ16A5
VDD
VSS
VDD
VSS
VDD
VSSQ
VDDQ
A8 DNU DNU
B2 A9 VSS
DK0 DK0# VDD
DK1 DK1# VDDVDD
REF# CS# VSS
A18
DNU A17
DNU
WE#
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
VTT
ZQVREF
VSSQ
VSS
VDDQ
VSSQ
DQ18VDD
VEXT
DQ19
DQ20 DQ21
DQ26
DQ22
DQ24
DQ23
DQ25
VSS VEXT
VDD
TCK
VSS
DQ1 DQ0VSSQ
VTTVDDQ DQ2
VSSQ
DQ3
DQ8
TMS
DQ5VDDQ DQ4
VSSQ DQ7 DQ6
A0DNUDNUVDD
VSS VSS A4 A3
VDD VDD B0 CK
VDD VDD B1 CK#
VSSVSS A14 A13
VDD DNU DNU A10
VSSQ
DQ33VDDQ
VSSQ
VSS
VDDQ
VSSQ
VEXT
VDD
TDITDO
VSS
VTT
DQ32
DQ34
DQ30
DQ28
DQ27
DQ29
DQ35
DQ31
DM
1234 910111256 7 8
DNU
QK1 QK1#
QVLD
DNU
QK0QK0#
1
1
2
22
22
2
2
2
22
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 35 Infineon Technologies
This specification is preliminary and subject to change without notice
Figure 32 16M x 18 Ball assignment in multiplexed address mode ( Top view) 144 P-TFBGA package
Note: 1. Reserved for future use. May optionaly be connected to GND for improved heat dissipation.
Note: 2. Do not connect. This signal has parasitic characteristics of a clock input
Note: 3. Do not use This signal has parasitic characteristics of an address input. May optionally be connected to GND in order to
improve heat dissipation.
Note: 4. Do not use This signal has parasitic characteristics of an IO. May optionally be connected to GND in order to improve heat
dissipation.
VREF VEXT
VDD
VSSVSS
DNU
DQ9 VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
DNU
DQ10VTT
DNU
DQ13
DNU
DQ11
DQ12DNU
DNUA5
VDD
VSS
VDD
VSS
VDD
VSSQ
VDDQ
A8 DNU DNU
B2 A9 VSS
DK DK#
VDD
VDDVDD
REF# CS# VSS
A18
DNU A17
DNU
WE#
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
VTT
ZQVREF
VSSQ
VSS
VDDQ
VSSQ
DNUVDD
VEXT
DQ17
DNU DQ16
DNU
DNU
DNU
DQ15
DQ14
VSS VEXT
VDD
TCK
VSS
DQ0 DNUVSSQ
VTTVDDQ DNU
VSSQ
DQ1
DNU
TMS
DQ2VDDQ DNU
VSSQ DQ3 DNU
A0DNUDNUVDD
VSS VSS A4 A3
VDD VDD B0 CK
VDD VDD B1 CK#
VSSVSS A14 A13
VDD DNU DNU A10
VSSQ
DQ5VDDQ
VSSQ
VSS
VDDQ
VSSQ
VEXT
VDD
TDITDO
VSS
VTT
DNU
DNU
DNU
DNU
DQ8
DQ7
DQ4
DQ6
DM
1234 91011125678
DNU
QK1 QK1#
QVLD
DNU
QK0QK0#
1
1
NC
2
NC
2
4
4
4
4
4
33
3
3
4
4
4
4 4
4
4
4
4
4
4
4
4
3
33
33
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 36 Infineon Technologies
This specification is preliminary and subject to change without notice
3.6 Configuration table
In this mode, the Read and Write latencies are increased of one clock cycle. The RLDRAM cycle time
remains the same as described in table 12.
Table 15 RLDRAM Configuration table in multiplexed address mode
Note: 1: BL=8 is not available in configuration 1
Configuration
Frequency Parameter 1123Unit
tRC 4 6 8 cycles
tRL 5 7 9 cycles
tWL 6 8 10 cycles
400MHz tRC 20 ns
tRL 22.5 ns
tWL 25 ns
300MHz tRC 20 26.7 ns
tRL 23.3 30 ns
tWL 26.7 33.3 ns
200MHz tRC 20 30 40 ns
tRL 25 35 45 ns
tWL 30 40 50 ns
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 37 Infineon Technologies
This specification is preliminary and subject to change without notice
3.7 Timing diagrams
3.7.1 Write Command
The basic WRITE timing is identical for the default mode and the multiplexed address mode, except for the
latency. In particular, the DM signal is handled in the same way as in the default mode of operation. Please
refer to chapter 2.6 for more details.
Figure 33 Write burst basic sequence BL4 with multiplexed addresses, config. 1, WL = 6
Figure 34 Write followed by Read with multiplexed addresses, BL=4, RL=5, WL=6
WR NOP WRCom. NOP NOP WR NOP WR
012345678
Addr.
WL = 6
WR
Ax/
BA1
Ax/
BA2
Ax/
BA3
Ax/
BA0
Ax/
BA0 Ay Ay Ay Ay
Don't Care
WR: WRITE
Dik: Data part i to bank k
Ax/BAk: address Ax of bank k
WL: Write Latency
Ay: address Ay of bank k
DQ D0a D0dD0cD0b D0d D1a D1b
CK#
CK
DK#
DK
Com.
Addr.
D0a
RL = 5
D0b D0c D0dDQ
012345678
WL = 6
9
WR RDNOP NOPRD NOPNOP
Ax/
BA1
Ax/
BA2
QKx
QKx#
CK#
CK
DKx#
DKx
Q1a Q1b Q1c
Ay Ay
NOP NOP
Ax/
BA0 Ay
WR: WRITE
Dxy: Data y to bank x
Ax/BAk: address Ax of bank k
WL: Write Latency Don't Care
RD: READ
RL: Read Latency
Qxy: Data y to bank x
Ay: address Ay
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 38 Infineon Technologies
This specification is preliminary and subject to change without notice
3.7.2 Read Command
The basic READ timing is identical for the default mode and the multiplexed address mode, except for the
latency. In particular, the QVLD signal will be generated in the same manner as in the default mode of
operation. Please refer to chapter 2.7 for more details.
Figure 35 Read burst basic sequence BL4 with multiplexed addresses, config. 1, RL = 5
Figure 36 Read followed by Write with multiplexed addresses, BL=4, RL=5, WL=6
Com.
Addr.
RL = 5
DQ
CK#
CK
RD
012345678
Ax/
BA0
Ax/
BA1
Ax/
BA2
Ax/
BA0
RD RD RD
Ax/
BA1
RDNOP NOP NOP NOP
Ay Ay Ay Ay
QKx
QKx#
Q0a Q0cQ0b Q0d Q1a Q1b Q1c
Don't Care
Ax/BAk: address Ax of bank k
RD: READ
Qik: Data part i from bank k
RL: Read Latency
Ay: address Ay
QVLD
Com.
Addr.
RL = 5
DQ D1a D1dD1cD1b
QKx
WL = 6
Q0a
Q0dQ0c
Q0b
01234567
NOPRD NOP NOP NOPNOPWRNOP
QKx#
NOP
CK#
CK
DKx#
DKx
Ax/
BA0
Ax/
BA1 Ay
WR: WRITE
Dxy: Data y to bank x
Ax/BAk: address Ax of bank k
WL: Write Latency Don't Care
RD: READ
RL: Read Latency
Qxy: Data y to bank x
Ay: address Ay
Ay
NOP
89
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 39 Infineon Technologies
This specification is preliminary and subject to change without notice
3.7.3 Refresh command
In the multiplexed address mode the refresh command is, like the other commands, executed on the next
rising clock edge. However, since no second address part is required, the next AREF command can already
be applied. No NOP operation is required either between an AREF command and any other valid command
as represented on Figure 37.
Figure 37 Burst refresh operation
Com.
Addr.
CK#
CK
012345678
AREF
Ay
BAk BA0 BA2 BA4 BA6BA1 BA3 BA5BAdd.
Ax
AREF AREF AREF AREF
BA7
AREF AREF AREF
AC AC
Ay
91011
Don't Care
Ax: First part Ax of address
Ay: Second part Ay of address
BAk: Bank k.
k is chosen so that tRC is met
AREF: Autorefresh
AC : Any command
Ax
BAk
NOP
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 40 Infineon Technologies
This specification is preliminary and subject to change without notice
4 IEEE 1149.1 Serial Boundary Scan (JTAG)
The RLDRAM incorporates a serial boundary scan Test Access Port (TAP). This port operates fully
complient with IEEE Standard 1149.1-1990. It contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID code register.
It is possible to operate the RLDRAM without using the JTAG feature. To disable the TAP controller, TCK
must be tied low while TDI, TMS and TDO may be left unconnected. Upon power-up, the TAP will come up
in a reset state which will not interfere with the normal operation of the device.
4.1 Test Access Port (TAP)
4.1.1 Test Clock (TCK)
The test clock is used only with the TAP controller. The pin must be tied low if the TAP is not used.
4.1.2 Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK.
This pin may be left unconnected if the TAP is not used.
4.1.3 Test Data-In (TDI)
The TDI pin is used to serially input information into the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. TDI is connected to the most
significant bit (MSB) of any register (see Figure 38). This pin may be left unconnected if the TAP is not used.
4.1.4 Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon
the current state of the TAP state machine (see Figure 39). The output changes on the falling edge of TCK.
TDO is connected to the least significant bit (LSB) of any register (see Figure 38). This pin may be left
unconnected if the TAP is not used.
4.2 TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and shifted out
of the RLDRAM test circuitry (see Figure 38). Only one register is selected at a time through the instruction
register. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
4.2.1 Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is loaded when it is
placed between the TDI and TDO pins as shown in Figure 38. Upon power-up, the instruction register is
internally preloaded with the IDCODE instruction.
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01"
pattern to allow for fault isolation of the board-level serial test data path.
4.2.2 Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO pins. This allows
data to be shifted through the RLDRAM with minimal delay.
The bypass register is set LOW during the Capture-DR state when the BYPASS instruction is loaded in the
instruction register.
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 41 Infineon Technologies
This specification is preliminary and subject to change without notice
4.2.3 Boundary Scan Register
The boundary scan register is connected to all the IO pins on the RLDRAM. It allows to observe and control
the data flowing into and out of the device, depending on the instruction being loaded in the instruction
register.
The boundary scan register is 113 bits long. The register is the same for the x18 and x36 configurations of
the RLDRAM. Pins not used in x18 configuration read a LOW into the boundary scan register in the Capture-
DR controller state.
Differential inputs (CK/CK#, DKx/DKx#) and outputs (QKx/QKx#) are equipped with two boundary scan cells
each. Thus, the differential nature of these pins is not visible to the test circuitry. However, it is recommended
that during testing differential signals are always applied to these pin pairs.
4.2.4 Identification (ID) Register
The ID register is loaded with a hardwired, vendor-specific, 32-bit code during the Capture-DR state when
the IDCODE instruction is loaded in the instruction register. The code can be shifted out when the TAP
controller is in the Shift-DR state. Two different codes are implemented for the x18 and x36 configurations
of the RLDRAM (see Table 16).
.
Table 16 ID Register Definition
Revision
Number
Part Number Infineon JEDEC Code L
S
B
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
x18 00010000000011001110000010000011
x36 00010000000011001111000010000011
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 42 Infineon Technologies
This specification is preliminary and subject to change without notice
4.3 TAP Instructions
The TAP implements the 6 instructions BYPASS, EXTEST, SAMPLE/PRELOAD, IDCODE, HIGHZ and
CLAMP for user access (see Table 17). The implementation of these instructions fully complies with the
IEEE standard. All other instructions are reserved and should not be used.
Table 17 JTAG Instruction Register
Instruction Register
Code
Instruction Description
Hex x7 .. x0
00 0000 0000 EXTEST Selects the boundary scan register to be connected between TDI
and TDO. Data received at input pins are sampled and loaded into
the boundary scan register. Data driven by output pins are
determined from values contained in the boundary scan register.
03 0000 0011 HIGHZ Selects the bypass register to be connected between TDI and TDO.
All ouputs are forced into high impedance state.
05 0000 0101 SAMPLE / PRELOAD Selects the boundary scan register to be connected between TDI
and TDO. Data receivedat input pins are sampled and loaded int the
boundary scan register. initial ouput data are shifted into the
boundary scan register prior to an EXTEST intruction. Instruction
does not interfere with the normal operation of the device.
07 0000 0111 CLAMP Selects the bypass register to be connected between TDI and TDO.
Data driven by output pins are determined from values held in the
boundary scan regsiter.
21 0010 0001 IDCODE Selects the ID code register to be connected to TDI and TDO.
Instructin does not interfere with the normal operation of the device.
E0-EF 1110 0000 -
1110 1111
RESERVED Do not use.
FF 1111 1111 BYPASS Selects the bypass register to be connected between TDI and TDO.
Instruction does not interfere with the normal operation of the
device.
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 43 Infineon Technologies
This specification is preliminary and subject to change without notice
4.4 Boundary Scan Exit Order
4.4.1 x18 Configuration
Note: 1: Input pins are connected to Observe-Only Boundary Scan Register Cells.
Note: 2: Output pins are connected to Force-Only Boundary Scan Register Cells.
Note: 3: IO pins are connected to Force-and-Observe Boundary Scan Register Cells.
Note: 4 : Enb should be set to 0 for DNU pins, if they are connected to GND
Note: 5: Any unused pins that are in the order will read as the logic level applied to the ball site. If the ball is unconnected a logic level
"LOW" will be read.
Scan
Reg#
Reg
Content
Pin
Descr
.
Pin
Name Ball # Ball # Pin
Name
Pin
Descr
.
Reg
Content
Scan
Reg #
83
82
Data
Enb I/O DQ0 B10 B3 DQ4 I/O Enb
Data
84
85
81
80
Data
Enb I/O DNU B11 B2 DNU I/O Enb
Data
86
87
79
78
Data
Enb I/O DQ1 C10 C3 DQ5 I/O Enb
Data
88
89
77
76
Data
Enb I/O DNU C11 C2 DNU I/O Enb
Data
90
91
75 Data O QK0# D10 D3 DQ6 I/O Enb
Data
92
93
74 Data O QK0 D11 D2 DNU I/O Enb
Data
94
95
73
72
Data
Enb I/O DNU E11 E2 DNU I/O Enb
Data
96
97
71
70
Data
Enb I/O DQ2 E10 E3 DQ7 I/O Enb
Data
98
99
69
68
Data
Enb I/O DNU F11 F2 DNU I/O Enb
Data
100
101
67
66
Data
Enb I/O DQ3 F10 F3 DQ8 I/O Enb
Data
102
103
65 Data O QVLD F12 E1 (A21) I Data 104
64 Data I (A20) E12 F1 A5 I Data 105
63 Data I A1 G11 G2 A6 I Data 106
62 Data I A2 G10 G3 A7 I Data 107
61 Data I A0 G12 G1 A8 I Data 108
60 Data I A3 H12 H1 B2 I Data 109
59 Data I A4 H11 H2 A9 I Data 110
58 Data I B0 J11 J2 NC I Data 111
57 Data I CK J12 J1 NC I Data 112
56 Data I CK# K12 K1 DK I Data 0
55 Data I B1 K11 K2 DK# I Data 1
54 Data I A14 L11 L2 CS# I Data 2
53 Data I A13 L12 L1 REF# I Data 3
52 Data I A10 M12 M1 WE# I Data 4
51 Data I A12 M10 M3 A17 I Data 5
50 Data I A11 M11 M2 A16 I Data 6
49 Data I A19 N12 N1 A18 I Data 7
48 Data I DM P12 P1 A15 I Data 8
47
46
Data
Enb I/O DQ9 N10 N3 DQ14 I/O Enb
Data
9
10
45
44
Data
Enb I/O DNU N11 N2 DNU I/O Enb
Data
11
12
43
42
Data
Enb I/O DQ10 P10 P3 DQ15 I/O Enb
Data
13
14
41
40
Data
Enb I/O DNU P11 P2 DNU I/O Enb
Data
15
16
39
38
Data
Enb I/O DNU R11 R2 QK1 O Data 17
37
36
Data
Enb I/O DQ11 R10 R3 QK1# O Data 18
35
34
Data
Enb I/O DNU T11 T2 DNU I/O Enb
Data
19
20
33
32
Data
Enb I/O DQ12 T10 T3 DQ16 I/O Enb
Data
21
22
31
30
Data
Enb I/O DNU U11 U2 DNU I/O Enb
Data
23
24
29
28
Data
Enb I/O DQ13 U10 U3 DQ17 I/O Enb
Data
25
26
V2ZQIData27
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 44 Infineon Technologies
This specification is preliminary and subject to change without notice
4.4.2 x36 Configuration
Note: 1: Input pins are connected to Observe-Only Boundary Scan Register Cells.
Note: 2: Output pins are connected to Force-Only Boundary Scan Register Cells.
Note: 3: IO pins are connected to Force-and-Observe Boundary Scan Register Cells.
Note: 4 : Enb should be set to 0 for DNU pins, if they are connected to GND
Note: 5: Any unused pins that are in the order will read as the logic level applied to the ball site. If the ball is unconnected a logic level
"LOW" will be read.
Scan
Reg#
Reg
Content
Pin
Descr
.
Pin
Name Ball # Ball # Pin
Name
Pin
Descr
.
Reg
Content
Scan
Reg #
83
82
Data
Enb I/O DQ1 B10 B3 DQ9 I/O Enb
Data
84
85
81
80
Data
Enb I/O DQ0 B11 B2 DQ8 I/O Enb
Data
86
87
79
78
Data
Enb I/O DQ3 C10 C3 DQ11 I/O Enb
Data
88
89
77
76
Data
Enb I/O DQ2 C11 C2 DQ10 I/O Enb
Data
90
91
75 Data O QK0# D10 D3 DQ13 I/O Enb
Data
92
93
74 Data O QK0 D11 D2 DQ12 I/O Enb
Data
94
95
73
72
Data
Enb I/O DQ4 E11 E2 DQ14 I/O Enb
Data
96
97
71
70
Data
Enb I/O DQ5 E10 E3 DQ15 I/O Enb
Data
98
99
69
68
Data
Enb I/O DQ6 F11 F2 DQ16 I/O Enb
Data
100
101
67
66
Data
Enb I/O DQ7 F10 F3 DQ17 I/O Enb
Data
102
103
65 Data O QVLD F12 E1 (A21) I Data 104
64 Data I (A20) E12 F1 A5 I Data 105
63 Data I A1 G11 G2 A6 I Data 106
62 Data I A2 G10 G3 A7 I Data 107
61 Data I A0 G12 G1 A8 I Data 108
60 Data I A3 H12 H1 B2 I Data 109
59 Data I A4 H11 H2 A9 I Data 110
58 Data I B0 J11 J2 DK0# I Data 111
57 Data I CK J12 J1 DK0 I Data 112
56 Data I CK# K12 K1 DK1 I Data 0
55 Data I B1 K11 K2 DK1# I Data 1
54 Data I A14 L11 L2 CS# I Data 2
53 Data I A13 L12 L1 REF# I Data 3
52 Data I A10 M12 M1 WE# I Data 4
51 Data I A12 M10 M3 A17 I Data 5
50 Data I A11 M11 M2 A16 I Data 6
49 Data I (A19) N12 N1 A18 I Data 7
48 Data I DM P12 P1 A15 I Data 8
47
46
Data
Enb I/O DQ35 N10 N3 DQ25 I/O Enb
Data
9
10
45
44
Data
Enb I/O DQ34 N11 N2 DQ24 I/O Enb
Data
11
12
43
42
Data
Enb I/O DQ33 P10 P3 DQ23 I/O Enb
Data
13
14
41
40
Data
Enb I/O DQ32 P11 P2 DQ22 I/O Enb
Data
15
16
39
38
Data
Enb I/O DQ30 R11 R2 QK1 O Data 17
37
36
Data
Enb I/O DQ31 R10 R3 QK1# O Data 18
35
34
Data
Enb I/O DQ28 T11 T2 DQ20 I/O Enb
Data
19
20
33
32
Data
Enb I/O DQ29 T10 T3 DQ21 I/O Enb
Data
21
22
31
30
Data
Enb I/O DQ26 U11 U2 DQ18 I/O Enb
Data
23
24
29
28
Data
Enb I/O DQ27 U10 U3 DQ19 I/O Enb
Data
25
26
V2ZQIData27
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 45 Infineon Technologies
This specification is preliminary and subject to change without notice
4.5 TAP Operation
The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while
the RLDRAM clock operates much faster. As a consequence, it is possible that an input or output will
undergo a transition right at the moment when the TAP takes the snapshot in the Capture-DR state of
EXTEST or SAMPLE/PRELOAD instructions. The TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but there is no guarantee as to the value that will be
captured. To guarantee that the boundary scan register will capture the correct value of a signal, the signal
must meet the TAP's setup and hold time ( tCS plus tCH) around the rising edge of TCK.
4.6 JTAG TAP Block Diagram
Figure 38 TAP Block Diagram
Test Access Port (TAP) Controller
TMS
TCK
0
34 2 1 0567
3031 1 0
Bypass Register
Instruction Register
ID Code Register
TDI TDO
0
1
113
112
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 46 Infineon Technologies
This specification is preliminary and subject to change without notice
4.7 JTAG TAP Controller State Diagram
Figure 39 TAP Controller State Diagram
4.8 JTAG DC Operating Conditons
(0°C ≤Tj ≤100°C; 1.7V ≤ VDD ≤ 1.9V unless otherwise noted)
Parameter Symbol Limit Values Unit Notes
min. typ. max.
Input logic high voltage,
DC
VTIH VREF
+ 0.15
-V
DDQ
+ 0.3
V
Input logic low voltage,
DC
VTIL VSSQ
-0.3
-V
REF
- 0.15
V
Output logic high
voltage (IOH = -tbd mA)
VTOH VREF
+ tbd
--V
Output logic low voltage
(IOL = tbd mA)
VTOL --V
REF
- tbd
V
Test Logic Reset
Run Test Idle Select DR Select IR
1
0
0
111
Capture DR
0
Shift DR
1
Exit DR
Pause DR
Exit2 DR
Update DR
Capture IR
0
Shift IR
Exit IR
Pause IR
Exit2 IR
Update IR
0
1
0
1
1
1
0
1
0
1
1
1
1
0
0
1
0
0
0
0
0
0
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 47 Infineon Technologies
This specification is preliminary and subject to change without notice
4.9 JTAG AC Operating Conditions
(0°C ≤Tj ≤100°C; 1.7V ≤ VDD ≤ 1.9V unless otherwise noted)
4.10 JTAG AC Electrical Characteristics
(0°C ≤Tj ≤100°C; 1.7V ≤ VDD ≤ 1.9V unless otherwise noted)
4.11 JTAG Timing Diagram
Parameter Symbol Limit Values Unit Notes
min. typ. max.
Input logic high voltage,
AC
VTIH VREF
+ 0.3
-V
DDQ
+ 0.3
V
Input logic low voltage,
AC
VTIL VSSQ
- 0.3
-V
REF
- 0.3
V
Input Slew Rate TTSL 1.0 - - V/ns
Input and Output Timing
Reference Level
VREF VDDQ
/2
V
Parameter Symbol Limit Values Unit Notes
min. typ. max.
TCK Cycle Time TTCK 20 - - ns
TCK High Pulse Width TTCKH 10 - - ns
TCK Low Pulse Width TTCKL 10 - - ns
TCK Low to TDO Valid TTCKDO - - 10 ns
TDI Set Up Time TTDIS 5- -ns
TMS Set Up Time TTMSS 5- -ns
TDI Hold Time TTDIH 5--ns
TMS Hold Time TTMSH 5--ns
TTCK
TTCKH TTCKL
TTMSH TTMSS
TTDIH TTDIS
TTCKDO
TCK
TMS
TDI
TDO
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 48 Infineon Technologies
This specification is preliminary and subject to change without notice
5 Electrical Characteristics
5.1 Absolute Maximum Ratings
zStorage temperature range............................................– 55 to + 150 °C
zI/O voltage .......................................................... – 0.3 to +VDDQ + 0.3V
zPower supply voltage VEXT ............................................. – 0.3 to + 2.8V
zPower supply voltage VDD ....................................................– 0.3 to + 2.1V
zPower supply voltage VDDQ ............................................ – 0.3 to + 2.1V
zJunction Temperature......................................................... 0°C to 100°C
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
5.2 Recommended Power & DC Operation Ratings
All values are recommended operating conditions unless otherwise noted.
Table 18 Power & DC Operating Conditions
(0°C ≤Tj ≤100°C; 1.7V ≤ VDD ≤ 1.9V unless otherwise noted)
Note: 1. All voltages referenced to VSS (GND)
Note: 2. VDDQmax = 1.8V or VDD which ever is lower.
Note: 3. Typically the value of Vref is expected to be VDDQ/2 of the transmitting device. Vref is expected to track variations in VDDQ
Note: 4. Peak to peak AC noise on Vref may not exceed 2% Vref (DC). Thus, from VDDQ/2, VREF is allowed 2% for DC error and 2%
for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor.
Note: 5. The RTT value is measured at 70°C
Note: 6. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the device, IOL flows into the
device.
Note: 7. A power supply should be used for the generation of Vtt to sink and source the transiant currents. A 1k voltage divider will
not work.
Description Conditions Symbol Min. Max. Unit Notes
Supply Voltage VEXT 2.38 2.63 V 1
VDD 1.7 1.9 V 1
IO Supply Voltage VDDQ 1.7 VDD V 1,2
Termination Voltage VTT 0.95*VREF 1.05*VREF V 1,7
Reference Voltage Vref 0.49*VDDQ 0.51*VDDQ V1,3,4
External Resistor RQ 125 250 Ω
On-die Termination RTT 135 165 Ω5
Input HIGH (Logic 1) voltage VIHVref + 0.1 VDDQ + 0.3 V 1
Input LOW (Logic 0) voltage VILVSSQ - 0.3 Vref - 0.1 V 1
Output high current
VOUT = VDDQ/2
IOH (VDDQ/2)
(1.15xRQ/5)
(VDDQ/2)
(0.85xRQ/5)
A6
Output low current IOL (VDDQ/2)
(1.15xRQ/5)
(VDDQ/2)
(0.85xRQ/5)
A6
Input leakage current
0V< VIN < VDDQ
ILI -5 +5 µA
CLK Input leakage current ILCI -5 +5 µA
Output leakage current ILO -5 +5 µA
VREF Current IREF -5 +5 µA
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 49 Infineon Technologies
This specification is preliminary and subject to change without notice
5.3 AC Operation Ratings
Table 19 AC Operation Conditions
(0°C ≤ Tj ≤100°C; 1.7V ≤ VDD ≤ 1.9V unless otherwise noted)
Note: 1. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; The input
reference level for signals other than CK/CK# is VREF.
Note: 2. The signal input slew rate must be ≥ 2V/ns.
5.4 Clock Input Operation Ratings
Table 20 Clock Input Operating Conditions
Note: 1. DKx and DKx# have the same requirements as CK and CK#
Note: 2. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; The input
reference level for signals other than CK/CK# is VREF.
Note: 3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
Note: 4. The value if VIX is expected to equal VDDQ/2 of the transmitting device and must track variations of the DC value of the same.
5.5 Output Test Conditions
Figure 40 Output Test Circuits
Note:VDDQ=1.8V ±0.1V, TJ = 0 °C to 100 ° C
DESCRIPTION CONDITIONS Symbol min. max. Unit Notes
Input HIGH (Logic 1) Voltage VIHVref + 0.2 VDDQ + 0.3 V
Input LOW (Logic 0) Voltage VILVSSQ - 0.3 Vref - 0.2 V
DESCRIPTION Symbol min. max. Unit Notes
Clock Input Voltage Levels (CK / CK#) VIN(DC) -0.3 VDDQ + 0.3 V
DC Clock Input Differential Voltage (CK / CK#) VID(DC) 0.2 VDDQ + 0.6 V 3
AC Clock Input Differential Voltage (CK / CK#) VID(AC) 0.4 VDDQ + 0.6 V 3
Clock Input Crossing Point Voltage (CK/ CK#) VIX(AC) VDDQ/2
-0.15
VDDQ/2
+0.15 V4
10 pF
DQ
50 Ohm
Test point
+ V
tt
= 0.5 x V
DD
Q
HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Version 1.60 Page 50 Infineon Technologies
This specification is preliminary and subject to change without notice
5.6 Pin Capacitances
Table 21 Pin Capacitances
5.7 Operating Currents
Table 22 IDD Specifications and Conditions
Pin Conditions Symbol Min Max Unit
A<20:0>, BA<2:0>, CS#, AREF#, WE#
TA = 25°C; f = 1MHz
CI1.5 2.5 pF
DQ<35:0>, QKx, QKx#, QVLD, DM CO3.0 4.0 pF
CK, CK#, DKx, DKx# CCK 2.0 3.0 pF
Parameter
Freq
Limit Values
(max.) Unit Notes
x18 x36
IDD1 (*)
Operating Current
(Average Power
Supply Current)
400MHz VDD
VEXT
260
55
260
55
mA
mA
Burst Length = 2
tCK=min, tRC=min,
1 bank active,
Address change one time
during min tRC,
Read/Write command
cycling
300MHz VDD
VEXT
240
55
240
55
mA
mA
200MHz VDD
VEXT
215
55
215
55
mA
mA
IDD4R (*)
Operating Current
(Average Power
Supply Current)
400MHz VDD
VEXT
340
65
390
65
mA
mA
Burst Length = 4
tCK=min, tRC=min,
4 banks interleave,
address change with
each bank activation,
continuous read
operation 1.)
300MHz VDD
VEXT
315
65
360
65
mA
mA
200MHz VDD
VEXT
295
65
340
65
mA
mA
IDD8 (*)
Operating Current
(Average Power
Supply Current)
400MHz VDD
VEXT
505
90
505
90
mA
mA
Burst Length = 2
tCK=min, tRC=min, up to
8banks interleave,
address change with
each bank activation,
continuous read
operation 2.)
300MHz VDD
VEXT
475
90
565
90
mA
mA
200MHz VDD
VEXT
445
90
535
90
mA
mA
Standby Current
400MHz VDD
VEXT
175
45
175
45
mA
mA
tCK=min
All banks idle, CS=1
Command toggling
300MHz VDD
VEXT
160
45
160
45
mA
mA
200MHz VDD
VEXT
140
45
140
45
mA
mA
