Vishay Siliconix
Si4831BDY
Document Number: 70483
S09-0394-Rev. B, 09-Mar-09
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1
P-Channel 30-V (D-S) MOSFET with Schottky Diode
FEATURES
• Halogen-free According to IEC 61249-2-21
Available
• LITTLE FOOT® Plus Power MOSFET
• 100 % Rg Tested
APPLICATIONS
• HDD
• Asynchronous Rectification
MOSFET PRODUCT SUMMARY
VDS (V) RDS(on) (Ω)I
D (A)aQg (Typ.)
- 30 0.042 at VGS = - 10 V - 6.6
7.8
0.065 at VGS = - 4.5 V - 5.3
SCHOTTKY PRODUCT SUMMARY
VKA (V)
VF (V)
Diode Forward Voltage ID (A)a
30 0.53 V at 3 A 3.0
AK
A K
SD
G D
SO-8
5
6
7
8
Top View
2
3
4
1
Ordering Information: Si4831BDY-T1-E3 (Lead (Pb)-free)
Si4831BDY-T1-GE3 (Lead (Pb)-free and Halogen-free)
K
A
S
G
D
P-Channel MOSFET
Notes:
a. Based on TC = 25 °C.
b. Surface Mounted on FR4 board.
c. t ≤ 10 s.
d. Maximum under Steady State conditions is 110 °C/W.
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol Limit Unit
Drain-Source Voltage (MOSFET) VDS - 30
VReverse Voltage (Schottky) VKA - 30
Gate-Source Voltage (MOSFET) VGS ± 20
Continuous Drain Current (TJ = 150 °C) (MOSFET)
TC = 25 °C
ID
- 6.6
A
TC = 70 °C - 5.2
TA = 25 °C - 5.1b, c
TA = 70 °C - 3.9b, c
Pulsed Drain Current (MOSFET) IDM - 30
Continuous Source Current (MOSFET Diode Conduction) TC = 25 °C
IS
- 2.7
TA = 25 °C - 1.6b, c
Average Forward Current (Schottky) IF- 3b
Pulsed Forward Current (Schottky) IFM - 20
Maximum Power Dissipation (MOSFET and Schottky)
TC = 25 °C
PD
3.3
W
TC = 70 °C 2.1
TA = 25 °C 2.0b, c
TA = 70 °C 1.2b, c
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambient (MOSFET and Schottky)b, c, d RthJA 53 62.5 °C/W
Maximum Junction-to-Foot (Drain) (MOSFET and Schottky) RthJF 30 37
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Document Number: 70483
S09-0394-Rev. B, 09-Mar-09
Vishay Siliconix
Si4831BDY
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
MOSFET SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Drain-Source Breakdown Voltage VDS VDS = 0 V, ID = - 250 µA - 30 V
VDS Temperature Coefficient ΔVDS/TJ ID = 250 µA - 30 mV/°C
VGS(th) Temperature Coefficient
Δ
V
GS(th)/TJ
3.6
Gate Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 1 - 3 V
Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = - 30 V, VGS = 0 V - 1 µA
VDS = - 30 V, VGS = 0 V, TJ = 75 °C - 10
On-State Drain CurrentaID(on) V
DS ≥ - 5 V, VGS = - 10 V - 10 A
Drain-Source On-State ResistanceaRDS(on)
VGS = - 10 V, ID = - 5 A 0.034 0.042 Ω
VGS = - 4.5 V, ID = - 3 A 0.052 0.065
Forward Transconductanceagfs VDS = - 15 V, ID = - 5 A 11 S
Dynamicb
Input Capacitance Ciss
VDS = - 15 V, VGS = 0 V, f = 1 MHz
625
pF
Output Capacitance Coss 150
Reverse Transfer Capacitance Crss 115
Total Gate Charge Qg VDS = - 15 V, VGS = - 10 V, ID = - 5 A 17 26
nC
VDS = - 15 V, VGS = - 4.5 V, ID = - 5 A
7.8 12
Gate-Source Charge Qgs 1.6
Gate-Drain Charge Qgd 3.5
Gate Resistance Rg f = 1 MHz 7 14 Ω
Tur n - O n D e l ay Time td(on)
VDD = - 15 V, RL = 3 Ω
ID ≅ - 5 A, VGEN = - 4.5 V, Rg = 1 Ω
35 55
ns
Rise Time tr100 150
Turn-Off Delay Time td(off) 22 35
Fall Time tf12 20
Tu r n- O n D e lay T i m e
td(on)
VDD = - 15 V, RL = 3 Ω
ID ≅ - 5 A, VGEN = - 10 V, Rg = 1 Ω
816
Rise Time
tr816
Turn-Off Delay Time
td(off) 24 40
Fall Time
tf714
Drain-Source Body Diode Characteristics
Continous Source-Drain Diode Current ISTC = 25 °C - 3.3 A
Pulse Diode Forward CurrentaISM - 30
Body Diode Voltage VSD IS = - 1.4 A, VGS = 0 V - 0.78 - 1.2 V
Body Diode Reverse Recovery Time trr
IF = - 2 A, dI/dt = 100 A/µs, TJ = 25 °C
30 45 ns
Body Diode Reverse Recovery Charge Qrr 15 25 nC
Reverse Recovery Fall Time ta14
ns
Reverse Recovery Rise Time tb16
Document Number: 70483
S09-0394-Rev. B, 09-Mar-09
www.vishay.com
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Vishay Siliconix
Si4831BDY
Stresses beyond those listed under “A bsolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, an d functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SCHOTTKY SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Forward Voltage Drop VF
IF = 3 A 0.485 0.53 V
IF = 3 A, TJ = 125 °C 0.42 0.47
Maximum Reverse Leakage Current Irm
VR = 30 V 0.008 0.1
mA
VR = 30 V, TJ = 75 °C 0.4 5
VR = 30 V, TJ = 125 °C 6.5 20
Junction Capacitance CTVR = 15 V 102 pF
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Document Number: 70483
S09-0394-Rev. B, 09-Mar-09
Vishay Siliconix
Si4831BDY
MOSFET TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
0
6
12
18
24
30
0.0 0.5 1.0 1.5 2.0 2.5
VGS = 10 thru 5 V
VDS - Drain-to-Source Voltage (V)
- Drain Current (A)ID
4 V
3 V
0.00
0.02
0.04
0.06
0.08
0.10
0 6 12 1824 30
- On-Resistance (Ω)
ID - Drain Current (A)
R
DS(on)
VGS = 4.5 V
VGS = 10 V
ID = 5 A
0
2
4
6
8
10
0 3.6 7.2 10.8 14.4 18.0
- Gate-to-Source Voltage (V)
Qg - Total Gate Charge (nC)
VGS
VDS = 10 V
VDS = 20 V
VDS = 15 V
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0.0
0.4
0.8
1.2
1.6
2.0
0.0 0.8 1.6 2.4 3.2 4.0
TJ = 125 °C
VGS - Gate-to-Source Voltage (V)
- Drain Current (A)ID
TJ = 25 °C
- 55 °C
Ciss
Crss
Coss
0
200
400
600
800
1000
0 6 12 18 24 30
VDS - Drain-to-Source Voltage (V)
C - Capacitance (pF)
(Normalized)
- On-ResistanceR
DS(on)
0.6
0.9
1.2
1.5
1.8
- 50 - 25 0 25 50 75 100 125 150
TJ - Junction Temperature (°C)
VGS = 4.5 V
VGS = 10 V
ID = 5 A
Document Number: 70483
S09-0394-Rev. B, 09-Mar-09
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5
Vishay Siliconix
Si4831BDY
MOSFET TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Source-Drain Diode Forward Voltage
Threshold Voltage
0
1
10
100
0.0 0.3 0.6 0.9 1.2 1.5
TJ = 150 °C
VSD - Source-to-Drain Voltage (V)
- Source Current (A)IS
TJ = 25 °C
- 0.3
- 0.1
0.1
0.3
0.5
- 50 - 25 0 25 50 75 100 125 150
TJ - Temperature (°C)
VGS(th) Variance (V)
ID = 5 mA
ID = 250 µA
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power, Junction-to-Ambient
VGS - Gate-to-Source Voltage (V)
0
0.04
0.08
0.12
0.16
0.20
012345678910
TA = 25 °C
- On-Resistance (Ω)RDS(on)
TA = 125 °C
ID = 5 A
0
12
24
36
48
60
0.001 0.01 0.1 1 10
Time (s)
Power (W)
Safe Operating Area, Junction-to-Case
1
0.1 1 10 100
0.01
10
1 ms
- Drain Current (A)I
D
0.1
TA = 25 °C
Single Pulse
10 ms
100 ms
VDS - Drain-to-Source Voltage (V)
* VGS minimum VGS at which RDS(on) is specified
Limited by RDS(on)*
100
DC
1 s
10 s
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Document Number: 70483
S09-0394-Rev. B, 09-Mar-09
Vishay Siliconix
Si4831BDY
MOSFET TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Current Derating*
0
2
3
5
6
8
0 25 50 75 100 125 150
T
C
- Case Temperature (°C)
I
D
- Drain Current (A)
Power Derating, Junction-to-Foot
0.0
0.8
1.6
2.4
3.2
4.0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Power Dissipation (W)
Power Derating, Junction-to-Ambient
0.0
0.3
0.6
0.9
1.2
1.5
0 25 50 75 100 125 150
TA - Ambient Temperature (°C)
Power Dissipation (W)
Document Number: 70483
S09-0394-Rev. B, 09-Mar-09
www.vishay.com
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Vishay Siliconix
Si4831BDY
MOSFETS TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Normalized Thermal Transient Impedance, Junction-to-Ambient
10-3 10-2 000110110-1
10-4 100
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
t
1
t
2
Notes:
P
DM
1. Duty Cycle, D =
2. Per Unit Base = R
thJA
= 65 °C/W
3. T
JM
- T
A
= P
DM
Z
thJA(t)
t
1
t
2
4. Surface Mounted
Single Pulse
0.2
0.1
0.05
0.02
Duty Cycle = 0.5
0.01
0.1
1
Normalized Thermal Transient Impedance, Junction-to-Foot
10-3 10-2 01110-1
10-4
0.2
0.1
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1
0.1
0.01
0.05
0.02
Single Pulse
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Document Number: 70483
S09-0394-Rev. B, 09-Mar-09
Vishay Siliconix
Si4831BDY
SCHOTTKY TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70483.
Reverse Current vs. Junction Temperature
0.0001
0.001
0.01
0.1
1
10
100
0 25 50 75 100 125 150
- Reverse Current (A)IR
TJ - Temperature (°C)
10 V
30 V
Forward Voltage Drop
0.0 0.1 0.2 0.4 0.5 0.6
TJ = 150 °C
10
VF - Forward Voltage Drop (V)
- Forward Current (A)
I
F
1
TJ = 25 °C
0
Capacitance
0
100
200
300
400
500
0 6 12 18 24 30
VKA - Reverse Voltage (V)
C - Capacitance (pF)
T
Vishay Siliconix
Package Information
Document Number: 71192
11-Sep-06
www.vishay.com
1
DIM
MILLIMETERS INCHES
Min Max Min Max
A 1.35 1.75 0.053 0.069
A10.10 0.20 0.004 0.008
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q0°8°0°8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
4
3
12
5
6
87
HE
h x 45
C
All Leads
q0.101 mm
0.004"
L
BA
1
A
e
D
0.25 mm (Gage Plane)
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
S
VISHAY SILICONIX
TrenchFET® Power MOSFETs Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
APPLICATION NOTE
Document Number: 70740 www.vishay.com
Revision: 18-Jun-07 1
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a s ingle MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providin g the thermal connect ion
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
Figure 1. Single M O SFET SO-8 Pad
Pattern With Copper Spreading
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Sprea ding
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footpri nt with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
0.027
0.69
0.078
1.98
0.2
5.07
0.196
5.0
0.288
7.3
0.050
1.27
0.027
0.69
0.078
1.98
0.2
5.07
0.088
2.25
0.288
7.3
0.050
1.27
0.088
2.25
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72606
22 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SO-8
0.246
(6.248)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.172
(4.369)
0.152
(3.861)
0.047
(1.194)
0.028
(0.711)
0.050
(1.270)
0.022
(0.559)
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Revision: 12-Mar-12 1Document Number: 91000
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