®
1PCM3500
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
FEATURES
●16-BIT DELTA-SIGMA DAC AND ADC
●DESIGNED FOR MODEM ANALOG FRONT END:
Supports up to 56kbps Operation
●ANALOG PERFORMANCE:
Sampling Frequency: 7.2kHz to 26kHz
Dynamic Range: 88dB (typ) at f
S
= 8kHz, f
IN
= 1kHz
●SYSTEM CLOCK: 512fS
●MASTER OR SLAVE OPERATION
●ON-CHIP CRYSTAL OSCILLATOR CIRCUIT
●ADC-TO-DAC LOOP-BACK MODE
●TIME SLOT MODE SUPPORTS UP TO
FOUR CODECs ON A SINGLE SERIAL
INTERFACE
●POWER-DOWN MODE: 60µA (typ)
DESCRIPTION
The PCM3500 is a low cost, 16-bit CODEC designed
for modem Analog Front End (AFE) and speech pro-
cessing applications. The PCM3500’s low power op-
eration from +2.7V to +3.6V power supplies, along
with an integrated power-down mode, make it ideal for
portable applications.
The PCM3500 integrates all of the functions needed for
a modem or voice CODEC, including delta-sigma
© 1999 Burr-Brown Corporation PDS-1524B Printed in U.S.A. February, 2000
PCM3500
®
Low Voltage, Low Power, 16-Bit, Mono
VOICE/MODEM CODEC
APPLICATIONS
●SOFTWARE MODEMS FOR:
Personal Digital Assistant
Notebook and Hand-Held PCs
Set-Top Box
Digital Television
Embedded Systems
●PORTABLE VOICE RECORDER/PLAYER
●SPEECH RECOGNITION/SYNTHESIS
●TELECONFERENCING PRODUCTS
TM
digital-to-analog and analog-to-digital converters, in-
put anti-aliasing filter, digital high-pass filter for DC
blocking, and an output low-pass filter. The synchro-
nous serial interface provides for a simple, or glue-free
interface to popular DSP and RISC processors. The
serial interface also supports Time Division Multiplex-
ing (TDM), allowing up to four CODECs to share a
single 4-wire serial bus.
PCM3500
Interpolation
Digital Filter
Mode Control
Decimation
Digital Filter
Reference
AAF HPF
M/S
HPFD TSC XTIXTOLOOP
V
REF
1
V
COM
V
REF
2
V
IN
AGND
Serial I/O Interface
PDWN
Power
DGND
AGND V
DD
V
CC
Loop
FS
BCK
DIN
DOUT
FSO
SCKIO
Clock
Gen/
OSC
∆Σ
Modulator
(ADC)
∆Σ
Modulator
SMF
V
OUT
AGND
Multi-Level
DAC
●POWER SUPPLY: Single +2.7V to +3.6V
●SMALL PACKAGE: SSOP-24
For most current data sheet and other product
information, visit www.burr-brown.com
SBAS117
®
2
PCM3500
SPECIFICATIONS
All specifications at +25°C, VDD = VCC = 3.3V, fS = 8kHz, and nominal system clock (XTI) = 512fS, unless otherwise noted. Measurement band is 100Hz to 0.425fS.
NOTES: (1) Pins 6, 7, 8, 9, 10, 15, 17, 18, 19, 20 (M/S, TSC, BCK, FS, DIN, SCKIO, XTI, HPFD, LOOP, PDWN). (2) Pins 8, 9, 10, 15, 17 (BCK, FS, DIN, SCKIO
(Schmitt-Trigger input) XTI. (3) Pins 6, 7, 18, 19, 20 (M/S, TSC, HPFD, LOOP, PDWN; Schmitt-Trigger input with internal pull-down). (4) Pins 8, 9, 11, 12, 15,
16 (BCK, FS, DOUT, FSO, SCKIO, XTO).
PCM3500E
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 16 Bits
DATA FORMAT
Serial Data Interface Format DSP Format
Serial Data Bit Length 16 Bits
Serial Data Format
Sampling Frequency, fSADC and DAC 7.2 8 26 kHz
System Clock Frequency, 512fS3.686 4.096 13.312 MHz
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Input Logic Level: VIH(1) 0.7 • VDD VDC
VIL(1) 0.3 • VDD VDC
Input Logic Current: IIN(2) ±1µA
IIN(3) 100 µA
Output Logic Level: VOH(4) IOUT = –1mA VDD – 0.3 VDC
VOL(4) IOUT = +1mA 0.3 VDC
ADC CHARACTERISTICS
DC ACCURACY
Input Voltage 0.6 VCC Vp-p
Gain Error ±2±5 % of FSR
Offset Error High-Pass Filter Disabled ±2 % of FSR
Input Resistance 50 kΩ
AC ACCURACY
THD+N fIN = 1kHz, VIN = –0.5dB –85 –80 dB
Dynamic Range Without A-Weighting 82 88 dB
Signal-to-Noise Ratio Without A-Weighting 82 88 dB
Crosstalk DAC Channel Idle, 0dB Input 80 85 dB
Passband Ripple (internal HPF enabled) 0.0002fS to 0.425fS±0.05 dB
Passband Ripple (internal HPF disabled) 0fS to 0.425fS±0.05 dB
Roll-Off at 0.00002fSHigh-Pass Filter Enabled –3 dB
Roll-Off at 0.56fSHigh-Pass Filter Enabled –30 dB
Stopband Rejection 0.58fS to fS–65 dB
Group Delay 18/fS4m sec
DAC CHARACTERISTICS
DC ACCURACY
Output Voltage 0.6 VCC Vp-p
Gain Error ±1±5 % of FSR
Offset Error High Pass Filter Disabled ±1 % of FSR
Load Resistance 10 kΩ
AC ACCURACY
THD+N fIN = 1kHz, VOUT = 0dB –90 –82 dB
Dynamic Range Without A-Weighted 84 92 dB
Signal-to-Noise Ratio Without A-Weighted 84 92 dB
Crosstalk ADC Channel Idle, 0dB Input 84 92 dB
Passband Ripple 0fS to 0.425fS±0.4 dB
Group Delay 12/fS4m sec
POWER SUPPLY REQUIREMENTS
Voltage Range VCC, VDD 2.7 3.3 3.6 VDC
Supply Current, ICC + IDD VCC = 3.3V 9 12 mA
Total Supply Current in Power-Down Mode VCC = VDD = 3.3V, XTI Stopped 60 µA
Total Power Dissipation VCC = VDD = 3.3V 30 40 mW
TEMPERATURE RANGE
Operating –25 +85 °C
Storage –55 +125 °C
Thermal Resistance,
Θ
JA 100 °C/W
MSB-First, Binary Two’s Complement
®
3PCM3500
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN
product for use in life support devices and/or systems.
Supply Voltage, +VDD, +VCC ............................................................. +6.5V
Supply Voltage Differences............................................................... ±0.1V
GND Voltage Differences.................................................................. ±0.1V
Digital Input Voltage................................................... –0.3V to VDD + 0.3V
Input Current (any pins except supply) ........................................... ±10mA
Power Dissipation .......................................................................... 300mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature...................................................... –55°C to +125°C
Junction Temperature ...................................................................... 150°C
Lead Temperature (soldering, 5s).................................................. +260°C
(reflow, 10s) ................................................................................ +235°C
ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER(1) MEDIA
PCM3500E 24-Lead SSOP 338 –25°C to +85°C PCM3500E PCM3500E Rails
" " " " " PCM3500E/2K Tape and Reel
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2,000 pieces
of “PCM3500E/2K” will get a single 2000-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
®
4
PCM3500
PIN CONFIGURATION
Top View SSOP
PIN NAME I/O DESCRIPTION
1V
COM OUT Common-Mode Voltage (0.5VCC). This pin should be connected to ground through a capacitor.
2V
REF1 — Decouple Pin for Reference Voltage 1 (0.99VCC). This pin should be connected to ground through a capacitor.
3V
REF2 — Decouple Pin for Reference Voltage 2 (0.2VCC). This pin should be connected to ground through a capacitor.
4V
IN IN Analog Input for the ADC.
5 AGND — Analog Ground for the ADC Input Signal.
6 M/S IN Master/Slave Select. This pin is used to determine the operating mode for the serial interface. A logic ‘0’ on this pin selects the Slave
Mode. A logic ‘1’ on this pin selects the Master Mode.(2)
7 TSC IN Time Slot Mode Control. This pin is used to select the time slot operating mode. A logic ‘0’ on this pin disables Time Slot Mode. A
logic ‘1’ on this pin enables Time Slot Mode.(2)
8 BCK I/O Bit Clock. This pin serves as the bit (or shift) clock for the serial interface. This pin is an input in Slave Mode and an output in Master
Mode.(1)
9 FS I/O Frame Sync. This pin serves as the frame synchronization clock for the serial interface. This pin is an input in Slave Mode and an
output in Master Mode.(1)
10 DIN IN Serial Data Input. This pin is used to write 16-bit data to the DAC.(1)
11 DOUT OUT Serial Data Output. The ADC outputs 16-bit data on this pin.(3)
12 FSO OUT Frame Sync Output. Active only when Time Slot Mode is enabled. This pin is set to a high impedance state when Time Slot mode
is disabled (TSC = 0).
13 VDD — Digital Power Supply. Used to power the digital section of the ADC and DAC, as well as the serial interface and mode control logic.
This pin is not internally connected to VCC.
14 DGND — Digital Ground. Internally connected through the substrate to analog ground.
15 SCKIO I/O System Clock Input/Output. This pin is a system clock output when using the crystal oscillator or XTI as the system clock input; when
XTI is connected to ground, this pin is a system clock input.(1)
16 XTO OUT Crystal Oscillator Output.
17 XTI IN Crystal Oscillator Input or an External System Clock Input.
18 HPFD IN High-Pass Filter Disable. When this pin is set to a logic ‘1’, the HPF function in the ADC is disabled.(2)
19 LOOP IN ADC-to-DAC Loop-Back Control. When this pin is set to logic ‘1’, the ADC data is fed to the DAC input.(2)
20 PDWN IN Power Down and Reset Control. When this pin is logic ‘0’, Power-Down Mode is enabled. The PCM3500 is reset on the rising edge
of this signal.(2)
21 AGND — Analog Ground for the DAC Output Signal.
22 VOUT OUT Analog Output from the DAC Output Filter.
23 AGND — Analog Ground. This is the ground for the internal analog circuitry.
24 VCC — Analog Power Supply. Used to power the analog circuitry of the ADC and DAC.
NOTES: (1) Schmitt-Trigger input. (2) Schmitt-Trigger input with an internal pull-down resistor. (3) Tri-state output in Time Slot Mode.
PIN ASSIGNMENTS
V
COM
V
REF
1
V
REF
2
V
IN
AGND
M/S
TSC
BCK
FS
DIN
DOUT
FSO
V
CC
AGND
V
OUT
AGND
PDWN
LOOP
HPFD
XTI
XTO
SCKIO
DGND
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PCM3500
®
5PCM3500
TYPICAL PERFORMANCE CURVES
INTERPOLATION FILTER
PASSBAND RIPPLE CHARACTERISTICS
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0 0 0.1 0.2 0.3 0.4 0.5
Amplitude (dB)
Normalized Frequency (• f
S
Hz)
OUTPUT FILTER FREQUENCY RESPONSE
STOPBAND CHARACTERISTICS
Frequency (Hz)
Amplitude (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100100 1k 10k 100k 1M 10M
ANALOG FILTER
OUTPUT FILTER FREQUENCY RESPONSE
PASSBAND CHARACTERISTICS
Frequency (Hz)
Amplitude (dB)
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10 100101 1k 10k 100k
DAC SECTION
DIGITAL FILTER
Amplitude (dB)
INTERPOLATION FILTER FREQUENCY RESPONSE
Normalized Frequency (• f
S
)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 01234
®
6
PCM3500
TYPICAL PERFORMANCE CURVES (Cont.)
TA = +25°C, VCC = VDD = +3.3V, fS = 8kHz, and fSIGNAL = 1kHz, unless otherwise specified.
DAC OUTPUT SPECTRUM (–0dB, N = 8192)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
–140 12340
DAC OUTPUT SPECTRUM (–60dB, N = 8192)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
–140 12340
TOTAL HARMONIC DISTORTION + NOISE
vs SIGNAL NOISE
Signal Level (dB)
THD+N (dB)
0
–20
–40
–60
–80
–100 –84 –72 –60 –48 –36 –24 –12 0–96
THD+N fluctuates with signal level
as harmonics are limited to second
and third components.
DAC OUT-OF-BAND NOISE SPECTRUM
(BPZ, N = 2048)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
–140 8 162432 404856640
DAC SECTION
DAC OUTPUT SPECTRA
®
7PCM3500
TYPICAL PERFORMANCE CURVES (Cont.)
THD+N at –0dB (dB)
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
(T
A
= –25°C to +85°C)
Temperature (°C)
–88
–90
–92
–94
–96 –25 0 25 50 75 100–50
Dynamic Range and SNR (dB)
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs TEMPERATURE
(T
A
= –25°C to +85°C)
Temperature (°C)
96
94
92
90
88 –25 0 25 50 75 100–50
Dynamic Range
SNR
THD+N at –0dB (dB)
TOTAL HARMONIC DISTORTION + NOISE
vs SUPPLY VOLTAGE
(V
CC
= V
DD
= +2.7V to +3.6V)
Supply Voltage (V)
–88
–90
–92
–94
–96 2.7 3.0 3.3 3.6 3.92.4
Dynamic Range and SNR (dB)
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs SUPPLY VOLTAGE
(V
CC
= V
DD
= +2.7V to +3.6V)
Supply Voltage (V)
96
94
92
90
88 2.7 3.0 3.3 3.6 3.92.4
Dynamic Range
SNR
THD+N at –0dB (dB)
TOTAL HARMONIC DISTORTION + NOISE
vs SAMPLING FREQUENCY
(f
S
= 8kHz to 26kHz)
f
S
(kHz)
–88
–90
–92
–94
–96 81624320
BW = 3.4kHz
Dynamic Range and SNR (dB)
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs SAMPLING FREQUENCY
(f
S
= 8kHz to 26kHz)
f
S
(kHz)
96
94
92
90
88 81624320
BW = 3.4kHz
Dynamic Range
SNR
DAC SECTION
DAC CHARACTERISTICS vs TEMPERATURE, SUPPLY, AND SAMPLING FREQUENCY
®
8
PCM3500
TYPICAL PERFORMANCE CURVES
ADC SECTION
DIGITAL FILTER
DECIMATION FILTER FREQUENCY RESPONSE
Normalized Frequency (• f
S
Hz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200 81624320
DECIMATION FILTER
STOPBAND ATTENUATION CHARACTERISTICS
Normalized Frequency (• f
S
Hz)
Amplitude (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 0.2 0.4 0.6 0.8 1.00
DECIMATION FILTER
PASSBAND RIPPLE CHARACTERISTICS
Normalized Frequency (• f
S
Hz)
Amplitude (dB)
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0 0.1 0.2 0.3 0.4 0.50
DECIMATION FILTER TRANSITION
BAND CHARACTERISTICS
Normalized Frequency (• f
S
Hz)
Amplitude (dB)
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
–4.13dB at 0.5 • f
S
HIGH-PASS FILTER FREQUENCY RESPONSE
STOPBAND CHARACTERISTICS
Normalized Frequency (• fS/1000 Hz)
Amplitude (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 0.1 0.2 0.3 0.4 0.50
HIGH-PASS FILTER FREQUENCY RESPONSE
PASSBAND CHARACTERISTICS
Normalized Frequency (• f
S
/1000 Hz)
Amplitude (dB)
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–10 12340
®
9PCM3500
TYPICAL PERFORMANCE CURVES (Cont.)
TA = +25°C, VCC = VDD = +3.3V, fS = 8kHz, and fSIGNAL = 1kHz, unless otherwise specified.
ADC SECTION
ANALOG FILTER
ANTI-ALIASING FILTER
STOPBAND CHARACTERISTICS
Frequency (Hz)
Amplitude (dB)
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50 1k100 10k 100k 1M 10M
ANTI-ALIASING FILTER
PASSBAND CHARACTERISTICS
Frequency (Hz)
Amplitude (dB)
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0 1k100101 10k 100k
ADC OUTPUT SPECTRUM (–0.5dB, N = 8192)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
–140 12340
ADC OUTPUT SPECTRA
ADC OUTPUT SPECTRUM (–60dB, N = 8192)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
–140 12340
TOTAL HARMONIC DISTORTION + NOISE
vs SIGNAL NOISE
Signal Level (dB)
THD+N (dB)
0
–20
–40
–60
–80
–100 –84 –72 –60 –48 –36 –24 –12 0–96
THD+N fluctuates with signal level
as harmonics are limited to second
and third components.
®
10
PCM3500
TYPICAL PERFORMANCE CURVES (Cont.)
TA = +25°C, VCC = VDD = +3.3V, fS = 8kHz, and fSIGNAL = 1kHz, unless otherwise specified.
ADC SECTION
ADC CHARACTERISTICS vs TEMPERATURE, SUPPLY AND SAMPLING FREQUENCY
THD+N at –0.5dB (dB)
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
(T
A
= –25°C to +85°C)
Temperature (°C)
–84
–86
–88
–90
–92 –25 0 25 50 75 100–50
Dynamic Range and SNR (dB)
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs TEMPERATURE
(T
A
= –25°C to +85°C)
Temperature (°C)
92
90
88
86
84 –25 0 25 50 75 100–50
Dynamic Range
SNR
THD+N at –0.5dB (dB)
TOTAL HARMONIC DISTORTION + NOISE
vs SUPPLY VOLTAGE
(V
CC
= V
DD
= +2.7V to +3.6V)
Supply Voltage (V)
–84
–86
–88
–90
–92 2.7 3.0 3.3 3.6 3.92.4
Dynamic Range and SNR (dB)
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs SUPPLY VOLTAGE
(V
CC
= V
DD
= +2.7V to +3.6V)
Supply Voltage (V)
92
90
88
86
84 2.7 3.0 3.3 3.6 3.92.4
SNR
Dynamic Range
THD+N at –0.5dB (dB)
TOTAL HARMONIC DISTORTION + NOISE
vs SAMPLING FREQUENCY
(f
S
= 8kHz to 26kHz)
f
S
(kHz)
–84
–86
–88
–90
–92 81624320
BW = 3.4kHz
Dynamic Range and SNR (dB)
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs SAMPLING FREQUENCY
(f
S
= 8kHz to 26kHz)
f
S
(kHz)
96
94
92
90
88 81624320
BW = 3.4kHz
Dynamic Range
SNR
®
11 PCM3500
I
CC
, I
DD
and I
CC
+ I
DD
(mA)
SUPPLY CURRENT vs SUPPLY VOLTAGE
Supply Voltage (V)
12
10
8
6
4
2
02.7 3.0 3.3 3.6 3.92.4
I
CC
+ I
DD
I
CC
+ I
DD
at Power Down
I
CC
I
DD
SUPPLY CURRENT vs SUPPLY VOLTAGE AND SAMPLING FREQUENCY
I
CC
, I
DD
and I
CC
+ I
DD
(mA)
SUPPLY CURRENT vs SUPPLY VOLTAGE
Supply Voltage (V)
12
10
8
6
4
2
02.7 3.0 3.3 3.6 3.92.4
I
CC
+ I
DD
I
CC
+ I
DD
at Power Down
I
CC
I
DD
TYPICAL PERFORMANCE CURVES (Cont.)
TA = +25°C, VCC = VDD = +3.3V, fS = 8kHz, and fSIGNAL = 1kHz, unless otherwise specified.
®
12
PCM3500
SYSTEM CLOCK AND RESET/
POWER DOWN
SYSTEM CLOCK INPUT AND OUTPUT
The PCM3500 requires a system clock for operating the
digital filters and delta-sigma data converters.
The system clock may be supplied from an external master
clock or generated using the on-chip crystal oscillator cir-
cuit. Figure 1 shows the required connections for external
and crystal clock operation. The system clock must operate
at 512 times the sampling frequency, fS, with sampling
frequencies from 7.2kHz to 26kHz. This gives an effective
system clock frequency range of 3.6864MHz to 13.312MHz.
Table I shows system clock frequencies for common sam-
pling frequencies.
For external clock operation, XTI (pin 17) or SCKIO (pin 15)
is driven by a master clock source. If SCKIO is used as the
system clock input, then XTI must be connected to ground.
SAMPLING FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz)
8 4.096
11.025 5.6448
16 8.192
22.05 11.2896
24 12.288
TABLE I. System Clock Frequencies for Common Sam-
pling Frequencies.
FIGURE 1. System Clock Generation.
For either case, XTO (pin 16) should be left open. The system
clock source should be free of noise and exhibit low phase
jitter in order to obtain optimal dynamic performance from
the PCM3500. Figure 2 shows the system clock timing
requirements associated with an external master clock.
For crystal oscillator operation, a crystal is connected be-
tween XTI (pin 17) and XTO (pin 16), along with the
necessary load capacitors (10pF to 33pF per pin, as shown
in Figure 1). A fundamental-mode, parallel resonant crystal
is required.
FIGURE 2. External System Clock Timing Requirements.
C
1
C
2
C
1
, C
2
= 10pF to 33pF
XTI
R
Crystal
XTO
PCM3500
SCKIO
CRYSTAL RESONATOR
CONNECTION
External
Clock
External
Clock XTI
XTO
R
PCM3500
EXTERNAL CLOCK INPUT-XTI
(XTO must be open)
SCKIO
XTI
XTO
R
PCM3500
EXTERNAL CLOCK INPUT-SCKIO
(XTO must be open)
SCKIO
System Clock Pulse Width HIGH t
CLKIH
20ns (min)
System Clock Pulse Width LOW t
CLKIL
20ns (min)
t
CLKIH
t
CLKIL
1/512f
S
0.7V
DD
"H"
XTI
or
SCKIO "L" 0.3V
DD
®
13 PCM3500
Reset and Power Down
The PCM3500 supports power-on reset, external reset, and
power-down operations. Power-on reset is performed by
internal circuitry automatically at power up, while the exter-
nal reset is initiated using the PDWN input (pin 20).
Power-on reset occurs when power and system clock are
initially applied to the PCM3500. The internal reset cir-
cuitry requires that the system clock be active at power up,
with at least three system clock cycles occurring prior to
VDD = 2.2V. When VDD exceeds 2.2V, the power-on reset
comparator enables the initialization sequence, which re-
quires 1024 system clock periods for completion. During
the initialization sequence, the DAC output is forced to
AGND, and the ADC output is forced to a high impedance
state. After the initialization sequence has completed, the
DAC and ADC outputs experience a delay before they
output a valid signal or data. Refer to Figures 3 and 5 for
power-on reset and post-reset delay timing.
External reset is performed by first setting PDWN = ‘0’ and
then setting PDWN = ‘1’. The LOW to HIGH transition on
PDWN causes the reset initialization sequence to start.
During the initialization sequence, the DAC output is forced
to AGND, and the ADC output is forced to a high impedance
state. After the initialization sequence has completed, the
DAC and ADC outputs experience a delay before they
output a valid signal or data. Refer to Figures 4 and 5 for
external reset and post-reset delay timing.
Power-down mode is enabled by setting PDWN = ‘0’.
During power-down mode, minimum current is drawn when
the system clock is removed, resulting in 60µA (typical)
power supply current. The PDWN input includes an internal
pull-down resistor, which places the PCM3500 in power-
down mode at power-up if the PDWN pin is left uncon-
nected. Ideally, the PDWN input should be driven by active
logic in order to control reset and power-down operation. If
the PDWN pin is to be unused in the system application, it
should be connected to VDD to enable normal operation. By
setting PDWN = ‘1’ when exiting power-down mode, the
PCM3500 will initiate an external reset as described earlier
in this section.
1024 System Clock Periods
Reset Reset Removal
2.4V
2.2V
2.0V
V
DD
Internal Reset
System Clock
FIGURE 3. Power-On Reset Timing.
1024 System Clock Periods
Reset Reset Removal
System Clock
Internal Reset
PDWN t
RST
PWDN = LOW Pulse Width
t
RST
= 40ns minimum
FIGURE 4. External Reset Timing.
FIGURE 5. DAC and ADC Output for Reset and Power Down.
Reset
Power Down
GND V
COM
(0.5V
CC
)
Ready/Operation
Internal Reset
or Power Down
ADC DOUT
DAC V
OUT
High Impedance
(1)
t
ADCDLY1
(2304/f
S
)
t
DACDLY1
(2048/f
S
)
Reset Removal or Power Down OFF
NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR with 200ms time constant) appears initially.
®
14
PCM3500
SERIAL INTERFACE
The serial interface of the PCM3500 is a 4-wire synchronous
serial port. It includes FS (pin 9), BCK (pin 8), DIN (pin 10)
and DOUT (pin 11). FS is the frame synchronization clock,
BCK is the serial bit or shift clock, DIN is the serial data input
for the DAC, and DOUT is the serial data output for the ADC.
The frame sync, FS, operates at the sampling frequency (fS).
The bit clock, BCK, operates at 16fS for normal operation.
DIN and DOUT also operate at the bit clock rate. Both FS
and BCK must be synchronous with the system clock (guar-
anteed in Master Mode). Data for DIN is clocked into the
serial interface on the rising edge of BCK, while data for
DOUT is clocked out of the serial interface on the falling
edge of BCK.
Figure 6 shows the serial interface format for the PCM3500.
The serial data for DIN and DOUT must be in Binary Two’s
Complement, MSB-first format. Figures 7 and 8 show the
timing specifications for the serial interface when used in
Slave and Master Modes.
FS
BCK
DIN
DOUT
MSBMSB LSB LSB
MSBMSB LSB LSB
15 14 13 12 11 210543 151413 12 11 210543
15 14 13 12 11 210543 151413 12 11 210543
1/f
S
16-Bit/Frame
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tBCKP BCK Period 2400 ns
tBCKH BCK Pulse Width HIGH 800 ns
tBCKL BCK Pulse Width LOW 800 ns
tFSW FS Pulse Width HIGH tBCKP – 60 tBCKP tBCKP + 60 ns
tFSP FS Period 1/fS
tFSSU FS Set Up Time to BCK Rising Edge 60 ns
tFSHD FS Hold Time to BCK Rising Edge 60 ns
tDISU DIN Set Up Time to BCK Rising Edge 60 ns
tDIHD DIN Hold Time to BCK Rising Edge 60 ns
tCKDO Delay Time BCK Falling Edge to DOUT 0 80 ns
tRRising Time of All Signals 30 ns
tFFalling Time of All Signals 30 ns
FIGURE 6. Serial Interface Format.
FIGURE 7. Serial Interface Timing for Slave Mode.
t
FSW
t
FSSU
t
FSHD
t
BCKP
t
BCKH
t
DISU
t
DIHD
t
BCKL
t
CKDO
t
FSP
FS
(input)
BCK
(input)
DIN
(input)
DOUT
(output)
NOTES: Timing measurement reference level is (VIH/VIL)/2. RIsing and falling time is measured
from 10% to 90% of IN/OUT signal swing. Load capacitance of DOUT signal is 50pF.
0.5V
DD
0.5V
DD
0.5V
DD
0.5V
DD
®
15 PCM3500
SERIAL
INTERFACE
M/S (PIN 6) MODE FS (PIN) BCK (PIN 8)
0 Slave Input Input
1 Master Output Output
TABLE II. Master/Slave Mode Selection.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tBCKP BCK Period 2400 16000 ns
tBCKH BCK Pulse Width HIGH 1200 8000 ns
tBCKL BCK Pulse Width LOW 1200 8000 ns
tCKFS Delay Time BCK Falling Edge to FS – 40 40 ns
tFSW FS Pulse Width HIGH tBCKP – 60 tBCKP tBCKP + 60 ns
tFSP FS Period 1/fS
tDISU DIN Set Up Time to BCK Rising Edge 60 ns
tDIHD DIN Hold Time to BCK Rising Edge 60 ns
tCKDO Delay Time BCK Falling Edge to DOUT 0 80 ns
tRRising Time of All Signals 30 ns
tFFalling Time of All Signals 30 ns
FIGURE 8. Serial Interface Timing for Master Mode.
MASTER/SLAVE OPERATION
The serial interface supports both Slave and Master Mode
operation. The mode is selected by the M/S input (pin 6).
Table II shows mode and pin settings corresponding to the
M/S input selection. Figure 9 shows connections for Slave
and Master mode operation.
FIGURE 9. Slave and Master Mode Connections.
Slave Mode Operation
In Slave Mode, the FS and BCK pins are inputs to the
PCM3500. Both FS and BCK should be derived from the
system clock signal (XTI or SCKIO) to ensure proper
synchronization. Slave Mode is best suited for applications
where the DSP or controller is capable of generating the FS,
BCK, and system clocks using an on-chip serial port and/or
timing generator.
Master Mode Operation
In Master Mode operation, both FS and BCK are clock
outputs generated by the PCM3500 from the system clock
input (XTI, SCKIO, or a crystal). In Master Mode, the timing
and phase relationships between system clock, FS, and BCK
are managed internally to provide optimal synchronization.
XTI
FS
BCK
DIN
DOUT M/S
TSC
GND
GND
Controller
System
Clock
Slave Mode
PCM3500
XTI
FS
BCK
DIN
DOUT M/S
TSC V
DD
GND
PCM3500
System
Clock
Controller
Master Mode
t
FSW
t
CKFS
t
BCKP
t
BCKH
t
DISU
t
DIHD
t
BCKL
t
CKDO
t
FSP
NOTES: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from
10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, FS, BCK signal is 50pF.
0.5V
DD
0.5V
DD
0.5V
DD
0.5V
DD
FS
(output)
BCK
(output)
DIN
(input)
DOUT
(output)
®
16
PCM3500
SYNCHRONIZATION REQUIREMENTS
The PCM3500 requires that FS and BCK be synchronous
with the system clock. Internal circuitry is included to detect
a loss of synchronization between FS and the system clock
input. If the phase relationship between FS and the system
clock varies more than ± 1.5 BCK periods, the PCM3500
will detect a loss of synchronization. Upon detection, the
DAC output is forced to 0.5VCC and the DOUT pin is forced
to a high impedance state. This occurs within one sampling
clock (FS) period of initial detection. Figure 10 shows the
loss of synchronization operation and the DAC and ADC
output delays associated with it.
TIME SLOT OPERATION
The PCM3500 serial interface supports Time Division
Multiplexing (TDM) using the Time Slot Mode. Up to four
PCM3500s may be connected on the same 4-wire serial
interface bus. This is useful for system applications that
require multiple modem or voice channels. Figure 11 shows
examples of Time Slot Mode connections.
Time Slot Mode defines a 64-bit long frame, composed of
four time slots. Each slot is 16 bits long and corresponds to
one of four CODECs. The FS pin on the first PCM3500
(CODEC A, Slot 0) is used as the master frame sync, and
operates at the sampling frequency, fS. The bit clock, BCK,
operates at 64fS. DIN and DOUT of each CODEC also
operate at 64fS. Figure 12 shows the operation of the Time
Slot Mode.
Time Slot operation is enabled or disabled using the TSC
input (pin 7). The state of the TSC pin is updated at power-
on reset, or on the rising edge of PWDN input (if using
external reset or power-down mode). A forced reset is
required when changing from Slave to Master Mode, or visa
versa, in real time.
FIGURE 10. Loss of Synchronization Operation and Timing.
FIGURE 11. Time Slot Mode Connections.
Synchronous Asynchronous
Synchronization
Lost Resynchronization
within
1/f
S
Synchronous
Normal Normal
t
ADCDLY2
(32/f
S
)
t
DACDLY2
(32/f
S
)
V
COM
(0.5 V
CC
)V
COM
(0.5 V
CC
)
State of
Synchronization
DAC V
OUT
Normal Normal
(1)
High Impedance
ADC DOUT
NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
Undefined Data
Undefined Data
V
DD
V
DD
Controller
GND
V
DD
SCKIO
XTI
XTO
FS
BCK
DIN
DOUT
FSO
M/S
TSC
PCM3500
(CODEC B, Slot 1)
PCM3500
(CODEC A, Slot 0)
To Two PCM3500s
SCKIO
XTI
XTO
FS
BCK
DIN
DOUT
FSO
M/S
TSC
®
17 PCM3500
FIGURE 12. Time Slot Mode Operation.
FS
BCK
FS (A)
FSO (A)
FS (B)
FS (C)
FSO (C)
FS (D)
FSO (D)
DIN
FSO (B)
DOUT (A)
DOUT (B)
DOUT (C)
DOUT (D)
MSB LSB
High Impedance
High Impedance
High ImpedanceHigh Impedance
High Impedance
Slot 0, 16 Bits Slot 1, 16 Bits Slot 2, 16 Bits Slot 3, 16 Bits
CODEC A CODEC B
One Frame = 1/f
S
, 64 Bits per Frame, 16 Bits per Slot
CODEC C CODEC D
®
18
PCM3500
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tBCKP BCK Period 600 ns
tBCKH BCK Pulse Width HIGH 200 ns
tBCKL BCK Pulse Width LOW 200 ns
tFSW FS Pulse Width HIGH tBCKP – 60 tBCKP tBCKP + 60 ns
tFSP FS Period 1/fS
tFSSU FS Set Up TIme to BCK Rising Edge 60 ns
tFSHD FS Hold TIme to BCK RIsing Edge 60 ns
tDISU DIN Set Up Time to BCK Rising Edge 60 ns
tDIHD DIN Hold Time to BCK Rising Edge 60 ns
tCKDO Delay Time BCK Falling Edge to DOUT 0 80 ns
tHZDO Delay Time BCK Falling Edge to DOUT Active 20 ns
tDOHZ Delay Time BCK Falling Edge to DOUT Inactive 19.5 ns
tFSOW FSO Pulse Width HIGH tBCKP – 60 tBCKP tBCKP + 60 ns
tBFSO Delay Time BCK Falling Edge to FSO 0 80 ns
tRRising Time of All Signals 30 ns
tFFalling Time of All Signals 30 ns
FIGURE 13. Serial Interface Timing for Time Slot Mode Operation (Slave Mode).
Table III shows the TSC pin settings and corresponding
mode selections. When Time Slot Mode is enabled, FSO
(pin 12) is used as a frame sync output, which is connected
to the FS input of the next PCM3500 in the Time Slot
sequence. Figures 13 and 14 provide detailed timing for
Time Slot Mode operation.
TSC (PIN 7) TIME SLOT MODE
0 Time Slot Mode Disabled, Normal Operation
1 Time Slot Operation Enable
LOOP (PIN 19) LOOP-BACK MODE
0 Loop-Back Mode Disabled, Normal Operation
1 Loop-Back Mode Enabled
TABLE IV. Loop-Back Mode Selection.
TABLE III. Time Slot Mode Selection.
HPFD (PIN 18) HIGH-PASS FILTER MODE
0 High-Pass Filter On
1 High-Pass Filter Off
TABLE V. High-Pass Filter Mode Selection.
HIGH-PASS FILTER
The PCM3500 includes a digital high-pass filter in the ADC
which may be used to remove the DC offset created by the
analog front-end (AFE) section. The high-pass filter response
is shown in Figure 15. The high-pass filter may be enabled or
disabled using the HPFD input (pin 18). Table V shows the
HPFD pin settings and corresponding mode selections.
ADC-TO-DAC LOOP BACK
The PCM3500 includes a Loop-Back Mode, which directly
feeds the ADC data to the DAC input. This mode is designed
for diagnostic testing and system adjustment. Loop-Back
Mode is enabled and disabled using the LOOP input (pin
19). Table IV shows the LOOP pin settings and correspond-
ing mode selections. The serial interface continues to oper-
ate in Loop-Back Mode, allowing the host to read the ADC
data at the DOUT pin.
t
FSW
t
FSSU
High Impedance High Impedance
t
FSHD
t
BCKP
t
BCKL
t
DISU
t
DIHD
t
BCKH
t
CKDO
t
HZDO
t
DOHZ
t
FSP
NOTES: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from
10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, and FSO signal is 50pF.
0.5V
DD
0.5V
DD
0.5V
DD
0.5V
DD
0.5V
DD
t
FSOW
t
BFSO
FS
(input)
BCK
(input)
DIN
(input)
DOUT
(output)
FSO
(output)
®
19 PCM3500
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tBCKP BCK Period 600 4000 ns
tBCKH BCK Pulse Width HIGH 300 2000 ns
tBCKL BCK Pulse Width LOW 300 2000 ns
tCKFS Delay Time BCK Falling Edge to FS –40 40 ns
tFSW FS Pulse Width HIGH tBCKP – 60 tBCKP tBCKP + 60 ns
tFSP FS Period 1/fS
tDISU DIN Set Up Time to BCK Rising Edge 60 ns
tDIHD DIN Hold Time to BCK Rising Edge 60 ns
tCKDO Delay Time BCK Falling Edge to DOUT 0 80 ns
tHZDO Delay Time BCK Falling Edge to DOUT Active 20 ns
tDOHZ Delay Time BCK Falling Edge to DOUT Inactive 19.5 ns
tFSOW FSO Pulse Width HIGH tBCKP – 60 tBCKP tBCKP + 60 ns
tBFSO Delay Time BCK Falling Edge to FSO 0 80 ns
tRRising Time of All Signals 30 ns
tFFalling Time of All Signals 30 ns
FIGURE 14. Serial Interface Timing for Time Slot Mode Operation (Master Mode).
FIGURE 15. High-Pass Filter Response.
HIGH-PASS FILTER FREQUENCY RESPONSE
STOPBAND CHARACTERISTICS
Normalized Frequency (• fS/1000 Hz)
Amplitude (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 0.1 0.2 0.3 0.4 0.50
HIGH-PASS FILTER FREQUENCY RESPONSE
PASSBAND CHARACTERISTICS
Normalized Frequency (• fS/1000 Hz)
Amplitude (dB)
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–10 12340
t
FSW
High Impedance High Impedance
t
BCKP
t
CKFS
t
BCKL
t
DISU
t
DIHD
t
BCKH
t
CKDO
t
HZDO
t
DOHZ
t
FSP
NOTES: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from
10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, FSO, FS, and BCK signal is 50pF.
0.5V
DD
0.5V
DD
0.5V
DD
0.5V
DD
0.5V
DD
t
FSOW
t
BFSO
FS
(output)
BCK
(output)
DIN
(input)
DOUT
(output)
FSO
(output)
®
20
PCM3500
APPLICATIONS INFORMATION
BASIC CIRCUIT CONNECTIONS
The basic connection diagram for the PCM3500 is shown in
Figure 16. Included are the required power supply bypass and
reference decoupling capacitors. The DAC output, VOUT, and
the ADC input, VIN, should be AC-coupled to external cir-
cuitry.
Reference Pin Connections
The VCOM voltage is used internally to bias the input and
output amplifier stages of the PCM3500. It is brought out
FIGURE 16. Basic Connection Diagram.
unbuffered on pin 1 for decoupling. A 1µF to 10µF alumi-
num electrolytic or tantalum capacitor is recommended for
decoupling purposes. This capacitor should be located as
close as possible to pin 1.
The VCOM voltage is typically equal to VCC/2, and may be
used to bias external input and output circuitry. However,
since the VCOM pin is not a buffered output, it must drive a
high impedance load to avoid excessive loading. Buffering
the VCOM pin with an external op amp configured as a
voltage follower is recommended when driving multiple bias
nodes. Figure 17 shows examples of using VCOM with
external circuitry.
FIGURE 17. Using VCOM to Bias External Circuitry.
V
COM
V
REF
1
V
REF
2
V
IN
AGND
M/S
TSC
BCK
FS
DIN
DOUT
FSO
V
CC
AGND
V
OUT
AGND
PDWN
LOOP
HPFD
XTI
XTO
SCKIO
DGND
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PCM3500
+
+
+
+
C
3
C
4
C
5
C
6
Serial
Interface
+
+C
1
+3.3V
External Reset
Power-Down Control
External Clock System
Analog Line Interface Circuit
Telecom Line
+
C
2
C
7
C
1
, C
2
: Power supply bypass capacitors. Parallel combination of a 1µF to 10µF aluminum electrolytic capacitor and 0.1µF ceramic capacitor.
C
3
, C
4
, C
5
: V
REF
and V
COM
bypass capacitors. Use a 1µF to 10µF aluminum electrolytic capacitor.
C
6
, C
7
: Input/output AC-coupling capacitors. Use a 0.1µF to 10µF aluminum electrolytic capacitor.
+
V
OUT
Non-Polarized
1µF
PCM3500
4.7µF
V
COM
V
CC
PCM3500
OPA340
OPA343
+4.7µF
Use voltage follower
to buffer V
COM
To Bias
Nodes
V
COM
(a) Biasing an External Active Filter Stage
(b) Using a Buffer to Provide Bias for Multiple or
Low Input Impedance Nodes
®
21 PCM3500
VREF1 (pin 2) and VREF2 (pin 3) are reference voltages used
by the delta-sigma modulators. They are brought out strictly
for decoupling purposes. VREF1 and VREF2 are not to be
used to bias external circuits. A 1µF to 10µF aluminum
electrolytic or tantalum capacitor is recommended for
decoupling on each pin. These capacitors should be located
as close as possible to pins 2 and 3.
Power Supplies and Grounding
VCC (pin 24) and VDD (pin 13) should be connected directly
to the +2.7V to +3.6V analog power supply, as shown in
Figure 16. The AGNDs (pins 5, 21, and 23) and DGND (pin
14) should be connected directly to the analog ground.
Power supply bypass capacitors should be located as close
to the power supply pins as possible in order to ensure a low
impedance connection. A combination of a 10µF aluminum
electrolytic or tantalum capacitor in parallel with a 0.1µF
ceramic capacitor is recommended for both VCC and VDD.
VDD and VCC should not be connected to separate digital and
analog power supplies. This can lead to an SCR latch-up
condition, which can cause either degraded device perfor-
mance or catastrophic failures.
PCB LAYOUT GUIDELINES
The recommended PCB layout technique is shown in Figure
18. The analog and digital section of the board are separated
by a split ground plane, with the PCM3500 positioned
entirely over the analog section of the board. The AGNDs
(pins 5, 20, and 23) and DGND (pin 14) are connected
directly to the analog ground plane. The power supply pins,
VCC (pin 13) and VDD (pin 24), are routed directly to the
+2.7V to +3.6V analog power supply using wide copper
traces (100 mils or wider recommended) or a power plane.
Power supply bypass and reference decoupling capacitors
are shown located as close as possible to the PCM3500.
The PCM3500 is oriented so that the digital pins are facing
the ground plane split. Digital connections should be made
as short and direct as possible to limit high frequency
radiation and coupling. Series resistors (from 20Ω to 100Ω)
may be put in series with the system clock, FS, BCK, and
FSO lines to reduce or eliminate overshoot on clock edges,
further reducing radiated emissions. The split ground plane
should be connected at one point by a trace, wire, or ferrite
bead. Often the board will be designed to have several
jumper points for the common ground connection, so that
the best performance can be derived through experimenta-
tion.
An alternative technique, using a single power supply or
battery, is shown in Figure 19. This technique is more
suitable for portable applications.
FIGURE 18. Recommended PCB Layout Technique. FIGURE 19. PCB Layout Using a Single-Supply or Battery.
PCM3500
VCC VDD
AGND
Analog
Ground Digital
Ground
DGND
Digital Power
Supply Analog Power
Supply
+3.3V Common
Connection
DIGITAL SECTION ANALOG SECTION
Host
and
Logic
+3.3V
Digital I/Os
Split Grounds
PCM3500
V
CC
V
DD
AGND
Split Grounds
Ferrite
Beads
Analog
Ground Digital
Ground
DGND
DIGITAL SECTION ANALOG SECTION
Host
and
Logic
Common
Supply
Digital I/Os
®
22
PCM3500
OUTPUT FILTER CIRCUITS FOR THE DAC
The PCM3500’s DAC uses delta-sigma conversion tech-
niques. It uses oversampling and noise shaping to improve
in-band (f = fS/2) signal-to-noise performance at the expense
of increased out-of-band noise. The DAC output must be
low-pass filtered to attenuate the out-of-band noise to a
reasonable level.
The PCM3500 includes a low-pass filter in the on-chip
output amplifier circuit. The frequency response for this
filter is shown in Figure 20. Although this filter helps to
lower the out-of-band noise, it is not adequate for many
applications. This is especially true for applications where
the sampling frequency is below 16kHz, since the out-of-
band noise above fS/2 is in the audio spectrum. An external
filter circuit, either passive or active, is required to provide
additional attenuation of the out-of-band noise. The low-
pass filter order will be dependent upon the out-of-band
noise requirements for a particular system. Generally, a 2nd-
order or better low-pass circuit will be required, with the
cut-off frequency set to fS/2 or less.
Burr-Brown Application Bulletin AB-034 provides infor-
mation for designing both Multiple Feedback and Sallen-
Key active filter circuits using software available from Burr-
Brown’s web site. Another excellent reference for both
passive and active filter design is the “Electronic Filter
Design Handbook, Third Edition” by Williams and Taylor,
published by McGraw-Hill.
ON-CHIP ANALOG FRONT END FOR THE ADC
The PCM3500 A/D converter includes a fully differential
input delta-sigma modulator. In order to simplify connection
for single-ended applications, an analog front end (AFE)
circuit has been included on the PCM3500 just prior to the
modulator. The AFE circuit is shown in Figure 21.
FIGURE 20. DAC Output Amplifier Filter Response.
FIGURE 21. On-Chip AFE Circuit for the ADC.
50kΩ
V
IN
4
1
2
3
V
COM
V
REF
1
V
REF
2
Delta-Sigma
Modulator
(+)
(–)
Reference
+
+
1.0µF
+
+
OUTPUT FILTER
STOPBAND FREQUENCY RESPONSE
Frequency (Hz)
Amplitude (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100100 1k 10k 100k 1M 10M
OUTPUT FILTER
PASSBAND FREQUENCY RESPONSE
Frequency (Hz)
Amplitude (dB)
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10 100101 1k 10k 100k
®
23 PCM3500
ANTI-ALIASING FILTER
STOPBAND CHARACTERISTICS
Frequency (Hz)
Amplitude (dB)
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50 1k100 10k 100k 1M 10M
ANTI-ALIASING FILTER
PASSBAND CHARACTERISTICS
Frequency (Hz)
Amplitude (dB)
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0 1k100101 10k 100k
The AFE circuit consists of a single-ended-to-differential
converter, with the first stage of the circuit doubling as a
low-pass, anti-alias filter. The frequency response for the
filter is shown in Figure 22. Since the delta-sigma modulator
oversamples the input at 64fS, the anti-alias filter require-
ments are relaxed, with only a single-pole filter being re-
quired. If an application requires further band limiting of the
input signal, a simple RC filter at the VIN input (pin 4) can
be used, as shown in Figure 23.
SOFTWARE MODEM
APPLICATIONS
The PCM3500 was designed to meet the requirements for
software-based analog modems, supporting up to 56kbps(1).
In a software modem application, the PCM3500 is paired
with a Data Access Arrangement (DAA) and a host CPU to
provide the complete modem function. Figure 24 shows a
simplified block diagram of a software modem using the
PCM3500.
The DAA provides the interface between the CODEC and
two-wire telephone line. The DAA provides numerous
functions, including two-to-four wire conversion, modem-
side to line-side isolation, ring detection, hook switch con-
trol, line current compensation, and overvoltage protection.
The host CPU provides the data pump and supervisory
functions for the software modem application. The host
executes modem software code, which includes the neces-
sary routines for transmit and receive functions, error detec-
tion and correction, echo cancellation, and CODEC/DAA
control and supervision.
NOTE: (1) Data transmission is limited to 53kbps over standard telephone
lines. Actual transmission rates vary depending upon the quality of the
lines and switching equipment for a given connection.
FIGURE 22. Anti-Alias Filter Frequency Response.
FIGURE 23. Optional External Low-Pass Filter for the
ADC. FIGURE 24. Software Modem Block Diagram.
+V
IN
PCM3500
Analog
Input
R
C
f
–3dB
= 1
2π RC
Host
CPU
Controls (ring detect, off hook, etc.)
Modem
Software
PCM3500
CODEC
Data
Access
Arrangement
(DAA)
Data Tip
Ring
®
24
PCM3500
FIGURE 25. Modem AFE Application Circuit.
HLDR
LEDCT
HLDCAP
HKP
HKN
LINPWR
HLFWV
LR1
LR2
END
CEN
C1A
V
DD
V
SS
SRVCT
SRVAN
HIN
VFCAP
ONHKMC
TXAN
TXCT
C2
BIASEN
C1B
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
U1
DL207 IL388
8
7
6
5
1
2
3
4
R5
150kΩ
R6
150kΩ
C1
15nF
C
1
15nF
C3
150nF
C4
27nF
R
2
10MΩ
D2 Bridge
R1
✽
16.5Ω
1%
R9
3.9Ω
R4
356kΩ
Q2
TN2540
SOT89
Q1
MMBT6520
SOT23
R
3
10MΩ
C
23✽
0.33µF
250V
R
20✽
15kΩ
C
15
1nF
L
2
LI0805D121R
P3100BA70
✽
RV
1
L
1
LI0805D121R
D
1
CMPZDA18V
C
14
1nF
C
8✽
15nF C
2
150nF C
9
470pF
C
7
68nF
C
10
470pF
IL388
U4
U3
1
2
3
4
8
7
6
5
RING
TIP
F1
F1250T
R
19✽
2.4kΩ
1W, 2010
R
16✽
6.8MΩ
R
18✽
12Ω
Q
3✽
FZT605
Q
4✽
BC817-40
C
22
22µF, 35V
R
14✽
0Ω
+
+
C1B
V
REF
C2
RXCT
RXAN
ONHKML
ONHKM
HIN
SRVAN
SRVCT
TXMP
V
DD
C1A
LSTAT
RNG
OFFHKL
OFFHK
RXOUT
ACREF
TXBIAS
AUDIN
AUDOUT
V
SS
LEDCT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
U2
DM207
V
IN
V
OUT
V
COM
4
22
1
U5
PCM3500
R
10
10kΩ
R
7
25.5kΩ
R
13
✽
27kΩC
17
✽
4.7nF
R
14
22kΩ
RINGD
+3.3V to 7V
OH–
R
8
121kΩ
C
5
15nF
C
18
1µF
C
20
10µF
ISOLATION BARRIERISOLATION BARRIER
NOTES: All resistors are 0.1W, 5%, 0805, unless otherwise noted.
All capacitors values are 10%, unless otherwise noted.
✽ Optional components.
®
25 PCM3500
Software Modem AFE Application Circuit
Figure 25 shows an applications circuit which utilizes the
PCM3500 and the DAA2000 from Infineon Technologies
(Siemens) to implement a complete modem AFE. The
DAA2000 provides modem-side (DM207) and line-side
(DL207) interfaces, with optical isolation separating the
functions. The PCM3500 is connected to the modem-side of
the DAA2000. The PCM3500’s serial interface and hard-
ware mode controls are connected to the host CPU.
THEORY OF OPERATION
ADC SECTION
The PCM3500 A/D converter consists of two reference
circuits, a mono single-to-differential converter, a fully dif-
ferential 5th-order delta-sigma modulator, a decimation fil-
ter (including digital high pass), and a serial interface circuit.
The block diagram on the front page of this data sheet
illustrates the architecture of the ADC section, Figure 21
shows the single-to-differential converter, and Figure 26
illustrates the architecture of the 5th-order delta-sigma modu-
lator and transfer functions.
An internal reference circuit with three external capacitors
provides all reference voltages which are required by the
ADC, which defines the full-scale range for the converter.
The internal single-to-differential voltage converter saves
the design, space and extra parts needed for external cir-
cuitry required by many delta-sigma converters. The internal
full-differential signal processing architecture provides a
wide dynamic range and excellent power supply rejection
performance. The input signal is sampled at a 64x
oversampling rate, eliminating the need for a sample-and-
hold circuit, and simplifying anti-alias filtering require-
ments. The 5th-order delta-sigma noise shaper consists of
five integrators which use a switched-capacitor topology, a
comparator, and a feedback loop consisting of a one-bit
DAC. The delta-sigma modulator shapes the quantization
noise, shifting it out of the audio band in the frequency
domain. The high order of the modulator enables it to
randomize the modulator outputs, reducing idle tone levels.
The 64fS one-bit data stream from the modulator is con-
verted to 1fS, 16-bit data words by the decimation filter,
which also acts as a low-pass filter to remove the shaped
quantization noise. The DC components can be removed by
a high-pass filter function contained within the decimation
filter.
DAC SECTION
The delta-sigma DAC section of PCM3500 is based on a 5-
level amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level delta-
sigma format. A block diagram of the 5-level delta-sigma
modulator is shown in Figure 27. This 5-level delta-sigma
modulator has the advantage of stability and clock jitter
sensitivity over the typical one-bit (2 level) delta-sigma
modulator. The combined oversampling rate of the delta-
sigma modulator and the internal 8x interpolation filter is
64fS for a 512fS system clock. The theoretical quantization
noise performance of the 5-level delta-sigma modulator is
shown in Figure 28.
+
+
–
+
+
+
5th SW-CAP
Integrator
4th SW-CAP
Integrator
3rd SW-CAP
Integrator
2nd SW-CAP
Integrator
1st SW-CAP
Integrator
+
+
+
+
–
+
+
–
1-Bit
DAC
H(z)
Qn(z)
Analog In
X(z)
Digital Out
Y(z)
Y(z) = STF(z) • X(z) + NTF(z) • Qn(z)
Signal Transfer Function
Noise Transfer Function STF(z) = H(z)/[1 + H(z)]
NTF(z) = 1/[1 + H(z)]
Comparator
FIGURE 26. Simplified 5th-Order Delta-Sigma Modulator.
®
26
PCM3500
Out
64f
S
In 8f
S
18-Bit
+++
4
3
2
1
0
5-level Quantizer
+
–
+Z
–1
+
–
+Z
–1
+
+Z
–1
FIGURE 27. 5-Level Delta-Sigma Modulator Block Digram.
FIGURE 28. Quantization Noise Spectrum.
3rd-ORDER ∆Σ MODULATOR
Frequency (kHz)
Gain (–dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150 0 5 10 15 20 25 30
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCM3500E ACTIVE SSOP DB 24 58 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3500E/2K ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3500E/2KG4 ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3500EG4 ACTIVE SSOP DB 24 58 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Nov-2005
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM3500E/2K SSOP DB 24 2000 330.0 17.4 8.5 8.6 2.4 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM3500E/2K SSOP DB 24 2000 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2008
Pack Materials-Page 2
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