JM38510/11401BG - National Semiconductor

TL/H/5646

LF155/LF156/LF157 Series Monolithic JFET Input Operational Amplifiers

December 1994

LF155/LF156/LF157 Series Monolithic

JFET Input Operational Amplifiers

General Description

These are the first monolithic JFET input operational ampli-

fiers to incorporate well matched, high voltage JFETs on the

same chip with standard bipolar transistors (BI-FETTM Tech-

nology). These amplifiers feature low input bias and offset

currents/low offset voltage and offset voltage drift, coupled

with offset adjust which does not degrade drift or common-

mode rejection. The devices are also designed for high slew

rate, wide bandwidth, extremely fast settling time, low volt-

age and current noise and a low 1/f noise corner.

Advantages

YReplace expensive hybrid and module FET op amps

YRugged JFETs allow blow-out free handling compared

with MOSFET input devices

YExcellent for low noise applications using either high or

low source impedanceÐvery low 1/f corner

YOffset adjust does not degrade drift or common-mode

rejection as in most monolithic amplifiers

YNew output stage allows use of large capacitive loads

(5,000 pF) without stability problems

YInternal compensation and large differential input volt-

age capability

Applications

YPrecision high speed integrators

YFast D/A and A/D converters

YHigh impedance buffers

YWideband, low noise, low drift amplifiers

YLogarithmic amplifiers

YPhotocell amplifiers

YSample and Hold circuits

Common Features

(LF155A, LF156A, LF157A)

YLow input bias current 30 pA

YLow Input Offset Current 3 pA

YHigh input impedance 1012X

YLow input offset voltage 1 mV

YLow input offset voltage temp. drift 3 mV/§C

YLow input noise current 0.01 pA/0Hz

YHigh common-mode rejection ratio 100 dB

YLarge dc voltage gain 106 dB

Uncommon Features

YExtremely

fast settling

time to

0.01%

YFast slew

rate

YWide gain

bandwidth

YLow input

noise voltage

LF155A LF156A LF157A Units

(AVe5)

4 1.5 1.5 ms

51250V/ms

2.5 5 20 MHz

20 12 12 nV/0Hz

Simplified Schematic

*3 pF in LF157 series. TL/H/5646–1

BI-FETTM, BI-FET IITM are trademarks of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings

If Military/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors for

availability and specifications.

(Note 8)

LF155A/6A/7A LF155/6/7 LF355B/6B/7B LF355/6/7

LF255/6/7 LF355A/6A/7A

Supply Voltage g22V g22V g22V g18V

Differential Input Voltage g40V g40V g40V g30V

Input Voltage Range (Note 2) g20V g20V g20V g16V

Output Short Circuit Duration Continuous Continuous Continuous Continuous

TjMAX

H-Package 150§C 150§C 115§C 115§C

N-Package 100§C 100§C

M-Package 100§C 100§C

Power Dissipation at TAe25§C (Notes 1 and 9)

H-Package (Still Air) 560 mW 560 mW 400 mW 400 mW

H-Package (400 LF/Min Air Flow) 1200 mW 1200 mW 1000 mW 1000 mW

N-Package 670 mW 670 mW

M-Package 380 mW 380 mW

Thermal Resistance (Typical) iJA

H-Package (Still Air) 160§C/W 160§C/W 160§C/W 160§C/W

H-Package (400 LF/Min Air Flow) 65§C/W 65§C/W 65§C/W 65§C/W

N-Package 130§C/W 130§C/W

M-Package 195§C/W 195§C/W

(Typical) iJC

H-Package 23§C/W 23§C/W 23§C/W 23§C/W

Storage Temperature Range b65§Ctoa

150§Cb65§Ctoa

150§C

Soldering Information (Lead Temp.)

Metal Can Package

Soldering (10 sec.) 300§C 300§C 300§C 300§C

Dual-In-Line Package

Soldering (10 sec.) 260§C 260§C 260§C

Small Outline Package

Vapor Phase (60 sec.) 215§C 215§C

Infrared (15 sec.) 220§C 220§C

See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering surface

mount devices.

ESD tolerance

(100 pF discharged through 1.5 kX) 1000V 1000V 1000V 1000V

DC Electrical Characteristics (Note 3) TAeTje25§C

Symbol Parameter Conditions LF155A/6A/7A LF355A/6A/7A Units

Min Typ Max Min Typ Max

VOS Input Offset Voltage RSe50X,T

25§C1212mV

Over Temperature 2.5 2.3 mV

DVOS/DT Average TC of Input RSe50X35 35mV/§C

Offset Voltage

DTC/DVOS Change in Average TC RSe50X, (Note 4) 0.5 0.5 mV/§C

with VOS Adjust per mV

IOS Input Offset Current Tje25§C, (Notes 3, 5) 3 10 3 10 pA

TjsTHIGH 10 1 nA

IBInput Bias Current Tje25§C, (Notes 3, 5) 30 50 30 50 pA

TjsTHIGH 25 5 nA

RIN Input Resistance Tje25§C10

12 1012 X

AVOL Large Signal Voltage VSeg15V, TAe25§C 50 200 50 200 V/mV

Gain VOeg10V, RLe2k 25 25 V/mV

Over Temperature

VOOutput Voltage Swing VSeg15V, RLe10k g12 g13 g12 g13 V

VSeg15V, RLe2k g10 g12 g10 g12 V

DC Electrical Characteristics (Note 3) TAeTje25§C (Continued)

Symbol Parameter Conditions LF155A/6A/7A LF355A/6A/7A Units

Min Typ Max Min Typ Max

VCM Input Common-Mode VSeg15V g11 a15.1 g11 a15.1 V

Voltage Range b12 b12 V

CMRR Common-Mode Rejection 85 100 85 100 dB

Ratio

PSRR Supply Voltage Rejection (Note 6) 85 100 85 100 dB

Ratio

AC Electrical Characteristics TAeTje25§C, VSeg15V

Symbol Parameter Conditions LF155A/355A LF156A/356A LF157A/357A Units

Min Typ Max Min Typ Max Min Typ Max

SR Slew Rate LF155A/6A; AVe1, 3 5 10 12 V/ms

LF157A; AVe54050V/ms

GBW Gain Bandwidth 2.5 4 4.5 15 20 MHz

Product

tsSettling Time to 0.01% (Note 7) 4 1.5 1.5 ms

enEquivalent Input Noise RSe100X

Voltage fe100 Hz 25 15 15 nV/0Hz

fe1000 Hz 20 12 12 nV/0Hz

inEquivalent Input fe100 Hz 0.01 0.01 0.01 pA/0Hz

Noise Current fe1000 Hz 0.01 0.01 0.01 pA/0Hz

CIN Input Capacitance 3 3 3 pF

DC Electrical Characteristics (Note 3)

Symbol Parameter Conditions LF155/6/7 LF255/6/7 LF355/6/7 Units

LF355B/6B/7B

Min Typ Max Min Typ Max Min Typ Max

VOS Input Offset Voltage RSe50X,T

25§C 3 5 3 5 3 10 mV

Over Temperature 7 6.5 13 mV

DVOS/DT Average TC of Input RSe50X555mV/§C

Offset Voltage

DTC/DVOS Change in Average TC RSe50X, (Note 4) 0.5 0.5 0.5 mV/§C

with VOS Adjust per mV

IOS Input Offset Current Tje25§C, (Notes 3, 5) 3 20 3 20 3 50 pA

TjsTHIGH 20 1 2 nA

IBInput Bias Current Tje25§C, (Notes 3, 5) 30 100 30 100 30 200 pA

TjsTHIGH 50 5 8 nA

RIN Input Resistance Tje25§C10

12 1012 1012 X

AVOL Large Signal Voltage VSeg15V, TAe25§C 50 200 50 200 25 200 V/mV

Gain VOeg10V, RLe2k

Over Temperature 25 25 15 V/mV

VOOutput Voltage Swing VSeg15V, RLe10k g12 g13 g12 g13 g12 g13 V

VSeg15V, RLe2k g10 g12 g10 g12 g10 g12 V

VCM Input Common-Mode VSeg15V g11 a15.1 g11 g15.1 a10 a15.1 V

Voltage Range b12 b12 b12 V

CMRR Common-Mode Rejec- 85 100 85 100 80 100 dB

tion Ratio

PSRR Supply Voltage Rejec- (Note 6) 85 100 85 100 80 100 dB

tion Ratio

DC Electrical Characteristics TAeTje25§C, VSeg15V

LF155A/155, LF156A/156, LF157A/157

Parameter LF255, LF355 LF256/356B LF356A/356 LF257/357B LF357A/357 Units

LF355A/355B

Typ Max Typ Max Typ Max Typ Max Typ Max Typ Max

Supply Current 2 4 2 4 5 7 5 10 5 7 5 10 mA

AC Electrical Characteristics TAeTje25§C, VSeg15V

LF155/255/ LF156/256, LF156/256/ LF157/257, LF157/257/

Symbol Parameter Conditions 355/355B LF356B 356/356B LF357B 357/357B Units

Typ Min Typ Min Typ

SR Slew Rate LF155/6: AVe1, 5 7.5 12 V/ms

LF157: AVe53050V/ms

GBW Gain Bandwidth 2.5 5 20 MHz

Product

tsSettling Time to 0.01% (Note 7) 4 1.5 1.5 ms

enEquivalent Input Noise RSe100X

Voltage fe100 Hz 25 15 15 nV/0Hz

fe1000 Hz 20 12 12 nV/0Hz

inEquivalent Input fe100 Hz 0.01 0.01 0.01 pA/0Hz

Current Noise fe1000 Hz 0.01 0.01 0.01 pA/0Hz

CIN Input Capacitance 3 3 3 pF

Notes for Electrical Characteristics

Note 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TjMAX,ijA, and the ambient temperature,

TA. The maximum available power dissipation at any temperature is Pde(TjMAXbTA)/ijA or the 25§CP

dMAX, whichever is less.

Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.

Note 3: Unless otherwise stated, these test conditions apply:

LF155A/6A/7A LF255//6/7 LF355A/6A/7A LF355B/6B/7B LF355//6/7

LF155//6/7

Supply Voltage, VSg15VsVSsg20V g15VsVSsg20V g15VsVSsg18V g15VsVSg20V VSeg15V

TAb55§CsTAsa125§Cb25§CsTAsa85§C0

70§C0

70§C

THIGH a125§Ca85§Ca70§Ca70§Ca70§C

and VOS,I

Band IOS are measured at VCMe0.

Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5mV/§C typically) for each mV of adjustment from its

original unadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment.

Note 5: The input bias currents are junction leakage currents which approximately double for every 10§C increase in the junction temperature, TJ. Due to limited

production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient

temperature as a result of internal power dissipation, Pd. TjeTAaijA Pd where ijA is the thermal resistance from junction to ambient. Use of a heat sink is

recommended if input bias current is to be kept to a minimum.

Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.

Note 7: Settling time is defined here, for a unity gain inverter connection using 2 kXresistors for the LF155/6. It is the time required for the error voltage (the

voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is applied to the inverter. For the LF157,

AVeb5, the feedback resistor from output to input is 2 kXand the output step is 10V (See Settling Time Test Circuit).

Note 8: Refer to RETS155AX for LF155A, RETS155X for LF155, RETS156AX for LF156A, RETS156X for LF156, RETS157A for LF157A and RETS157X for

LF157 military specifications.

Note 9: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate

outside guaranteed limits.

Typical DC Performance Characteristics

Curves are for LF155, LF156 and LF157 unless otherwise specified.

Input Bias Current Input Bias Current Input Bias Current

Voltage Swing Supply Current Supply Current

Negative Current Limit Positive Current Limit

Positive Common-Mode

Input Voltage Limit

TL/H/5646–2

Negative Common-Mode

Input Voltage Limit Open Loop Voltage Gain Output Voltage Swing

TL/H/5646–3

Typical AC Performance Characteristics

Gain Bandwidth Gain Bandwidth Normalized Slew Rate

TL/H/5646–4

Output Impedance Output Impedance Output Impedance

TL/H/5646–12

LF155 Small Signal Pulse

Response, AVea1

TL/H/5646–5

LF156 Small Signal Pulse

Response, AVea1

TL/H/5646–6

Small Signal Pulse

Response, AVea5

TL/H/5646–7

LF155 Large Signal Pulse

Response, AVea1

TL/H/5646–8

LF156 Large Signal Pulse

Response, AVea1

TL/H/5646–9

LF157 Large Signal Pulse

Response, AVea5

TL/H/5646–10

Typical AC Performance Characteristics (Continued)

Inverter Settling Time Inverter Settling Time

Open Loop Frequency

Response

Bode Plot Bode Plot Bode Plot

Common-Mode Rejection

Ratio Power Supply Rejection Ratio Power Supply Rejection Ratio

Undistorted Output Voltage

Swing

Equivalent Input Noise

Voltage

Equivalent Input Noise

Voltage (Expanded Scale)

TL/H/5646–11

Detailed Schematic

*Ce3 pF in LF157 series. TL/H/5646–13

Connection Diagrams (Top Views)

Metal Can Package (H)

TL/H/5646–14

Order Number LF156AH, LF155H, LF156H, LF255H,

LF256H, LF257H, LF355AH, LF356AH,

LF357AH, LF356BH, LF355H, LF356H,

LF357H, LM155AH/883, LM155H/883, LM156AH/883,

LM156H/883, LM157AH/883 or LM157H/883*

See NS Package Number H08C

Dual-In-Line Package (M and N)

TL/H/5646–29

Order Number LF355M, LF356M, LF357M, LF355BM,

LF356BM, LF355BN, LF356BN, LF357BN, LF355N,

LF356N or LF357N

See NS Package Number M08A or N08E

*Available per JM38510/11401 or JM38510/11402

Application Hints

The LF155/6/7 series are op amps with JFET input de-

vices. These JFETs have large reverse breakdown voltages

from gate to source and drain eliminating the need for

clamps across the inputs. Therefore large differential input

voltages can easily be accomodated without a large in-

crease in input current. The maximum differential input volt-

age is independent of the supply voltages. However, neither

of the input voltages should be allowed to exceed the nega-

tive supply as this will cause large currents to flow which

can result in a destroyed unit.

Exceeding the negative common-mode limit on either input

will force the output to a high state, potentially causing a

reversal of phase to the output. Exceeding the negative

common-mode limit on both inputs will force the amplifier

output to a high state. In neither case does a latch occur

since raising the input back within the common-mode range

again puts the input stage and thus the amplifier in a normal

operating mode.

Exceeding the positive common-mode limit on a single input

will not change the phase of the output however, if both

inputs exceed the limit, the output of the amplifier will be

forced to a high state.

These amplifiers will operate with the common-mode input

voltage equal to the positive supply. In fact, the common-

mode voltage can exceed the positive supply by approxi-

mately 100 mV independent of supply voltage and over the

full operating temperature range. The positive supply can

therefore be used as a reference on an input as, for exam-

ple, in a supply current monitor and/or limiter.

Precautions should be taken to ensure that the power sup-

ply for the integrated circuit never becomes reversed in

polarity or that the unit is not inadvertently installed back-

wards in a socket as an unlimited current surge through the

resulting forward diode within the IC could cause fusing of

the internal conductors and result in a destroyed unit.

All of the bias currents in these amplifiers are set by FET

current sources. The drain currents for the amplifiers are

therefore essentially independent of supply voltage.

As with most amplifiers, care should be taken with lead

dress, component placement and supply decoupling in or-

der to ensure stability. For example, resistors from the out-

put to an input should be placed with the body close to the

input to minimize ‘‘pickup’’ and maximize the frequency of

the feedback pole by minimizing the capacitance from the

input to ground.

A feedback pole is created when the feedback around any

amplifier is resistive. The parallel resistance and capaci-

tance from the input of the device (usually the inverting in-

put) to ac ground set the frequency of the pole. In many

instances the frequency of this pole is much greater than

the expected 3 dB frequency of the closed loop gain and

consequently there is negligible effect on stability margin.

However, if the feedback pole is less than approximately six

times the expected 3 dB frequency a lead capacitor should

be placed from the output to the input of the op amp. The

value of the added capacitor should be such that the RC

time constant of this capacitor and the resistance it parallels

is greater than or equal to the original feedback pole time

constant.

Typical Circuit Connections

VOS Adjustment

#VOS is adjusted with a 25k potenti-

ometer

#The potentiometer wiper is con-

nected to Va

#For potentiometers with tempera-

ture coefficient of 100 ppm/§Cor

less the additional drift with adjust

is &0.5 mV/§C/mV of adjustment

#Typical overall drift: 5 mV/§Cg(0.5

mV/§C/mV of adj.)

Driving Capacitive Loads LF157. A Large Power BW Amplifier

TL/H/5646–15

*LF155/6 Re5k

LF157 Re1.25k

Due to a unique output stage design, these am-

plifiers have the ability to drive large capacitive

loads and still maintain stability. CL(MAX) j0.01

mF.

Overshoot s20%

Settling time (ts)j5ms

For distortion s1% and a 20 Vp-p VOUT swing,

power bandwidth is: 500 kHz.

Typical Applications

Settling Time Test Circuit

#Settling time is tested with the LF155/6 connected

as unity gain inverter and LF157 connected for

AVeb

#FET used to isolate the probe capacitance

#Output e10V step

#AVeb

5 for LF157

TL/H/5646–16

Large Signal inverter Output, VOUT (from Settling Time Circuit)

LF355

TL/H/5646–17

LF356

TL/H/5646–18

LF357

TL/H/5646–19

Low Drift Adjustable Voltage Reference

TL/H/5646–20

#DVOUT/DTeg0.002%/§C

#All resistors and potentiometers should be wire-wound

#P1: drift adjust

#P2: VOUT adjust

#Use LF155 for

XLow IB

XLow drift

XLow supply current

Typical Applications (Continued)

Fast Logarithmic Converter

TL/H/5646–21

#Dynamic range: 100 mAsIis1 mA (5 dec-

ades),

e1V/decade

#Transient response: 3 ms for DIie1 decade

#C1, C2, R2, R3: added dynamic compensation

#VOS adjust the LF156 to minimize quiescent error

#RT: Tel Labs type Q81 a0.3%/§C

VOUT

eÐ1aR2

RT(kT

qln ViÐRr

VREF Ri (elog Vi

RiIr

R2 e15.7k, RTe1k, 0.3%/§C (for temperature compensation)

Precision Current Monitor

TL/H/5646–31

#VOe5 R1/R2 (V/mA of IS)

#R1, R2, R3: 0.1% resistors

#Use LF155 for

XCommon-mode range to supply range

XLow IB

XLow VOS

XLow Supply Current

8-Bit D/A Converter with Symmetrical Offset Binary Operation

TL/H/5646–32

#R1, R2 should be matched within g0.05%

#Full-scale response time: 3ms

EOB1 B2 B3 B4 B5 B6 B7 B8 Comments

a9.920 1 1 1 1 1 1 1 1 Positive Full-Scale

a0.040 1 0 0 0 0 0 0 0 (a) Zero-Scale

b0.040 0 1 1 1 1 1 1 1 (b) Zero-Scale

b9.920 0 0 0 0 0 0 0 0 Negative Full-Scale

Typical Applications (Continued)

Wide BW Low Noise, Low Drift Amplifier Isolating Large Capacitive Loads

TL/H/5646–22

#Power BW: fMAX eSr

2qVP

j191 kHz

#Parasitic input capacitance C1 j(3 pF for LF155, LF156 and LF157 plus

any additional layout capacitance) interacts with feedback elements and

creates undesirable high frequency pole. To compensate add C2 such

that: R2 C2 jR1 C1.

#Overshoot 6%

#ts10 ms

#When driving large CL, the VOUT slew rate determined by CLand

IOUT(MAX):

DVOUT

DTeIOUT

j0.02

0.5 V/mse0.04 V/ms (with CLshown)

Boosting the LF156 with a Current Amplifier

Low Drift Peak Detector

TL/H/5646

#IOUT(MAX)j150 mA (will drive RLt100X)

#DVOUT

DTe0.15

10b2V/ms (with CLshown)

#No additional phase shift added by the current amplifier

3 Decades VCO

#By adding D1 and Rf,V

D1e0 during hold mode. Leakage of D2 provided

by feedback path through Rf.

#Leakage of circuit is essentially Ib(LF155, LF156) plus capacitor leakage

of Cp.

#Diode D3 clamps VOUT (A1) to VINbVD3 to improve speed and to limit

reverse bias of D2.

#Maximum input frequency should be kk (/2qRfCD2 where CD2 is the

shunt capacitance of D2.

TL/H/5646–24

feVC(R8aR7)

(8 VPU R8 R1) C,0

30V, 10 Hzsfs10 kHz

R1, R4 matched. Linearity 0.1% over 2 decades.

Non-Inverting Unity Gain Operation for LF157

Inverting Unity Gain for LF157

TL/H/5646–25

R1C t1

(2q) (5 MHz)

R1 eR2 aRS

AV(DC) e1

fb3dB&5 MHz

R1C t1

(2q) (5 MHz)

R1 eR2

AV(DC) eb

3dB&5 MHz

Typical Applications (Continued)

High Impedance, Low Drift Instrumentation Amplifier

TL/H/5646–26

#VOUT eR3

RÐ2R2

R1 a1(DV, Vba2V sVIN common-mode sVa

#System VOS adjusted via A2 VOS adjust

#Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier

resistor array recommended for best accuracy and lowest drift

Typical Applications (Continued)

Fast Sample and Hold

TL/H/5646–33

#Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible)

#Acquisition time TA, estimated by:

TAjÐ2RON,V

IN,C

r((/2 provided that:

VIN k2qSrRON Chand TAlVIN Ch

IOUT(MAX)

ON is of SW1

If inequality not satisfied: TAjVIN Ch

20 mA

#LF156 develops full Sroutput capability for VINt1V

#Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop

#Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2

High Accuracy Sample and Hold

TL/H/5646–27

#By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1.

No VOS adjust required for A2.

#TAcan be estimated by same considerations as previously but, because of the added

propagation delay in the feedback loop (A2) the overshoot is not negligible.

#Overall system slower than fast sample and hold

#R1, CC: additional compensation

#Use LF156 for

XFast settling time

XLow VOS

Typical Applications (Continued)

High Q Band Pass Filter

TL/H/5646–28

#By adding positive feedback (R2)

Q increases to 40

#fBPe100 kHz

VOUT

VIN

e100Q

#Clean layout recommended

#Response to a 1 Vp-p tone burst:

300 ms

High Q Notch Filter

TL/H/5646–34

#2R1 eRe10 MX

2C eC1 e300 pF

#Capacitors should be matched to obtain high Q

#fNOTCH e120 Hz, notch eb

55 dB, Q l

100

#Use LF155 for

XLow IB

XLow supply current

Physical Dimensions inches (millimeters)

Metal Can Package (H)

Order Number LF156AH, LF155H, LF156H, LF255H, LF256H, LF257H, LF355AH, LF356AH, LF357AH, LF356BH,

LF355H, LF356H or LF357H

NS Package Number H08C

Small Outline Package (M)

Order Number LF355M, LF356M, LF357M, LF355BM or LF356BM

NS Package Number M08A

LF155/LF156/LF157 Series Monolithic JFET Input Operational Amplifiers

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number LF355N, LF356N, LF357N, LF355BN, LF356BN, LF357BN

NS Package Number N08E

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with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

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