KS0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
January.2000
Ver. 4.0
Prepared by: Jae-Su, Ko
Ko1942@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
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KS0715 Specification Revision History
Version Content Date
1.0
CAP3P → C3+, CAP2P → C2+, CAP1P → C1+
CAP3M → C3-, CAP2M → C2-, CAP1M → C1-
Oscillator frequency
FOSC (kHz) = → 19 (Min.): 22.5 (Typ.): 26 (Max.)
FCL (kHz) = → 2.37 (Min.): 2.81 (Typ.): 3.25 (Max.)
2.0
Temperature coefficient
TEMPS = L: -0.0%/°C → -0.05%/°C
Absolute maximum ratings
VLCD: +0.3 to +15.0 → -0.3 to +17.0
Dynamic current consumption
IDD1: 40µA (Max.)
IDD2: 75µA (Typ.), 100µA (Max.)
3.0
Oscillator frequency (internal)
19: 22.5: 26 → 17: 22.5: 27
Oscillator frequency (external)
2.13: 2.81: 3.25 → 2.13: 2.81: 3.37
3.1 Apr.1999
4.0 Change VDD Range : 2.4V to 5.5V → 2.4V to 3.6V Jan.2000
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
3
CO
NTENTS
INTRODUCTION ..................................................................................................................................................1
FEATURES..........................................................................................................................................................1
BLOCK DIAGRAM...............................................................................................................................................3
PAD CONFIGURATION .......................................................................................................................................4
PAD CENTER COORDINATES............................................................................................................................5
PIN DESCRIPTION ..............................................................................................................................................7
POWER SUPPLY..........................................................................................................................................7
LCD DRIVER SUPPLY..................................................................................................................................7
SYSTEM CONTROL .....................................................................................................................................8
MICROPROCESSOR INTERFACE...............................................................................................................9
LCD DRIVER OUTPUTS.............................................................................................................................11
TEST PINS..................................................................................................................................................11
FUNCTIONAL DESCRIPTION............................................................................................................................12
MICROPROCESSOR INTERFACE.............................................................................................................12
DISPLAY DATA RAM (DDRAM)..................................................................................................................16
LCD DISPLAY CIRCUITS............................................................................................................................19
LCD DRIVER CIRCUIT ...............................................................................................................................21
POWER SUPPLY CIRCUITS ......................................................................................................................22
REFERECE CIRCUIT EXAMPLES..............................................................................................................28
RESET CIRCUIT.........................................................................................................................................29
INSTRUCTION DESCRIPTION...........................................................................................................................30
SPECIFICATIONS..............................................................................................................................................43
ABSOLUTE MAXIMUM RATINGS...............................................................................................................43
DC CHARACTERISTICS.............................................................................................................................44
REFERENCE DATA....................................................................................................................................47
AC CHARACTERISTICS.............................................................................................................................49
REFERENCE APPLICATIONS...........................................................................................................................53
MICROPROCESSOR INTERFACE.............................................................................................................53
CONNECTIONS BETWEEN KS0715 AND LCD PANEL..............................................................................54
TCP PIN LAYOUT (SAMPLE)......................................................................................................................57
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
1
INTRODUCTION
The KS0715 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 33
common and 100 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8-
bit parallel display data and stores in an on-chip display data RAM of 65 x 132 bits. It provides a highly-flexible
display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it
performs display data RAM read/write operation with no external operating clock to minimize power consumption.
In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a
display system with the fewest components.
FEATURES
Driver Output Circuits
−33 common outputs / 100 segment outputs
On-chip Display Data RAM
−Capacity: 65 x 132 = 8,580 bits
−Bit data "1": a dot of display is illuminated.
−Bit data "0": a dot of display is not illuminated.
Multi-chip Operation (Master, Slave) Available
Applicable Duty Ratios
Duty ratio Applicable LCD bias Maximum display area
1/33 1/5 or 1/6 33 × 100
Microprocessor Interface
−8-bit parallel bi-directional interface with 6800-series or 8080-series
−Serial interface (only write operation) available
Various Instruction Setting
On-chip Low Power Analog Circuit
−On-chip oscillator circuit
−Voltage converter (x2, x3 and x4)
−Voltage regulator (temperature coefficient: -0.05%/°C, -0.2%/°C)
−On-chip electronic contrast control function (32 steps)
−Voltage follower (LCD bias: 1/5 or 1/6)
Operating Voltage Range
−Supply voltage (VDD): 2.4 to 3.6 V
−LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V
Low Power Consumption
−100 µΑ Typ. (VDD = 3V, x4 boosting, V0 = 8V, internal power supply ON and display OFF)
−10 µΑ Max. (during power save [standby] mode)
Wide Operating Temperature Range
−Ta = -40°C to +85°C
Package Type
− Gold bumped chip or TCP
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
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Series Specifications
Product code TEMPS pin Temp. coefficient Package Chip thickness
KS0715UM-L0CC 670 µm
KS0715UM-L4CC 0
(VSS connected) -0.05%/°C470 µm
KS0715UM-H0CC 670 µm
KS0715UM-H4CC 1
(VDD connected) -0.2%/°C
COG
470 µm
KS0715TB-XX-L0TF 670 µm
KS0715TB-XX-L4TF 0
(VSS connected) -0.05%/°C470 µm
KS0715TB-XX-H0TF 670 µm
KS0715TB-XX-H4TF 1
(VDD connected) -0.2%/°C
TCP
470 µm
* XX: TCP ordering number
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
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BLOCK DIAGRAM
MS
CL
M
FRS
DISP
VDD
V0
V1
V2
V3
V4
V
SS
V0
VR
TEMPS
VOUT
C1-
C1+
C2-
C2+
C3-
C3+
V / C
CIRCUIT
V / R
CIRCUIT
V / F
CIRCUIT
34 COMMON
DRIVER CIRCUITS
MPU INTERFACE (PARALLEL & SERIAL)
INSTRUCTION DECODERBUS HOLDER
COLUMN ADDRESS
CIRCUIT
LINE
ADDRESS
CIRCUIT
PAGE
ADDRESS
CIRCUIT
DISPLAY DATA RAM
65 X 132 = 8,580 Bits
SEGMENT CONTROLLER
DISPLAY
TIMING
GENERATOR
CIRCUIT
COMMON CONTROLLER
DB0
DB1
DB2
DB3
DB4
DB5
DB6(SCLK)
DB7(SID)
MI
RESETB
PS
RW_WR
E_RD
RS
CS2
CS1B
COMS
COM31
:
:
COM0
COMS
SEG99
SEG98
:
SEG66
SEG65
SEG64
:
SEG1
SEG0
OSCILLATOR
I/O
BUFFER
STATUS REGISTER INSTRUCTION REGISTER
TESTL2
100 SEGMENT
DRIVER CIRCUITS
TESTL1
Figure 1. Block Diagram
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
4
PAD CONFIGURATION
ððð
ððððððððððððððððððð
- - - - - - - - - -
ððððððððððððððððððð
ððð
Y
108
209
107
210
83
234
82
1
KS0715
(TOP VIEW) (0,0) X
ðððððððððððððððððððððð
- - - - - - - - - -
ððððððððððððððððððððððð
ðððð
- - - -
ðððð
ðððð
- - - -
ðððð
Figure 2. KS0715 Chip Configuration
Table 1. KS0715 Pad Dimensions
Size
Item Pad No. X Y Unit
Chip size -7980 2700
1 to 82 90
Pad pitch 83 to 234 70
1 to 82 56 114
83 to 107 108 50
108 to 209 50 108
Bumped pad size
210 to 234 108 50
Bumped pad height All pad 17 (Typ.)
µm
COG Align Key Coordinate ILB Align Key Coordinate
30µm30µm30µm
(-3832, -1055)
30µm30µm30µm
(+3832, -1070)
30µm
30µm
30µm
60µm
30µm
42µm108µm
42µm
108µm
42µm
108µm
(-3870, +1230)
(+3870, +1230)
42µm108µm
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
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PAD CENTER COORDINATES
Table 2. Pad Center Coordinates
[Unit: µm]
No. Name X Y No. Name X Y No. Name X Y
1DUMMY -3645 -1226 51 C1+ 855 -1226 101 COM1 3830 420
2TESTL1 -3555 -1226 52 C1+ 945 -1226 102 COM0 3830 490
3VDD -3465 -1226 53 C1- 1035 -1226 103 COMS 3830 560
4FRS -3375 -1226 54 C1- 1125 -1226 104 DUMMY 3830 630
5M-3285 -1226 55 C2+ 1215 -1226 105 DUMMY 3830 700
6CL -3195 -1226 56 C2+ 1305 -1226 106 DUMMY 3830 770
7DISP -3105 -1226 57 C2- 1395 -1226 107 DUMMY 3830 840
8VDD -3015 -1226 58 C2- 1485 -1226 108 DUMMY 3535 1190
9MS -2925 -1226 59 VSS 1575 -1226 109 SEG0 3465 1190
10 VSS -2835 -1226 60 VSS 1665 -1226 110 SEG1 3395 1190
11 RESETB -2745 -1226 61 VR 1755 -1226 111 SEG2 3325 1190
12 VDD -2655 -1226 62 VR 1845 -1226 112 SEG3 3255 1190
13 PS -2565 -1226 63 V0 1935 -1226 113 SEG4 3185 1190
14 VSS -2475 -1226 64 V0 2025 -1226 114 SEG5 3115 1190
15 CS1B -2385 -1226 65 V0 2115 -1226 115 SEG6 3045 1190
16 CS2 -2295 -1226 66 V0 2205 -1226 116 SEG7 2975 1190
17 VDD -2205 -1226 67 V0 2295 -1226 117 SEG8 2905 1190
18 MI -2115 -1226 68 V0 2385 -1226 118 SEG9 2835 1190
19 VSS -2025 -1226 69 V1 2475 -1226 119 SEG10 2765 1190
20 VDD -1935 -1226 70 V1 2565 -1226 120 SEG11 2695 1190
21 RS -1845 -1226 71 V2 2655 -1226 121 SEG12 2625 1190
22 VSS -1755 -1226 72 V2 2745 -1226 122 SEG13 2555 1190
23 RW_WR -1665 -1226 73 V3 2835 -1226 123 SEG14 2485 1190
24 E_RD -1575 -1226 74 V3 2925 -1226 124 SEG15 2415 1190
25 VDD -1485 -1226 75 V4 3015 -1226 125 SEG16 2345 1190
26 VDD -1395 -1226 76 V4 3105 -1226 126 SEG17 2275 1190
27 VDD -1305 -1226 77 VSS 3195 -1226 127 SEG18 2205 1190
28 VDD -1215 -1226 78 VSS 3285 -1226 128 SEG19 2135 1190
29 VDD -1125 -1226 79 TEMPS 3375 -1226 129 SEG20 2065 1190
30 VDD -1035 -1226 80 VDD 3465 -1226 130 SEG21 1995 1190
31 DB0 -945 -1226 81 TESTL2 3555 -1226 131 SEG22 1925 1190
32 DB1 -855 -1226 82 DUMMY 3645 -1226 132 SEG23 1855 1190
33 DB2 -765 -1226 83 DUMMY 3830 -840 133 SEG24 1785 1190
34 DB3 -675 -1226 84 DUMMY 3830 -770 134 SEG25 1715 1190
35 DB4 -585 -1226 85 DUMMY 3830 -700 135 SEG26 1645 1190
36 DB5 -495 -1226 86 DUMMY 3830 -630 136 SEG27 1575 1190
37 DB6 -405 -1226 87 COM15 3830 -560 137 SEG28 1505 1190
38 DB7 -315 -1226 88 COM14 3830 -490 138 SEG29 1435 1190
39 VSS -225 -1226 89 COM13 3830 -420 139 SEG30 1365 1190
40 VSS -135 -1226 90 COM12 3830 -350 140 SEG31 1295 1190
41 VSS -45 -1226 91 COM11 3830 -280 141 SEG32 1225 1190
42 VSS 45 -1226 92 COM10 3830 -210 142 SEG33 1155 1190
43 VSS 135 -1226 93 COM9 3830 -140 143 SEG34 1085 1190
44 VSS 225 -1226 94 COM8 3830 -70 144 SEG35 1015 1190
45 VOUT 315 -1226 95 COM7 3830 0145 SEG36 945 1190
46 VOUT 405 -1226 96 COM6 3830 70 146 SEG37 875 1190
47 C3+ 495 -1226 97 COM5 3830 140 147 SEG38 805 1190
48 C3+ 585 -1226 98 COM4 3830 210 148 SEG39 735 1190
49 C3- 675 -1226 99 COM3 3830 280 149 SEG40 665 1190
50
C3-
765
-1226
100
COM2
3830
350
150
SEG41
595
1190
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
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Table 2. Pad Center Coordinates (Continued)
[Unit: µm]
No. Name X Y No. Name X Y No. Name X Y
151 SEG42 525 1190 201 SEG92 -2975 1190
152 SEG43 455 1190 202 SEG93 -3045 1190
153 SEG44 385 1190 203 SEG94 -3115 1190
154 SEG45 315 1190 204 SEG95 -3185 1190
155 SEG46 245 1190 205 SEG96 -3255 1190
156 SEG47 175 1190 206 SEG97 -3325 1190
157 SEG48 105 1190 207 SEG98 -3395 1190
158 SEG49 35 1190 208 SEG99 -3465 1190
159 SEG50 -35 1190 209 DUMMY -3535 1190
160 SEG51 -105 1190 210 DUMMY -3830 840
161 SEG52 -175 1190 211 DUMMY -3830 770
162 SEG53 -245 1190 212 DUMMY -3830 700
163 SEG54 -315 1190 213 DUMMY -3830 630
164 SEG55 -385 1190 214 COM16 -3830 560
165 SEG56 -455 1190 215 COM17 -3830 490
166 SEG57 -525 1190 216 COM18 -3830 420
167 SEG58 -595 1190 217 COM19 -3830 350
168 SEG59 -665 1190 218 COM20 -3830 280
169 SEG60 -735 1190 219 COM21 -3830 210
170 SEG61 -805 1190 220 COM22 -3830 140
171 SEG62 -875 1190 221 COM23 -3830 70
172 SEG63 -945 1190 222 COM24 -3830 0
173 SEG64 -1015 1190 223 COM25 -3830 -70
174 SEG65 -1085 1190 224 COM26 -3830 -140
175 SEG66 -1155 1190 225 COM27 -3830 -210
176 SEG67 -1225 1190 226 COM28 -3830 -280
177 SEG68 -1295 1190 227 COM29 -3830 -350
178 SEG69 -1365 1190 228 COM30 -3830 -420
179 SEG70 -1435 1190 229 COM31 -3830 -490
180 SEG71 -1505 1190 230 COMS -3830 -560
181 SEG72 -1575 1190 231 DUMMY -3830 -630
182 SEG73 -1645 1190 232 DUMMY -3830 -700
183 SEG74 -1715 1190 233 DUMMY -3830 -770
184 SEG75 -1785 1190 234 DUMMY -3830 -840
185 SEG76 -1855 1190
186 SEG77 -1925 1190
187 SEG78 -1995 1190
188 SEG79 -2065 1190
189 SEG80 -2135 1190
190 SEG81 -2205 1190
191 SEG82 -2275 1190
192 SEG83 -2345 1190
193 SEG84 -2415 1190
194 SEG85 -2485 1190
195 SEG86 -2555 1190
196 SEG87 -2625 1190
197 SEG88 -2695 1190
198 SEG89 -2765 1190
199 SEG90 -2835 1190
200
SEG91
-2905
1190
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
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PIN DESCRIPTION
POWER SUPPLY
Table 3. Power Supply Pin Description
Name I/O Description
VDD Supply Power supply
VSS Supply Ground
LCD driver supply voltages
The voltage determined by LCD pixel is impedance-converted by an operational amplifier
for application.
Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the internal power circuit is active, these voltages are generated as following table
according to the state of LCD Bias.
LCD bias V1 V2 V3 V4
1/6 bias (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/5 bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0
V0
V1
V2
V3
V4
I/O
LCD DRIVER SUPPLY
Table 4. LCD Driver Supply Pin Description
Name I/O Description
C1- OCapacitor 1 negative connection pin for voltage converter
C1+ OCapacitor 1 positive connection pin for voltage converter
C2- OCapacitor 2 negative connection pin for voltage converter
C2+ OCapacitor 2 positive connection pin for voltage converter
C3-OCapacitor 3 negative connection pin for voltage converter
C3+OCapacitor 3 positive connection pin for voltage converter
VOUT I/O Voltage converter input / output pin
VR IV0 voltage adjustment pin
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
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SYSTEM CONTROL
Table 5. System Control Pin Description
Name I/O Description
Master / Slave operation select pin
− MS = "H": master operation
− MS = "L": slave operation
The following table depends on the MS status.
MS OSC
circuit
Power
supply
circuit CL MFRS DISP
HEnabled Input Output Output Output Output
LDisabled Disabled Input Input Output Input
MS I
CL I/O Display clock input / output pin
When the KS0715 is used in master/slave mode (multi-chip), the CL pins must be
connected each other for sync.
MI/O
LCD AC signal input / output pin
When the KS0715 is used in master/slave mode (multi-chip), the M pins must be
connected each other.
− MS = “H”: output
− MS = “L”: input
FRS OStatic driver segment output pin
This pin is used together with the M pin.
DISP I/O
LCD display blanking control input/output.
When KS0715 is used in master/slave mode
(multi-chip), the DISP pins must be connected each other.
− MS = “H”: output
− MS = “L”: input
TEMPS ISelects temperature coefficient of the reference voltage
− TEMPS = "L": -0.05%/°C
− TEMPS = "H": -0.2%/°C
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
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MICROPROCESSOR INTERFACE
Table 6. Microprocessor Interface Pin Description
Name I/O Description
RESETB IReset input pin
When RESETB is “L”, initialization is executed.
Parallel / serial data input select input
PS Interface
mode Chip
select Data /
instruction Data Read / write Serial clock
HParallel CS1B,
CS2 RS DB0 to DB7 E_RD
RW_WR -
LSerial CS1B,
CS2 RS SID (DB7) Write only SCLK (DB6)
PS I
*NOTE: When PS is “L”, DB0 to DB5 are high impedance and E_RD and RW_WR
should be fixed to either “H” or “L”.
MI IMicroprocessor interface select input pin
− MI = "H": 6800-series MPU interface
− MI = "L": 8080-series MPU interface
CS1B
CS2 IChip select input pins
Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”.
When chip select is non-active, DB0 to DB7 may be high impedance.
RS IRegister select input pin
− RS = "H": DB0 to DB7 are display data.
− RS = "L": DB0 to DB7 are control data.
Read / Write execution control pin
MI MPU type RW_WR Description
H6800-series RW Read/Write control input pin
− RW = “H”: read
− RW = “L”: write
L8080-series /WR Write enable clock input pin
The data on DB0 to DB7 are latched at the rising
edge of the /WR signal.
RW_WR I
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
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Table 6. Microprocessor Interface Pin Description (Continued)
Name I/O Description
Read / Write execution control pin
MI MPU Type E_RD Description
H6800-series E
Read / Write control input pin
− RW = “H”: When E is “H”, DB0 to DB7 are in an
output status.
− RW = “L”: The data on DB0 to DB7 are latched at
the falling edge of the E signal.
L8080-series /RD Read enable clock input pin
When /RD is “L”, DB0 to DB7 are in an output status.
E_RD I
DB0
to
DB7 I/O
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data
bus. When the serial interface selected (PS = "L");
− DB0 to DB5: high impedance
− DB6: serial input clock (SCLK)
− DB7: serial input data (SID)
When chip select is not active, DB0 to DB7 may be high impedance.
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
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LCD DRIVER OUTPUTS
Table 8. LCD Driver Outputs Pin Description
Name I/O Description
LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.
Segment driver output voltage
Display data MNormal display Reverse display
H H V0 V2
HLVSS V3
LHV2 V0
L L V3 VSS
Power save mode VSS VSS
SEG0
to
SEG99 O
LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.
Scan data MCommon driver output voltage
H H VSS
HLV0
LHV1
L L V4
Power save mode VSS
COM0
to
COM31 O
COMS OCommon output for the icons
The output signals of two pins are same. When not used, these pins should be left open.
In multi-chip (master/slave) mode, all COMS pins on both master and slave units are the
same signal.
TEST PINS
Table 8. Test Pin Description
Name I/O Description
TESTL1
TESTL2 IIC test pins with pull-up
These pins must be open.
NOTE: DUMMY – These pins should be opened (floated).
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
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FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There are CS1B and CS2 pins for Chip Selection. The KS0715 can interface with an MPU only when CS1B is “L”
and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled
and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the
counter are reset.
Parallel / Serial Interface
KS0715 has three types of interface with an MPU, which are one serial and two parallel interface. This parallel or
serial interface is determined by PS pin as shown in table 9.
Table 9. Parallel / Serial Interface Mode
PS Type CS1B CS2 MI Interface mode
H6800-series MPU mode
HParallel CS1B CS2 L8080-series MPU mode
LSerial CS1B CS2 *×Serial-mode
*×: Don't care
Parallel Interface (PS = "H")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by MI as shown in
table 10. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 11.
Table 10. Microprocessor Selection for Parallel Interface
MI CS1B CS2 RS E_RD RW_WR DB0 to DB7 MPU bus
HCS1B CS2 RS ERW DB0 to DB7 6800-series
LCS1B CS2 RS /RD /WR DB0 to DB7 8080-series
Table 11. Parallel Data Transfer
Common 6800-series 8080-series
RS E_RD
(E) RW_WR
(RW) E_RD
(/RD) RW_WR
(/WR) Description
HHHLHDisplay data read out
H H LHLDisplay data write
LH H LHRegister status read
LHLHLWrites to internal register (instruction)
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
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Serial interface (PS = "L")
When the KS0715 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the
internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock
going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data
when RS is high and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the
external noise caused by the line length, the operation check on the actual machine is recommended.
CS1B
CS2
SID
SCLK
RS
DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7
Figure 3. Serial Interface Timing
Busy Flag
The Busy Flag indicates whether the KS0715 is operating or not. When DB7 is “H” in read status operation, this
device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor
needs not to check this flag before each instruction, which improves the MPU performance.
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
14
Data Transfer
The KS0715 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the
MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And
when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder
(dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure
5. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of
address sets is executed. Therefore, the data of the specified address cannot be output with the read display data
instruction right after the address sets, but can be output at the second read of data.
RS
/WR
DB0 to DB7 ND(N) D(N+1) D(N+2) D(N+3)
Internal signals
MPU signals
/WR
BUS HOLDER
COLUMN ADDRESS NN+1 N+2 N+3
ND(N) D(N+1) D(N+2) D(N+3)
Figure 4. Write Timing
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
15
RS
/WR
/RD
DB0 to DB7 N
MPU signals
Dummy D(N) D(N+1)
Internal signals
/WR
/RD
BUS HOLDER
COLUMN ADDRESS
N
D(N)
D(N+1)
D(N+2)
N
N+1
N+2
N+3
Figure 5. Read Timing
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
16
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 65-row by 132-column addressable array. Each pixel
can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8
lines and the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page
directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD
common lines as shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer.
Since the LCD controller operates independently, data can be written into RAM at the same time as data is being
displayed without causing the LCD flicker.
COM0
- -
COM1
- -
COM2- -
COM3
- -
COM4
- -
DB0
0
0
1
- -
0
DB1
1
0
0
- -
1
DB2 0 1 1 - - 0
DB3
1
0
1
- -
0
DB4
0
0
0
- -
1
Display Data RAM LCD Display
Figure 6. RAM-to-LCD Data Transfer
Page Address Circuit
This circuit is for providing a page address to Display Data RAM shown in figure 8. It incorporates 4-bit Page
Address register changed by only the “Set Page” instruction. Page Address 8 (DB3 is “H”, but DB2, DB1 and DB0
are “L”) is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it
is impossible to access to on-chip RAM.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by
setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing
the contents of on-chip RAM as shown in figure 8. It incorporates 6-bit line address register changed by only the
initial display line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register
are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the
132-bit RAM data to the 100 display data latch circuit. However, display data of icons are not scrolled because the
MPU can not access Line Address of icons.
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
17
Column Address Circuit
Column Address circuit has an 8-bit preset counter that provides column address to the Display Data RAM as
shown in figure 8. When set Column Address MSB / LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since
this address is increased by 1 each a read or write Data instruction, microprocessor can access the display data
continuously. However, the counter is not increased and locked if a non-existing address above 84H. It is
unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the column address
counter is independent of page address register.
ADC select instruction makes it possible to invert the relationship between the column address and the segment
outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to
the following figure 7.
SEG output -SEG
0SEG
1SEG
2... ... SEG
97 SEG
98 SEG
99 -
Column address [Y7:Y0] 00H~
0FH 10H 01H 02H ... ... 71H72H73H 74H~
83H
Display data ×1 0 0 0 1 1 0
LCD panel display
( ADC = 0 )
Not
outputted
... ...
Not
outputted
LCD panel display
( ADC = 1 )
Not
outputted
... ...
Not
outputted
Figure 7. The Relationship between the Column Address and the Segment Outputs
Segment Control Circuit
This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON /
OFF instructions without changing the data in the display data RAM.
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
18
Page0
Page2
Page1
Page4
Page3
Page6
Page5
Page7
Page8
Line
Address COM
Output
Page Address
DB3 DB0DB1DB2
Data
- - - - -
- - - - -
---- -
SEG99
SEG98
SEG97
-
SEG0
SEG1
SEG2
- - - - -
ADC=1
ADC=0
Column
Address
LCD Output
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
00H
08H
07H
06H
05H
04H
03H
02H
01H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
18H
17H
16H
15H
14H
13H
12H
11H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
28H
27H
26H
25H
24H
23H
22H
21H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
38H
37H
36H
35H
34H
33H
32H
31H
39H
3AH
3BH
3CH
3DH
3EH
3FH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
COM1
COM0
-
-
-
-
-
-
-
COM2
COM11
COM10
COM9
COM8
COM7
COM5
COM6
COM4
COM3
COM12
COM21
COM20
COM19
COM18
COM17
COM15
COM16
COM14
COM13
COM22
COM31
COM30
COM29
COM28
COM27
COM25
COM26
COM24
COM23
-
-
COMS
-
-
83
Start
Initial start line address = 1CH
-74 7273 71
00 -0F 1110 12 12 11 10 -1F 00
71 72 73 -74 83
000 0
000 1
001 0
001 1
010 0
010 1
011 0
011 1
1 0 0 0
Figure 8. Display Data RAM Map
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
19
LCD DISPLAY CIRCUITS
Oscillator
This is completely on-chip Oscillator and its frequency is nearly independent of VDD. This oscillator signal is used
in the voltage converter and display timing generation circuit.
* Test Condition: Temperature: 25°C & 85°C, TEMPS = ”L”, No Load
VDD vs. fosc
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5
VDD [V]
fosc
[kHz] 1/33 Duty (25°C)
1/33 Duty (85°C)
Figure 9. VDD vs. fOSC
Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip
RAM is generated in synchronization with the display clock (CL) and the 100-bit display data is latched by the
display data latch circuit in synchronization with the display clock. The display data, which is read to the LCD
driver, is completely independent of the access to the display data RAM from the microprocessor. The display
clock generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also
generates an internal common timing signal and start signal to the common driver. Driving 2-frame AC driver
waveform and internal timing signal are shown in figure 10.
In a multiple-chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 12
shows the M, CL, and DISP status.
Table 12. Master and Slave Timing Signal Status
Operation mode Oscillator MCL DISP
ON (internal clock used) Output Output Output
Master OFF (external clock used) Output Input Output
Slave -Input Input Input
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
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M
COM0
V0
V1
V2
V3
V4
VSS
COM1
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
SEGn
32 33 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 32 33 1 2 3 4 5 6
CL
Figure 9. 2-frame AC Driving Waveform
Common Output Control Circuit
This circuit controls the relationship between the number of common output and specified duty ratio. SHL Select
Instruction specifies the scanning direction of the common output pins.
Table 13. The Relationship between Duty Ratio and Common Output
Common output pins
Duty SHL COM0 to COM31 COMS
0COM0 to COM31
1/33 1COM31 to COM0 COMS
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
21
LCD DRIVER CIRCUIT
This driver circuit is configured by 34-channel (including 2 COMS channel) common driver and 100-channel
segment driver. This LCD panel driver voltage depends on the combination of display data and M signal.
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
S
E
G
4
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0SEG2
SEG1
SEG0
COM2
COM0
COM1
M
V0
V1
V2
V3
V4
V
SS
V0
V1
V2
V3
V4
V
SS
V0
V1
V2
V3
V4
V
SS
V0
V1
V2
V3
V4
V
SS
V0
V1
V2
V3
V4
V
SS
V0
V1
V2
V3
V4
V
SS
VDD
VSS
Figure 10. Segment and Common Timing
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
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POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-
power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits,
and voltage follower circuits. They are valid only in master operation and controlled by power control instruction.
For details, refers to "Instruction Description". Table 14 shows the referenced combinations in using Power Supply
circuits.
Table 14. Recommended Power Supply Combinations
User setup Power
control
(VC VR VF)
V/C
circuits V/R
circuits V/F
circuits VOUT V0 V1 to V4
Only the internal power
supply circuits are used 1 1 1ON ON ON Open Open Open
Only the voltage
regulator circuits and
voltage follower circuits
are used
0 1 1OFF ON ON External
input Open Open
Only the voltage follower
circuits are used 0 0 1 OFF OFF ON Open External
input Open
Only the external power
supply circuits are used 0 0 0OFF OFF OFF Open External
input External
input
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
23
Voltage Converter Circuits
These circuits boost up the electric potential between VDD and VSS to 2, 3, or 4 times toward positive side and
boosted voltage is outputted from VOUT pin.
[C1 = 1.0 to 4.7 µF]
VOUT = 2
×
VDD
VOUT
C3+
C3 -
C2+
C2 -
C1+
C1 -
VDD
VDD
VSS
-
+
-
+
C1
C1
GND
VSS
VDD
VOUT = 3 × VDD
VDD
VSS
V
DD
-
+
+
-
-
+
C1
C1
C1
GND
VSS
VDD
VOUT
C3+
C3 -
C2+
C2 -
C1+
C1 -
Figure 11. Two Times Boosting Circuit Figure 12. Three Times Boosting Circuit
VOUT = 4 × VDD
V
DD
VDD
VSS
-
-
+
+
-
+
-
+
C1
C1
C1
C1
GND
V
SS
V
DD
VOUT
C3+
C3 -
C2+
C2 -
C1+
C1 -
Figure 13. Four Times Boosting Circuit
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
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Voltage Regulator Circuits
The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by
adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of
operational-amplifier circuits shown in figure 14, it is necessary to be applied internally or externally.
For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by
INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is the
value selected by instruction, "Set Reference Voltage Register", within the range 0 to 31. VREF voltage at Ta =
25°C is shown in table 15-1.
Rb
V0 = ( 1 + ) x VEV [V] ------ (Eq. 1)
Ra
(31 - α)
VEV = ( 1 - ) x VREF [V] ------ (Eq. 2)
150
Table 15-1. VREF Voltage at Ta = 25°°C
TEMPS Temp. coefficient VREF [V]
L-0.05% / °C1.9
H-0.2% / °C2.1
Table 15-2. Reference Voltage Parameter (αα)
SV4 SV3 SV2 SV1 SV0 Reference voltage parameter (αα)
0 0 0 0 0 0
0 0 0 0 1 1
:
::
::
::
::
::
:
1 1 1 1 0 30
1 1 1 1 1 31
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
25
VEV
GND
Ra
Rb
V
SS
VR
V0
VOUT
+
-
Figure 14. Internal Voltage Regulator Circuit
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
26
In Case of Using External Resistors, Ra and Rb
It is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR.
Example: For the following requirements
1. LCD driver voltage, V0 = 8V
2. 5-bit reference voltage register = (1, 1, 1, 1, 1)
3. Maximum current flowing Ra, Rb = 1 uA
From Eq. 1
Rb
8 = ( 1 + ) x VEV [V] ------ (Eq. 3)
Ra
From Eq. 2
(31 - 31)
VEV = ( 1 - ) x 1.9 = 1.9 [V] ------ (Eq. 4)
150
From requirement 3.
8
= 1 [uA] ------ (Eq. 5)
Ra + Rb
From equations Eq. 3, 4 and 5
Ra = 1.9 [MΩ]
Rb = 6.1 [MΩ]
The following table shows the range of V0 depending on the above requirements.
Table 16. V0 depending on Electronic Volume Level
Electronic volume level
0....... 16 ....... 31
V0 6.33 ....... 7.19 ....... 8
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
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Voltage Follower Circuits
VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4) and those output impedance
are converted by the Voltage Follower for increasing drive capability. Table 17 shows the relationship between V1
to V4 level and bias.
Table 17. The Relationship between V1 to V4 Level and Bias
Duty ratio LCD bias V1 V2 V3 V4
1/6 (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/33 1/5 (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
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REFERECE CIRCUIT EXAMPLES
VDD
MS
VSS
C1
Ra
Rb
C2 - +
C2 - +
C2 - +
C2 - +
C2 - +
VOUT
C3+
C3-
C2+
C2-
C1+
C1-
VR
V0
V1
V2
V3
V4
C1
C1
C1
VDD
MS
VSS
Ra
Rb
C2 - +
C2 - +
C2 - +
C2 - +
C2 - +
VOUT
C3+
C3-
C2+
C2-
C1+
C1-
VR
V0
V1
V2
V3
V4
External
Power
Supply
Figure 15. When Using all LCD Power Circuits Figure 16. When not Using V/C Circuit
(4-time V/C: ON, V/R: ON, V/F: ON)
VDD
MS
VSS
VDD
MS
VSS
External
Power
Supply
External
Power
Supply
C2 - +
C2 - +
C2 - +
C2 - +
C2 - +
VOUT
C3+
C3-
C2+
C2-
C1+
C1-
VR
V0
V1
V2
V3
V4
VOUT
C3+
C3-
C2+
C2-
C1+
C1-
VR
V0
V1
V2
V3
V4
Value of external Capacitance
Item
Value
Unit
C1 1.0 to 4.7
C2 0.47 to 1.0 µF
Figure 17. When Using some LCD Power Circuits Figure 18. When not Using Internal
(V/C: OFF, V/R: OFF, V/F: ON) LCD Power Supply Circuit
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
29
RESET CIRCUIT
Setting RESETB to “L” or Reset instruction can initialize internal function.
When RESETB becomes “L”, following procedure is occurred.
Display ON / OFF: OFF
Entire display ON / OFF: OFF (normal)
ADC select: OFF (normal)
Reverse display ON / OFF: OFF (normal)
Power control register (VC, VR, VF) = (0, 0, 0)
LCD bias ratio: 1/6
Read-modify-write: OFF
SHL select: OFF (normal)
Static indicator mode: OFF
Display start line: 0 (first)
Column address: 0
Page address: 0
Reference voltage set: off
Reference voltage control register: (SV4, SV3, SV2, SV1, SV0) = (0, 0, 0, 0, 0)
When RESET instruction is issued, following procedure is occurred.
Read-modify-write: OFF
Static indicator mode: OFF
SHL select: 0
Display start line: 0 (first)
Column address: 0
Page address: 0
Reference voltage set: OFF
Reference voltage control register: (SV4, SV3, SV2, SV1, SV0) = (0, 0, 0, 0, 0)
While RESETB is “L” or reset instruction is executed, no instruction except read status could be accepted. Reset
status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to
the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is
essential before used.
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
30
INSTRUCTION DESCRIPTION
Table 18. Instruction Table
× : Don’t care
Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
Read display data 1 1 Read data Read data from DDRAM
Write display data 1 0 Write data Write data into DDRAM
Read status 0 1
BUSY
ADC
ON/OFF
RESETB
0000Read the internal status
Display ON / OFF 001010111
DON
Turn ON / OFF LCD panel
When DON = 0: display OFF
When DON = 1: display ON
Initial display line 0001ST5ST4ST3ST2ST1ST0Specify DDRAM line for COM0
Set reference voltage
mode 0010000001Set reference voltage mode
Set reference voltage
register 00100SV4 SV3 SV2 SV1 SV0 Set reference voltage register
Set page address 001011P3 P2 P1 P0 Set page address
Set column address MSB 0000010Y6 Y5 Y4 Set column address MSB
Set column address LSB 000000Y3 Y2 Y1 Y0 Set column address LSB
ADC select 001010000ADC
Select SEG output direction
When ADC = 0: normal direction
(SEG0→SEG99)
When ADC = 1: reverse
direction (SEG99→SEG0)
Reverse display ON / OFF 001010011REV Select normal / reverse display
When REV = 0: normal display
When REV = 1: reverse display
Entire display ON / OFF 001010010EON Select normal/ entire display ON
When EON = 0: normal display.
When EON = 1: entire display
ON
LCD bias select 001010001
BIAS
Select LCD bias
Set modify-read 0011100000Set modify-read mode
Reset modify-read 0011101110release modify-read mode
Reset 0011100010Initialize the internal functions
SHL select 001100SHL ×××
Select COM output direction
When SHL = 0: normal direction
(COM0→COM31)
When SHL = 1: reverse direction
(COM31→COM0)
Power control 0000101VC VR VF Control power circuit operation
Set static indicator register 001010110SISet static indicator register
SI = 0 (OFF), SI = 1 (ON)
Power save ----------Compound instruction of display
OFF and entire display ON
Test instruction 001111××××Don't use this instruction.
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
31
Read Display Data
8-bit data from Display Data RAM specified by the column address and page address could be read by this
instruction. As the column address is increased by 1 automatically after each this instruction, the
microprocessor can continuously read data from the addressed page. A dummy read is required after loading
an address into the column address register. Display data cannot be read through the serial interface.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 1 Read data
Write Display Data
8-bit data of display data from the microprocessor can be written to the RAM location specified by the column
address and page address. The column address is increased by 1 automatically so that the microprocessor
can continuously write data to the addressed page.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 Write data
Data Write
Set Column Address
Set Page Address
Optional Status
Column = Column + 1
NO
YES
Data Write Continue ?
Dummy Data Read
Set Column Address
Set Page Address
Optional Status
Column = Column + 1
NO
YES
Data Read Continue ?
Data Read
Column = Column + 1
Figure 19. Sequence for Writing Display Data Figure 20. Sequence for Reading Display Data
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
32
Read Status
Indicates the internal status of the KS0715
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 1 BUSY ADC ON / OFF RESETB 0 0 0 0
Flag Description
BUSY The device is busy when internal operation or reset
Any instruction is rejected until BUSY goes Low.
0: chip is active, 1: chip is being busy.
ADC Indicates the relationship between RAM column address and segment driver.
0: reverse direction (SEG99 → SEG0), 1: normal direction (SEG0 → SEG99)
ON / OFF Indicates display ON / OFF status
0: display ON, 1: display OFF
RESETB Indicates the initialization is in progress by RESETB signal
0: chip is active, 1: chip is being reset
Display ON / OFF
Turns the display ON or OFF
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001010111DON
DON = 1: display ON
DON = 0: display OFF
Initial Display Line
Sets the line address of display RAM to determine the Initial Display Line. The RAM display data is displayed
at the top row (COM0 when SHL = L, COM31 when SHL = H) of LCD panel.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 1 ST5ST4ST3ST2ST1ST0
ST5ST4ST3ST2ST1ST0Line address
0 0 0 0 0 0 0
0 0 0 0 0 1 1
:::::: :
1 1 1 1 1 0 62
1 1 1 1 1 1 63
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
33
Reference Voltage Select
Consists of 2-byte Instruction
The 1st instruction sets reference voltage mode, the 2nd one updates the contents of reference voltage
register. After second instruction, reference voltage mode is released.
The 1st Instruction: Set Reference Voltage Select Mode
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0010000001
The 2nd Instruction: Set Reference Voltage Register
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00100SV4 SV3 SV2 SV1 SV0
SV4 SV3 SV2 SV1 SV0 Reference voltage parameter (αα)
0 0 0 0 0 0
0 0 0 0 1 1
:
::
::
::
::
::
:
1 1 1 1 0 30
1 1 1 1 1 31
2
nd
Instruction for Register Setting
Setting Reference Voltage End
1
st
Instruction for Mode Setting
Setting Reference Voltage Start
Figure 21. Sequence for Setting the Reference Voltage
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
34
Set Page Address
Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any
RAM data bit can be accessed when its Page Address and column address are specified. Along with the
column address, the Page Address defines the address of the display RAM to write or read display data.
Changing the Page Address doesn't effect to the display status.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 1 0 1 1 P3 P2 P1 P0
P3 P2 P1 P0 Page
0 0 0 0 0
0 0 0 1 1
: : : : :
0 1 1 1 7
1 0 0 0 8
Set Column Address
Sets the Column Address of display RAM from the microprocessor into the column address register. Along
with the Column Address, the Column Address defines the address of the display RAM to write or read
display data. When the microprocessor reads or writes display data to or from display RAM, Column
Addresses are automatically increased.
Set Column Address MSB
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0000010Y6 Y5 Y4
Set Column Address LSB
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
000000Y3 Y2 Y1 Y0
Y6 Y5 Y4 Y3 Y2 Y1 Y0 Column address
0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1
: : : : : : : :
1 1 0 0 0 1 0 98
1 1 0 0 0 1 1 99
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
35
ADC Select
Changes the relationship between RAM column address and segment driver. The direction of segment driver
output pins could be reversed by software. This makes IC layout flexible in LCD module assembly.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001010000ADC
ADC = 0: normal direction (SEG0 → SEG99)
ADC = 1: reverse direction (SEG99 → SEG0)
Reverse Display ON / OFF
Reverses the display status on LCD panel without rewriting the contents of the display data RAM.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001010011REV
REV RAM bit data = “1” RAM bit data = “0”
0 (normal) LCD pixel is illuminated LCD pixel is not illuminated
1 (reverse) LCD pixel is not illuminated LCD pixel is illuminated
Reverse Display ON / OFF
Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time,
the contents of the display data RAM are held. This instruction has priority over the reverse display ON / OFF
instruction.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001010010EON
EON = 0: normal display
EON = 1: entire display ON
Select LCD Bias
Selects LCD bias ratio of the voltage required for driving the LCD.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001010001Bias
LCD bias
Duty
ratio Bias = 0 Bias = 1
1/33 1/61/5
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
36
Set Modify-read
This instruction stops the automatic increment of the column address by the read display data instruction, but
the column address is still increased by the write display data instruction. And it reduces the load of
microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This
mode is canceled by the reset Modify-read instruction.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0011100000
Reset Modify-read
This instruction cancels the Modify-read mode, and makes the column address return to its initial value just
before the set Modify-read instruction is started.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0011101110
Set Modify-Read
Reset Modify-Read
Set Page Address
Data Process
NO
YES
Change Complete ?
Set Column Address (N)
Dummy Read
Data Read
Data Write
Return Column Address (N)
Figure 22. Sequence for Cursor Display
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
37
Reset
This instruction Resets initial display line, column address, page address, and common output status select to
their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the
LCD power supply, which is initialized by the RESETB pin.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0011100010
SHL Select
COM output scanning direction is selected by this instruction which determines the LCD driver output status.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 1 1 0 0 SHL × × ×
× : Don’t care
SHL = 0: normal direction (COM0 → COM31)
SHL = 1: reverse direction (COM31 → COM0)
Power Control
Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of
internal power supply functions can be used simultaneously.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0000101VC VR VF
VC VR VF Status of internal power supply circuits
0
1Internal voltage converter circuit is OFF
Internal voltage converter circuit is ON
0
1Internal voltage regulator circuit is OFF
Internal voltage regulator circuit is ON
0
1Internal voltage follower circuit is OFF
Internal voltage follower circuit is ON
Set Static Indicator State
This instruction sets the Static Indicator ON / OFF. When it is on, the static indicator operates and blinks at an
interval of approximately 1second.
Set Static Indicator Register
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001010110SI
SIStatus of static indicator output
0OFF
1ON (about 1 second blinking)
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
38
Power Save (Compound Instruction)
If the entire display ON / OFF instruction is issued during the display OFF state, KS0715 enters the Power
Save status to reduce the power consumption to the static power consumption value. According to the status
of static indicator mode, Power Save is entered to one of two modes (sleep and standby mode). When static
indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power Save mode is
released by the display ON & entire display OFF instruction.
Release Standby Mode
Power Save OFF (Compound Instruction)
[Entire Display OFF]
[Display ON]
Release Sleep Mode
Power Save OFF (Compound Instruction)
[Entire Display OFF]
[Static Indicator ON]
[Display ON]
Power Save (Compound Instruction)
[Display OFF]
[Entire Display ON]
Static Indicator OFF Static Indicator ON
Sleep Mode
[Oscillator Circuit: OFF]
[LCD Power Supply Circuit: OFF]
[All COM / SEG Outputs: VSS]
[Consumption Current: < 2µA]
Standby Mode
[Oscillator Circuit: ON]
[LCD Power Supply Circuit: OFF]
[All COM / SEG Outputs: VSS]
[Consumption Current: < 10µA]
Figure 23. Power Save Routine
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
39
Referential Instruction Setup Flow (1)
End of Initialization
Waiting for Stabilizing the LCD Power Levels
User Application Setup by Internal Instructions
[ADC Select]
[SHL Select]
[LCD Bias Select]
Start of Initialization
RESETB Pin = “H”
Waiting for Stabilizing the Power
Power ON (VDD - VSS) Keeping the RESETB Pin = “L”
User System Setup by External Pins
User LCD Power Setup by Internal Instructions
[Voltage Converter ON]
User LCD Power Setup by Internal Instructions
[Voltage Regulator ON]
User LCD Power Setup by Internal Instructions
[Voltage Follower ON]
Waiting for ≥ 1ms
Waiting for ≥ 1ms
User LCD Power Setup by Internal Instructions
[Reference Voltage Register Set]
Figure 24. Initializing with the Built-in Power Supply Circuits
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
40
Referential Instruction Setup Flow (2)
User Application Setup by Internal Instructions
[ADC Select]
[SHL Select]
[LCD Bias Select]
Start of Initialization
RESETB Pin = “H”
Waiting for Stabilizing the Power
Power ON (VDD - VSS) Keeping the RESETB Pin = “L”
User System Setup by External Pins
Set Power Save
Release Power Save
User LCD Power Setup by Internal Instructions
[Reference Voltage Register Set]
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 25. Initializing without the Built-in Power Supply Circuits
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
41
Referential Instruction Setup Flow (3)
End of Initialization
Write Display ON / OFF by Instruction
[Display ON / OFF]
Display Data RAM Addressing by Instruction
[Initial Display Line]
[Set Page Address]
[Set Column Address]
End of Data Display
Turn Display ON / OFF by Instruction
[Display ON / OFF]
Figure 26. Data Displaying
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
42
Referential Instruction Setup Flow (4)
Turn Display ON / OFF by Instruction
[Display OFF]
Optional Status
Power OFF (VDD-VSS)
User LCD Power Setup by Internal Instructions
[Voltage Follower OFF]
User LCD Power Setup by Internal Instructions
[Voltage Regulator OFF]
User LCD Power Setup by Internal Instructions
[Voltage Converter OFF]
Waiting for ≥ 50ms
Waiting for ≥ 1ms
Waiting for ≥ 1ms
Figure 27. Power OFF
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
43
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table 19. Absolute Maximum Ratings
Parameter Symbol Rating Unit
VDD - 0.3 to +7.0 V
Supply voltage range VLCD - 0.3 to +17.0 V
Input voltage range VIN - 0.3 to VDD +0.3 V
Operating temperature range TOPR - 40 to +85 °C
Storage temperature range TSTR - 55 to +125 °C
NOTES:
1. VDD and VLCD are based on VSS = 0V.
2. Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied. (VLCD = V0 – VSS)
3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation.
Otherwise, this LSI may malfunction or reduced LSI reliability may result.
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
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DC CHARACTERISTICS
Table 20. DC Characteristics
( VSS = 0V, VDD = 2.4 to 3.6V, Ta = -40 to 85°C )
Item Symbol Condition Min. Typ. Max. Unit Pin used
Operating voltage (1) VDD 2.4 -3.6 V VDD *1
Operating voltage (2) V0 4.0 -15.0 V V0 *2
High VIH 0.8VDD -VDD
Input voltage Low VIL VSS -0.2VDD V*3
High VOH IOH = -0.5mA 0.8VDD -VDD
Output
voltage Low VOL IOL = 0.5mA VSS -0.2VDD V*4
Input leakage current IIL VIN = VDD or VSS - 1.0 -+ 1.0 µA*5
Output leakage current IOZ VIN = VDD or VSS - 3.0 -+ 3.0 µA*6
LCD driver ON
resistance RON Ta = 25°C, V0 = 8V -2.0 3.0 kΩ SEGn
COMn *7
Internal
fOSC 17 22.5 27
Oscillator
frequency (1)
External
fCL Ta = 25°C2.13 2.81 3.37 kHz CL *8
× 22.4 -3.6
× 32.4 -3.6
Voltage converter
input voltage VDD
× 42.4 -3.6
V VDD
Voltage converter
output voltage VOUT ×2 / ×3 / ×4
voltage conversion
(no-load ) 95 99 -%VOUT
Voltage regulator
operating voltage VOUT 4.0 -15.0 V VOUT
Voltage follower
operating voltage V0 4.0 -15.0 V V0 *9
VREF0
-0.05%/
°
C
1.84 1.9 1.96 V*10
Reference voltage VREF1
Ta = 25
°
C-0.2%/
°
C
2.04 2.12.16 V*10
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
45
Dynamic Current Consumption (1): when the Built-in Power Circuit is OFF (At Operate Mode)
(Ta = 25°C)
Item Symbol Condition Min. Typ. Max. Unit Pin used
Dynamic current
consumption (1) IDD1 VDD = 3.0V
V0 – VSS = 8.0V
Display OFF, checker pattern -5 20 µΑ*11
Dynamic Current Consumption (2): when the built-in power circuit is ON (At operate mode)
(Ta = 25°C)
Item Symbol Condition Min. Typ. Max. Unit Pin used
VDD = 3.0V,
quad boosting,
V0 – VSS = 8.0V,
1/65 duty ratio,
Display OFF, checker pattern
Normal power mode
-47 70
Dynamic current
consumption (2) IDD2
VDD = 3.0V,
quad boosting,
V0 – VSS = 8.0V,
Display ON, checker pattern
Normal power mode
-75 100
µΑ*12
Current Consumption during Power Save mode
(Ta = 25°C)
Item Symbol Condition Min. Typ. Max. Unit Pin used
Sleep mode IDDS1 During sleep - - 2.0 µA
Standby mode IDDS2During standby - - 10.0 µA
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
46
Table 21. The relationship between oscillation frequency and frame frequency
Duty ratio Item fCL fM
On-chip oscillator circuit is
used
fOSC
8
fOSC
16 × 33
1/33 On-chip oscillator circuit is
not used External input (fCL)fOSC
2 × 33
(fOSC: oscillation frequency, fCL: display clock frequency, fM: LCD AC signal frequency)
[* Remark Solves]
*1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage
assurance during access from the MPU.
*2. In case of external power supply is applied.
*3. CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, MI, PS, TEMPS, CL, M, DISP pins.
*4. DB0 to DB7, M, FRS, DISP, CL pins.
*5. CS1B, CS2, RS, DB[7:0], E_RD, RW_WR, RESETB, MS, MI, PS, TEMPS, CL, M, DISP pins.
*6. Applies when the DB[7:0], M, DISP, and CL pins are in high impedance.
*7. Resistance value when ± 0.1[mA] is applied during the ON status of the output pin SEGn or COMn.
RON= ∆V / 0.1 [kΩ] (∆V: voltage change when ± 0.1[mA] is applied in the ON status.)
*8. See table 21 for the relationship between oscillation frequency and frame frequency.
*9. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range.
*10. On-chip reference voltage source of the voltage regulator circuit to adjust V0.
*11,12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU.
The current consumption, when the built-in power supply circuit is ON or OFF.
The current flowing through voltage regulation resistors (Ra and Rb) is not included.
It does not include the current of the LCD panel capacity, wiring capacity, etc.
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
47
REFERENCE DATA
IDD1 vs. VDD
l Test Condition: Temperature (25°C & 85°C), V0 = 8V (External), TEMPS = 'L', 1/33 Duty, Ra = 1 [MΩ],
Rb = 3 [MΩ], Normal Power Mode
VDD vs. IDD1(Pattern OFF)
0.00
2.00
4.00
6.00
8.00
10.00
12.00
2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5
VDD [V]
IDD1
[uA] 8.0V, 1/33 Duty (25°C)
8.0V, 1/33 Duty (85°C)
Figure 28. Display Pattern is OFF
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
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IDD2 vs. VDD
l Test Condition: Temperature (25°C & 85°C), Quad boosting, RR = 6, EV = 32, TEMPS = 'L', 1/33 duty,
Ra = 1 [MΩ], Rb = 3 [MΩ], Normal Power Mode
VDD vs. IDD2 (Pattern OFF)
0.00
5.00
10.00
15.00
20.00
25.00
30.00
35.00
40.00
45.00
50.00
2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5
VDD [V]
IDD2
[uA] 1/33 Duty (25°C)
1/33 Duty (85°C)
Figure 29. Display Pattern is OFF
VDD vs. IDD2 (Checker Pattern)
0.00
50.00
100.00
150.00
200.00
250.00
2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5
VDD [V]
IDD2
[uA] 1/33 Duty (25°C)
1/33 Duty (85°C)
Figure 30. Display Pattern is Checker
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
49
AC CHARACTERISTICS
Read / Write Characteristics (8080-series MPU)
t
DH80
t
OD80
t
DS80
t
ACC80
0.9V
DD
0.1V
DD
t
PW80(R)
, t
PW80(W)
t
CY80
t
AH80
t
AS80
DB0 to DB7
(Write)
DB6 to DB7
(Read)
RD, WR
CS1B
(CS2 = 1)
RS
Figure 31. Read / Write Characteristics (8080-series MPU)
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Item Signal Symbol Min. Typ.Max. Unit Remark
Address setup time
Address hold time RS tAS80
tAH80 13
17 - - ns
System cycle time RS tCY80 400 - - ns
Pulse width (WR) RW_WR tPW80(W) 55 - - ns
Pulse width (RD) E_RD tPW80(R) 125 - - ns
Data setup time
Data hold time tDS80
tDH80 35
13 - - ns
Read access time
Output disable time
DB7
to
DB0 tACC80
tOD80 -
10 -125
90 ns CL = 100 pF
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
50
Read / Write Characteristics (6800-series Microprocessor)
t
DH68
tOD68
t
DS68
tACC68
0.9VDD0.1VDD
t
PW68(R),
t
PW68(W)
tCY68
t
AH68
t
AS68
DB0 to DB7
(Write)
E
CS1B
(CS2 = 1)
RS
DB0 to DB7
(Read)
Figure 32. Read / Write Characteristics (6800-series Microprocessor)
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Item Signal Symbol Min. Typ.Max. Unit Remark
Address setup time
Address hold time RS tAS68
tAH68 13
17 - - ns
System cycle time RS tCY68 400 - - ns
Data setup time
Data hold time tDS68
tDH68 35
13 - - ns
Access time
Output disable time
DB7
to
DB0 tACC68
tOD68 -
10 -125
90 ns CL = 100 pF
Enable pulse
width Read
Write E_RD tPW68(R)
tPW68(W) 125
55 - - -
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
51
Serial Interface Characteristics
DB7
(SID)
DB6
(SCLK)
RS
CS1B
(CS2 = 1)
tDHS
tDSS
tWHS
0.9VDD 0.1VDD tWLS
tCYS
tAHStASS
tCHStCSS
Figure 33. Serial Interface Characteristics
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C )
Item Signal Symbol Min Typ Max Unit Remark
Serial clock cycle
SCLK high pulse width
SCLK low pulse width
DB6
(SCLK)
tCYS
tWHS
tWLS
450
180
135
-
-
-
-
-
-ns
Address setup time
Address hold time RS tASS
tAHS 90
360 -
--
-ns
Data setup time
Data hold time DB7
(SID) tDSS
tDHS 90
90 -
--
-ns
CS1B setup time
CS1B hold time CS1B tCSS
tCHS 55
180 -
--
-ns
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
52
Reset Input Timing
RESETB
tRW
Figure 34. Reset Input Timing
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Item Signal Symbol Min. Typ.Max. Unit Remark
Reset low pulse width RESETB tRW 900 - - ns
Display Control Output Timing
t
DM
CL
M
Figure 35. Display Control Output Timing
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Item Signal Symbol Min. Typ.Max. Unit Remark
M delay time MtDM -13 70 ns
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
53
REFERENCE APPLICATIONS
MICROPROCESSOR INTERFACE
In Case of Interfacing with 6800-series (PS = “H”, MI = “H”)
DB0 to DB7
RESETB
VDD
VDD
RW
E
RS
CS2
CS1B
6800-series
MPU
CS1B
CS2
RS
E_RD
RW_WR
DB0 to DB7
RESETB
MI
PS
KS0715
Figure 36. Interfacing with 6800-series (PS = “H”, MI = “H”)
In Case of Interfacing with 8080-series (PS = “H”, MI = “L”)
DB0 to DB7
RESETB
VDD
VSS
/WR
/RD
RS
CS2
CS1B
8080-series
MPU
CS1B
CS2
RS
E_RD
RW_WR
DB0 to DB7
RESETB
MI
PS
KS0715
Figure 37. Interfacing with 8080-series (PS = “H”, MI = “L”)
In Case of Serial Interface (PS = “L”, MI = “H/L”)
OPEN
RESETB
V
SS
V
DD
or V
SS
SCLK
SID
RS
CS2
CS1B
MPU
CS1B
CS2
RS
DB7(SID)
DB6(SCLK)
RESETB
DB0 to DB5
MI
PS
KS0715
Figure 38. Serial interface (PS = “L”, MI = “H/L”)
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
54
CONNECTIONS BETWEEN KS0715 AND LCD PANEL
Single Chip Configuration (1/33 Duty Configurations)
COM15
:
COM0
COMS
COMS
COM31
:
COM16
SEG99 ........... SEG0
KS0715
(Bottom View)
COM15
:
COM0
COMS
COMS
COM31
:
COM16
SEG0 ............ SEG99
KS0715
(Top View)
♣ ♦ ♥ ♠ Ξ
♣ ♦ ♥ ♠ Ξ
32 × 100 pixels
♣ ♦ ♥ ♠ Ξ
♣ ♦ ♥ ♠ Ξ
32 × 100 pixels
Figure 39. SHL = 0, ADC = 1 Figure 40. SHL = 0, ADC = 0
COMS
COM0
:
COM15
COM16
:
COM31
COMS
SEG99 ........... SEG0
KS0715
(Top View)
32 × 100 pixels
COM16
:
COM31
COMS
COMS
COM0
:
COM15
SEG0 ........... SEG99
KS0715
(Bottom View)
32 × 100 pixels
♣ ♦ ♥ ♠ Ξ
♣ ♦ ♥ ♠ Ξ
♣ ♦ ♥ ♠ Ξ
♣ ♦ ♥ ♠ Ξ
Figure 41. SHL = 1, ADC = 0 Figure 42. SHL = 1, ADC = 1
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
55
Multiple Chip Configuration
- 33COM (32COM + 1COMS) ×× 200SEG (100SEG ×× 2)
COM15
:
COM0
COMS
COMS
COM31
:
COM16
SEG99 ................... SEG0
KS0715
( Bottom View )
( Master )
COM15
:
COM0
COMS
COMS
COM31
:
COM16
SEG99 ................... SEG0
KS0715
( Bottom View )
( Slave )
♣ ♦ ♥ ♠ Ξ
♣ ♦ ♥ ♠ Ξ
32 × 200 pixels
Figure 43. SHL = 0, ADC = 1
♦ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
♣ ♦ ♥ ♠ Ξ
♣ ♦ ♥ ♠ Ξ
32 × 200 pixels
COM16
:
COM31
COMS
COMS
COM0
:
COM15
SEG0 ............... SEG99
KS0715
( Bottom View )
( Master )
COM16
:
COM31
COMS
COMS
COM0
:
COM15
SEG0 ............... SEG99
KS0715
( Bottom View )
( Slave )
Figure 44. SHL = 1, ADC = 0
♦ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
56
- 66COM (64COM + 2COMS) ×× 100SEG
COMS
COM0
:
COM15
COM16
:
COM31
COMS
SEG99 ................... SEG0
KS0715
( Top View )
( Slave )
COMS
COM31
:
COM16
COM15
:
COM0
COMS
SEG0 ................... SEG99
KS0715
( Top View )
( Master )
♣ ♦ ♥ ♠ Ξ
♣ ♦ ♥ ♠ Ξ
64 × 100 pixels
Figure 45. 66COM (64COM + 2COMS) ×× 100SEG
♦ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
♦ Common / Segment output direction select
- Master chip: SHL = 0, ADC = 0
- Slave chip: SHL = 1, ADC = 1
KS0715 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
57
TCP PIN LAYOUT (SAMPLE)
KS0715
(TOP VIEW)
FRS
M
CL
DISP
MS
RESETB
PS
CS1B
CS2
MI
RS
RW_WR
E_RD
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS
VOUT
C3+
C3-
C1+
C1-
C2+
C2-
VSS
VR
V0
V1
V2
V3
V4
VSS
TEMPS
COMS
COM31
COM30
:
:
:
COM26
COM25
COM24
:
:
:
COM19
COM18
COM17
COM16
SEG99
SEG98
SEG97
SEG96
:
:
:
:
SEG66
SEG65
SEG64
SEG63
:
:
:
:
SEG3
SEG2
SEG1
SEG0
COMS
COM0
COM1
:
:
:
COM7
COM8
COM9
:
:
:
COM13
COM14
COM15
COMS
Figure 46. TCP Pin Layout
