Semiconductor Components Industries, LLC, 2002
April, 2002 – Rev. 4 1Publication Order Number:
MC10E122/D
MC10E122, MC100E122
5VECL 9Bit Buffer
The MC10E/100E122 is a 9-bit buffer. The device contains nine
non-inverting buffer gates.
The 100 Series contains temperature compensation.
500 ps Max. Propagation Delay
PECL Mode Operating Range: VCC= 4.2 V to 5.7 V
with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V
with VEE= –4.2 V to –5.7 V
Internal Input Pulldown Resistors
ESD Protection: > 2 KV HBM, > 200 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 111 devices
Device Package Shipping
ORDERING INFORMATION
MC10E122FN PLCC–28 37 Units/Rail
MC10E122FNR2 PLCC–28 500 Units/Reel
MC100E122FN PLCC–28 37 Units/Rail
MC100E122FNR2 PLCC–28 500 Units/Reel
MARKING
DIAGRAMS
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PLCC–28
FN SUFFIX
CASE 776
MC10E122FN
AWLYYWW
MC100E122FN
AWLYYWW
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128
128
MC10E122, MC100E122
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2
VCCO
VCCO
NCNCNCD8
D7
D6
D5
VEE
D4
D3
D2
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115678910
VCCO Q8
Q7
Q6
VCC
Q5
Q4
VCCO
Q3
D1D0VCCO Q0Q1Q2
1Pinout: 28-Lead PLCC
(Top View)
* All VCC and VCCO pins are tied together on the die.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
PIN DESCRIPTION
PIN FUNCTION
D0 – D8ECL Data Inputs
Q0 – Q8ECL Data Outputs
VCC, VCCO Positive Supply
VEE Negative Supply
NC No Connect
MAXIMUM RATINGS (Note 1)
Symbol Parameter Condition 1 Condition 2 Rating Units
VCC PECL Mode Power Supply VEE = 0 V 8 V
VEE NECL Mode Power Supply VCC = 0 V –8 V
VIPECL Mode Input Voltage VEE = 0 V VI VCC 6 V
I
C ode u o age
NECL Mode Input Voltage
EE 0
VCC = 0 V
ICC
VI VEE
6
–6 V
Iout Output Current Continuous
Surge 50
100 mA
mA
TA Operating Temperature Range 0 to +85 °C
Tstg Storage Temperature Range –65 to +150 °C
θJA Thermal Resistance (Junction to Ambient) 0 LFPM
500 LFPM 28 PLCC
28 PLCC 63.5
43.5 °C/W
°C/W
θJC Thermal Resistance (Junction to Case) std bd 28 PLCC 22 to 26 °C/W
VEE PECL Operating Range
NECL Operating Range 4.2 to 5.7
–5.7 to –4.2 V
V
Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C
1. Maximum Ratings are those values beyond which device damage may occur.
MC10E122, MC100E122
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3
10E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1)
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 41 49 41 49 41 49 mA
VOH Output HIGH Voltage (Note 2) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mV
VOL Output LOW Voltage (Note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mV
VIH Input HIGH Voltage 3830 3995 4160 3870 4030 4190 3940 4110 4280 mV
VIL Input LOW Voltage 3050 3285 3520 3050 3285 3520 3050 3302 3555 mV
IIH Input HIGH Current 200 200 200 µA
IIL Input LOW Current 0.5 0.3 0.5 0.25 0.3 0.2 µA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / –0.06 V.
2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts.
10E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= –5.0 V (Note 1)
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 41 49 41 49 41 49 mA
VOH Output HIGH Voltage –1020 –930 –840 –980 –895 –810 –910 –815 –720 mV
VOL Output LOW Voltage –1950 –1790 –1630 –1950 –1790 –1630 –1950 –1773 –1595 mV
VIH Input HIGH Voltage –1170 –1005 –840 –1130 –970 –810 –1060 –890 –720 mV
VIL Input LOW Voltage –1950 –1715 –1480 –1950 –1715 –1480 –1950 –1698 –1445 mV
IIH Input HIGH Current 200 200 200 µA
IIL Input LOW Current 0.5 0.3 0.5 0.065 0.3 0.2 µA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / –0.06 V.
2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts.
100E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1)
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 41 49 41 49 47 57 mA
VOH Output HIGH Voltage 3975 4050 4120 3975 4050 4120 3975 4050 4120 mV
VOL Output LOW Voltage 3190 3295 3380 3190 3255 3380 3190 3260 3380 mV
VIH Input HIGH Voltage 3835 4050 4120 3835 4120 4120 3835 4120 4120 mV
VIL Input LOW Voltage 3190 3300 3525 3190 3525 3525 3190 3525 3525 mV
IIH Input HIGH Current 200 200 200 µA
IIL Input LOW Current 0.5 0.3 0.5 0.25 0.5 0.2 µA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / –0.8 V.
2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts.
100E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= –5.0 V (Note 1)
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 41 49 41 49 47 57 mA
VOH Output HIGH Voltage –1025 –950 –880 –1025 –950 –880 –1025 –950 –880 mV
VOL Output LOW Voltage –1810 –1705 –1620 –1810 –1745 –1620 –1810 –1740 –1620 mV
VIH Input HIGH Voltage –1165 –950 –880 –1165 –880 –880 –1165 –880 –880 mV
VIL Input LOW Voltage –1810 –1700 –1475 –1810 –1475 –1475 –1810 –1475 –1475 mV
IIH Input HIGH Current 200 200 200 µA
IIL Input LOW Current 0.5 0.3 0.5 0.25 0.5 0.2 µA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / –0.8 V.
2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts.
MC10E122, MC100E122
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4
AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= –5.0 V (Note 1)
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
fMAX Maximum Toggle Frequency TBD TBD TBD GHz
tPLH Propagation Delay to Output ps
tPHL D to Q 150 350 500 150 350 500 150 350 500
tSKEW Within-Device Skew ps
D to Q (Note 1.) 75 75 75
tJITTER Cycle–to–Cycle Jitter TBD TBD TBD ps
trRise/Fall Times ps
tf (20 - 80%) 300 425 800 300 425 800 300 425 800
1. 10 Series: VEE can vary +0.46 V / –0.06 V.
100 Series: VEE can vary +0.46 V / –0.8 V.
1. Within-device skew is defined as identical transitions on similar paths through a device.
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Driver
Device Receiver
Device
QD
50
50
VTT
Q D
VTT = VCC – 2.0 V
Resource Reference of Application Notes
AN1404 ECLinPS Circuit Performance at Non–Standard VIH Levels
AN1405 ECL Clock Distribution Techniques
AN1406 Designing with PECL (ECL at +5.0 V)
AN1503 ECLinPS I/O SPICE Modeling Kit
AN1504 Metastability and the ECLinPS Family
AN1568 Interfacing Between LVDS and ECL
AN1596 ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650 Using Wire–OR Ties in ECLinPS Designs
AN1672 The ECL Translator Guide
AND8001 Odd Number Counters Design
AND8002 Marking and Date Codes
AND8020 Termination of ECL Logic Devices
MC10E122, MC100E122
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5
PACKAGE DIMENSIONS
PLCC–28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE E
–N–
–M–
–L–
V
WD
D
Y BRK
28 1
VIEW S
S
L-M
S
0.010 (0.250) N S
T
S
L-M
M
0.007 (0.180) N S
T
0.004 (0.100)
G1
GJ
C
ZR
E
A
SEATING
PLANE
S
L-M
M
0.007 (0.180) N S
T
–T–
B
S
L-M
S
0.010 (0.250) N S
T
S
L-M
M
0.007 (0.180) N S
T
U
S
L-M
M
0.007 (0.180) N S
T
Z
G1X
VIEW D–D
S
L-M
M
0.007 (0.180) N S
T
K1
VIEW S
H
K
FS
L-M
M
0.007 (0.180) N S
T
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.485 0.495 12.32 12.57
B0.485 0.495 12.32 12.57
C0.165 0.180 4.20 4.57
E0.090 0.110 2.29 2.79
F0.013 0.019 0.33 0.48
G0.050 BSC 1.27 BSC
H0.026 0.032 0.66 0.81
J0.020 --- 0.51 ---
K0.025 --- 0.64 ---
R0.450 0.456 11.43 11.58
U0.450 0.456 11.43 11.58
V0.042 0.048 1.07 1.21
W0.042 0.048 1.07 1.21
X0.042 0.056 1.07 1.42
Y--- 0.020 --- 0.50
Z2 10 2 10
G1 0.410 0.430 10.42 10.92
K1 0.040 --- 1.02 ---
 
MC10E122, MC100E122
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6
Notes
MC10E122, MC100E122
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7
Notes
MC10E122, MC100E122
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8
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MC10E122/D
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