Confidential HV7131R
This document is a general product description and is subject to change without notice. MagnaChip
Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent
licenses are implied.
- 11 - 2004 MagnaChip Semiconductor Ltd.
Register Description
Register Symbol Address Default Description
Device ID DEVID 00h 02h Product Identification, Revision
Number.
Sensor Control A SCTRA 01h 09h ClkDiv[6:4], ABLCEn[3], PxlVs[2],
XFlip[1], YFlip[0]
Sensor Control B SCTRB 02h 01h VCLK Disable[6], ADCPwDn[5], Black
Mode[4], Sleep[3], VsHsEn[2],
BLDataEn[1], StrobeEn[0]
Output Inversion OUTIV 03h 00h ByrDpcEn[6], ByrDpcTh[5:4],
ClkHSC[3], InvVSC[2], InvHSC[1],
InvVCLK[0]
Row Start Add Upper RSAU 10h 00h Row Start Address Upper Byte[8]
Row Start Add Lower RSAL 11h 02h Row Start Address Lower Byte[7:0]
Col. Start Add Upper CSAU 12h 00h Column Start Address Upper Byte[9:8]
Col. Start Add Lower CSAL 13h 02h Column Start Address Lower Byte[7:0]
Window Height Upper WIHU 14h 01h Window Height Upper Byte[8]
Window Height Lower WIHL 15h e2h Window Height Lower Byte[7:0]
Window Width Upper WIWU 16h 02h Window Width Upper Byte[9:8]
Window Width Lower WIWL 17h 82h Wind ow Width Lower Byte[7:0]
HBLANK T ime Upper HBLU 20h 00h HBLANK Time Upper Byte[15:8].
HBLANK T ime Lower HBLL 21h d0h HBLANK Time Lower Byte[7:0].
VBLANK Time Upper VBLU 22h 00h VBLANK Time Upper Byte[15:8].
VBLANK Time Lower VBLL 23h 08h VBLANK Time Lower Byte[7:0].
Integration T i me High INTH 25h 06h Integration T i me [23:16]
Integration Time
Middle INTM 26h 5Bh Integration Time [15:8]
Integration T i me Low INTL 27h 9ah Integration T i me [7:0]
Pre-amp Gain PAG 30h 10h Gain for Pre-amp (0.5~16.5 times with
8bit resolution) [7:0]
Red Color Gain RCG 31h 10h Gain for Red Pixel Read-out (0.5~2
times with 6bit resolution) [5:0]
Green Color Gain GCG 32h 10h Gain for Green Pixel Read-out (0.5~2
times with 6bit resolution [5:0]
Blue Color Gain BCG 33h 10h Gain for Blue Pixel Read-out (0.5~2
times with 6bit resolution [5:0]
Analog Bias Control A ACTRA 34h 17h CDS Bias [6:4], PGA Bias [3:0]
Analog Bias Control B ACTRB 35h 7fh Reset Clamp [7:4], ADC Bias [3:0]
Black Level Threshold BLCTH 40h ffh Auto Black Level Pixel Threshold
Value
Initial ADC Offset Red ORedI 41h 7fh Initial ADC Offset Red
Initial ADC Offset
Green OGrnI 42h 7fh Initial ADC Offset Green
Initial ADC Offset Blue OBluI 43h 7fh Initial ADC Offset Blue