STR71xF ARM7TDMITM 32-bit MCU with Flash, USB, CAN 5 timers, ADC, 10 communications interfaces Features Core - ARM7TDMI 32-bit RISC CPU - 59 MIPS @ 66 MHz from SRAM - 45 MIPS @ 50 MHz from Flash LQFP64 10 x 10 Memories - Up to 256 Kbytes Flash program memory (10 kcycles endurance, 20 years retention @ 85 C) - 16 Kbytes Flash data memory (100 kcycles endurance, 20 years retention@ 85 C) - Up to 64 Kbytes RAM - External Memory Interface (EMI) for up to 4 banks of SRAM, Flash, ROM - Multi-boot capability LFBGA64 8 8x x8 8x x1.7 LFBGA64 1.7 Clock, reset and supply management - 3.0 to 3.6V application supply and I/Os - Internal 1.8V regulator for core supply - Clock input from 0 to 16.5 MHz - Embedded RTC osc. running from external 32 kHz crystal - Embedded PLL for CPU clock - Realtime Clock for clock-calendar function - 5 power saving modes: SLOW, WAIT, LPWAIT, STOP and STANDBY modes Nested interrupt controller - Fast interrupt handling with multiple vectors - 32 vectors with 16 IRQ priority levels - 2 maskable FIQ sources Up to 48 I/O ports - 30/32/48 multifunctional bidirectional I/Os Up to 14 ports with interrupt capability February 2008 LQFP144 20 x 20 LFBGA144 10 x 10 x 1.7 5 Timers - 16-bit watchdog timer - 3 16-bit timers with 2 input captures, 2 output compares, PWM and pulse counter - 16-bit timer for timebase functions 10 communications interfaces - 2 I2C interfaces (1 multiplexed with SPI) - 4 UART asynchronous serial interfaces - Smartcard ISO7816-3 interface on UART1 - 2 BSPI synchronous serial interfaces - CAN interface (2.0B Active) - USB Full Speed (12 Mbit/s) Device Function with Suspend and Resume - HDLC synchronous communications 4-channel 12-bit A/D converter - Sampling frequency up to 1 kHz - Conversion range: 0 to 2.5 V Development tools support - Atomic bit SET and RES operations Table 1. Device summary Reference Root part number STR71xF STR710FZ1, STR710FZ2, STR711FR0, STR711FR1, STR711FR2, STR712FR0, STR712FR1, STR712FR2, STR715FR0 Rev 12 1/78 www.st.com 78 Contents STR71xF Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 3.1 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Pin description for 144-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 Pin description for 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 External connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6 I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.7 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1 2/78 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.1 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.2 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3.3 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.4 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3.5 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.6 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3.7 EMI - external memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3.8 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.3.9 BSPI - buffered serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.10 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.3.11 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 STR71xF 5 Contents Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6 Product history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Note: For detailed information on the STR71x Microcontroller memory, registers and peripherals, please refer to the STR71x Reference Manual. 3/78 Introduction 1 STR71xF Introduction This datasheet provides the STR71x pinout, ordering information, mechanical and electrical device characteristics. For complete information on the STR71x microcontroller memory, registers and peripherals. please refer to the STR71x reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STR7 Flash programming reference manual. For information on the ARM7TDMI core please refer to the ARM7TDMI technical reference manual. Table 2. Device overview Features STR710 FZ1 STR710 FZ2 STR710 RZ STR711 FR0 STR711 FR1 STR711 FR2 STR712 FR0 STR712 FR1 STR712 FR2 STR715 FRx Flash - Kbytes 128+16 256+16 0 64+16 128+16 256+16 64+16 128+16 256+16 64+16 RAM - Kbytes 32 64 64 16 32 64 16 32 64 16 Peripheral Functions CAN, EMI, USB, 48 I/Os USB, 30 I/Os Operating Voltage 3.0 to 3.6 V Operating Temperature -40 to +85C or 0 to 70 C T=LQFP144 20 x 20 H=LFBGA144 10 x10 Packages . 4/78 CAN, 32 I/Os T=LQFP64 10 x10 / H=LFBGA64 8 x 8 x 1.7 32 I/Os STR71xF 2 Description Description ARM(R) core with embedded Flash and RAM The STR71x series is a family of ARM-powered 32-bit microcontrollers with embedded Flash and RAM. It combines the high performance ARM7TDMI CPU with an extensive range of peripheral functions and enhanced I/O capabilities. STR71xF devices have on-chip high-speed single voltage FLASH memory and high-speed RAM. STR710R devices have high-speed RAM but no internal Flash. The STR71x family has an embedded ARM core and is therefore compatible with all ARM tools and software. Extensive tools support STMicroelectronics' 32-bit, ARM core-based microcontrollers are supported by a complete range of high-end and low-cost development tools to meet the needs of application developers. This extensive line of hardware/software tools includes starter kits and complete development packages all tailored for ST's ARM core-based MCUs. The range of development packages includes third-party solutions that come complete with a graphical development environment and an in-circuit emulator/programmer featuring a JTAG application interface. These support a range of embedded operating systems (OS), while several royalty-free OSs are also available. For more information, please refer to ST MCU site http://www.st.com/mcu 5/78 System architecture 3 STR71xF System architecture Package choice: low pin-count 64-pin or feature-rich 144-pin LQFP or BGA The STR71x family is available in 5 main versions. The 144-pin versions have the full set of all features including CAN, USB and External Memory Interface (EMI). STR710F: 144-pin BGA or LQFP with CAN, USB and EMI STR710R: Flashless 144-pin BGA or LQFP with CAN, USB and EMI (no internal Flash memory) The three 64-pin versions (BGA or LQFP) do not include External Memory Interface. STR715F: 64-pin BGA or LQFP without CAN or USB STR711F: 64-pin BGA or LQFP with USB STR712F: 64-pin BGA or LQFP with CAN High speed Flash memory (STR71xF) The Flash program memory is organized in two banks of 32-bit wide Burst Flash memories enabling true read-while-write (RWW) operation. Device Bank 0 is up to 256 Kbytes in size, typically for the application program code. Bank 1 is 16 Kbytes, typically used for storing data constants. Both banks are accessed by the CPU with zero wait states @ 33 MHz Bank 0 memory endurance is 10K write/erase cycles and Bank 1 endurance is 100K write/erase cycles. Data retention is 20 years at 85C on both banks. The two banks can be accessed independently in read or write. Flash memory can be accessed in two modes: Burst mode: 64-bit wide memory access at up to 50 MHz. Direct 32-bit wide memory access for deterministic operation at up to 33 MHz. The STR7 embedded Flash memory can be programmed using In-Circuit Programming or In-Application programming. IAP (in-application programming): The IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. ICP (in-circuit programming): The ICP is the ability to program the Flash memory of a microcontroller using JTAG protocol while the device is mounted on the user application board. The Flash memory can be protected against different types of unwanted access (read/write/erase). There are two types of protection: Sector Write Protection Flash Debug Protection (locks JTAG access) Refer to the STR7 Flash Programming Reference manual for details. Optional external memory (STR710) The non-multiplexed 16-bit data/24-bit address bus available on the STR710 (144-pin) supports four 16-Mbyte banks of external memory. Wait states are programmable individually for each bank allowing different memory types (Flash, EPROM, ROM, SRAM etc.) to be used to store programs or data. Figure 1 shows the general block diagram of the device family. 6/78 STR71xF System architecture Flexible power management To minimize power consumption, you can program the STR71x to switch to SLOW, WAIT, LPWAIT (low power wait), STOP or STANDBY mode depending on the current system activity in the application. Flexible clock control Two external clock sources can be used, a main clock and a 32 kHz backup clock. The embedded PLL allows the internal system clock (up to 66 MHz) to be generated from a main clock frequency of 16 MHz or less. The PLL output frequency can be programmed using a wide selection of multipliers and dividers. The microcontroller core, APB1 and APB2 peripherals are in separate clock domains and can be programmed to run at different frequencies during application runtime. The clock to each peripheral is gated with an individual control bit to optimize power usage by turning off peripherals any time they are not required. Voltage regulators The STR71x requires an external 3.0-3.6V power supply. There are two internal Voltage Regulators for generating the 1.8V power supply for the core and peripherals. The main VR is switched off during low power operation. Low voltage detectors Both the Main Voltage Regulator and the Low Power Voltage Regulator contain each a low voltage detection circuitry which keep the device under reset when the corresponding controlled voltage value (V18 or V18BKP) falls below 1.35V (+/- 10%). This enhances the security of the system by preventing the MCU from going into an unpredictable state. An external reset circuit must be used to provide the RESET at V33 power-up. It is not sufficient to rely on the RESET generated by the LVD in this case. This is because LVD operation is guaranteed only when V33 is within the specification. 3.1 On-chip peripherals CAN interface (STR710 and STR712) The CAN module is compliant with the CAN specification V2.0 part B (active). The bit rate can be programmed up to 1 MBaud. USB interface (STR710 and STR711) The full-speed USB interface is USB V2.0 compliant and provides up to 16 bidirectional/32 unidirectional endpoints, up to 12 Mb/s (full-speed), support for bulk transfer, isochronous transfers and USB Suspend/Resume functions. Standard timers Each of the four timers have a 16-bit free-running counter with 7-bit prescaler Three timers each provide up to two input capture/output compare functions, a pulse counter function, and a PWM channel with selectable frequency. The fourth timer is not connected to the I/O ports. It can be used by the application software for general timing functions. 7/78 System architecture STR71xF Realtime clock (RTC) The RTC provides a set of continuously running counters driven by the 32 kHz external crystal. The RTC can be used as a general timebase or clock/calendar/alarm function. When the STR71x is in Standby mode the RTC can be kept running, powered by the low power voltage regulator and driven by the 32 kHz external crystal. UARTs The 4 UARTs allow full duplex, asynchronous, communications with external devices with independently programmable TX and RX baud rates up to 1.25 Mb/s. Smartcard interface UART1 is configurable to function either as a general purpose UART or as an asynchronous Smartcard interface as defined by ISO 7816-3. It includes Smartcard clock generation and provides support features for synchronous cards. Buffered serial peripheral interfaces (BSPI) Each of the two SPIs allow full duplex, synchronous communications with external devices, master or slave communication at up to 5.5 Mb/s in Master mode and 4 Mb/s in Slave mode. I2C interfaces The two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 kHz) and 7 or 10-bit addressing modes. One I2C Interface is multiplexed with one SPI, so either 2xSPI+1x I2C or 1xSPI+2x I2C may be used at a time. HDLC interface The High Level Data Link Controller (HDLC) unit supports full duplex operation and NRZ, NRZI, FM0 or MANCHESTER protocols. It has an internal 8-bit baud rate generator. A/D converter The Analog to Digital Converter, converts in single channel or up to 4 channels in singleshot or round robin mode. Resolution is 12-bit with a sampling frequency of up to 1 kHz. The input voltage range is 0-2.5V. Watchdog The 16-bit Watchdog Timer protects the application against hardware or software failures and ensures recovery by generating a reset. I/O ports The 48 I/O ports are programmable as Inputs or Outputs. External interrupts Up to 14 external interrupts are available for application use or to wake up the application from STOP mode. 8/78 STR71xF System architecture Figure 1. STR71x block diagram A[19:0] D[15:0] RDN WEN[1:0] JTDI JTCK JTMS JTRST JTDO DBGRQS BOOTEN PRCCU/PLL EXT. MEM. INTERFACE (EMI) ARM7TDMI CPU FLASH* Program Memory 64/128/256K ARM7 NATIVE BUS CK CKOUT RSTIN A[23:20] (AF) CS[3:0) JTAG 16K Data FLASH* RAM 16/32/64K APB BRIDGE 1 V18[1:0] V33[6:0] VSS[9:0] V18BKP AVDD AVSS POWER SUPPLY VREG INTERRUPT CTL(EIC) I2C1 2 AF A/D BSPI0 4 AF TIMER0 BSPI1 4 AF 4 AF TIMER1 UART0 2 AF 2 AF TIMER2 UART1 / SMARTCARD 3 AF 4 AF TIMER3 UART2 2 AF RTC UART3 2 AF EXT INT (XTI) HDLC 3 AF OSC 14 AF APB BUS 2 AF APB BUS I2C0 4 AF STDBY RTCXTO RTCXTI WAKEUP APB BRIDGE 2 WATCHDOG USB P0[15:0] I/O PORT 0 P1[15:0] I/O PORT 1 P2[15:0] I/O PORT 2 1 AF CAN *Flash present in STR710F, not in STR710R USBDP USBDN 2 AF AF: alternate function on I/O port pin 9/78 System architecture 3.2 STR71xF Related documentation Available from www.arm.com: ARM7TDMI Technical reference manual Available from http://www.st.com: STR71x Reference manual STR7 Flash programming manual AN1774 - STR71x Software development getting started AN1775 - STR71x Hardware development getting started AN1776 - STR71x Enhanced interrupt controller AN1777 - STR71x memory mapping AN1780 - Real time clock with STR71x AN1781 - Four 7 segment display drive using the STR71x The above is a selected list only, a full list STR71x application notes can be viewed at http://www.st.com. 10/78 STR71xF Pin description for 144-pin packages STR710 LQFP pinout 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V33 WEn.0 WEn.1 A.19 A.18 A.17 A.16 A.15 A.14 V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX A.13 A.12 A.11 A.10 A.9 A.8 A.7 A.6 A.5 V33 VSS P1.15/HTXD N.C. N.C. Figure 2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9 V33 VSS A.4 A.3 A.2 A.1 A.0 D.15 D.14 D.13 D.12 D.11 D.10 USBDN USBDP P1.12/CANTX P1.11/CANRX N.C. P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL D.9 D.8 D.7 D.6 D.5 P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 P0.10/U1.RX/U1.TX/SCDATA RDn P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS V33 P2.0/CSn.0 P2.1/CSn.1 P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA P2.2/CSn.2 P2.3/CSn.3 P2.4/A.20 P2.5/A.21 P2.6/A.22 BOOTEN P2.7/A.23 P2.8 N.C. N.C. VSS V33 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 JTDI JTMS JTCK JTDO JTRSTn NU TEST N.C. TEST N.C. V33IO-PLL N.C. VSSIO-PLL N.C. DBGRQS CKOUT CK P0.15/WAKEUP N.C. RTCXTI RTCXTO STDBY RSTIN N.C. VSSBKP V18BKP N.C. N.C. V18 VSS18 N.C. D.0 D.1 D.2 D.3 D.4 AVDD AVSS N.C. N.C. N.C. P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1 3.3 System architecture 11/78 System architecture Table 3. STR71xF STR710 BGA ball connections A B C D E F G H J K L M 1 P0.10 P2.0 P2.1 VSS P2.2 P2.6 BOOT EN P2.12 P2.13 P2.15 JTDI N.C. 2 VSS RDn P0.11 V33 P2.3 P2.8 P2.9 JTMS JTRST n TEST TEST N.C. 3 V33 P0.9 P0.12 P0.13 P2.4 N.C. P2.10 JTCK NU V33 N.C. DBG RQS 4 P0.6 P0.7 P0.8 P0.14 P2.5 N.C. P2.11 JTDO CK CKOUT VSSIOPLL N.C. 5 A.19 WEn.1 WEn.0 P0.5 P2.7 VSS P2.14 N.C. RTCXTO RTCXTI N.C. P0.15 6 P0.3 A.15 A.16 A.17 A.18 V33 V18 N.C. N.C. V18BK P VSS BKP STDBY 7 P0.2 P0.1 P0.4 VSS18 V18 A.14 D.12 D.1 D.0 nc VSS18 RSTIN 8 A.9 A.10 A.11 A.13 P0.0 A.0 D.11 P1.12/ CANTX N.C. AVSS D.3 D.2 9 VSS V33 A.5 A.6 V33 D.15 D.10 P1.8 D.9 P1.0 N.C. N.C. 10 A.8 N.C. P1.15 P1.13 VSS D.14 USBDN P1.7 D.8 P1.5 P1.1 D.4 11 A.7 N.C. P1.14 P1.10 A.2 D.13 USBDP VSS D.5 P1.4 P1.3 AVDD 12 A.12 A.4 A.3 P1.9 A.1 P1.11/ CANRX N.C. V33IOPLL P1.6 D.7 D.6 P1.2 Legend / abbreviations for Table 4: Type: I = input, O = output, S = supply, HiZ= high impedance, In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.3VDD/0.7VDD with input trigger TT= TTL 0.8 V/2 V with input trigger C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8 V / 2 V Port and control configuration: 12/78 Input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100k weak pull-up is enabled. pd = in reset state, the internal 100k weak pull-down is enabled. Output: OD = open drain (logic level) PP = push-pull T = true OD, (P-Buffer and protection diode to VDD not implemented), 5 V tolerant. STR71xF PP OD Output Capability interrupt Input Input level Pin name Type BGA144 LQFP144 Pin n Active in Stdby STR710 pin description Reset state1) Table 4. System architecture Main function (after reset) Alternate function UART1: Receive Data input UART1: Transmit data output. Note: This pin may be used for Port 0.10 Smartcard DataIn/DataOut or single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress 1 A1 P0.10/U1.RX/ U1.TX/ SC.DATA I/O pd 2 B2 RD O 3 C2 P0.11/BOOT.1 I/O pd /U1.TX CT 4 C3 P0.12/SC.CLK I/O pd CT 5 D1 VSS S Ground voltage for digital I/Os4) 6 D2 V33 S Supply voltage for digital I/Os4) CT X 4mA T X External Memory Interface: Active low read signal for external memory. It maps to the OE_N input of the external components. 4mA X X Select Boot Port 0.11 Configuration input 4mA X X Port 0.12 Smartcard reference clock output 5) UART1: Transmit data output. CT 8mA X X Port 2.0 External Memory Interface: Select Memory Bank 0 output Note: This pin is forced to output push-pull 1 mode at reset to allow boot from external memory 2) CT 8mA X X Port 2.1 External Memory Interface: Select Memory Bank 1 output P0.13/U2.RX/ T2.OCMPA I/O pu CT X 4mA X X UART2: Port 0.13 Receive Data input Timer2: Output Compare A output D4 P0.14/U2.TX/ T2.ICAPA I/O pu CT 4mA X X UART2: Port 0.14 Transmit data output Timer2: Input Capture A input 11 E1 P2.2/CS.2 I/O CT 8mA X X Port 2.2 External Memory Interface: Select Memory Bank 2 output 12 E2 P2.3/CS.3 I/O CT 8mA X X Port 2.3 External Memory Interface: Select Memory Bank 3 output 7 B1 P2.0/CS.0 I/O 8 C1 P2.1/CS.1 I/O 9 D3 10 8) pu pu 2) pu 2) 13/78 System architecture Capability Output Main function (after reset) P2.4/A.20 I/O 14 E4 P2.5/A.21 I/O 15 F1 P2.6/A.22 I/O 16 G1 BOOTEN 17 E5 P2.7/A.23 I/O 3) CT 8mA X X Port 2.7 External Memory Interface: address bus 18 F2 P2.8 I/O pu CT X 4mA X X Port 2.8 External interrupt INT2 19 F3 N.C. Not connected (not bonded) 20 F4 N.C. Not connected (not bonded) 21 F5 VSS S Ground voltage for digital I/Os4) 22 F6 V33 S Supply voltage for digital I/Os4) 23 G2 P2.9 I/O pu CT X 4mA X X Port 2.9 External interrupt INT3 24 G3 P2.10 I/O pu CT X 4mA X X Port 2.10 External interrupt INT4 25 G4 P2.11 I/O pu CT X 4mA X X Port 2.11 External interrupt INT5 26 H1 P2.12 I/O pu CT 4mA X X Port 2.12 27 J1 P2.13 I/O pu CT 4mA X X Port 2.13 28 G5 P2.14 I/O pu CT 4mA X X Port 2.14 29 K1 P2.15 I/O pu CT 4mA X X Port 2.15 30 L1 JTDI I TT JTAG Data input. External pull-up required. 31 H2 JTMS I TT JTAG Mode Selection Input. External pull-up required. 32 H3 JTCK I C JTAG Clock Input. External pull-up or pull-down required. 33 H4 JTDO O 34 J2 JTRST I 35 J3 NU Reserved, must be forced to ground. 36 K2 TEST Reserved, must be forced to ground. 37 M1 N.C. Not connected (not bonded) 38 L2 TEST Reserved, must be forced to ground. 39 L3 N.C. Not connected (not bonded) 14/78 pd 3) pd 3) pd 3) I PP E3 OD 13 Pin name interrupt BGA144 Input level Input LQFP144 Type Pin n Active in Stdby STR710 pin description Reset state1) Table 4. STR71xF CT 8mA X X Port 2.4 CT 8mA X X Port 2.5 CT 8mA X X Port 2.6 8mA TT External Memory Interface: address bus Boot control input. Enables sampling of BOOT[1:0] pins CT pd Alternate function X JTAG Data output. Note: Reset state = HiZ. JTAG Reset Input. External pull-up required. STR71xF M4 N.C. 42 L4 43 M2 N.C. 44 M3 DBGRQS I 45 K4 CKOUT O 46 J4 CK I C 47 M5 P0.15/ WAKEUP I TT VSSIO-PLL PP 41 V33IO-PLL OD K3 Output Capability 40 Pin name interrupt BGA144 Input level Input LQFP144 Type Pin n Active in Stdby STR710 pin description Reset state1) Table 4. System architecture Main function (after reset) Alternate function Supply voltage for digital I/O circuitry and for PLL reference S Not connected (not bonded) Ground voltage for digital I/O circuitry and for PLL reference4) S Not connected (not bonded) CT Debug Mode request input (active high) 8mA Clock output (fPCLK2) Note: Enabled by CKDIS register in APB Bridge 2 X Reference clock input Port 0.15 X Wakeup from Standby mode input. X Note: This port is input only. 48 L5 N.C. Not connected (not bonded) 49 K5 RTCXTI Realtime Clock input and input of 32 kHz oscillator amplifier circuit 50 J5 RTCXTO Output of 32 kHz oscillator amplifier circuit 51 M6 STDBY I/O CT 52 M7 RSTIN I CT 53 H5 N.C. 54 L6 VSSBKP 4mA X Input: Hardware Standby mode entry input active low. Caution: External pull-up to V33 required to select normal mode. X Output: Standby mode active low output following Software Standby mode entry. Note: In Standby mode all pins are in high impedance except those marked Active in Stdby X Reset input Not connected (not bonded) S X Stabilization for low power voltage regulator. S Stabilization for low power voltage regulator. Requires external capacitors of at least 1F between V18BKP and VSS18BKP. See Figure 5. X Note: If the low power voltage regulator is bypassed, this pin can be connected to an external 1.8V supply. 55 K6 V18BKP 56 J6 N.C. Not connected (not bonded) 57 H6 N.C. Not connected (not bonded) 58 G6 V18 S Stabilization for main voltage regulator. Requires external capacitors of at least 10F + 33nF between V18 and VSS18. See Figure 5. 15/78 System architecture N.C. 61 J7 D.0 S I/O 8mA 8mA H7 D.1 I/O 63 M8 D.2 I/O 6) 8mA I/O 6) 8mA I/O 6) 8mA D.3 65 M10 D.4 66 M11 VDDA Alternate function Not connected (not bonded) 6) 62 L8 Main function (after reset) Stabilization for main voltage regulator. 6) 64 PP K7 OD 60 Output Capability VSS18 interrupt L7 Input Input level BGA144 59 Pin name Type LQFP144 Pin n Active in Stdby STR710 pin description Reset state1) Table 4. STR71xF External Memory Interface: data bus S Supply voltage for A/D Converter S Ground voltage for A/D Converter 67 K8 VSSA 68 J8 N.C. Not connected (not bonded) 69 M9 N.C. Not connected (not bonded) 70 L9 N.C. Not connected (not bonded) 71 K9 P1.0/T3.OCM PB/AIN.0 72 P1.1/T3.ICAP L10 A/T3.EXTCLK/ I/O pu AIN.1 73 M12 P1.2/T3.OCM PA/AIN.2 74 L11 75 I/O pu CT 4mA X X Port 1.0 Timer 3: Output Compare B ADC: Analog input 0 CT 4mA X X Port 1.1 Timer 3: Input Capture A or ADC: Analog input 1 External Clock input I/O pu CT 4mA X X Port 1.2 Timer 3: Output Compare A ADC: Analog input 2 P1.3/T3.ICAP B/AIN.3 I/O pu CT 4mA X X Port 1.3 Timer 3: Input Capture B ADC: Analog input 3 K11 P1.4/T1.ICAP A/T1.EXTCLK I/O pu CT 4mA X X Port 1.4 Timer 1: Input Capture A Timer 1: External Clock input 76 K10 P1.5/T1.ICAP B I/O pu CT 4mA X X Port 1.5 Timer 1: Input Capture B 77 J12 P1.6/T1.OCM PB I/O pu CT 4mA X X Port 1.6 Timer 1: Output Compare B 78 J11 D.5 I/O 6) 8mA 79 L12 D.6 I/O 6) 8mA I/O 6) 8mA I/O 6) 8mA I/O 6) 8mA 80 81 82 16/78 K12 D.7 J10 D.8 J9 D.9 External Memory Interface: data bus STR71xF PP OD Output Capability interrupt Input Input level Pin name Type BGA144 LQFP144 Pin n Active in Stdby STR710 pin description Reset state1) Table 4. System architecture Main function (after reset) Alternate function 83 H12 V33IO-PLL S Supply voltage for digital I/O circuitry and for PLL reference4) 84 H11 VSSIO-PLL S Ground voltage for digital I/O circuitry and for PLL reference4) 85 H10 P1.7/T1.OCM PA I/O pu CT 4mA X X 86 H9 P1.8 I/O pd CT 4mA X X Port 1.7 Timer 1: Output Compare A Port 1.8 87 G12 N.C. 88 F12 P1.11/CANRX I/O pu CT X 4mA X X Port 1.11 CAN: receive data input Note: On STR710 and STR712 only 89 H8 CT 4mA X X Port 1.12 CAN: Transmit data output Note: On STR710 and STR712 only P1.12/CANTX Not connected (not bonded) I/O pu 90 G11 USBDP I/O CT USB bidirectional data (data +). Reset state = HiZ Note: On STR710 and STR711 only This pin requires an external pull-up to V33 to maintain a high level. 91 G10 USBDN I/O CT USB bidirectional data (data -). Reset state = HiZ Note: On STR710 and STR711 only. 92 G9 D.10 I/O 6) 8mA 93 G8 D.11 I/O 6) 8mA I/O 6) 8mA 8mA 94 G7 D.12 External Memory Interface: data bus 95 F11 D.13 I/O 6) 96 F10 D.14 I/O 6) 8mA 97 F9 I/O 6) 8mA O 7) 8mA X O 7) 8mA X 100 E11 A.2 O 7) 8mA X 101 C12 A.3 O 7) 8mA X 102 B12 A.4 O 7) 8mA X 103 E10 VSS S Ground voltage for digital I/O circuitry4) 104 S Supply voltage for digital I/O circuitry4) 98 99 F8 D.15 A.0 E12 A.1 E9 V33 105 D12 P1.9 106 D11 P1.10/ USBCLK External Memory Interface: address bus I/O pd CT 4mA X X Port 1.9 I/O pd C/ T 4mA X X Port 1.10 USB: 48 MHZ clock input 17/78 System architecture STR710 pin description X Port 1.13 HDLC: reference clock input I2C clock 108 C11 P1.14/HRXD/ I0.SDA I/O pu CT X 4mA X X Port 1.14 HDLC: Receive data input I2C serial data PP X 4mA X OD CT Capability I/O pd Pin name Type P1.13/HCLK/ I0.SCL BGA144 107 D10 LQFP144 interrupt Output Input level Input Reset state1) Pin n Active in Stdby Table 4. STR71xF Main function (after reset) Alternate function 109 B11 N.C. Not connected (not bonded) 110 B10 N.C. Not connected (not bonded) 111 C10 P1.15/HTXD I/O pu CT 4mA X X Port 1.15 HDLC: Transmit data output 112 A9 VSS S Ground voltage for digital I/O circuitry4) 113 B9 V33 S Supply voltage for digital I/O circuitry4) 114 C9 A.5 O 7) 8mA X 115 D9 A.6 O 7) 8mA X O 7) 8mA X O 7) 8mA X 8mA X 116 A11 A.7 117 A10 A.8 118 A8 A.9 O 7) 119 B8 A.10 O 7) 8mA X O 7) 8mA X O 7) 8mA X O 7) 8mA X 120 C8 A.11 121 A12 A.12 122 D8 A.13 External Memory Interface: address bus SPI0 Master in/Slave out data 123 E8 P0.0/S0.MISO I/O pu /U3.TX CT 4mA X X Port 0.0 UART3 Transmit data output Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Master UART3: Receive out/Slave in Data input data 124 18/78 B7 P0.1/S0.MOSI I/O pu /U3.RX CT X 4mA X X Port 0.1 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. STR71xF PP OD Output Capability interrupt Input Input level Pin name Type BGA144 LQFP144 Pin n Active in Stdby STR710 pin description Reset state1) Table 4. System architecture Main function (after reset) Alternate function BSPI0: Serial Clock 125 A7 P0.2/S0.SCLK I/O pu /I1.SCL CT X 4mA X X Port 0.2 I2C1: Serial clock Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. SPI0: Slave Select input active low. I2C1: Serial Data 126 A6 P0.3/S0.SS/ I1.SDA I/O pu CT 4mA X X Port 0.3 Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. 127 C7 P0.4/S1.MISO I/O pu CT 4mA X X Port 0.4 SPI1: Master in/Slave out data 128 D7 VSS18 S Stabilization for main voltage regulator. 129 E7 V18 S Stabilization for main voltage regulator. Requires external capacitors of at least 10F + 33nF between V18 and VSS18. See Figure 5. 130 F7 A.14 O 7) 8mA X O 7) 8mA X O 7) 8mA X 8mA X 131 132 B6 C6 A.15 A.16 External Memory Interface: address bus 133 D6 A.17 O 7) 134 E6 A.18 O 7) 8mA X 8mA X 135 A5 A.19 O 7) 136 B5 WE.1 O 5) 8mA X External Memory Interface: active low MSB write enable output 137 C5 WE.0 O 5) 8mA X External Memory Interface: active low LSB write enable output 138 A3 V33 S Supply voltage for digital I/Os4) 139 A2 VSS S Ground voltage for digital I/Os4) 140 D5 P0.5/S1.MOSI I/O pu CT 4mA X X Port 0.5 SPI1: Master out/Slave In data 141 A4 P0.6/S1.SCLK I/O pu CT X 4mA X X Port 0.6 SPI1: Serial Clock 142 B4 P0.7/S1.SS CT 4mA X X Port 0.7 SPI1: Slave Select input active low I/O pu 19/78 System architecture PP OD Output Capability interrupt Input Input level Pin name Type BGA144 LQFP144 Pin n Active in Stdby STR710 pin description Reset state1) Table 4. STR71xF Main function (after reset) Port 0.8 143 C4 P0.8/U0.RX/ U0.TX I/O pd CT 144 B3 P0.9/U0.TX/ BOOT.0 I/O pd CT X 4mA T 4mA X Alternate function UART0: Receive Data input UART0: Transmit data output. Note: This pin may be used for single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X Port 0.9 Select Boot Configuration input UART0: Transmit data output 1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 8 on page 29. The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must be configured by software as Alternate Function (see Table 8: Port bit configuration table on page 29) to be used by the External Memory Interface. 3. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output Address 0x0000 0000 using the External Memory Interface. To access memory banks greater than 1Mbyte, they need to be configured by software as Alternate Function (see Table 8: Port bit configuration table on page 29). 4. V33IO-PLL and V33 are internally connected. VSSIO-PLL and VSS are internally connected. 5. During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as Output Push-Pull. 6. During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as Hi-Z. 7. During the reset phase, these pins are in input pull-down state. When reset is released, they are configured as Output Push-Pull. 8. During the reset phase, this pin is in input floating state. When reset is released, it is configured as Output Push-Pull. 20/78 STR71xF Pin description for 64-pin packages STR712/STR715 LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX V33 VSS P1.15/HTXD Figure 3. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LQFP64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10 P1.9 VSS P1.12/CANTX1) P1.11/CANRX1) P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P0.10/U1.RX/U1.TX/SCDATA P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA BOOTEN VSS V33 JTDI JTMS JTCK JTDO nJTRST NU TEST V33IO-PLL VSSIO-PLL CK P0.15/WAKEUP RTCXTI RTCXTO STDBY RSTIN VSSBKP V18BKP V18 VSS18 AVDD AVSS P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1 3.4 System architecture 1) CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os. 21/78 System architecture STR71xF STR711 LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX V33 VSS P1.15/HTXD Figure 4. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LQFP64 P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9 VSS USBDN USBDP P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2 V33IO-PLL VSSIO-PLL CK P0.15/WAKEUP RTCXTI RTCXTO STDBY RSTIN VSSBKP V18BKP V18 VSS18 AVDD AVSS P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P0.10/U1.RX/U1.TX/SCDATA P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA BOOTEN VSS V33 JTDI JTMS JTCK JTDO nJTRST NU TEST Table 5. 22/78 STR711 BGA ball connections A B C D E F G H 1 P0.10 P0.11 P0.12 P0.14 V33 JTCK TEST V33IOPLL 2 P0.9 VSS P0.13 VSS JTMS JTRSTn P0.15 VSSIOPLL 3 P0.5 P0.7 BOOTEN JTDI NU STDBY RTCXTI CK 4 VSS18 VSS P0.8 JTDO AVDD V18BKP RSTIN RTCXTO 5 P0.2 P0.4 V18 P0.6 P1.9 P1.0 V18 VSSBKP 6 V33 P0.1 P0.3 P1.13 USBDP VSSIOPLL AVSS VSS18 7 VSS P0.0 P1.10 USBDN P1.7 P1.6 P1.5 P1.1 8 P1.15 P1.14 VSS P1.8 V33IOPLL P1.4 P1.3 P1.2 STR71xF System architecture Table 6. STR712/715 BGA Ball Connections A B C D E F G H 1 P0.10 P0.11 P0.12 P0.14 V33 JTCK TEST V33IOPLL 2 P0.9 VSS P0.13 VSS JTMS JTRSTn P0.15 VSSIOPLL 3 P0.5 P0.7 BOOTEN JTDI NU STDBY RTCXTI CK 4 VSS18 VSS P0.8 JTDO AVDD V18BKP RSTIN RTCXTO 5 P0.2 P0.4 V18 P0.6 P1.9 P1.0 V18 VSSBKP 6 V33 P0.1 P0.3 P1.13 P1.11/ CANRX1) VSSIOPLL AVSS VSS18 7 VSS P0.0 P1.10 P1.12/ CANTX1) P1.7 P1.6 P1.5 P1.1 8 P1.15 P1.14 VSS P1.8 V33IOPLL P1.4 P1.3 P1.2 1) CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os. Legend / abbreviations for Table 7: Type: I = input, O = output, S = supply, HiZ= high impedance, In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.3VDD/0.7VDD with input trigger TT= TTL 0.8V / 2V with input trigger C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8V / 2V Port and control configuration: Input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100k weak pull-up is enabled. pd = in reset state, the internal 100k weak pull-down is enabled. Output: OD = open drain (logic level) PP = push-pull T = true OD, (P-Buffer and protection diode to VDD not implemented), 5V tolerant. 23/78 System architecture PP OD Output Capability interrupt Input Input level Pin name Type BGA64 LQFP64 Pin n Active in Stdby STR711/STR712/STR715 pin description Reset state1) Table 7. STR71xF Main function (after reset) Alternate function UART1: Receive Data input 1 P0.10/U1.RX/ A1 U1.TX/ SC.DATA 2 B1 UART1: Transmit data output. Note: This pin may be used for Port 0.10 Smartcard DataIn/DataOut or single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress I/O pd CT X 4mA T P0.11/BOOT.1 I/O pd /U1.TX CT 4mA X X Select Boot Port 0.11 Configuration input 3 C1 P0.12/SC.CLK I/O pd CT 4mA X X Port 0.12 Smartcard reference clock output 4 B2 VSS 5 C2 P0.13/U2.RX/ T2.OCMPA I/O pu CT X 4mA X X UART2: Port 0.13 Receive Data input Timer2: Output Compare A output 6 D1 P0.14/U2.TX/ T2.ICAPA I/O pu CT 4mA X X UART2: Port 0.14 Transmit data output Timer2: Input Capture A input 7 C3 BOOTEN I 8 D2 VSS S Ground voltage for digital I/Os2) 9 E1 V33 S Supply voltage for digital I/Os2) UART1: Transmit data output. Ground voltage for digital I/Os2) S Boot control input. Enables sampling of BOOT[1:0] pins CT 10 D3 JTDI I TT JTAG Data input. External pull-up required. 11 E2 JTMS I TT JTAG Mode Selection Input. External pull-up required. 12 F1 JTCK I C JTAG Clock Input. External pull-up or pull-down required. 13 D4 JTDO O 14 F2 JTRST I 8mA TT X JTAG Data output. Note: Reset state = HiZ. JTAG Reset Input. External pull-up required. 15 E3 NU Reserved, must be forced to ground. 16 G1 TEST Reserved, must be forced to ground. 17 H1 V33IO-PLL S Supply voltage for digital I/O circuitry and for PLL reference2) 18 H2 VSSIO-PLL S Ground voltage for digital I/O circuitry and for PLL reference2) 19 H3 CK I 24/78 C Reference clock input STR71xF System architecture PP X OD TT Output Capability interrupt P0.15/ WAKEUP Input Input level 20 G2 Pin name Type BGA64 LQFP64 Pin n Active in Stdby STR711/STR712/STR715 pin description Reset state1) Table 7. Main function (after reset) Alternate function Port 0.15 Wakeup from Standby mode input. I X Note: This port is input only. 21 G3 RTCXTI Realtime Clock input and input of 32 kHz oscillator amplifier circuit 22 H4 RTCXTO Output of 32 kHz oscillator amplifier circuit 23 F3 STDBY I/O CT 24 G4 RSTIN I CT X Reset input S X Stabilization for low power voltage regulator. S Stabilization for low power voltage regulator. Requires external capacitors of at least 1F between V18BKP and VSS18BKP. See Figure 5. X Note: If the low power voltage regulator is bypassed, this pin can be connected to an external 1.8V supply. 25 H5 VSSBKP 26 F4 V18BKP 4mA Input: Hardware Standby mode entry input active low. Caution: External pull-up to V33 required to select normal mode. X Output: Standby mode active low output following Software Standby mode entry. Note: In Standby mode all pins are in high impedance except those marked Active in Stdby. X 27 G5 V18 S Stabilization for main voltage regulator. Requires external capacitors of at least 10F + 33nF between V18 and VSS18. See Figure 5. 28 H6 VSS18 S Stabilization for main voltage regulator. 29 E4 VDDA S Supply voltage for A/D Converter 30 G6 VSSA S Ground voltage for A/D Converter 31 F5 P1.0/T3.OCM PB/AIN.0 I/O pu CT 4mA X X Port 1.0 Timer 3: Output ADC: Analog input 0 Compare B P1.1/T3.ICAP 32 H7 A/T3.EXTCLK I/O pu /AIN.1 CT 4mA X X Port 1.1 Timer 3: Input Capture A or External Clock input 33 H8 P1.2/T3.OCM PA/AIN.2 I/O pu CT 4mA X X Port 1.2 Timer 3: Output ADC: Analog input 2 Compare A 34 G8 P1.3/T3.ICAP B/AIN.3 I/O pu CT 4mA X X Port 1.3 Timer 3: Input Capture B ADC: Analog input 3 35 F8 P1.4/T1.ICAP I/O pu A/T1.EXTCLK CT 4mA X X Port 1.4 Timer 1: Input Capture A Timer 1: External Clock input ADC: Analog input 1 25/78 System architecture Input CT 4mA X X Port 1.5 Timer 1: Input Capture B 37 F7 P1.6/T1.OCM PB I/O pu CT 4mA X X Port 1.6 Timer 1: Output Compare B interrupt I/O pu Pin name Type P1.5/T1.ICAP B BGA64 36 G7 LQFP64 PP Main function (after reset) OD Output Capability Input level Pin n Active in Stdby STR711/STR712/STR715 pin description Reset state1) Table 7. STR71xF Alternate function 38 E8 V33IO-PLL S Supply voltage for digital I/O circuitry and for PLL reference2) 39 F6 VSSIO-PLL S Ground voltage for digital I/O circuitry and for PLL reference2) 40 E7 P1.7/T1.OCM PA Timer 1: Output Compare A I/O pu CT 4mA X X Port 1.7 I/O pd CT 4mA X X Port 1.8 42 E6 P1.11/CANRX I/O pu CT X 4mA X X Port 1.11 CAN: receive data input Note: On STR710 and STR712 only 43 D7 P1.12/CANTX I/O pu CT 4mA X X Port 1.12 CAN: Transmit data output Note: On STR710 and STR712 only 41 D8 P1.8 42 E6 USBDP I/O CT USB bidirectional data (data +). Reset state = HiZ Note: On STR710 and STR711 only This pin requires an external pull-up to V33 to maintain a high level. 43 D7 USBDN I/O CT USB bidirectional data (data -). Reset state = HiZ Note: On STR710 and STR711 only. 44 C8 VSS 45 E5 P1.9 Ground voltage for digital I/O circuitry2) S I/O pd CT 4mA X X Port 1.9 46 C7 P1.10/USBCL K I/O pd C/ T 4mA X X Port 1.10 47 D6 P1.13/HCLK/I 0.SCL I/O pd CT X 4mA X X HDLC: Port 1.13 reference clock I2C clock input 48 B8 P1.14/HRXD/I I/O pu 0.SDA CT X 4mA X X Port 1.14 CT 4mA X X Port 1.15 HDLC: Transmit data output 49 A8 P1.15/HTXD I/O pu USB: 48 MHZ clock input HDLC: Receive I2C serial data data input 50 A7 VSS S Ground voltage for digital I/O circuitry2) 51 A6 V33 S Supply voltage for digital I/O circuitry2) 26/78 STR71xF System architecture PP OD Output Capability interrupt Input Input level Pin name Type BGA64 LQFP64 Pin n Active in Stdby STR711/STR712/STR715 pin description Reset state1) Table 7. Main function (after reset) Alternate function SPI0 Master in/Slave out data 52 B7 P0.0/S0.MISO I/O pu /U3.TX CT 4mA X X Port 0.0 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Master out/Slave in data 53 B6 P0.1/S0.MOSI I/O pu /U3.RX CT X 4mA X X Port 0.1 P0.2/S0.SCLK I/O pu /I1.SCL CT X 4mA X X Port 0.2 CT 4mA 56 B5 P0.4/S1.MISO I/O pu CT 4mA X X I2C1: Serial clock Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. SPI0: Slave Select input active low. P0.3/S0.SS/I1 I/O pu 55 C6 .SDA UART3: Receive Data input Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Serial Clock 54 A5 UART3 Transmit data output I2C1: Serial Data Port 0.3 Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. X X Port 0.4 SPI1: Master in/Slave out data 57 A4 VSS18 S Stabilization for main voltage regulator. 58 C5 V18 S Stabilization for main voltage regulator. Requires external capacitors of at least 10F + 33nF between V18 and VSS18. See Figure 5. 59 B4 VSS S Ground voltage for digital I/Os 60 A3 P0.5/S1.MOSI I/O pu CT 4mA X X Port 0.5 SPI1: Master out/Slave In data 61 D5 P0.6/S1.SCLK I/O pu CT X 4mA X X Port 0.6 SPI1: Serial Clock I/O pu CT 4mA X X Port 0.7 SPI1: Slave Select input active low 62 B3 P0.7/S1.SS 27/78 System architecture PP OD interrupt Output Capability Input Input level Pin name Type BGA64 LQFP64 Pin n Active in Stdby STR711/STR712/STR715 pin description Reset state1) Table 7. STR71xF Main function (after reset) Port 0.8 63 C4 P0.8/U0.RX/U I/O pd 0.TX CT X 4mA T 64 A2 P0.9/U0.TX/B OOT.0 CT 4mA X I/O pd Alternate function UART0: Receive Data input UART0: Transmit data output. Note: This pin may be used for single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X Port 0.9 Select Boot Configuration input UART0: Transmit data output 1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 8 on page 29. The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. V33IO-PLL and V33 are internally connected. VSSIO-PLL and VSS are internally connected. 3.5 External connections Figure 5. Recommended external connection of V18 and V18BKP pins 33 nF 33 nF 129 128 58 57 V18 LQFP144 V18BKP V18 28/78 V18 LQFP64 V18BKP V18 54 55 58 59 25 26 27 28 1F 10 F 1F 10 F STR71xF System architecture 3.6 I/O port configuration Table 8. Port bit configuration table PxD Configuration Mode Input buffer PxC2 PxC1 PxC0 register register register Read access Write access TTL floating I/O pin don't care 0 0 1 CMOS floating I/O pin don't care 0 1 0 CMOS PullDown I/O pin 0 0 1 1 CMOS Pull-Up I/O pin 1 0 1 1 Analog input AIN 0 don't care 0 0 0 Output Open-Drain N.A. I/O pin 0 or 1 1 0 0 Output Push-Pull N.A. last value written 0 or 1 1 0 1 Alternate Function Open-Drain CMOS floating I/O pin don't care 1 1 0 Alternate Function Push-Pull I/O pin don't care 1 1 1 TTL Input Floating CMOS Input Floating INPUT register CMOS Input Pull-Down (IPUPD) CMOS Input Pull-Up (IPUPD) OUTPUT CMOS floating Legend: AIN: Analog Input CMOS: CMOS Input levels IPUPD: Input Pull Up /Pull Down TTL: TTL Input levels N.A.: not applicable. In Output mode, a read access to the port gets the output latch value. 29/78 System architecture 3.7 STR71xF Memory mapping Figure 6. Memory map APB Memory Space 0xFFFF FFFF Addressable Memory Space 4 Gbytes 0xFFFF FFFF EIC 0xFFFF F800 0xE000 E000 4K 0xFFFF F800 EIC 4K WDG 4K RTC 4K TIMER 3 4K TIMER 2 4K TIMER 1 4K TIMER 0 4K CLKOUT 4K ADC 4K reserved 4K IOPORT 2 4K IOPORT 1 4K IOPORT 0 4K reserved 4K XTI 4K APB BRIDGE 2 REGS 4K 0xE000 D000 0xE000 C000 7 0xE000 B000 0xE000 0000 64K APB2 0xE000 A000 0xE000 9000 0xE000 8000 6 0xE000 7000 0xC000 0000 64K APB1 0xE000 6000 FLASH Memory Space 272 Kbytes + regs 0xE000 5000 0x4010 DFBF FLASH Registers 5 36b 0xE000 4000 0x4010 0000 0xE000 3000 0xA000 0000 reserved 1K PRCCU 0xE000 2000 0x400C 4000 0xE000 1000 B1F1 8K 0xE000 0000 4 0x400C 2000 B1F0 0x8000 0000 Reserved 4K 0xC001 0000 reserved 0xC000 F000 0x4004 0000 3 0xC000 E000 EXTMEM See Figure 8 reserved 8K 0x400C 0000 0xC000 D000 64MB B0F7 0x6000 0000 64K 0xC000 C000 0xC000 B000 reserved 4K HDLC + RAM 4K reserved 4K reserved 4K BSPI 1 4K BSPI 0 4K CAN 4K USB + RAM 4K UART 3 4K UART 2 4K UART 1 4K UART 0 4K reserved 4K I2C 1 4K 0x4003 0000 0xC000 A000 2 B0F6 0x4000 0000 64K 256K+16K+36b FLASH 0xC000 8000 0x4002 0000 0xC000 7000 0xC000 6000 1 B0F5 0x2000 0000 0xC000 9000 64K 64K RAM 0xC000 5000 0xC000 4000 0x4001 0000 0xC000 3000 0 0x0000 0000 FLASH/RAM/EMI (*) FLASH aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes) Reserved 30/78 0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000 B0F4 32K B0F3 B0F2 B0F1 B0F0 8K 8K 8K 8K 0xC000 2000 2 0xC000 1000 0xC000 0000 I C0 4K APB BRIDGE 1 REGS 4K STR71xF System architecture Figure 7. Mapping of Flash memory versions FLASH Memory Space 64 Kbytes + 16K RWW + regs 0x4010 DFBF FLASH Memory Space 128 Kbytes + 16K RWW + regs 0x4010 DFBF FLASH Registers 36b 0x4010 0000 B1F1 8K B1F1 8K 0x400C 0000 8K 8K 0x4003 0000 reserved 64K 0x4002 0000 reserved 64K reserved 64K 0x4001 0000 64K 32K B0F3 B0F2 B0F1 B0F0 8K 8K 8K 8K B0F5 0x4000 0x4000 0x4000 0x4000 0x4000 STR715FR0xx STR711FR0xx STR712FR0xx 8000 6000 4000 2000 0000 64K B0F6 64K B0F5 64K 0x4002 0000 64K 0x4001 0000 B0F4 B0F7 0x4003 0000 0x4002 0000 reserved 8K 0x4004 0000 0x4003 0000 reserved B1F0 reserved 64K 8K 0x400C 0000 0x4004 0000 reserved B1F1 0x400C 2000 B1F0 reserved Table 9. reserved 0x400C 0000 0x4004 0000 36b 0x400C 4000 0x400C 2000 B1F0 FLASH Registers 0x4010 0000 0x400C 4000 0x400C 2000 8000 6000 4000 2000 0000 36b reserved 0x400C 4000 0x4000 0x4000 0x4000 0x4000 0x4000 0x4010 DFBF FLASH Registers 0x4010 0000 reserved FLASH Memory Space 256 Kbytes + 16K RWW + regs 0x4001 0000 B0F4 32K B0F3 B0F2 B0F1 B0F0 8K 8K 8K 8K STR710FZ1xx STR711FR1xx STR712FR1xx 0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000 B0F4 32K B0F3 B0F2 B0F1 B0F0 8K 8K 8K 8K STR710F72xx STR711FR2xx STR712FR2xx RAM memory mapping Part number RAM size Start address End address STR715FR0xx STR711FR0xx STR712FR0xx 16 Kbytes 0x2000 0000 0x2000 3FFF STR710FZ1xx STR711FR1xx STR712FR1xx 32 Kbytes 0x2000 0000 0x2000 7FFF STR710FR2xx STR710Rxx STR711FR2xx STR712FR2xx 64 Kbytes 0x2000 0000 0x2000 FFFF 31/78 System architecture Figure 8. STR71xF External memory map Addressable Memory Space 4 Gbytes 0xFFFF FFFF EIC 0xFFFF F800 7 0xE000 0000 APB2 6 0xC000 0000 APB1 External Memory Space 64 MBytes 5 0xA000 0000 0x6C00 0x6C00 0x6C00 0x6C00 PRCCU 000C 0008 0004 0000 BCON3 BCON2 BCON1 BCON0 register register register register 4 0x66FF FFFF 0x8000 0000 Reserved Bank3 16M Bank2 16M Bank1 16M Bank0 16M CSn.3 0x6600 0000 3 0x64FF FFFF 0x6000 0000 EXTMEM CSn.2 0x6400 0000 2 0x4000 0000 0x62FF FFFF CSn.1 FLASH 0x6200 0000 0x60FF FFFF 1 CSn.0 0x2000 0000 RAM 0x6000 0000 0 0x0000 0000 FLASH/RAM/EMI Reserved Drawing not in scale 32/78 STR71xF Electrical parameters 4 Electrical parameters 4.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 4.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 4.1.2 Typical values Unless otherwise specified, typical data are based on TA=25C, V33=3.3V (for the 3.0VV333.6V voltage range) and V18=1.8V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 4.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 4.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. 4.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 9. Pin loading conditions Figure 10. Pin input voltage STR7 PIN STR7 PIN L=50pF VIN 33/78 Electrical parameters 4.2 STR71xF Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 10. Voltage characteristics Symbol Ratings Min Max V33- VSS External 3.3V Supply voltage (including AVDD and V33IO- -0.3 4.0 Digital 1.8V Supply voltage on V18BKP backup supply 2) -0.3 2.0 Input voltage on true open drain pin (P0.10) 1) VSS-0.3 +5.5 Input voltage on any other pin 1) VSS-0.3 V33+0.3 PLL) V18BKP - VSSBKP VIN 34/78 2) |V33x| Variations between different 3.3V power pins 50 50 |V18x| Variations between different 1.8V power pins 5) 25 25 Variations between all the different ground pins 50 50 |VSSX - VSS| Unit VESD(HBM) Electro-static discharge voltage (Human Body Model) VESD(MM) Electro-static discharge voltage (Machine Model) see : Absolute maximum ratings (electrical sensitivity) on page 48 V mV STR71xF Electrical parameters Table 11. Current characteristics Symbol Ratings Max. IV33 Total current into V33/V33IO-PLL power lines (source) 2) 150 IVSS Total current out of VSS/VSSIO-PLL ground lines (sink) 2) 150 Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin - 25 Injected current on RSTIN pin 5 Injected current on CK pin 5 Injected current on any other pin 4) 5 Total injected current (sum of all I/O and control pins) 4) 25 IIO IINJ(PIN) 1) 3) IINJ(PIN) 1) Unit mA Notes: 1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>V33 while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected. Data based on TA = 25 C. 2. All 3.3V power (V33, AVDD, V33IO-PLL) and ground (VSS, AVSS, VSSIO-PLL) pins must always be connected to the external 3.3V supply. 3. Negative injection disturbs the analog performance of the device. See note in Section 4.3.11: ADC characteristics on page 66. 4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device. 5. Only when using external 1.8V power supply. All the power (V18, V18BKP) and ground (VSS18, VSSBKP) pins must always be connected to the external 1.8V supply. Table 12. Thermal characteristics Symbol Ratings Value Unit TSTG Storage temperature range -65 to +150 C TJ Maximum junction temperature (see Section 5.2: Thermal characteristics on page 72) 35/78 Electrical parameters 4.3 STR71xF Operating conditions Subject to general operating conditions for V33, and TA. Table 13. Symbol fMCLK fPCLK V33 V18BKP TA General operating conditions Parameter Conditions Min Max Accessing SRAM or external memory with 0 wait states 0 66 Accessing FLASH in burst mode 0 50 Executing from FLASH with RWW 0 45 1) Accessing FLASH with 0 wait states 0 33 0 33 MHz Standard Operating Voltage (includes V33I0_PLL) 3.0 3.6 V Backup Operating Voltage 1.4 1.8 V Ambient temperature range 6 Partnumber Suffix -40 85 C Typ Max Unit Internal CPU Clock frequency Unit MHz Internal APB Clock frequency 1. Data guaranteed by characterization, not tested in production Table 14. Symbol tV33 36/78 Operating conditions at power-up / power-down Parameter V33 rise time rate Conditions Subject to general operating conditions for TA. Min s/V 20 20 ms/V STR71xF 4.3.1 Electrical parameters Supply current characteristics The current consumption is measured as described in Figure 9 on page 33 and Figure 10 on page 33. Total current consumption The MCU is placed under the following conditions: All I/O pins in input mode with a static value at V33 or VSS (no load) All peripherals are disabled except if explicitly mentioned. Embedded Regulators are used to provide 1.8V (except if explicitly mentioned) Subject to general operating conditions for V33, and TA. Table 15. Symbol Total current consumption Parameter Supply current in RUN mode IDD4) Conditions Typ 1) Max 2) fMCLK=66 MHz, RAM execution 73.6 fMCLK=32 MHz, Flash non-burst execution 49.3 Unit 100 mA Supply current in STOP mode TA=25C 10 503) A Supply current in STANDBY mode OSC32K bypassed 12 30 A Notes: 1. Typical data are based on TA=25C, V33=3.3V. 2. Data based on characterization results, tested in production at V33, fMCLK max. and TA max. 3. Based on device characterisation, device power consumption in STOP mode at TA 25C is predicted to be 30A or less in 99.730020% of parts. 4. The conditions for these consumption measurements are described in application note AN2100. 37/78 Electrical parameters Table 16. Symbol STR71xF Typical power consumption data Parameter Conditions Typical current on V33 MCLK = 16 MHz, PCLK1 = PCLK2 = 16 MHz 23 MCLK = 32 MHz, PCLK1 = PCLK2 = 32 MHz 40 MCLK = 48 MHz, PCLK1 = PCLK2 = 24 MHz 50 MCLK = 64 MHz, PCLK1 = PCLK2 = 32 MHz 63 MCLK = 16 MHz 16 MCLK = 32 MHz 26 MCLK = 48 MHz 39 MCLK = 64 MHz 48 Unit All periphs ON RUN mode current from RAM All periphs OFF IDDRUN mA MCLK = 16 MHz, PCLK1 = PCLK2 = 16 MHz 27 MCLK = 32 MHz, PCLK1 = PCLK2 = 32 MHz 47 MCLK = 48 MHz, PCLK1 = PCLK2 = 24 MHz 62 MCLK = 16 MHz 21 All periphs OFF MCLK = 32 MHz 36 MCLK = 48 MHz 53 All periphs ON RUN mode current from FLASH IDDSLOW SLOW mode current MCLK = CK_AF (32 kHz), MVR off 1.7 IDDWAIT WAIT mode current (all periphs ON) PCLK1 = PCLK2 = 1 MHz 13 IDDLPWAIT LPWAIT mode current CK_AF (32 kHz), Main VReg off, FLASH in power-down 37 Main VReg off, FLASH in power down, RTC on 18 Main VReg off, FLASH in power down, RTC off 10 LP VReg on, LVD on, RTC on 10 LP VReg off (ext 1.8V on V18BKP), LVD on, RTC on 9 LP VReg off (ext1.8V on V18BKP), LVD off, RTC on 5 LP VReg off (ext 1.8V on V18BKP), LVD off, RTC off 1 IDDSTOP IDDSB 38/78 STOP mode current STANDBY mode current A STR71xF Electrical parameters Figure 11. STOP IDD vs. V33 Figure 12. STANDBY IDD vs. V33 25 100 90 TA=-45 to +25C 80 20 IDDSTDBY (A) TA=+90C 70 IDDSTOP (A) TA=-45C TA=0C TA=+25C TA=+90C 60 50 40 15 10 30 5 20 10 0 0 3 3.1 3.2 3.3 3.4 3.5 3.6 V33 (V) 3 3.1 3.2 3.3 3.4 3.5 3.6 V33 (V) Figure 13. WFI IDD vs. V33 100 IDDWFI (A) 90 80 70 TA=-40 to +90C 60 50 3 3.1 3.2 3.3 3.4 3.5 3.6 V33 (V) 39/78 Electrical parameters STR71xF On-chip peripherals Table 17. Symbol Peripheral current consumption Parameter IDD(PLL1) PLL1 supply current IDD(PLL2) PLL2 supply current IDD(TIM) Conditions TA= 25C TIM Timer supply current 1) Typ 3.42 5.81 0.88 IDD(BSPI) BSPI supply current 2) 1.1 IDD(UART) UART supply current 2) 1.05 IDD(I2C) I2C supply current 2) IDD(ADC) ADC supply current when converting 5) IDD(HDLC) HDLC supply current 2) Unit mA TA= 25C, fPCLK1= fPCLK2=33 MHz 0.45 1.89 1.82 IDD(USB) USB supply current 2) 2.08 IDD(CAN) CAN supply current 2) 1.11 Notes: 1. Data based on a differential IDD measurement between reset configuration and timer counter running at 16MHz. No IC/OC programmed (no I/O pads toggling). 2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. 3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. 40/78 STR71xF 4.3.2 Electrical parameters Clock and timing characteristics External clock sources Subject to general operating conditions for V33, and TA. Table 18. CK external clock characteristics Symbol Parameter Conditions Min Typ Max Unit MHz fCK External clock source frequency 0 16.5 VCKH CK input pin high level voltage 0.7xV33 V33 VCKL CK input pin low level voltage VSS tw(CK) tw(CK) CK high or low time 1) 25 V ns tr(CK) tf(CK) CK rise or fall time 1) 20 CK input capacitance1) CIN(CK) DuCy(XT1) IL 0.3xV33 5 Duty cycle 40 VSSVINV33 CK Input leakage current pF 60 % 1 A Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production. Figure 14. CK external clock source 90% VCKH 10% VCKL tr(CK) TCK tf(CK) tw(CKH) tw(CKL) fCLK EXTERNAL CLOCK SOURCE CK IL STR710 41/78 Electrical parameters Table 19. Symbol fRTCXT1 STR71xF RTCXT1 external clock characteristics Parameter Conditions External clock source frequency Min Typ Max Unit 0 500 kHz VRTCXT1H RTCXT1 input pin high level voltage 0.7xV33 V33 VRTCXT1L RTCXT1 input pin low level voltage VSS 0.3xV33 tw(RTCXT1) tw(RTCXT1) RTCXT1 high or low time 1) 100 V tr(RTCXT1) tf(RTCXT1) ns RTCXT1 rise or fall CIN(RTCXT1) RTCXT1 input capacitance1) DuCy(RTCXT1) Duty cycle IL time 1) RTCXT1 Input leakage current 5 5 30 VSSVINV33 Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production. 42/78 pF 70 % 1 A STR71xF Electrical parameters OSC32K crystal / ceramic resonator oscillator The STR7 RTC clock can be supplied with a 32 kHz Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 20. 32K oscillator characteristics (fOSC32K= 32.768 kHz) Symbol Parameter Conditions Typ Unit 2.7 M RF Feedback resistor CL1 CL2 Recommended load capacitance versus equivalent serial resistance of the crystal (RS)1) RS=40K 12.5 pF i2 RTCXT2 driving current V33=3.3 V VIN=VSS 3.2 A gm Oscillator Transconductance 8 A/V 5 s tSU(OSC32KHZ)2) startup time V33 is stabilized Notes: 1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 2. tSU(OSC32KHZ) is the start-up time measured from the moment it is enabled (by software) to a stabilized 32 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 15. Typical application with a 32 kHz crystal WHEN RESONATOR WITH INTEGRATED CAPACITORS i2 CL1 CL2 fOSC32K RTCXT1 32 kHz RESONATOR FEEDBACK LOOP RF RTCXT2 STR710 43/78 Electrical parameters STR71xF DEVICE RTCXTO RTCXTI RTCXTI DEVICE RTCXTO Figure 16. RTC crystal oscillator and resonator RS CL CL PLL electrical characteristics V33 = 3.0 to 3.6V, V33IOPLL = 3.0 to 3.6V, TA = -40 / 85 C unless otherwise specified. Table 21. PLL1 characteristics Symbol Parameter Value Test conditions Unit Min Typ fPLLCLK1 PLL multiplier output clock FREF_RANGE = 0 FREF_RANGE = 1 PLL input clock fPLL1 MX[1:0]='00' or `01' FREF_RANGE = 1 MX[1:0]='10' or `11' PLL input clock duty cycle FREF_RANGE = 0 MX[1:0]='01' or `11' FREF_RANGE = 0 MX[1:0]='00' or `10' fFREE1 Max 165 MHz 1.5 3.0 MHz 3.0 8.25 MHz 3.0 6 MHz 25 75 % 125 kHz 250 kHz 250 kHz 500 kHz PLL free running frequency FREF_RANGE = 1 MX[1:0]='01' or `11' FREF_RANGE = 1 MX[1:0]='00' or `10' FREF_RANGE = 0 Stable Input Clock tLOCK1 PLL lock time 300 s 600 s 2 ns Stable V33IOPLL, V18 FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 tJITTER1 PLL jitter (peak to peak) 44/78 tPLL = 4 MHz, MX[1:0]='11' Global Output division = 32 (Output Clock = 2 MHz) 0.7 STR71xF Electrical parameters Table 22. PLL2 characteristics Value Symbol Parameter Test conditions Unit Min fPLLCLK2 fPLL2 tLOCK2 tJITTER2 Table 23. Symbol Typ PLL multiplier output clock Max 140 MHz FREF_RANGE = 0 1.5 3.0 MHz FREF_RANGE = 1 3.0 5 MHz FREF_RANGE = 0 Stable Input Clock Stable V33IOPLL, V18 300 s FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 600 s 2 ns PLL input clock PLL lock time PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]='11' Global Output division = 32 (Output Clock = 2 MHz) 0.7 Low-power mode wakeup timing Parameter Typ Unit tWULPWFI Wakeup from LPWFI mode 26(1) s tWUSTOP Wakeup from STOP mode 2048 CLK Cycles tWUSTBY Wakeup from STANDBY mode (2) 2048 CLK Cycles + 8 CLK2 Cycles(3) Cycles 1. Clock selected is CK2_16, Main VReg OFF and Flash in power-down 2. The CLK clock is derived from the external oscillator. 3. Refer to Figure 7. Reset General Timing in the STR71xF Reference Manual (UM0084) 45/78 Electrical parameters 4.3.3 STR71xF Memory characteristics Flash memory V33 = 3.0 to 3.6V, TA = -40 to 85 C unless otherwise specified. Table 24. Flash memory characteristics Value Symbol Parameter Test conditions Unit Min. Max1) tPW Word Program 40 s tPDW Double Word Program 60 s tPB0 Bank 0 Program (256K) Double Word Program 1.6 2.1 s tPB1 Bank 1 Program (16K) Double Word Program 130 170 ms tES Sector Erase (64K) Not preprogrammed Preprogrammed 2.3 1.9 4.0 3.3 s tES Sector Erase (8K) Not preprogrammed Preprogrammed 0.7 1.1 0.6 1.0 tES Bank 0 Erase (256K) Not preprogrammed Preprogrammed 8.0 13.7 6.6 11.2 tES Bank 1 Erase (16K) Not preprogrammed Preprogrammed 0.9 1.5 0.8 1.3 s s s tRPD2) Recovery when disabled 20 s tPSL2) Program Suspend Latency 10 s tESL2) Erase Suspend Latency 300 s NEND_B0 Endurance (Bank 0 sectors) 10 kcycles NEND_B1 Endurance (Bank 1 sectors) 100 kcycles tRET Data Retention (Bank 0 and Bank 1) TA=85 20 Years tESR Erase Suspend Rate Min time from Erase Resume to next Erase Suspend 20 ms Notes: 1. TA=45C after 0 cycles. Guaranteed by characterization, not tested in production. 2. Guaranteed by design, not tested in production 46/78 Typ STR71xF 4.3.4 Electrical parameters EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electro magnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). In the case of an ARM7 CPU, in order to write robust code that can withstand all kinds of stress, such as very strong electromagnetic disturbance, it is mandatory that the Data Abort, Prefetch Abort and Undefined Instruction exceptions are managed by the application software. This will prevent the code going into an undefined state or performing any unexpected operation. 47/78 Electrical parameters Table 25. STR71xF EMS data Symbol Parameter Level/ Class Conditions VFESD Voltage limits to be applied on any I/O pin V33=3.3 V, TA=+25C, fMCLK=32 MHz to induce a functional disturbance conforms to IEC 1000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100pF on VDD and VSS pins to induce a functional disturbance 4A V33=3.3 V, TA=+25C, fMCLK=32 MHz conforms to IEC 1000-4-4 Electro magnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Table 26. Symbol SEMI EMI data Parameter Peak level Conditions Monitored frequency band 0.1 MHz to 30 MHz V33=3.3 V, TA=+25C, 30 MHz to 130 MHz LQFP64 package conforming to SAE J 130 MHz to 1 GHz 1752/3 SAE EMI Level Max vs. [fOSC4M/fHCLK] Unit 16/ 48 MHz 16/8 MHz 17 19 17 16 11 11 4 3 dBV - Notes: 1. Not tested in production. 2. BGA and LQFP devices have similar EMI characteristics. Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electro-static discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard. 48/78 STR71xF Electrical parameters Table 27. Symbol ESD absolute maximum ratings Ratings Conditions VESD(HBM) Electro-static discharge voltage (Human Body Model) VESD(MM) Electro-static discharge voltage (Machine Model) VESD(CDM) Electro-static discharge voltage (Charge Device Model) Maximum value 1) Unit 2000 200 TA=+25C V 750 on corner pins, 500 on others Notes: 1. Data based on characterization results, not tested in production. Static and dynamic latch-up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. Electrical sensitivities Table 28. Symbol LU DLU Static and dynamic latch-up Parameter Conditions Class (1) Static latch-up class TA=+25C TA=+85C TA=+105C A A A Dynamic latch-up class VDD=3.3 V, fOSC4M=4 MHz, fMCLK=32 MHz, TA=+25C A 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 49/78 Electrical parameters 4.3.5 STR71xF I/O port pin characteristics General characteristics Subject to general operating conditions for V33 and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 29. I/O static characteristics Symbol Parameter VIL Input low level voltage 1) VIH Input high level voltage 1) Vhys Schmitt trigger voltage hysteresis VIL Input low level voltage 1) VIH Input high level voltage 1) Vhys Schmitt trigger voltage hysteresis VIL Input low level voltage 1) Conditions Min Typ Max Unit 0.3V33 V CMOS ports 0.7V33 0.8 2) 0.9 V 0.8 V P0.15 WAKEUP 2 1.35 0.4 2) V 0.8 TTL ports VIH IINJ(PIN) Input high level voltage 1) V 2.0 Injected Current on any I/O pin 4 mA IINJ(PIN) Total injected current (sum of all I/O and control pins) 3) 25 Ilkg Input leakage current 4) VSSVINV33 RPU Weak pull-up equivalent resistor5) VIN=VSS 110 RPD Weak pull-down equivalent resistor5) VIN=V33 110 CIO I/O pin capacitance 1 A 150 700 k 150 700 k 5 pF Notes: 1. Data based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 3. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>V33 while a negative injection is induced by VIN<VSS. Refer to Section 4.2 on page 34 for more details. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. The RPU pull-up and RPD pull-down equivalent resistor are based on a resistive transistor (corresponding IPU and IPD current characteristics described in Figure 18 to Figure 19). 50/78 STR71xF Electrical parameters Figure 17. RPU vs. V33 with VIN=VSS Figure 18. IPU vs. V33 with VIN=VSS 0 0.0 TA=-45C TA=0C TA=+25C TA=+90C -50.0 TA=-45C TA=0C TA=+25C TA=+90C -5 IPU (A) RPU (kohm) -10 -100.0 -150.0 -15 -20 -200.0 -25 -250.0 -30 3 3.1 3.2 3.3 3.4 3.5 3 3.6 3.1 3.2 V33 (V) Figure 19. RPD vs. V33 with VIN=V33 300.0 3.5 3.6 30 TA=-45C TA=0C TA=+25C TA=+90C 25 200.0 20 IPD (A) RPD (kohm) 3.4 Figure 20. IPD vs. V33 with VIN=V33 TA=-45C TA=0C TA=+25C TA=+90C 250.0 3.3 V33 (V) 150.0 100.0 15 10 50.0 5 0.0 3 3.1 3.2 3.3 V33 (V) 3.4 3.5 3.6 0 3 3.1 3.2 3.3 3.4 3.5 3.6 V33 (V) 51/78 Electrical parameters STR71xF Output driving current Subject to general operating conditions for V33 and TA unless otherwise specified. Table 30. Output driving current High Current Standard I/O Symbol Type Parameter Conditions VOL 1) Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO=+4mA VOH 2) Output high level voltage for an I/O pin when 4 pins are sourced at same time IIO=-4mA Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO=+8mA Output high level voltage for an I/O pin when 4 pins are sourced at same time IIO=-8mA VOL 1) VOH 2) Min Max Unit 0.4 V33-0.8 V 0.4 V33-0.8 Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 11 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Table 11 and the sum of IIO (I/O ports and control pins) must not exceed IV33. 52/78 STR71xF Electrical parameters Figure 21. Typical VOL and VOH at V33=3.3V (high current ports) 3.09 0.16 TA=-45C TA=0C TA=+25C TA=+90C 3.08 3.07 0.14 0.12 0.10 VOL(V) VOH(V) 3.06 3.05 0.08 3.04 0.06 3.03 0.04 3.02 0.02 3.01 TA=-45C TA=0C TA=+25C TA=+90C 0.00 -4 -8 Ioh (mA) -4 -8 Iol (mA) 53/78 Electrical parameters STR71xF Figure 22. Typical VOL vs. V33 0.16 0.18 0.14 0.16 0.14 VOL(V) Iio=8mA VOL (V) Iio=4mA 0.12 0.10 0.08 TA=-45C TA=0C TA=+25C TA=+90C 0.06 0.12 0.10 TA=-45C TA=0C TA=+25C TA=+90C 0.08 0.06 0.04 0.04 0.02 0.02 0.00 0.00 3 3.1 3.2 3.3 3.4 3.5 3 3.6 3.1 3.2 3.3 3.4 3.5 3.6 V33 (V) V33 (V) 3.60 3.60 3.40 3.40 3.20 3.20 VOH(V) Iio=8mA VOH (V) Iio=4mA Figure 23. Typical VOH vs. V33 3.00 2.80 TA=-45C TA=0C TA=+25C TA=+90C 2.60 2.40 2.80 2.60 TA=-45C TA=0C TA=+25C TA=+90C 2.40 2.20 2.20 2.00 2.00 3 3.1 3.2 3.3 V33 (V) 54/78 3.00 3.4 3.5 3.6 3 3.1 3.2 3.3 V33 (V) 3.4 3.5 3.6 STR71xF Electrical parameters RSTIN pin The RSTIN pin input driver is CMOS. A permanent pull-up is present which is the same as as RPU (seeTable 29 on page 50) Subject to general operating conditions for V33 and TA unless otherwise specified. Table 31. RESET pin characteristics Symbol Parameter Conditions Min Typ 1) VIL(RSTINn) RSTIN Input low level voltage 1) Max Unit 0.8 V VIH(RSTINn) RSTIN Input high level voltage 1) 2 RSTIN Input filtered pulse2) VF(RSTINn) 500 VNF(RSTINn) RSTIN Input not filtered pulse2) 1.2 ns s Notes: 1. Data based on characterization results, not tested in production. 2) Data guaranteed by design, not tested in production. Figure 24. Recommended RSTIN pin protection.1) Recommended V33 V33 V33 0.01F EXTERNAL RESET CIRCUIT 4.7k RSTIN RPU Filter 0.01F INTERNAL RESET STR7X Required Notes: 1. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 18). 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the RSTIN pin can go below the VIL(RSTINn) max. level specified in Table 31. Otherwise the reset will not be taken into account internally. 55/78 Electrical parameters 4.3.6 STR71xF TIM timer characteristics Subject to general operating conditions for V33, fMCLK, and TA unless otherwise specified. Refer to Section 4.3.5: I/O port pin characteristics on page 50 for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). Table 32. TIM characteristics Symbol Parameter tw(ICAP)in Input capture pulse time tres(TIM) Timer resolution time fPCLK2 = 30 MHz Timer external clock frequency fEXT ResTIM Conditions Min Typ Unit 2 tCK_TIM 1 tPCLK2 33.3 ns fCK_TIM(MAX) = fMCLK 0 fCK_TIM/4 MHz fCK_TIM = fMCLK = 60 MHz 0 15 MHz 16 bit 1 65536 tPCLK2 0.033 2184 s 65536x 65536 tPCLK 143.1 s Timer resolution tCOUNTER 16-bit Counter clock period when internal clock is selected fPCLK2 = 30 MHz TMAX_COUNT Maximum Possible Count fPCLK2 = 30 MHz 4.3.7 Max EMI - external memory interface Subject to general operating conditions for VDD, fHCLK, and TA unless otherwise specified. The tables below use a variable which is derived from the EMI_BCONn registers (described in the STR71x Reference Manual) and represents the special characteristics of the programmed memory cycle. Table 33. Symbol tMCLK tC 56/78 EMI general characteristics Parameter CPU clock period Memory cycle time wait states Value 1 / fMCLK tMCLK x (1 + [C_LENGTH]) STR71xF Electrical parameters Table 34. EMI read operation Symbol Parameter Value Test Conditions Unit Min1) Typ Max1) tRCR Read to CSn Removal Time 19 tMCLK 21 ns tRP Read Pulse Time 98 tC 100 ns tRDS Read Data Setup Time 22 ns tRDH Read Data Hold Time 0 ns tRAS Read Address Setup Time MCLK=50 MHz 4 wait states 27 50 pf load on all pins 1.5*tM CLK 33 ns tRAH Read Address Hold Time 0.65 2 ns tRAT Read Address Turnaround Time 1.9 3.25 ns tRRT RDn Turnaround Time 20 21 ns tMCLK See Figure 25, Figure 26, Figure 27 and Figure 28 for related timing diagrams. 1. Data based on characterisation results, not tested in production. Table 35. EMI write operation Symbol Parameter Value Test conditions Unit Min1) Typ Max1) tWCR WEn to CSn Removal Time 20 tMCLK 22.5 ns tWP Write Pulse Time 77.5 tC 80 ns tWDS1 Write Data Setup Time 1 97 tC + tMCLK 100 ns tWDS2 Write Data Setup Time 2 MCLK=50 MHz 77 tC 80 ns tWDH Write Data Hold Time 3 wait states 20 tMCLK 23 ns 27 1.5*tMCLK 33 ns 50 pf load on all pins tWAS Write Address Setup Time tWAH Write Address Hold Time 0.6 3 ns tWAT Write Address Turnaround Time 1.75 4.1 ns tWWT WEn Turnaround Time 20 23 ns tMCLK See Figure 29, Figure 30, Figure 31 and Figure 32 for related timing diagrams. 1. Data based on characterisation results, not tested in production. 57/78 Electrical parameters STR71xF Figure 25. Read cycle timing: 16-bit read on 16-bit memory tRAH A[23:0] Address tRP RDn tRCR CSn.x WEn.x tRDS tRDH tRAS Data Input D[15:0] (Input) Figure 26. Read cycle timing: 32-bit read on 16-bit memory tRAT tRAH A[23:0] tRAH Address Address tRP tRRT tRP RDn tRCR CSn.x WEn.x tRAS tRDS tRDH tRDS Data Input D[15:0] tRDH Data Input (Input) See Table 34 for read timing data. Figure 27. Read cycle timing: 16-bit read on 8-bit memory tRAT tRAH A[23:0] tRAH Address Address tRP tRRT tRP RDn tRCR CSn.x WEn.x tRAS D[7:0] (Input) 58/78 tRDS Data Input tRDH tRDS Data Input tRDH STR71xF Electrical parameters Figure 28. Read cycle timing: 32-bit read on 8-bit memory tRAT A[23:0] tRAH tRAH Address Address tRP tRAT tRAT tRAH tRRT tRAH Address Address tRP tRRT tRRT tRP tRP RDn tRCR CSn.x WEn.x tRAS tRDS tRDH tRDS Data Input D[7:0] tRDH tRDS Data Input tRDH tRDS Data Input tRDH Data Input (Input) See Table 34 for read timing data. Figure 29. Write cycle timing: 16-bit write on 16-bit memory tWAH A[23:0] Address RDn tWCR CSn.x tWAS tWP WEn.x tWDH tWDS1 Data Output D[15:0] (Output) Figure 30. Write cycle timing: 32-bit write on 16-bit memory tWAT tWAH A[23:0] tWAH address address RDn tWCR CSn.x tWP tWWT tWP WEn.x tWAS D[15:0] tWDS1 Data Output tWDH tWDS2 tWDH Data Output (Output) See Table 46 for write timing data. 59/78 Electrical parameters STR71xF Figure 31. Write cycle timing: 16-bit write on 8-bit memory tWAT tWAH A[23:0] tWAH address address RDn tWCR CSn.x tWP tWWT tWP WEn.x tWAS tWDS1 tWDH tWDS2 Data Output D[7:0] tWDH Data Output (Output) Figure 32. Write cycle timing: 32-bit write on 8-bit memory tWAT tWAT tWAH A[23:0] tWAT tWAH address address tWAH tWAH address address RDn tWCR CSn.x tWP tWWT tWP tWWT tWP tWWT tWP WEn.x tWAS D[7:0] tWDS1 tWDH Data Output tWDS2 Data Output tWDH tWDS2 Data Output tWDH tWDS2 tWDH Data Output (Output) See Table 35 for write timing data. 4.3.8 I2C - inter IC control interface Subject to general operating conditions for V33, fPCLK1, and TA unless otherwise specified. The STR7 I2C interface meets the requirements of the Standard I2C communications protocol described in the following table with the restriction mentioned below: Note: Restriction: The I/O pins which SDA and SCL are mapped to are not "True" Open-Drain: when configured as open-drain, the PMOS connected between the I/O pin and V33 is disabled, but it is still present. Also, there is a protection diode between the I/O pin and V33. Consequently, when using this I2C in a multi-master network, it is not possible to power off the STR7X while some another I2C master node remains powered on: otherwise, the STR7X will be powered by the protection diode. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). 60/78 STR71xF Electrical parameters Table 36. Symbol I2C characteristics Parameter Standard mode I2C Min 1) Max 1) Fast mode I2C5) Unit Min 1) Max 1) tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0 3) 0 2) 900 3) tr(SDA) tr(SCL) SDA and SCL rise time 1000 20+0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 20+0.1Cb 300 th(STA) START condition hold time 4.0 0.6 tsu(STA) Repeated START condition setup time 4.7 0.6 tsu(STO) STOP condition setup time 4.0 0.6 s STOP to START condition time (bus free) 4.7 1.3 s tw(STO:STA) Cb Capacitive load for each bus line 400 s ns s 400 pF Notes: 1. Data based on standard I2C protocol requirement, not tested in production. 2. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 3. The maximum hold time th(SDA) is not applicable. 4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 5. fPCLK1, must be at least 8 MHz to achieve max fast I2C speed (400 kHz). 6. The following table gives the values to be written in the I2CCCR register to obtain the required I2C SCL line frequency. 61/78 Electrical parameters STR71xF Figure 33. Typical application with I2C bus and timing diagram VDD 4.7k I 2C VDD 4.7k BUS 100 SDA 100 SCL STR7 REPEATED START START tsu(STA) tw(STO:STA) START SDA tr(SDA) tf(SDA) tsu(SDA) STOP th(SDA) SCL th(STA) Table 37. tw(SCKH) tw(SCKL) tr(SCK) tsu(STO) tf(SCK) SCL Frequency Table (fPCLK1=8 MHz.,V33 = 3.3 V) fSCL I2CCCR Value (kHz) RP=4.7k 400 83 300 85h 200 8Ah 100 24h 50 4Ch 20 C4h Legend: RP = External pull-up resistance fSCL = I2C speed NA = Not achievable Note: For speeds around 200 kHz, achieved speed can have 5% tolerance For other speed ranges, achieved speed can have 2% tolerance The above variations depend on the accuracy of the external components used. 62/78 STR71xF Electrical parameters 4.3.9 BSPI - buffered serial peripheral interface Subject to general operating conditions for VDD, TA and fPCLK1 ,unless otherwise specified. Refer to I/O port pin characteristics on page 50 for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Table 38. BSPI characteristics Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) (1) Min Max Master fPCLK1/254 fPCLK1/6 5.5 Slave 0 fPCLK1/8 3.3 capacitive charge C=50 pF 14 Slave 0 SS hold time Slave 0 Master fPCLK1=33 MHz, presc = 6 73 SCK high and low time tsu(MI) (1) tsu(SI) (1) Data input setup time Master Slave 7 0 th(MI) 1)(2) th(SI) 1)(2) Data input hold time Master Slave 1xtPCLK1 2xtPCLK1 th(MI) (1) th(SI) (1) Data input hold time Master fPCLK1=33 MHz Slave fPCLK1=33 MHz 30 60 Slave 0 1.5xtPCLK1+42 Slave fPCLK1=33 MHz 0 87 Slave 0 42 ta(SO) 1)(3) Data output access time tdis(SO) (1)(4) Data output disable time tv(SO) (1)(2) th(SO) (1) tv(MO) (1)(2) th(MO) (1) 3xtPCLK1+45 fPCLK1=33 MHz 135 Slave (after enable edge) 0 Master (after enable edge) 2xtPCLK1+12 fPCLK1=33 MHz 72 Data output valid time Data output hold time ns Slave (after enable edge) Data output valid time Data output hold time Unit MHz SS setup time (1) tw(SCKH) tw(SCKL) (1) Conditions SPI clock frequency SPI clock rise and fall time tsu(SS) (1) th(SS) Parameter Master (after enable edge) 0 1. Data based on design simulation and/or characterisation results, not tested in production. 2. Depends on fPCLK1. For example, if fPCLK1=8 MHz, then tPCLK1 = 1/fPCLK1 =125 ns and tv(MO) = 255 ns. 3. Min. time is the minimum time to drive the output and the max. time is the maximum time to validate the data. 4. Min time is the minimun time to invalidate the output and the max time is the maximum time to put the data in Hi-Z. 63/78 Electrical parameters STR71xF Figure 34. SPI slave timing diagram with CPHA=01) SS INPUT SCK INPUT tsu(SS) tc(SCK) th(SS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) MISO OUTPUT tv(SO) MSB OUT tsu(SI) th(SO) BIT6 OUT LSB OUT th(SI) MSB IN MOSI INPUT tdis(SO) tr(SCK) tf(SCK) LSB IN BIT1 IN Figure 35. SPI slave timing diagram with CPHA=11) SS INPUT SCK INPUT tsu(SS) tc(SCK) th(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 ta(SO) tw(SCKH) tw(SCKL) MISO OUTPUT tv(SO) th(SO) MSB OUT tsu(SI) BIT6 OUT LSB OUT th(SI) MSB IN MOSI INPUT tdis(SO) tr(SCK) tf(SCK) BIT1 IN LSB IN Figure 36. SPI master timing diagram1) SS INPUT tc(SCK) SCK OUTPUT CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 CPHA = 1 CPOL = 0 CPHA = 1 CPOL = 1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT tr(SCK) tf(SCK) th(MI) MSB IN BIT6 IN tv(MO) MOSI OUTPUT MSB OUT BIT6 OUT 1. Measurement points are done at CMOS levels: 0.3xV33 and 0.7xV33 64/78 LSB IN th(MO) LSB OUT STR71xF 4.3.10 Electrical parameters USB characteristics The USB interface is USB-IF certified (Full Speed). Table 39. USB startup time Symbol Parameter tSTARTUP USB transceiver startup time Table 40. Conditions Max Unit 1 s USB DC characteristics Symbol Parameter Min.(1)(2) Max.(1)(2) Unit Conditions Input Levels VDI Differential Input Sensitivity I(DP, DM) 0.2 VCM Differential Common Mode Range Includes VDI range 0.8 2.5 VSE Single Ended Receiver Threshold 1.3 2.0 V Output Levels VOL VOH Static Output Level Low RL of 1.5 k to 3.6V(3) Static Output Level High RL of 15 k to 0.3 V VSS(3) 2.8 3.6 1. All the voltages are measured from the local ground potential. 2. It is important to be aware that the DP/DM pins are not 5 V tolerant. As a consequence, in case of a a shortcut with Vbus (typ: 5.0V), the protection diodes of the DP/DM pins will be direct biased . This will not damage the device if not more than 50 mA is sunk for longer than 24 hours but the reliability may be affected. 3. RL is the load connected on the USB drivers Figure 37. USB: data signal rise and fall time Differential Data Lines Crossover points VCRS VSS tr tf Table 41. USB: Full speed driver electrical characteristics Symbol Parameter Conditions Min Max Unit tr Rise time(1) CL=50 pF 4 20 ns tf Time1) CL=50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Fall trfm Rise/ Fall Time matching VCRS Output signal Crossover Voltage 1. Measured from 10% to 90% of the data signal. For more detailed information, please refer to USB Specification - Chapter 7 (version 2.0). 65/78 Electrical parameters 4.3.11 STR71xF ADC characteristics Subject to general operating conditions for AVDD, fPCLK2, and TA unless otherwise specified. Table 42. Symbol ADC characteristics Parameter fMOD Modulator Oversampling frequency VAIN Conversion voltage range 2)3) Ilkg PBR SINAD THD ZIN Conditions Min Typ 1) 0 VIN<VSS, | IIN |< Negative input leakage current on 400A on adjacent analog pins analog pin 5 Passband Ripple Max Unit 2.1 MHz 2.5 V 6 A 0.1 dB S/N and Distortion 56 63 dB Total Harmonic Distortion 60 74 dB Input Impedance CADC Internal sample and hold capacitor tCONV Total Conversion time (including sampling time) fMOD = 2 MHz 1 M 3.2 pF 3.0 mA 1 A 2048/ IADC fMOD (max) Normal mode TA = 27 C Standby mode TA = 27 C 2.5 Notes: 1. Unless otherwise specified, typical data are based on TA=25C and AVDD-AVSS=3.3V. They are given only as design guidelines and are not tested. 2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 3. Calibration is needed once after each power-up. 66/78 STR71xF Table 43. Electrical parameters ADC accuracy with fPCLK2 = 20 MHz, fADC=10 MHz, AVDD=3.3 V Symbol Parameter ADC_DATA(0V) Conditions Converted code when AIN=0V 1) ADC_DATA(2.5V) Converted code when AIN=2.5V 1) Min Typ Max Unit 2370 2565 1480 1680 Decimal code 1.30 V VCM Center voltage of Sigma-Delta Modulator1) TUE Total unadjusted error |ED| Differential linearity error1) 1.96 2.19 |EL| Integral linearity error 1) 2.36 3.95 1.23 1.25 In this type of ADC, calibration is necessary to correct gain error and offset errors. Once calibrated, the TUE is limited to the ILE. LSB 1. Data based on characterisation, not tested in production. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. The effect of negative injection current on robust pins is specified in Section 4.3.5. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 4.3.5 does not affect the ADC accuracy. Figure 38. ADC accuracy characteristics 4095 4094 (2) 4093 (3) Digital Result ADC_DATA Register (1) ADC_DATA(0V) ADC_DATA(2.5V) 5 EL 4 3 Out of range ED 2 1 LSBIDEAL 1 0 1 AVSS 2 3 1633 VCM 3100 3101 3102 3103 4093 4094 4095 AVDD VAIN (LSBIDEAL) 1LSB IDEAL AVDD - AVSS 4095 = ------------------------------------------------ (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 67/78 Electrical parameters STR71xF Analog power supply and reference pins The AVDD and AVSS pins are the analog power supply of the A/D converter cell. They act as the high and low reference voltages for the conversion. Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see: General PCB design guidelines). General PCB design guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. Use separate digital and analog planes. The analog ground plane should be connected to the digital ground plane via a single point on the PCB. Filter power to the analog power planes. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1 F and optionally, if needed 10 pF capacitors as close as possible to the STR7 power supply pins and a 1 to 10 F capacitor close to the power source (see Figure 39). The analog and digital power supplies should be connected in a star network. Do not use a resistor, as AVDD is used as a reference voltage by the A/D converter and any resistance would cause a voltage drop and a loss of accuracy. Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs near the A/D input being converted. Software filtering of spurious conversion results For EMC performance reasons, it is recommended to filter A/D conversion outliers using software filtering techniques. Figure 39. Power supply filtering STR710 1 to 10F 0.1F STR7 DIGITAL NOISE FILTERING VSS V33 V33 POWER SUPPLY SOURCE (3.3V) 0.1F EXTERNAL NOISE FILTERING 68/78 AVDD AVSS STR71xF Package characteristics 5 Package characteristics 5.1 Package mechanical data Figure 40. 64-Pin low profile quad flat package (10x10) Dim. D A D1 A2 Typ A A1 b E1 mm Min E e c L1 h L A1 0.05 A2 1.35 1.40 b 0.17 0.22 c 0.09 inches Max Min Typ 0.063 0.15 0.002 0.006 1.45 0.053 0.055 0.057 0.27 0.007 0.009 0.011 0.20 0.004 0.008 D 12.00 0.472 D1 10.00 0.394 E 12.00 0.472 E1 10.00 0.394 e 0.50 0.020 0 3.5 L 0.45 0.60 L1 Max 1.60 7 0 3.5 7 0.75 0.018 0.024 0.030 1.00 0.039 Number of Pins N 64 Recommended footprint (dimensions in mm) 1 69/78 Package characteristics STR71xF Figure 41. 144-Pin low profile quad flat package Dim. D A A2 D3 A1 108 109 73 72 0.08 mm .003 in. b Seating Plane b E3 E1 E 36 c e L1 L h Max Min Typ Max 1.60 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.40 1.45 0.053 0.057 b 0.17 0.22 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 D 21.80 22.00 22.20 0.858 0.867 0.874 D1 19.80 20.00 20.20 0.780 0.787 0.795 D3 37 144 1 Typ A D1 inches(1) mm Min 17.50 0.689 E 21.80 22.00 22.20 0.858 0.867 0.874 E1 19.80 20.00 20.20 0.780 0.787 0.795 E3 17.50 0.689 e 0.50 0.020 K 0 3.5 L 0.45 0.60 L1 1.00 7 0 3.5 7 0.75 0.018 0.024 0.030 0.039 Number of Pins Jedec Ref. MS-026-BFB N 144 1.Values in inches are converted from mm and rounded to 3 decimal digits. Recommended footprint (dimensions in mm) 70/78 STR71xF Package characteristics Figure 42. 64-Low profile fine pitch ball grid array package Dim. mm Min A 1.210 A1 0.270 A2 Typ inches Max Min Typ 1.700 0.048 Max 0.067 0.011 1.120 0.044 b 0.450 0.500 0.550 0.018 0.020 0.022 D 7.750 8.000 8.150 0.305 0.315 0.321 D1 5.600 E 0.220 7.750 8.000 8.150 0.305 0.315 0.321 E1 5.600 0.220 e 0.720 0.800 0.880 0.028 0.031 0.035 f 1.050 1.200 1.350 0.041 0.047 0.053 ddd 0.120 0.005 Number of Pins N 64 Figure 43. 144-low profile fine pitch ball grid array package Dim. inches1) mm Min A 1.21 A1 0.21 A2 Typ Max Min Typ 1.70 0.0476 Ma 0.06 0.0083 1.085 0.35 D 9.85 10.00 10.15 0.3878 0.3937 0.39 D1 E 0.40 0.0427 b 0.45 0.0138 0.0157 0.01 8.80 0.3465 9.85 10.00 10.15 0.3878 0.3937 0.39 E1 8.80 0.3465 e 0.80 0.0315 F 0.60 0.0236 ddd 0.10 0.00 eee 0.15 0.00 fff 0.08 0.00 Number of Pins N 1 144 Values in inches are converted from mm and rounded to 4 decimal digits. Figure 44. Recommended PCB design rules (0.80/0.75mm pitch BGA) Dpad 0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.37 mm aperture diameter - Non solder mask defined pads are recommended - 4 to 6 mils screen print Dpad Dsm 71/78 Package characteristics 5.2 STR71xF Thermal characteristics The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation: TJ = TA + (PD x JA) (1) Where: TA is the Ambient Temperature in C, JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, PD is the sum of PINT and PI/O (PD = PINT + PI/O), PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power. PI/O represents the Power Dissipation on Input and Output Pins; Most of the time for the application PI/O < PINT and can be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273C) (2) Therefore (solving equations 1 and 2): K = PD x (TA + 273C) + JA x PD2 (3) where: K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA. Table 44. Symbol 72/78 Thermal characteristics Parameter Value Unit JA Thermal Resistance Junction-Ambient LQFP 144 - 20 x 20 mm / 0.5 mm pitch 42 C/W JA Thermal Resistance Junction-Ambient LQFP 64 - 10 x 10 mm / 0.5 mm pitch 45 C/W JA Thermal Resistance Junction-Ambient LFBGA 64 - 8 x 8 x 1.7mm 58 C/W JA Thermal Resistance Junction-Ambient LFBGA 144 - 10 x 10 x 1.7mm 50 C/W STR71xF 6 Product history Product history There are three versions of the STR710F series products. All versions are functionally identical and differ only with the points listed below. Version "A" was the first version produced and delivered. Version "Z" was the second in production replacing version "A". Version "Z" has lower power consumption in STOP mode. Version "X" is the latest introduced. Marking The difference between versions is visible on the marking of the product as shown in the four examples in Figure 45 through Figure 48. Figure 45. LQFP144 STR710 version "A" A STR710FZ2T6 Figure 46. LQFP64 STR712 version "Z" Z STR712FR2 T6 2208JVG MLT225571 2208JVG MLT225571 73/78 Product history STR71xF Figure 47. BGA144 STR710 version "Z" Figure 48. BGA64 STR711 version "X" R711R1H6 2208JVG R710Z2H6 MLT225571 2208JVG Z MLT 22 551 Table 45. X A, Z and X version differences Feature A version Z version X version ARM7TDMI core device Identification (ID) code register (see ARM7TDMI Technical Reference Manual) Version bits [31:28] = 0001 Version bits [31:28] = 0010 Version bits [31:28] = 0010 Low power mode consumption in STOP mode at 25 C Not guaranteed Typical 49 A 50 A maximum at 25C. Less than 30 A at 25 C for 99.730020% of parts Same as Z. SC.DATA pin 74/78 Not TRUE open drain When addressing 5V cards, the SCDATA Line must be connected to an open drain buffer. Pin P0.10/U1.RX/U1.TX/SC. DATA has been modified to offer TRUE OPEN DRAIN functionality when in Smartcard mode. When addressing 5V cards, the SCDATA line can now be connected directly to the card I/O. This modification is backward compatible with previous designs, and no board modification is required. STR71xF 7 Ordering information Ordering information Figure 49. STR71xF ordering information scheme Example: STR71 0 F Z 1 T 6 Product class STR71x microcontroller Peripheral set 0 = full peripheral set 1 = No EMI, no CAN 2 = No EMI, no USB 5 = No EMI, no USB, no CAN Program memory type F = Flash Pin count R = 64 pins Z = 144 pins Program memory size 0 = 64+16K 1 = 128+16K 2 = 256+16K no character = 0K Package type H = LFBGA T = LQFP Temperature range 1 = 0 C to 70 C 3 = -40 C to 125 C 6 = -40 C to 85 C Packing no character = tray or tube TR = tape and reel For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you. 75/78 Revision history 8 STR71xF Revision history Table 46. Document revision history Date Revision 17-Mar-2004 1 First Release 05-Apr-2004 2 Updated "Electrical parameters" on page 33 08-Apr-2004 2.1 Corrected STR712F Pinout. Pins 43/42 swapped. 15-Apr-2004 2.2 PDF hyperlinks corrected. 7-Jul-2004 29-Oct-2004 25-Jan-2005 19-Apr-2005 13-Oct-2005 76/78 Changes 3 Corrected description of STDBY, V18, VSS18 V18BKP VSSBKP pins Added IDDrun typical data Updated BSPI max. baudrate. Updated "EMI - external memory interface" on page 56 4 Corrected Flash sector B1F0/F1 address in Figure 6: Memory map on page 30 Corrected Table 7 on page 24 LQFP64 TEST pin is 16 instead of 17. Added to TQPFP64 column: pin 7 BOOTEN, pin 17 V33IO-PLL Changed description of JTCK from `External pull-down required' to `External pull-up or pull down required'. 5 Changed "Product Preview" to "Preliminary Data" on page 1 and 3 Renamed `PU/PD' column to `Reset state' in Table 7 on page 24 Added reference to STR7 Flash Programming Reference Manual 6 Added STR715F devices and modified RAM size of STR71xF1 devices Added BGA package in Section 5 Updated ordering information in Section 7. Added PLL duty cycle min and max. in PLL electrical characteristics on page 44 7 Updated feature description on page 1 Update overview Section 1.1 Added OD/PP to P0.12 in Table 7 Changed name of WFI mode to WAIT mode Changed Memory Map Table 6: Ext. Memory changed to 64 MB and flash register changed to 36 bytes. Added Power Consumption Table 15 Modified BGA144 F3, F5, F12 and G12 in Table 3 and Table 4 Update EMI Timing Table 26 and Figure 29 STR71xF Revision history Table 46. Document revision history (continued) Date Revision Changes 8 Added Flashless device. Changed reset state of pins P1.10 and P1.13 from pu to pd, P0.15 from pu to floating and removed x in interrupt column for P1.15 and P1.12 in Table 4 and Table 7 Added notes under Table 4 on EMI pin reset state. Corrected inch value for d3 in Figure 40 Added footprint diagrams in Figure 40 and Figure 43 Updated Section 4: Electrical parameters 01-Aug-2006 9 Flash data retention changed to 20 years at 85 C. Changed note 8 on page 19 Changed note 1 on page 45 06-Nov-2006 10 Added STR715FR0T1 in Table 42: Order codes P0.12 corrected in Table 7 on page 24 20-Mar-2007 11 Added characteristics of BSPI - buffered serial peripheral interface on page 63 Updated Table 23: Low-power mode wakeup timing on page 45 12 Updated ordering information Updated USB characteristics Updated external clock characteristics 22-May-2006 13-Feb-2008 77/78 STR71xF Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 78/78