1
Features
•Macrocell for Inter-IC communication using only two wires (serial clock and data)
•Data rates up to 400K bit/sec.
•ICs can be either masters or slaves (a master controls the communication bus)
•Master and slave can both transmit and receive data
•True multi-master protocol allows more than one master on an I2C bus
•Each IC on the bus has a unique address
•No theoretical limit to the number of ICs which can be attached to a bus (maximum
capacitance is 400 pF)
•Small physical size (2000 gates)
•Full support of the “Fast” I2C pro toco l
•Baud rate control (software and hardware)
•Includes a clock pre-scaler/divider to operate with a high-frequency input clock (over
12 MHz)
•Minimum clock frequency of 6 MHz for a good input filter performance
Description
The Inter -Integrated Cir cuit Bu s (I2C) has been deve loped by P hili ps f or inte rcon nect-
ing devices on a system by a unique two-wire bus, comprising serial data (SDA) and
serial clock (SCL).
The CB_I2C macroce ll handles bytes transferred autonomousl y to and f rom the I2C
bus. The sta tus of the C B_I2C inter face an d bu s can be read from an intern al sta tus
register automat ically up dated at eac h step of a tran sfer. It can be driven by a micro-
controller or a dedicated sequencer through its internal registers: data, control,
address and status register.
The CB_I2C interface can operate, in “fast” mode or in “normal” mode; this allows
baud rate s from 0 to 400 K b it/s ec. The dev ic e s up ports fou r m ode s: Mas ter Tr ansmit-
ter, Master Receiver, Slave Transmitter and Slave Receiver.
The CB_I2C interface recognizes/generates START and STOP c onditions, recog-
nizes the st retch ed lo w p eriod of th e seri al cl ock, adapts its baud rate to the rece ived
SCL frequency, handles bus arbitration, recognizes/generates acknowledges, recog-
nizes its own slave address and general calls.
The I2C has been adopted as a standard by the majority of consumer equipment man-
ufacturers.
Figure 1. System Diagram
ASIC
I/O
Cell
Customized
Logic CB_I2C
I/O
Cell
SDOUT
SDIN
SCOUT
SCIN
SCL SDA
Standard
Interface
Macrocell
CB_I2C
Rev. 0877B–09/98
CB_I2C
2
Figure 2. CB_I2C Symbol Notes
• The five lines of the RDN bus are not exclusive. Each bit
selects one inter nal r egister. So to set more than one bit
to “0” will create contentions on the IBT bus.
• The three lines of the WRN bus are not exclusive. Each
bit select one inter nal register. So to set more than one
bit to “0” will lo ad the data on the IB T bus into mor e than
one internal register.
• POC is a synchronous master reset. POC is loaded by
the falling edge of CLI2C.
• ENCLRBIT must be 1 to reset the S1CON.SI flag, during
the write cycle of S1CON.
• The four-line select bus RDN(4:0) selects the five
internal registers as follows:
RDN(4): internal status register (S1IST)
RDN(3): status register (S1STA)
RND(2): address register (S1ADR)
RDN(1): data register (S1DAT)
RDN(0): Control register (S1CON)
• The three-line write enable bus WRN(2:0) selects the
three (writable) internal registers as follows:
WRN(2): Address register (S1ADR)
WRN(1): Data register (S1DAT)
WRN(0): Control register (S1CON)
• Dur ing a rea d cycle of an inter nal regis ter, RDE and BE
must be high.
• Dur ing a wr ite cycle of an inte rnal register, RDE a nd BE
must be low.
CB_I2C
SCANAO
SCANBO
SCANCO
SCANDO
SCANAI
SCANBI
SCANCI
SCANDI
ENCLRBIT
RDE
RDN<4:0>
WRN<2:0>
BE
CL8
CL16
CL32
BRX0
BRX1
CR0
CR1
CR2
CR10N
SCOUT
SDOUT
Test
Interface
Clock/Band Rate
<- clock ->
<- data ->
CLI2C
SHIFT
SA
I
2
C Bus
BR0
BR1
BR2
BR3
IBT<7:0>
SCIN
SDIN
POC
IRI2C
CB_I2C
3
Table 1. Pin Description
Signal Name Type Description
Scan Test Pins
SCANAI Input Scan chain input of first scan path
SCANBI Input Scan chain input of second scan path
SCANCI Input Scan chain input of third scan path
SCANDI Input Scan chain input of fourth scan path
SHIFT Input Scan mode select. Change during CLI2C low. While SHIFT=1, the scan test shift mode is
enabled.
SA Input Scan access. Active high during scan test. Used to control some multiplexers in scan mode.
SCANAO Output Scan chain output of first scan path
SCANBO Output Scan chain output of second scan path
SCANCO Output Scan chain output of third scan path
SCANDO Output Scan chain output of fourth scan path
Baud Rate Control
BR0/BR1/BR2/BR3 Input Baud rate selection inputs
BRX0/BRX1 Input External bit rate clock.
A rising edge at one of these inputs (as selected by BR2) is synchronized and converted to an
internal enable of one CLI2C cycle duration.
CLI2C Input I2C internal clock.
Minimum frequency = 6MHz.
Active edge = falling edge.
CR0/CR1/CR2 Output Serial control register outputs.
Used to control the baud rate through the control register (software control).
CR10N Output Combination of CR1 and CR0: CR10N= CR1 + -CR0
CL8/CL16/CL32 Output Clock output, frequency is CLI2C/8 - CLI2C/16 - CLI2C/32
Parallel Interface
POC Input Power-on-Clear. Synchronous master reset (High)
ENCLRBIT Input Enable signal. Interrupt flag (control register) can be cleared only when ENCLRBIT = 1
RDE Input Dynamic read enable. When used with an 80C51, RDE is connected to PH1S.
RDN(4:0) Input Read enable. Select the CB_I2C internal register to read. Active low.
WRN(2:0) Input Write enable. Select the C B_I2C internal register to write. Active low.
BE Input Bus enable. Control the CB_I2C internal tri-state buffers. When High, IBT is in output mode.
IBT(7:0) InOut Bi-directional data bus. Used to read/write data from/to the internal registers.
IRI2C Output CB_I2C interrupt request. Active High.
I2C Bus
SCIN Input Ser ial clock input (SCL)
SDIN Input Serial data input (SDA)
SCOUT Output Serial clock output (S CL)
SDOUT Output Serial data output (SDA)
CB_I2C
4
Operating Modes
Mast er Transmitter
In the M aster /Tr ansm itter mo de t he C B_I2 C inte rfac e ge n-
erates the START condition, the slave address and the
transfer direction bit, recognizes the slave acknowledge,
sends the da ta bytes and gener ates the STOP con ditio n. If
no ackn owledge i s received , the C B_I2C interf ace gener-
ates the STOP condition and releases the bus. If it loses
the bus ar bitrati on durin g the tr ansfe r of th e slave a ddress ,
the CB_I2C interface switches to the slave mode to be able
to recognize its own slave address during the same trans-
fer cycle.
Master Receiver
In the Master/Receiver mode the CB_I2C interface gener-
ates the START condition, the slave address and the trans-
fer direction bit, generates the acknowledges at each data
byte received and the STOP condition (or repeated START
condition).
Slave Receiver
In the Slav e/Receiver mode an interrupt is requeste d as
soon as the own slave address is recognized. The interface
generates acknowledges, and recognize the STOP condi-
tion.
Slave Transmitter
In the Sla ve/Trans mitter mode th e interfac e recog nizes th e
START and STOP conditions, its own slave address,
sends the data bytes (through the SDA line) adapting its
baud rate to the received serial clock frequency (SCL).
Baud Rate Selection
The CB_I2C Macr oCell includes a clock pre-scaler. This
pre-scaler generates three clock signal: CL8
(CLI2C_freq/8), CL16 (CLI2C_freq/16) and CL32
(CLI2C_freq/3 2). One (or more) of these outputs can be
used to gener ate a lower frequenc y clock from a hi gh fre-
quency master clock.
The baud rate can be driven by one of the three input clock
signals: CLI2C (master clock), BRX0, or BRX1. Note that
CLI2C is the MacroCell clock input (so it must not be
stopped and must be at least, of 6MHz), BRX0 and BRX1
are only used to generate the SCL signal. BRX0 and BRX1
are edge sensitive to be independent from the pulse dura-
tion and generates an enable of one CLI2C period.
If the CB_I2C interface has to be used with a high fre-
quency master clock (CLI2C), one of the clock pre-scaler
outputs (C L8, CL16 or CL32) can be co nnected to one of
the external bit rate clocks (BRX1 or BRX0) to generate the
needed baud rate.
The ou tput baud rate is selected by the four inpu t signa ls
BR3, BR2, BR1 and BR0. The two MSBs select the I2C
mode (fast/normal) and the clock input used to generate
the output baud rate.
Note
In the normal mode the high-to-low ratio of the serial clock
(SCL) is 1:1 and the max imum baud rate is 100 K bit/s. In
the fast mode, the high-to-low ratio of SCL is 2:3 and the
maximum baud rate is 400K bit/s.
The two LSBs of the baud rate selection bus are used to
select the r at io b etwe en t he i npu t frequ enc y and the o utp ut
baud ra te. In the fol lo win g t abl e “ i npu t_f” s tan ds fo r the fre-
quency of the selected input clock (CLI2C, BRX1 or BRX0):
The baud rate s electio n bits of the con trol re gister are out-
put (C R2, CR1 a nd CR0). A n additi onal s ignal, CR1 0N is
output too:
CR10N = CR1 + -CR0
These four outputs can be connected to the baud rate
selection inputs (BR3, BR2, BR1 and BR0 ) to select the
output baud rate through the control register.
The fol lowing t able giv es you t he outp ut baud rate acco rd-
ing to the values of the baud rate selection bits (BR3 to
BR0 lines), for some common master clock frequencies
(CLI2C).
Table 2. Output Baud Rate
BR3 BR2 Mode Clock input
1 1 Normal CLI2C
1 0 Fast CLI2C
01NormalBRX1
00NormalBRX0
Table 3. Input Frequency/Output Baud Rate Ratio
BR1 BR0 Normal mode
baud rate Fast mode
baud rate
0 0 Input_f/120 Input_f/30
0 1 Input_f/100 Input_f/25
1 0 Input_f/80 Input_f/20
11Input_f/60 Input_f/15
CB_I2C
5
Notes: 1. Normal mode, SCL high-to-low ratio = 1:1
2. Fast mode, SCL high-to-low ratio = 2:3
Table 4. Output Baud Rate According to Baud Rate Selection Bits
BR3 BR2 BR1 BR0 Output Bit Rate
CLI2C See
Note
Below 6 8 10 12 MHz
1100f_CLI2C / 120 50 66.7 83.3 100 kHz
(1)
1101f_CLI2C / 100 60 80 100 --- kHz
1110 f_CLI2C / 80 75 100 --- --- kHz
1111 f_CLI2C / 60 100 --- --- --- kHz
1000 f_CLI2C / 30 200 266.7333.3 400 kHz
(2)
1001 f_CLI2C / 25 240 320 400 --- kHz
1010 f_CLI2C / 20 300 400 --- --- kHz
1011 f_CLI2C / 15 400 --- --- --- kHz
0100 f_BRX1 / 120
(1)
0101 f_BRX1 / 100
0110 f_BRX1 / 80
0111 f_BRX1 / 60
0000 f_BRX0 / 120
0001 f_BRX0 / 100
0010 f_BRX0 / 80
0011 f_BRX0 / 60
CB_I2C
6
Internal Registers
S1ADR, the Address Register
S1ADR contains the 7-bit I2C address to which the CB_I2C interface will respond when programmed as a slave (transmitter
or receiver). The “Own-Slave-Address” is stored in the 7 most significant bits of S1ADR. The LSB is used to enable the rec-
ognition of the “general call address”.
When GC is set to “1” the CB_I2C interface will generate an interrupt (IRI2C line) when the “general call address” is recog-
nized. Otherwise, the CB_I2C will generate an interrupt only when its “Own Slave Address” is recognized.
This register could be loaded with the I2C chip address during the initialization steps.
S1DAT, the Data Shift Register
S1DAT contains the incoming byte (just received from the I2C bus) in the receiver mode and the outgoing data (to be send
to the I2C bus) in the transmitter mode.
S1DAT is always shifte d from right to left. It means, the first bit trans mitted to the I2C bus is the MS B in the transmitter
mode, and the MSB is the first bit received from the I2C bus in the receiver mode.
During a trans missio n (when the CB_I2C sen d data to the I 2C bus) while the data is shifte d out, the val ue on the SDA line
is shifted in. So in case of an arbitration lost, S1DAT will contains the correct data (the value read from the bus).
S1CON, the Control Register
S1CON is used to control the CB_I2C interface. By setting the bits of this register you can make the CB_I2C interface gen-
erate a S TART co ndition, a STOP co ndition, an acknowledge , you can also contr ol the ou tput bit rate (see “Bau d Rate
Sel ectio n” on page 4).
The bits of S1CON have the following meanings and functions:
ENS1
enables (or disables) the CB_I2C interface. When set to “0”, the CB_I2C is in “not addressed” slave mode. It means, no
START (or STOP) condition can be gener ated, the “Own Slave Address” (or the “general call address”) is not recog-
nized/acknowledged, the SCL and SDA lines are disabled (no output is generated, and no input is taken into account).
When set to “1” the CB_I2C is enabled and can perform transmissions in master or slave mode.
It is n ot recommen ded to us e ENS1 to disa ble an ac knowled ge (or the recogniti on of the chip a ddress), be cause wh ile
ENS1 is set to “0”, the CB_I2C keeps no trace of the I2C bus status.
STA
enables the generation of a START condition. When set to “1”, the CB_I2C enters the master mode, checks the status of
the I2C bus and generates a START condition if the bus if free. If the bus is not free, the CB_I2C will wait until a STOP con-
dition to generate a START condition (after a minimum time). Set to “0” put the CB_I2C in the slave mode.
STO
control s the generation of a STOP conditi on. When set to “1” while bei ng in master mode, the CB_I2 C generates a STOP
conditi on. W hen th e STO P condi ti on is dete cte d on bu s, the STO bit is auto mati c all y cle ared. In sla ve mode th e STO bit is
used to r ec over fr om a bu s erro r. In s uch a case , no STO P co ndi tio n i s t ran smitted, but the i nte rf ac e do as if a S T OP con-
dition has been received and switch to the “not addressed” slave mode (the STO bit is then cleared by the interface).
76543210
ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 GC
76543210
DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0
76543210
CR2 ENS1 STA STO SI AA CR1 CR0
CB_I2C
7
SI
is a flag/control bit. SI is set to “1” by the CB_I2C interface to indicate that an interrupt has to be serviced. When SI is “1” the
IRI2C line is high, and the SCL line is pulled low. The SI flag must be reset by the controller/sequencer driving the CB_I2C
interface. It means the transfer is suspend until the SI flag is reset.
AA
is the As sert A cknow ledge flag. Wh en set to “ 1” an ack nowled ge is retur ned whe n the “ow n slav e addr ess” is rece ived (or
the general call address has been received while S1ADR.GC is “1”), or when a data byte has been received while being in
the receiver mode.
When AA is reset to “0”, no acknowledge is returned (SDA remains high during the acknowledge SCL clock pulse).
CR2-CR1-CR0
can be used to se lect the output baud rat e. Thes e 3 bits are conne cted to th e CR2-C R1-CR0 ou tputs of the ES2 IC inte r-
face. If the CR2-CR1-CR0 outputs are connected to BR inputs, the output baud rate can be selected by loading the appro-
priate values into S1CON (see “Baud Rate Selection” on page 4).
S1STA, the Status Register
S1STA is the status register. The 3 LSBs of S1STA are always “0”, the 5 MSBs contain the interface status code. S1STA is
updated after eac h chan ge on the inter rupt r equ est lin e (I RI2C). S1 STA sho uld be r ead af ter eac h in ter rupt r equ es t (IRI2C
goes high) to determine the current state of the CB_I2C interface, and the next action to perform (e.g: load the receive data
byte, suspend transfer, generate STOP condition, send data byte,...).
In the foll owing ta bles are for ea ch va lue of S 1STA, the mean ing ( curren t state o f the in terface) , the ne xt act ion to b e per-
formed by the controller/sequencer driving the CB_I2C interface, and the next action the CB_I2C will perform.
In these tables, the following abbreviation are used:
SLA => Slave address
S => START condition
R => Read
W => Write
ACK => Acknowledge
P => STOP condition
MST => Master
SLV => Slave
REC => Receiver
TRX => Transmitter
76543210
ST4 ST3 ST2 ST1 ST0 0 0 0
CB_I2C
8
Table 5. Master/Transmitter Mode
Status
Code Meaning
(status of CB_I2C) Next action to be done by the controller Next action CB_I2C will perform
08H START condition has
been transmitted Load S1DAT with slave address
and R/W bit. Reset S1CON.SI Slave address + R/W will be
transmitted. Wa it ACK.
10H Repeated START
condition
transmitted
Load S1DAT with slave address
and R/W bit. Reset S1CON.SI As above. If R/W = R, CB_I2C
switch into receiver mode.
18H SLA + W has bee n sent
ACK received.
Load S1DAT with data byte.
Reset S1CON.SI.
--- OR ---
Set S1CON.STA. Reset S1CON.SI
--- OR ---
Set S1CON.STO. Reset S1CON.SI
--- OR ---
Set S1CON.STA, S1CON.STO and reset
S1CON.SI.
Data byte will be transmitted
Wait for ACK.
Generates repeated START condition
Generates STOP condition.
Generates STOP condition, then generates
a START condition
20H SLA + W has been sent,
no ACK received. As above. As above.
28H Data byte transmitted
ACK received. As above. As above.
30H Data byte transmitted
no ACK received. As above. As above.
38H Arbitration lost in
SLA + R/W or data byte
Reset S1CON.SI.
--- OR ---
Set S1CON.STA, reset S1CON.SI
Release I2C bus, switch to slave mode.
Wait until the I2C bus is free to generate a
START condition
Table 6. Master/Receiver Mode
Status
Code Meaning
(status of CB_I2C) Next action to be done by the controller Next action CB_I2C will perform
08H START condition has
been transmitted Load S1DAT with slave address
and R/W bit. Reset S1CON.SI Slave address + R/W will be
transmitted. Wa it ACK.
10H Repeated START
conditi on transm itte d. Load S1DAT with slave address
and R/W bit. Reset S1CON.SI As above. If R/W = W, CB_I2C
switch into transmitter mode.
38H Arbitration lost in
SLA + R/W or data byte
Reset S1CON.SI
--- OR ---
Set S1CON.STA, reset S1CON.SI
Release I2C bus, switch to slave mode.
Wait until the I2C bus is free to generate a
START condition
40H SLA + R has been sent
ACK received.
Reset S1CON.SI. Set S1CON.AA
--- OR ---
Reset S1CON.SI. Reset S1CON.AA
Data byte will be received,
ACK will be returned.
Data byte will be received,
no ACK will be returned.
CB_I2C
9
48H SLA+R has been sent
no ACK received.
Set S1CON.STA. Reset S1CON.SI
--- OR ---
Set S1CON.STO. Reset S1CON.SI
--- OR ---
Set S1CON.STA, S1CON.STO and reset
S1CON.SI.
Generates repeated START condition
Generates STOP condition
Generates STOP condition, then generates
a START condition
50H Data byte received,
ACK returned.
Read data byte, reset S1CON.SI
set S1CON.AA
--- OR ---
Read data byte, reset S1CON.SI
reset S1CON.AA
New data byte will be r eceived
and ACK will be returned.
New data byte will be r eceived
and no ACK will be returned.
58H Data byte received
no ACK returned.
Read data byte, Set S1CON.STA
Reset S1CON.SI
--- OR ---
Read data byte, Set S1CON.STO
Reset S1CON.SI
--- OR ---
Read data byte, Set S1CON.STA,
S1CON.STO and reset S1CON.SI.
Generates repeated START condition
Generates STOP condition.
Generates STOP condition, then
generates a START condition
Table 6. Master/Receiver Mode
Status
Code Meaning
(status of CB_I2C) Next action to be done by the controller Next action CB_I2C will perform
Table 7. Slave/Receiver Mode
Status
code Meaning
(status of CB_I2C) Next action to be done by the controller Next action CB_I2C will perform
60H Own SLA + W received,
ACK returned.
Reset S1CON.SI, S1CON.AA = 1
--- OR ---
Reset S1CON.SI, S1CON.AA = 0
Data byte will be received,
ACK returned.
Data byte will be received,
no ACK returned.
68H Arbitration lost in SLA,
Own SLA received
ACK returned.
As above. As above.
70H General call address
received + ACK
returned
As above. As above.
78H
Arbitration lost in SLA,
general call ADD
received + ACK
returned
As above. As above.
80H Addressed with Own
SLA, data b yte receiv ed
+ ACK returned
As above. As above.
CB_I2C
10
88H Addressed with Own
SLA, data received,
no ACK returned
Read data byte, reset S1CON.SI
reset S1CON.AA
--- OR ---
Read data byte, reset S1CON.SI
set S1CON.AA
--- OR ---
Read data byte, reset S1CON.SI
reset S1CON.AA, set S1CON.STA
--- OR ---
Read data byte, reset S1CON.SI
set S1CON.AA, set S1CON.STA
Switch to “not addressed” SLV mode. Own
SLA/general call recognition disabled.
Switch to “not addressed” SLV mode.
Acknowledge own SLA and general call (if
S1ADR.GC = 1)
Switch to “not addressed” SLV mode. Own
SLA/general call recognition disabled.
START will be transmitted as soon as the
bus becomes free.
Switch to “not addressed” SLV mode.
Acknowledge own SLA and general call (if
S1ADR.GC = 1)
START condition will be sent as soon as the
bus is free.
90H
Addressed by general
call address, data byte
received,
ACK returned.
Read data bye, reset S1CON.SI
set S1CON.AA
--- OR ---
Read data byte, reset S1CON.SI
reset S1CON.AA
Data byte will be received,
ACK returned.
Data byte will be received,
no ACK returned.
98H
Addressed by general
call address, data byte
received, no ACK
returned.
Read data byte, reset S1CON.SI
set S1CON.AA
--- OR ---
Read data byte, reset S1CON.SI
reset S1CON.AA
--- OR ---
Read data byte, reset S1CON.SI
set S1CON.AA, set S1CON.STA
--- OR ---
Read data byte, reset S1CON.SI
reset S1CON.AA, set S1CON.STA
Switch to “not addressed” SLV mode.
Acknowledge own SLA and general call (if
S1ADR.GC = 1)
Switch to “not addressed” SLV mode. Own
SLA/general call recognition disabled.
Switch to “not addressed” SLV mode.
Acknowledge own SLA and general call (if
S1ADR.GC = 1) START condition will be
sent as soon as the bus is free.
Switch to “not addressed” SLV mode. Own
SLA/general call recognition disabled.
START will be transmitted as soon as the
bus becomes free.
A0H
STOP or repeated
START condition has
been rece ived while
addressed as SLV/REC
or SLV/TRX.
As above. As above.
Table 7. Slave/Receiver Mode
Status
code Meaning
(status of CB_I2C) Next action to be done by the controller Next action CB_I2C will perform
CB_I2C
11
Table 8. Slave/Transmitter Mode
Status
Code Meaning
(status of CB_I2C) Next action to be done by the controller. Next action CB_I2C will perform.
A8H Own SLA received,
ACK returned
Load data byte, reset S1CON.SI
set S1CON.AA
--- OR ---
Load data byte, reset S1CON.SI
reset S1CON.AA
A new data byte will be transmitted.
Last data byte will be transmitted.
B0H Arbitration lost in SLA,
own SLA received
ACK returned.
As above. As above.
B8H Data byte has been
transmitted, ACK has
been received
As above. As above.
C0H Data byte has been
transmitted, no ACK
received
Reset S1CON.SI, S1CON.AA = 0,
S1CON.STA = 0
--- OR ---
Reset S1CON.SI, S1CON.AA = 1,
S1CON.STA = 0
--- OR ---
Reset S1CON.SI, S1CON.AA = 0,
S1CON.STA = 1.
--- OR ---
Reset S1CON.SI, S1CON.AA = 1,
S1CON.STA = 1
Switch to “not addressed” SLV mode.
Own SLA/general call recognition
disabled.
Switch to “not addressed” SLV mode.
Acknowledge own SLA and general call
(if S1 ADR.GC = 1)
Switch to “not addressed” SLV
mode. Own SLA/g ene ra l call
recognition disabled. START
will be trans mit ted as so on a s
the bus becomes free.
Switch to “not addressed” SLV
mode. Acknowledge own SLA and
general call (if S1ADR.GC = 1)
START condition will be sent
as soon as the bus is free.
C8H Last data byte has
been transmitted, ACK
received.
As above. As above.
Table 9. Miscellaneous States
Status
code Meaning
(status of CB_I2C) Next action to be done by the controller. Next action CB_I2C will perform.
F8H No information: The CB_I2C can be proceeding with a transfer, or waiting to be addressed.
00H Bus error. Reset S1CON.SI, set S1CON.STO In all cases, the bus is released,
CB_I2C switches to the “not addressed”
SLV mode, then STO is cleared.
CB_I2C
12
Detailed Modes of Operation
The following sequences are not to be followed word-by-word; they are included here to help those who are not familiar
with the I2C interfacing, for those who are beginning with the CB_I2C interface, and to give examples for each major mode
of operati on of th e CB _I2C Mac roCel l. In th e fo llo win g s ec tio ns , whe n a d iag ram i s i nclu ded , no v al ue is given for th e con-
straints (because they are process dependent).
Initialization
To initializ e the CB_I2C interface, reset the internal registers by setting PO C to “1”. On the first clo ck cycle ( high-to-low
edge of CLI2C) POC is loaded into a D-flip-flop to generate the internal signal POCC. POCC is then used as a synchro-
nous reset by all the registers (and memory elements of the CB_I2C). To be taken into account POC should be high during
one CLI2C period. The following diagram shows the constraints on POC:
Figure 3. POC Constraints
PocS = POC to CLI2C (high-to-low edge) setup time
PocH = POC from CLI2C (high-to-low edge) hold time
Then (onc e POC i s ba ck to “0” ) lo ad the own sl av e a ddres s (the I 2C addr es s of yo u r ch ip) a nd the gen er al c all b it, int o th e
address register (S1ADR): set WRN(2) = 0, RDE = 0 and BE = 0, apply the own slave address and the GC bit onto the IBT
bus (the data present on IBT is loaded into S1ADR on the next high-to-low edge of CLI2C). The following diagram shows a
write cycle of the S1ADR inter nal register:
Figure 4. S1ADR Internal Register Write Cycle
WrnS = write enable (WRN) to CLI2C (high-to-low edge) setup time
WrnH = write enable (WRN) from CLI2C (high-to-low edge) hold time
IbtS = data (IBT) to CLI2C (high-to-low edge) setup time.
IbtH = data (IBT) from CLI2C (high-to-low edge) hold time.
CLI2C
POC PocS PocH
CLI2C
RDE
BE
7H 3H 7H
own slave address
WRN (2:0)
IBT (7:0)
WrnS WrnH
IbtS IbtH
CB_I2C
13
Note
The “X” value on the BE and RDE lines means those lines can be either “1” or “0”.
To enable the CB_I2C interface, set the S1CON.ENS1 bit to “1”. In the same write cycle of S1CON, you can set
S1CON. AA t o “1”, if y ou wa nt to re co gniz e th e ch ip a ddr ess (ow n sl ave addr ess prev iousl y l oaded int o S1 AD R) a nd g en-
eral calls (if S1ADR.GC = 1), set the output baud rate through S1CON.CR2, S1CON.CR1 and S1CON.CR0 (if the baud
rate is to be selected by software). Once S1CON.ENS1 is set, the CB_I2C interface begins checking the I2C bus. If its own
slave address or a general call is detected (and if S1CON.AA = 1) it generates an interrupt request on the IRI2C output and
loads the corresponding status word into S1STA.
The following diagram shows a write cycle of the S1CON internal register:
Figure 5. S1CON Internal Register Write Cycle
WrnS = write enable (WRN) to CLI2C (high-to-low edge) setup time
WrnH = write enable (WRN) from CLI2C (high-to-low edge) hold time
IbtS = data (IBT) to CLI2C (high-to-low edge) setup time.
IbtH = data (IBT) from CLI2C (high-to-low edge) hold time.
Note
The “X” value on the BE and RDE lines means those lines can be either “1” or “0”.
CLI2C
RDE
BE
7H 6H 7H
control word
WRN (2:0)
IBT (7:0)
WrnS WrnH
IbtS IbtH
CB_I2C
14
Master Transmit ter Mode
Before starting the Master/Transmitter mode,
S1CON.ENS1 must be “1”. To start a transfer in Mas-
ter/Transmitter mode, set S1CON.STA to “1” (during the
same write cycle of S1CON, ENS1 must stay “1”, CR2-
CR1-CR0 can be used to select the output baud rate, and
AA could be changed). If AA is set to “1”, in case of a loss
of arbitration during the slave address transfer (and direc-
tion bit) on to the I2C bus, the CB _I2C will be abl e to recog-
nize its own sl ave add ress ( or a ge neral ca ll) a nd gener ate
an acknowledge during the same I2C bus cycle.
Once S1CON.STA is set to “1”, the CB_I2C will test the I2C
bus and generate a START condition as soon as the bus is
free. When the START condi tion is rec ognized on the I2C
bus, the interrupt reques t line (IRI2C) goes high and the
status register (S1STA) loads the appropriate value (08H).
The SI flag (in the control register, S1CON) is also set to
stop the CB_I2C. At this time (in response to the interrupt
request), the controller/sequencer which drives the CB_I2C
interface should perform the following actions:
• load the slave address into the data register (S1DAT).
• reset the SI flag (from the control register, S1CON).
Notes
• If the controller/sequencer can not answ er to the CB_I2C
interrupt request (it is performing a real-time task or
treating an interrupt request of an higher priority), the
CB_I2C will stay in a “frozen” state and pul l low the SCL
line until the S1CON.SI flag is reset to “0”.
• In the Mast er/Transmitter mo de the LSB of the data byte
loaded into the data register as the slave address is “0”
(it is the direction bit).
The foll owing diagram sho ws th e begi nning of a tran sfer in
Master/Transmitter mode (the read and write cycles of the
internal registers are not detailed):
Figure 6. Beginning of a Transfer in Master/Transmitter Mode
7H6H
data in
3H 7H 6H 7H
08H data in data in
1FH 17H 1FH
write
S1CON
(STA = 1)
read
S1STA write
S1ADR reset
S1CON.SI
START
condition
interrupt
request
WRN (2:0)
IBT (7:0)
BE/RDE
RDN (4:0)
IRI2C
SCL
SDA
CB_I2C
15
Notes
In ord er to r ese t the S1CO N.SI flag, the input lin e ENC LR-
BIT must be set to 1 dur ing the write cycle of S1CON.
“data_in” means a data byte is written into an internal regis-
ter. BE and RDE have been grouped to make the diagram
more readable; they could be grouped or generated sepa-
rately in your application.
Once the interrupt flag of the control register (S1CON.SI) is
cleared, the interrupt request line (IRI2C) goes back low
and the CB_I2C interface starts transmitting the slave
address. After the transmission of the last bit (8th) of the
slave ad dress, the CB_I2 C rele ases the S DA lin e to let th e
slave acknowledge its address during the next (9th) SCL
clock puls e. Afte r the ninth SCL c lock pulse the s tatu s reg-
ister (S1STA ) is updated with the a pprop riate v alue (18 H if
the acknowledge has been received, 20H if not), and the
interrupt reques t line goes hig h to highlight the en d of the
first byte transfe r (the interrupt flag, S1CON.S I is also set).
The controller/sequencer driving the CB_I2C interface
should then perform the following tasks:
• read the status regist er (S1STA ) .
If an acknowledge has been received:
• write the next data byte into the data register (S1DAT)
• clear the interrupt flag (S1CON.STA)
It can also:
• set the STOP bit of the control register, to generate a
STOP condition, or
• set the START bit of the control register, to generate a
repeated START condition, or
• set the START and STOP bits of the control register, to
generate a STOP condition, then a START condition.
• If no acknowledge has been received:
• clear the interr upt flag (S1CON.S TA), write the STO P bit
of the control register to generate a STOP condition (or
write the START bit to generate a repeated START
condition).
If the arbitration has been lost, the CB_I2C interface
releases the SDA and SCL lines (to free the I2C bus for the
winnin g mas ter) , gen erat e an inte rrupt reque st ( IRI2C lin e)
and load the value 38H into the status register (S1STA). If
the ass er t a ck no wle dge bit o f th e control r egister i s “1 ” , th e
CB_I2C interface can recognize its own address and gen-
erate an acknowledge in the same I2C bus cycle.
It means , in case of two m asters (called MA and MB) gen-
erating at the same time, the START condition and the
slave address; if MA is calling MB and MB loses the arbitra-
tion, MB will gene rate a START condition, se nd the slave
address, (lose the arbitration), switch into the slave mode,
recogniz e its own slave addre ss and generate an ackno wl-
edge (if S1CON.AA = 1) in the same I2C bus cycle (during
the 9 SCL clock cycles).
For each data byte to send the sequence will be as follows:
• write the data byte into the CB_I2C data register
(S1DAT),
• clear the interrupt request flag (S1CON.SI),
CB_I2C sends data byte...
CB_I2C re lease s the SDA line and generate s the nin th
SCL pulse...
the receiver generates the acknowledge...
CB_I2C generates an interrupt request (IRI2C)...
• read the status register,
• write the next data byte into the data register,
• clear the interrupt flag, etc...
The last data byte transfer will be:
• write the data byte into the CB_I2C data register
(S1DAT),
• clear the interrupt request flag (S1CON.SI),
CB_I2C sends data byte...
CB_I2C re lease s the SDA line and generate s the nin th
SCL pulse...
the receiver generates the acknowledge...
CB_I2C generates an interrupt request (IRI2C)...
• read the status register,
• clear the interrupt request bit (S1CON.SI), set the stop
bit (S1CON.STO),
CB_I2C generates the STOP condition...
Once the STOP condition is detected on the I2C bus,
the stop bit is cleared...
Master Recei ver Mode
Before s tarting the M aster/Receiv er mode, S1 CON.ENS 1
must be “1”. To start a transfer in Master/Receiver mode,
set S1CON.STA to “1” (during the same write cycle of
S1CON, ENS1 must stay “1”, CR2-CR1-CR0 can be used
to select the output baud rate, and AA could be changed). If
AA is set to “1”, in case of a loss of arbitration during the
slave address transfer (and direction bit) onto the I2C bus,
the CB_I2 C will b e a bl e t o r ec og nize its own s lave add re ss
(or a general call) and generate an acknowledge during the
same I2C bus cy cle.
Once S1CON.STA is set to “1”, the CB_I2C will test the I2C
bus and generate a START condition as soon as the bus is
free. When the START cond ition is rec ognized on the I2C
bus, the interrupt request line (IRI2C) goes high and the
status regist er (S1S TA) loads the appro priat e value ( 08H).
The SI flag (in the control register, S1CON) is also set to
stop the CB_I2C. At this time (in response to the interrupt
request), the controller/sequencer which drives the CB_I2C
interface should perform the following actions:
CB_I2C
16
• load the slave address into the data register (S1DAT).
• reset the SI flag (from the control register, S1CON).
Notes
• In the Master/Receiver mode the LSB of the data byte
loaded into the data register is “1” (slave address).
• The first I2C bus cycle (transfer of the slave addres s an d
direction bit, and bus arbitration) is as in the
Master/Transmitter mode.
Then before receiving any data byte, the assert acknowl-
edge bit of the control register should be set to “1” to
acknow ledge the rece ived da ta byte. I f for any reas on, th e
transfer has to be suspended, or before receivi ng the last
data byte, the assert acknowledge bit of the control register
(S1CON.AA) must be reset to “0” in order for the CB_I 2C
interfac e not to generate an ackn owledge at the end of the
next I2C bus cycle . Then the s top bit of th e contro l regist er
should be se t, for the CB_I2C operati ng in master mod e to
generate the STOP condition.
The as sert ackno wledge bit sho uld be rese t at the begin-
ning of the last data byte transfer. By returning no acknowl-
edge, the r eceiver informs the transmitter that the c urrent
data byte is the last one.
The data bytes transfer cycles are as follows:
• clear the interrupt request flag (S1CON.SI),
CB_I2C receives data byte...
CB_I2C generates the ninth SCL pulse and the
acknowledge...
CB_I2C generates an interrupt request (IRI2C)...
• read the status regist er,
• read the received data byte from the data register,
• clear the interrupt flag, etc...
The last data byte transfer will be:
• clear the interrupt request flag (S1CON.SI), clear the
assert acknowledge bit of the control register
(S1CON.AA),
CB_I2C receives data byte...
CB_I2C generates the ninth SCL pulse not the
acknowledge...
CB_I2C generates an interrupt request (IRI2C)...
• read the status regist er,
• read the received data byte from the data register,
• clear the interrupt flag, set the stop bit of the control
register (S1CON.STO),
CB_I2C generates the STOP condition...
Once the STOP condition is detected on the I2C bus,
the stop bit is cleared...
Slave Receiver Mode
As for th e other mo des, be fore star ting the S lave/Re ceiver
mode, S1CON.ENS1 must be “1”. In order for the CB_I2C
interface to rec ognize its own sla ve address (or a genera l
call), the assert acknowledg e bit of the control register
(S1CON.AA) must be set (S1CON.AA = 1). In the slave
mode, the valu es of the B R3-BR2 -BR1-B R0 li nes does not
affec t the tran sfer baud r ate; the CB _I2C adap ts its inpu t
baud rate to the master baud rate.
Once the own slave address has been recognized, an
interrupt request is generated (IRI2C line goes high), the
status register loads the appropriate value, and the inter-
rupt flag of the control register (S1CON.SI) is set to “1”. The
CB_I2C will pull low the SDA line until the interrupt flag
(S1CON.SI) is reset.
Once S1CON.SI is reset, the SDA line is released and the
interrupt request line goes back low. While resetting the
S1CON.SI flag, the assert acknowledge bit (S1CON.AA)
could be set (or reset) in order for the CB_I2C interface to
generate (or not) an acknowledge after the next data byte
is received. S1CON.AA can be set (or reset) during a data
byte transfer to stop a transmission and isolate the CB_I2C
interfac e from the I2C bus. In su ch a ca se, the c urrent da ta
byte transfer will continue until the end, no acknowledge
will be returned, and the bus master will generate the
STOP condition. An interrupt request is generated (and has
to be treated) after the following events:
• own slave address received while S1CON.AA = 1
(acknowledge retur ned)
• generate call address received while S1CON.AA = 1 and
S1ADR.GC = 1 (acknowledge returned)
• arbitration lost in master mode, own slave address
received while S1CON.AA = 1 (acknowledge returned)
• arbitration lost in master mode, general call address
received while S1CON.AA = 1 and S1ADR.GC = 1
(acknowledge retur n ed)
• a data byte has been received while being in
Slave/receiver mode, acknowledge returned (or no
acknowledge returned)
• a STOP or rep eate d START condition has bee n re ce ived
while being in slave mode (Slave/Receiver or
Slave/Transmitter).
CB_I2C
17
Slave Transmitter Mode
As for the othe r mod es , be for e st a rting the Sl av e/Tran sm it-
ter mode, S1CON.ENS1 must be “1”. In order for the
CB_I2C interface to recognize its own slave address (or a
general cal l), the ass er t a ckno w le dge b it of the c on trol r eg-
ister (S1CON.AA) must be set (S1C ON.AA = 1). In th e
slave mode, the values of the BR3-BR2-BR1-BR0 lines
does not affect the transfer baud rate; the CB_I2C adapt its
input baud rate to the master baud rate.
Once the own slave address has been recognized, an
interrupt request is generated (IRI2C line goes high), the
status register loads the ap propriat e value, a nd the inter-
rupt flag of the control register (S1CON.SI) is set to “1”. The
CB_I2C will pull low the SDA line until the interrupt flag
(S1CON.SI) is reset.
Once S1CON.SI is reset, the SDA line is released and the
interrupt request line goes back low. While resetting the
S1CON.SI flag, the assert acknowledge bit (S1CON.AA)
could be set (or reset). S1CON.AA can also be set (or
reset) during a data byte transfer to stop a transmission
and is olate t he CB_I2 C inter face from the I2C bus. In such
a case, the c urrent data b yte tran sfer will continue until the
end, the st atus re gis te r will lo ad the value C8H ( and gener -
ate an interrupt request) and ignore the master receiver; no
more data byte will be transmitted. It means the master
receiver will continue reading “1” (as data) from the I2C bus
(“1” is the “default” va lue of the I 2C bus, and the acknowl-
edge is generated by the receiver).
An interrupt request is generated (and has to be treated)
after the following events:
• own slave address received while S1CON.AA = 1
(ac knowledge returned)
• generate call address received while S1CON.AA = 1 and
S1ADR.GC = 1 (acknowledge returned)
• arbitration lost in master mode, own slave address
received while S1CON.AA = 1 (acknowledge returned)
• arbitration lost in master mode, general call address
received while S1CON.AA = 1 and S1ADR.GC = 1
(ac knowledge returned)
• a data byte has been transmitted while being in
Slave/Transmitter mode, acknowledge received (or no
acknowledge received)
• the last data byte has been transmitted while being in
Slave/Transmitter mode, acknowledge received (or no
acknowledge received).
Bus Error
A bus error is detected when a START or a STOP condition
occurs at an illegal position in the I2C tr ansf er c ycle. I n such
a case, the CB_I2C interface generates an interrupt
reques t (IRI2C line) , loads the st atus re giste r with 00H and
releases the SDA and SCL lines.
To recove r from a bus error, i t is recommended to set the
S1CON.STO (STOP bit of the co ntrol register) to “1”, an d
to reset the interrupt flag (S1CON.SI). then the CB_I2C
inter face will not gener ate any S TOP condi tion (bec ause a
bus error has been detected), but it will act as if a STOP
condition has been produced; It will reset the STOP bit and
enter a defined state.
If a superfluous START condition is generated or a STOP
condition is masked, the I2C bus can stay “busy” indefi-
nitely. To exit from the “bus busy” state, set the STOP bit.
The CB_I2C will not generate any STOP condition but will
behave as if a STOP condition was received, then it will
clear the STOP bit, exit from the “bus busy” state, and will
be able to generate a START condition.
