LP38851
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SNVS492C –JUNE 2007–REVISED APRIL 2013
LP38851 800 mA Fast-Response High-Accuracy Adjustable LDO Linear Regulator with
Enable and Soft-Start
Check for Samples: LP38851
1FEATURES DESCRIPTION
The LP38851-ADJ is a high current, fast response
2• Adjustable VOUT Range of 0.80V to 1.8V regulator which can maintain output voltage
• Wide VBIAS Supply Operating Range of 3.0V to regulation with extremely low input to output voltage
5.5V drop. Fabricated on a CMOS process, the device
• Stable with 10µF Ceramic Capacitors operates from two input voltages: VBIAS provides
voltage to drive the gate of the N-MOS power
• Dropout Voltage of 115 mV (Typical) at 800 mA transistor, while VIN is the input voltage which
Load Current supplies power to the load. The use of an external
• Precision VADJ across All Line and Load bias rail allows the part to operate from ultra low VIN
Conditions: voltages. Unlike bipolar regulators, the CMOS
architecture consumes extremely low quiescent
– ±1.5% VADJ for TJ= 25°C current at any output load current. The use of an N-
– ±2.0% VADJ for 0°C ≤TJ≤+125°C MOS power transistor results in wide bandwidth, yet
– ±3.0% VADJ for -40°C ≤TJ≤+125°C minimum external capacitance is required to maintain
• Over-Temperature and Over-Current loop stability.
Protection The fast transient response of this device makes it
• Available in 8-Lead SO PowerPad, suitable for use in powering DSP, Microcontroller
7-Lead SFM and 7-Lead PFM Packages Core voltages and Switch Mode Power Supply post
regulators. The part is available in PSOP 8–pin, SFM
•−40°C to +125°C Operating Junction 7–pin, and TO-263 7-pin packages.
Temperature Range •Dropout Voltage: 115 mV (typical) at 800 mA
load current
APPLICATIONS •Low Ground Pin Current: 10 mA (typical) at 800
• ASIC Power Supplies in: mA load current
– Desktops, Notebooks, and Graphics Cards, •Soft-Start: Programmable Soft-Start time
Servers •Precision ADJ Voltage: ±1.5% for TJ= 25°C,
– Gaming Set Top Boxes, Printers and and ±2.0% for 0°C ≤TJ≤+125°C, across all line
Copiers and load conditions
• Server Core and I/O Supplies
• DSP and FPGA Power Supplies
• SMPS Post-Regulator
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TAB
IS
GND
LP38851T-ADJ
BIAS
OUT
GND
SS 1
2
3
4
5
IN
6
7
ADJ
EN
TAB
IS
GND
LP38851S-ADJ
BIAS
OUT
GND
SS 1
2
3
4
5
IN
6
7
ADJ
EN
DAP
Connect to GND
IN
EN
N/C
SS5
6
7
8
OUT
ADJ
GND
BIAS
1
2
3
4
IN
BIAS
GND
OUT VOUT
VIN
VBIAS
CIN
10 PF Ceramic
COUT
10 PF
Ceramic
CBIAS
1 PF
GND GND
LP38851-ADJ
ADJ
R1
R2
CFF
VEN
SS
CSS
EN
LP38851
SNVS492C –JUNE 2007–REVISED APRIL 2013
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TYPICAL APPLICATION CIRCUIT
Connection Diagram
Figure 3. 8-Lead SO PowerPad - Top View
Figure 1. 7-Lead PFM - Top View See DDA Package
See KTW0007B Package
Figure 2. 7-Lead SFM - Top View
See NDZ0007B Package
PIN DESCRIPTIONS
SFM PFM SO PowerPad Pin Pin Description
Pin # Pin # Pin # Symbol
Soft-Start capacitor connection. Used to control the rise time of
1 1 5 SS VOUT at turn-on.
2 2 6 EN Device Enable, High = On, Low = Off.
3 3 7 IN The unregulated voltage input
4 4 4 GND Ground
5 5 1 ADJ The feedback connection to set the output voltage
6 6 2 OUT The regulated output voltage
7 7 3 BIAS The supply for the internal control and reference circuitry.
- - 8 N/C No internal connection
The SFM and PFM TAB is a thermal and electrical connection that
is physically attached to the backside of the die, and used as a
TAB TAB - TAB thermal heat-sink connection. See APPLICATION INFORMATION
for details.
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PIN DESCRIPTIONS (continued)
SFM PFM SO PowerPad Pin Pin Description
Pin # Pin # Pin # Symbol
The SO PowerPad DAP is a thermal connection only that is
physically attached to the backside of the die, and used as a
- - DAP DAP thermal heat-sink connection. See APPLICATION INFORMATION
for details.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
Storage Temperature Range −65°C to +150°C
Lead Temperature Soldering, 5 seconds 260°C
ESD Rating Human Body Model (2) ±2 kV
Power Dissipation (3) Internally Limited
VIN Supply Voltage (Survival) −0.3V to +6.0V
VBIAS Supply Voltage (Survival) −0.3V to +6.0V
VSS SoftStart Voltage (Survival) −0.3V to +6.0V
VOUT Voltage (Survival) −0.3V to +6.0V
IOUT Current (Survival) Internally Limited
Junction Temperature −40°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For specifications and conditions, see the
Electrical Characteristics.
(2) The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Test method is per JESD22-A114.
(3) Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to
ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not
exceed the maximum operating rating. See APPLICATION INFORMATION for details.
OPERATING RATINGS (1)
VIN Supply Voltage (VOUT + VDO) to VBIAS
0.8V ≤VOUT ≤1.2V 3.0V to 5.5V
VBIAS Supply Voltage 1.2V < VOUT ≤1.8V 4.5V to 5.5V
VEN Voltage 0.0V to VBIAS
IOUT 0 mA to 800 mA
Junction Temperature Range (2) −40°C to +125°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For specifications and conditions, see the
Electrical Characteristics.
(2) Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to
ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not
exceed the maximum operating rating. See APPLICATION INFORMATION for details.
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ELECTRICAL CHARACTERISTICS
Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF,
CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the junction
temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes
only.
Symbol Parameter Conditions Min Typ Max Units
VOUT(NOM)+1V ≤VIN ≤VBIAS ≤4.5V (1) 492.5 507.5
3.0V ≤VBIAS ≤5.5V, 500.
485.0 515.0
10 mA ≤IOUT ≤800 mA
VADJ VADJ Accuracy mV
VOUT(NOM)+1V ≤VIN ≤VBIAS ≤4.5V (1)
3.0V ≤VBIAS ≤5.5V, 490.0 500. 510.0
10 mA ≤IOUT ≤800 mA,
0°C ≤TJ≤+125°C
3.0V ≤VBIAS ≤5.5V 0.80 1.20
VOUT VOUT Range V
4.5V ≤VBIAS ≤5.5V 0.80 1.80
ΔVOUT/ΔVIN Line Regulation, VIN(2) VOUT(NOM)+1V ≤VIN ≤VBIAS - 0.04 - %/V
ΔVOUT/ΔVBIAS Line Regulation, VBIAS(2) 3.0V ≤VBIAS ≤5.5V - 0.10 - %/V
ΔVOUT/ΔIOUT Output Voltage Load Regulation (3) 10 mA ≤IOUT ≤800 mA - 0.2 - %/A
150
VDO Dropout Voltage (4) IOUT = 800 mA - 115 mV
200
VOUT = 0.80V 8.5
VBIAS = 3.0V - 7.0 mA
9.0
Quiescent Current Drawn from VIN 10 mA ≤IOUT ≤800 mA
IGND(IN) Supply 100
VEN ≤0.5V 1 μA
300
3.8
10 mA ≤IOUT ≤800 mA - 3.0 mA
4.5
Quiescent Current Drawn from
IGND(BIAS) VBIAS Supply 170
VEN ≤0.5V 100 μA
200
2.20 2.70
UVLO Under-Voltage Lock-Out Threshold VBIAS rising until device is functional 2.45 V
2.00 2.90
VBIAS falling from UVLO threshold until 60 300
UVLO(HYS) Under-Voltage Lock-Out Hysteresis 150 mV
device is non-functional 50 350
VIN = VOUT(NOM) + 1V,
ISC Output Short-Circuit Current - 2.3 - A
VBIAS = 3.0V, VOUT = 0.0V
Soft-Start
rSS Soft-Start internal resistance 11.0 14.0 17.0 kΩ
Soft-Start time
tSS CSS = 10 nF - 700 - μs
tSS = CSS × rSS × 5
Enable
VEN = VBIAS - 0.01 -
IEN ENABLE pin Current μA
-24 -43
VEN = 0.0V, VBIAS = 5.5V -35
-21 -50
1.00 1.50
VEN(ON) Enable Voltage Threshold VEN rising until Output = ON 1.25 V
0.90 1.55
VEN falling from VEN(ON) until Output = 50 150
VEN(HYS) Enable Voltage Hysteresis 100 mV
OFF 30 200
tOFF Turn-OFF Delay Time RLOAD x COUT << tOFF - 20 - µs
tON Turn-ON Delay Time RLOAD x COUT << tON - 15 -
AC Parameters
(1) VIN cannot exceed either VBIAS or 4.5V, whichever value is lower.
(2) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
(3) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load
to full load.
(4) Dropout voltage is defined as the input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the
output voltage to drop 2% from the nominal value.
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF,
CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the junction
temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes
only.
Symbol Parameter Conditions Min Typ Max Units
VIN = VOUT(NOM) + 1V, - 72 -
f = 120 Hz
PSRR Ripple Rejection for VIN Input
(VIN) Voltage VIN = VOUT(NOM) + 1V, - 61 -
f = 1 kHz dB
VBIAS = VOUT(NOM) + 3V, - 54 -
f = 120 Hz
PSRR Ripple Rejection for VBIAS Voltage
(VBIAS)VBIAS = VOUT(NOM) + 3V, - 53 -
f = 1 kHz
Output Noise Density f = 120 Hz - 1 - µV/√Hz
enBW = 10 Hz −100 kHz - 150 -
Output Noise Voltage µVRMS
BW = 300 Hz −300 kHz - 90 -
Thermal Parameters
Thermal Shutdown Junction
TSD - 160 -
Temperature °C
TSD(HYS) Thermal Shutdown Hysteresis - 10 -
SFM - 60 -
Thermal Resistance, Junction to
θJ-A PFM - 60 -
Ambient(5) SO PowerPad - 168 - °C/W
SFM - 3 -
Thermal Resistance, Junction to
θJ-C PFM - 3 -
Case(5)(6) SO PowerPad - 11 -
(5) Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to
ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not
exceed the maximum operating rating. See APPLICATION INFORMATION for details.
(6) For SFM and PFM: θJ-C refers to the BOTTOM surface of the package, under the epoxy body, as the 'CASE'. For SO PowerPad: θJ-C
refers to the DAP (aka: Exposed Pad) on BOTTOM surface of the package as the 'CASE'.
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TYPICAL PERFORMANCE CHARACTERISTICS
Refer to the TYPICAL APPLICATION CIRCUIT. Unless otherwise specified: TJ= 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ,
CFF= 180 pF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic,
CBIAS = 1 µF Ceramic, , CSS = Open.
VBIAS Ground Pin Current (IGND(BIAS)) VBIAS Ground Pin Current (IGND(BIAS))
vs vs
VBIAS Temperature
Figure 4. Figure .
VIN Ground Pin Current Load Regulation
vs vs
Temperature Temperature
Figure 5. Figure 6.
Dropout Voltage (VDO) Output Current Limit (ISC)
vs vs
Temperature Temperature
Figure 7. Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Refer to the TYPICAL APPLICATION CIRCUIT. Unless otherwise specified: TJ= 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ,
CFF= 180 pF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic,
CBIAS = 1 µF Ceramic, , CSS = Open.
VOUT VOUT
vs vs
Temperature VIN
Figure 9. Figure 10.
UVLO Thresholds Soft-Start rSS Variation
vs vs
Temperature Temperature
Figure 11. Figure 12.
VOUT Enable Thresholds (VEN)
vs vs
CSS, 10 nF to 47 nF Temperature
Figure 13. Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Refer to the TYPICAL APPLICATION CIRCUIT. Unless otherwise specified: TJ= 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ,
CFF= 180 pF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic,
CBIAS = 1 µF Ceramic, , CSS = Open.
Enable Pull-Down Current (IEN) Enable Pull-Up Resistor (rEN)
vs vs
Temperature Temperature
Figure 15. Figure 16.
VIN Line Transient Response VIN Line Transient Response
Figure 17. Figure 18.
VBIAS Line Transient Response VBIAS Line Transient Response
Figure 19. Figure 20.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Refer to the TYPICAL APPLICATION CIRCUIT. Unless otherwise specified: TJ= 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ,
CFF= 180 pF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic,
CBIAS = 1 µF Ceramic, , CSS = Open.
Load Transient Response, COUT = 10 µF Ceramic Load Transient Response, COUT = 10 µF Ceramic
Figure 21. Figure 22.
Load Transient Response, COUT = 47 µF Ceramic Load Transient Response, COUT = 47 µF Ceramic
Figure 23. Figure 24.
Load Transient Response, COUT = 68 µF Tantalum Load Transient Response, COUT = 68 µF Tantalum
Figure 25. Figure 26.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Refer to the TYPICAL APPLICATION CIRCUIT. Unless otherwise specified: TJ= 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ,
CFF= 180 pF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic,
CBIAS = 1 µF Ceramic, , CSS = Open.
VBIAS PSRR VIN PSRR
Figure 27. Figure 28.
Output Noise
Figure 29.
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GND
OUT
IN
BIAS
EN
Under-Voltage
Lock-Out
Thermal
Shut Down
1.2V
Enable
VREF
0.5V
ILIMIT
ADJ
rSS
rEN
SS
LP38851-ADJ
LP38851
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SNVS492C –JUNE 2007–REVISED APRIL 2013
BLOCK DIAGRAM
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APPLICATION INFORMATION
EXTERNAL CAPACITORS
To assure regulator stability, input and output capacitors are required as shown in TYPICAL APPLICATION
CIRCUIT.
Output Capacitor
A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can
be increased without limit. The output capacitor must be located less than 1 cm from the output pin of the IC and
returned to the device ground pin with a clean analog ground.
Only high quality ceramic types such as X5R or X7R should be used, as the Z5U and Y5F types do not provide
sufficient capacitance over temperature.
Tantalum capacitors will also provide stable operation across the entire operating temperature range. However,
the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum
recommended 10 µF ceramic capacitor at the output will allow unlimited capacitance, Tantalum and/or
Aluminum, to be added in parallel.
Input Capacitor
The input capacitor must be at least 10 µF, but can be increased without limit. It's purpose is to provide a low
source impedance for the regulator input. A ceramic capacitor, X5R or X7R, is recommended.
Tantalum capacitors may also be used at the input pin. There is no specific ESR limitation on the input capacitor
(the lower, the better).
Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at
cold temperatures. They are not recommended for any application where the ambient temperature falls below
0°C.
Bias Capacitor
The capacitor on the bias pin must be at least 1 µF, and can be any good quality capacitor (ceramic is
recommended).
Feed Forward Capacitor, CFF
(Refer to TYPICAL APPLICATION CIRCUIT)
When using a ceramic capacitor for COUT, the typical ESR value will be too small to provide any meaningful
positive phase compensation, FZ, to offset the internal negative phase shifts in the gain loop.
FZ= 1 / (2 x πx COUT x ESR) (1)
A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient
response of the device. This capacitor, CFF, in parallel with R1, will form a zero in the loop response given by the
formula:
FZ= 1 / (2 x πx CFF x R1) (2)
For optimum load transient response select CFF so the zero frequency, FZ, falls between 500 kHz and 750 kHz.
CFF = 1 / (2 x πx R1 x FZ) (3)
The phase lead provided by CFF diminishes as the DC gain approaches unity, or VOUT approaches VADJ. This is
because CFF also forms a pole with a frequency of:
FP= 1 / (2 x πx CFF x (R1 || R2) ) (4)
It's important to note that at higher output voltages, where R1 is much larger than R2, the pole and zero are far
apart in frequency. At lower output voltages the frequency of the pole and the zero mover closer together. The
phase lead provided from CFF diminishes quickly as the output voltage is reduced, and has no effect when VOUT
= VADJ. For this reason, relying on this compensation technique alone is adequate only for higher output
voltages. For the LP38851, the practical minimum VOUT is 0.8V when a ceramic capacitor is used for COUT.
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+R2
R1
1x= VV ADJOUT ¸
¹
·
¨
©
§¸
©
§
¨ ¨
¹
·
LP38851
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SNVS492C –JUNE 2007–REVISED APRIL 2013
Figure 30. FZERO and FPOLE vs Gain
SETTING THE OUTPUT VOLTAGE
(Refer to TYPICAL APPLICATION CIRCUIT)
The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the
formula:
(5)
The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature
coefficients. It is important to remember that, although the value of VADJ is specified, the use of low quality
resistors for R1 and R2 can easily produce a VOUT value that is unacceptable.
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ.
This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZpole set by R1 and
CFF.( (R1 x R2) / (R1 + R2) ) ≤10 kΩ(6)
Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%
capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will give
similar results.
Table 1.
VOUT R1 R2 CFF FZ
0.8V 1.07 kΩ1.78 kΩ220 pF 676 kHz
0.9V 1.50 kΩ1.87 kΩ180 pF 589 kHz
1.00V 1.00 kΩ1.00 kΩ270 pF 589 kHz
1.1V 1.65 kΩ1.37 kΩ150 pF 643 kHz
1.2V 1.40 kΩ1.00 kΩ180 pF 631 kHz
1.3V 1.15 kΩ715 Ω220 pF 629 kHz
1.4V 1.07 kΩ590 Ω220 pF 676 kHz
1.5V 2.00 kΩ1.00 kΩ120pF 663 kHz
1.6V 1.65 kΩ750 Ω150 pF 643 kHz
1.7V 2.55 kΩ1.07 kΩ100 pF 624 kHz
1.8V 2.94 kΩ1.13 kΩ82 pF 660 kHz
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Please refer to Application Note AN-1378 (SNVA112) for additional information on how resistor tolerances affect
the calculated VOUT value.
INPUT VOLTAGE
The input voltage (VIN) is the high current external voltage rail that will be regulated down to a lower voltage,
which is applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever value is
used for VBIAS.
For applications where VBIAS is higher than 4.5V, VIN must be no greater than 4.5V, otherwise output voltage
accuracy may be affected.
BIAS VOLTAGE
The bias voltage (VBIAS) is a low current external voltage rail required to bias the control circuitry and provide
gate drive for the N-FET pass transistor. When VOUT is set to 1.20V, or less, VBIAS may be anywhere in the
operating range of 3.0V to 5.5V. If VOUT is set higher than 1.20V , VBIAS must be between 4.5V and 5.5V to
ensure proper operation of the device.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is
below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V.
As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is
approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.
When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the
device will be functional, but the operating parameters will not be within the specified limits.
SUPPLY SEQUENCING
There is no requirement for the order that VIN or VBIAS are applied or removed.
One practical limitation is that the Soft-Start circuit starts charging CSS when both VBIAS rises above the UVLO
threshold and the Enable pin is above the VEN(ON) threshold. If the application of VIN is delayed beyond this point
the benefits of Soft-Start will be compromised.
In any case, the output voltage cannot be specified until both VIN and VBIAS are within the range of specified
operating values.
If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin
must be diode clamped to ground. A Schottky diode is recommended for this diode clamp.
REVERSE VOLTAGE
A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.
Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that
the input to output voltage becomes reversed.
The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass
element is not driven, there will not be any reverse current flow through the pass element during a reverse
voltage event. The gate of the pass element is not driven when VBIAS is below the UVLO threshold, or when the
Enable pin is held low.
When VBIAS is above the UVLO threshold, and the Enable pin is above the VEN(ON) threshold, the control circuitry
is active and will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the
control circuit will drive the gate of the pass element to the full VBIAS potential when the output voltage begins to
fall. In this condition, reverse current will flow from the output pin to the input pin , limited only by the RDS(ON) of
the pass element and the output to input voltage differential. Discharging an output capacitor up 1000 µF in this
manner will not damage the device as the current will rapidly decay. However, continuous reverse current should
be avoided.
14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LP38851
LP38851
www.ti.com
SNVS492C –JUNE 2007–REVISED APRIL 2013
SOFT-START
The LP38851 incorporates a Soft-Start function that reduces the start-up current surge into the output capacitor
(COUT) by allowing VOUT to rise slowly to the final value. This is accomplished by controlling VREF at the SS pin.
The soft-start timing capacitor (CSS) is internally held to ground until both VBIAS rises above the Under-Voltage
Lock-Out threshold (ULVO) and the Enable pin is higher than the VEN(ON) threshold.
VREF will rise at an RC rate defined by the internal resistance of the SS pin (rSS), and the external capacitor
connected to the SS pin. This allows the output voltage to rise in a controlled manner until steady-state
regulation is achieved. Typically, five time constants are recommended to assure that the output voltage is
sufficiently close to the final steady-state value. During the soft-start time the output current can rise to the built-in
current limit.
Soft-Start Time = CSS × rSS × 5 (7)
Since the VOUT rise will be exponential, not linear, the in-rush current will peak during the first time constant (τ),
and VOUT will require four additional time constants (4τ) to reach the final value (5τ) .
After achieving normal operation, should either VBIAS fall below the ULVO threshold, or the Enable pin fall below
the VEN(OFF) threshold, the device output will be disabled and the Soft-Start capacitor (CSS) discharge circuit will
become active. The CSS discharge circuit will remain active until VBIAS falls to 500 mV (typical). When VBIAS falls
below 500 mV (typical), the CSS discharge circuit will cease to function due to a lack of sufficient biasing to the
control circuitry.
Since VREF appears on the SS pin, any leakage through CSS will cause VREF to fall, and thus affect VOUT. A
leakage of 50 nA (about 10 MΩ) through CSS will cause VOUT to be approximately 0.1% lower than nominal, while
a leakage of 500 nA (about 1 MΩ) will cause VOUT to be approximately 1% lower than nominal. Typical ceramic
capacitors will have a factor of 10X difference in leakage between 25°C and 85°C, so the maximum ambient
temperature must be included in the capacitor selection process.
Typical CSS values will be in the range of 1 nF to 100 nF, providing typical Soft-Start times in the range of 70 μs
to 7 ms (5τ). Values less than 1 nF can be used, but the Soft-Start effect will be minimal. Values larger than 100
nF will provide soft-start, but may not be fully discharged if VBIAS falls from the UVLVO threshold to less than 500
mV in less than 100 µs.
Figure 31 shows the relationship between the COUT value and a typical CSS value.
Figure 31. Typical CSS vs COUT Values
The CSS capacitor must be connected to a clean ground path back to the device ground pin. No components,
other than CSS, should be connected to the SS pin, as there could be adverse effects to VOUT.
If the Soft-Start function is not needed the SS pin should be left open, although some minimal capacitance value
is always recommended.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LP38851
D
J
JA P
T
T'
d
A(MAX)J(MAX)J T-T
'=
LP38851
SNVS492C –JUNE 2007–REVISED APRIL 2013
www.ti.com
ENABLE OPERATION
The Enable pin (EN) provides a mechanism to enable, or disable, the regulator output stage. The Enable pin has
an internal pull-up, through a typical 160 kΩresistor, to VBIAS.
If the Enable pin is actively driven, pulling the Enable pin above the VEN threshold of 1.25V (typical) will turn the
regulator output on, while pulling the Enable pin below the VEN threshold will turn the regulator output off. There
is approximately 100 mV of hysteresis built into the Enable threshold provide noise immunity.
If the Enable function is not needed this pin should be left open, or connected directly to VBIAS. If the Enable pin
is left open, stray capacitance on this pin must be minimized, otherwise the output turn-on will be delayed while
the stray capacitance is charged through the internal resistance (rEN).
POWER DISSIPATION AND HEAT-SINKING
Additional copper area for heat-sinking may be required depending on the maximum device dissipation (PD) and
the maximum anticipated ambient temperature (TA) for the device. Under all possible conditions, the junction
temperature must be within the range specified under operating conditions.
The total power dissipation of the device is the sum of three different points of dissipation in the device.
The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula:
PD(PASS) = (VIN - VOUT) × IOUT (8)
The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the
formula:
PD(BIAS) = VBIAS × IGND(BIAS)
where
• IGND(BIAS) is the portion of the operating ground current of the device that is related to VBIAS (9)
The third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with
the formula:
PD(IN) = VIN × IGND(IN)
where
• IGND(IN) is the portion of the operating ground current of the device that is related to VIN (10)
The total power dissipation is then:
PD= PD(PASS) + PD(BIAS) + PD(IN) (11)
The maximum allowable junction temperature rise (ΔTJ) depends on the maximum anticipated ambient
temperature (TA) for the application, and the maximum allowable operating junction temperature (TJ(MAX)) .
(12)
The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the
formula:
(13)
Heat-Sinking The SFM Package
The SFM package has a θJA rating of 60°C/W and a θJC rating of 3°C/W. These ratings are for the package only,
no additional heat-sinking, and with no airflow. If the needed θJA, as calculated above, is greater than or equal to
60°C/W then no additional heat-sinking is required since the package can safely dissipate the heat and not
exceed the operating TJ(MAX). If the needed θJA is less than 60°C/W then additional heat-sinking is needed.
The thermal resistance of a SFM package can be reduced by attaching it to a heat sink or a copper plane on a
PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for PFM
package.
The heat-sink to be used in the application should have a heat-sink to ambient thermal resistance, θHA:
θHA ≤ θJA - (θCH +θJC)
16 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LP38851
LP38851
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SNVS492C –JUNE 2007–REVISED APRIL 2013
where
•θJA is the required total thermal resistance from the junction to the ambient air, θCH is the thermal resistance
from the case to the surface of the heart-sink
•θJC is the thermal resistance from the junction to the surface of the case (14)
For this equation, θJC is about 3°C/W for a SFM package. The value for θCH depends on method of attachment,
insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. Consult the heat-sink manufacturer datasheet for details
and recommendations.
Heat-Sinking The PFM Package
The PFM package has a θJA rating of 60°C/W, and a θJC rating of 3°C/W. These ratings are for the package only,
no additional heat-sinking, and with no airflow.
The PFM package uses the copper plane on the PCB as a heat-sink. The tab of this package is soldered to the
copper plane for heat sinking. Figure 32 shows a curve for the θJA of PFM package for different copper area
sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat-sinking.
Figure 32. θJA vs Copper (1 Ounce) Area for the PFM package
Figure 32 shows that increasing the copper area beyond 1 square inch produces very little improvement. The
minimum value for θJA for the PFM package mounted to a PCB is 32°C/W.
Figure 33. Maximum Power Dissipation vs Ambient Temperature for the PFM Package
Figure 33 shows the maximum allowable power dissipation for PFM packages for different ambient temperatures,
assuming θJA is 35°C/W and the maximum junction temperature is 125°C.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LP38851
LP38851
SNVS492C –JUNE 2007–REVISED APRIL 2013
www.ti.com
Heat-Sinking The SO PowerPad Package
The LP38851MR package has a θJA rating of 168°C/W, and a θJC rating of 11°C/W. The θJA rating of 168°C/W
includes the device DAP soldered to an area of 0.008 square inches (0.09 in x 0.09 in) of 1 ounce copper, with
no airflow.
Figure 34. θJA vs Copper (1 Ounce) Area for the SO PowerPad Package
Increasing the copper area soldered to the DAP to 1 square inch of 1 ounce copper, using a dog-bone type
layout, will improve the θJA rating to 98°C/W. Figure 34 shows that increasing the copper area beyond 1 square
inch produces very little improvement.
Figure 35. Maximum Power Dissipation vs Ambient Temperature for the SO PowerPad Package
Figure 35 shows the maximum allowable power dissipation for the SO PowerPad package for a range of ambient
temperatures, assuming θJA is 98°C/W and the maximum junction temperature is 125°C.
18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LP38851
LP38851
www.ti.com
SNVS492C –JUNE 2007–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 18
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LP38851
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP38851MR-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 95 RoHS & Green SN Level-3-260C-168 HR -40 to 125 L38851
MRADJ
LP38851MRX-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 L38851
MRADJ
LP38851S-ADJ/NOPB ACTIVE DDPAK/
TO-263 KTW 7 45 RoHS-Exempt
& Green SN Level-3-245C-168 HR -40 to 125 LP38851S
-ADJ
LP38851SX-ADJ/NOPB ACTIVE DDPAK/
TO-263 KTW 7 500 RoHS-Exempt
& Green SN Level-3-245C-168 HR -40 to 125 LP38851S
-ADJ
LP38851T-ADJ/NOPB ACTIVE TO-220 NDZ 7 45 RoHS & Green SN Level-1-NA-UNLIM -40 to 125 LP38851T
-ADJ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP38851MRX-ADJ/NOPB SO
Power
PAD
DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LP38851SX-ADJ/NOPB DDPAK/
TO-263 KTW 7 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP38851MRX-ADJ/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0
LP38851SX-ADJ/NOPB DDPAK/TO-263 KTW 7 500 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
MECHANICAL DATA
KTW0007B
www.ti.com
BOTTOM SIDE OF PACKAGE
TS7B (Rev E)
www.ti.com
PACKAGE OUTLINE
C
TYP
6.2
5.8
1.7 MAX
6X 1.27
8X 0.51
0.31
2X
3.81
TYP
0.25
0.10
0 - 8
0.15
0.00
2.34
2.24
2.34
2.24
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
5.0
4.8
B4.0
3.8
4218825/A 05/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008A
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
PowerPAD is a trademark of Texas Instruments.
TM
18
0.25 C A B
5
4
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.400
EXPOSED
THERMAL PAD
4
1
5
8
www.ti.com
EXAMPLE BOARD LAYOUT
(5.4)
(1.3) TYP
( ) TYP
VIA
0.2
(R ) TYP0.05
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
8X (1.55)
8X (0.6)
6X (1.27)
(2.95)
NOTE 9
(4.9)
NOTE 9
(2.34)
(2.34)
SOLDER MASK
OPENING
(1.3)
TYP
4218825/A 05/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008A
PLASTIC SMALL OUTLINE
SYMM
SYMM
SEE DETAILS
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
SOLDER MASK
OPENING
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
TM
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(R ) TYP0.05
8X (1.55)
8X (0.6)
6X (1.27)
(5.4)
(2.34)
(2.34)
BASED ON
0.125 THICK
STENCIL
4218825/A 05/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008A
PLASTIC SMALL OUTLINE
1.98 X 1.980.175
2.14 X 2.140.150
2.34 X 2.34 (SHOWN)0.125
2.62 X 2.620.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
SYMM
SYMM
1
45
8
BASED ON
0.125 THICK
STENCIL
BY SOLDER MASK
METAL COVERED SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
MECHANICAL DATA
NDZ0007B
www.ti.com
TA07B (Rev E)
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