FDS8949-F085 Dual N-Channel Logic Level PowerTrench® MOSFET
©2010 Semiconductor Components Industries, LLC.
September-2017, Rev. 1
Publication Order Number:
FDS8949-F085/D
1
FDS8949-F085
Dual N-Channel Logic Level PowerTrench® MOSFET
40V, 6A, 29mΩ
Features
Max rDS(on) = 29mΩ at VGS = 10V
Max rDS(on) = 36mΩ at VGS = 4.5V
Low gate charge
High performance trench technology for extremely low
rDS(on)
High power and current handling capability
Qualified to AEC Q101
General Description
These N-Channel Logic Level MOSFETs are produced
using ON Semiconductor’s advanced
PowerTrench® process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
Applications
Inverter
Power suppliers
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDS Drain to Source Voltage 40 V
VGS Gate to Source Voltage ±20 V
ID
Drain Current -Continuous (Note 1a) 6 A
-Pulsed 20
EAS Drain-Source Avalanche Energy (Note 3) 26 mJ
PD
Power Dissipation for Dual Operation 2
W
Power Dissipation for Single Operation (Note 1a)
(Note 1b)
1.6
0.9
TJ, TSTG Operating and Storage Junction Temperature Range -55 to 150 °C
RθJA Thermal Resistance-Single operation, Junction to Ambient (Note 1a) 81
°C/WRθJA Thermal Resistance-Single operation, Junction to Ambient (Note 1b) 135
RθJC Thermal Resistance, Junction to Case (Note 1) 40
Device Marking Device Reel Size Tape Width Quantity
FDS8949 FDS8949-F085 13’’ 12mm 2500 units
Pin 1
SO-8
D1
D1
D2
D2
S2
S1
G1
G2
RoHS compliant
FDS8949-F085 Dual N-Channel Logic Level PowerTrench® MOSFET
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Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 40 V
∆BVDSS
∆TJ
Breakdown Voltage Temperature
Coefficient ID = 250µA, referenced to 25°C 33 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 32V, VGS = 0V 1µA
TJ = 55°C10 µA
IGSS Gate to Source Leakage Current VGS = ±20V,VDS = 0V ±100 nA
On Characteristics
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1 1.9 3 V
∆VGS(th)
∆TJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250µA, referenced to 25°C -4.6 mV/°C
rDS(on) Drain to Source On Resistance
VGS = 10V, ID = 6A 21 29
mΩVGS = 4.5V, ID = 4.5A 26 36
VGS = 10V, ID = 6A,TJ = 125°C 29 43
gFS Forward Transconductance VDS = 10V,ID = 6A 22 S
(Note 2)
Dynamic Characteristics
Ciss Input Capacitance VDS = 20V, VGS = 0V,
f = 1MHz
715 955 pF
Coss Output Capacitance 105 140 pF
Crss Reverse Transfer Capacitance 60 90 pF
RgGate Resistance f = 1MHz 1.1 Ω
Switching Characteristics
td(on) Turn-On Delay Time
VDD = 20V, ID = 1A
VGS = 10V, RGEN = 6Ω
918 ns
trRise Time 510 ns
td(off) Turn-Off Delay Time 23 37 ns
tfFall Time 3 6 ns
QgTotal Gate Charge
VDS = 20V, ID = 6A,VGS = 5V
7.7 11 nC
Qgs Gate to Source Gate Charge 2.4 nC
Qgd Gate to Drain “Miller”Charge 2.8 nC
Drain-Source Diode Characteristics
VSD Source to Drain Diode Forward Voltage VGS = 0V, IS = 6A (note 2) 0.8 1.2 V
trr Reverse Recovery Time (note 3) IF = 6A, diF/dt = 100A/µs17 26 ns
Qrr Reverse Recovery Charge 711 nC
and Maximum Ratings
Notes:
1: RθJA is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. RθJC is guaranteed by design while RθJA is determined by the user’s board design.
2: Pulse Test: Pulse Width < 300 us, Duty Cycle < 2.0%.
3: Starting TJ = 25°C, L = 1mH, IAS = 7.3A, VDD = 40V, VGS = 10V.
Scale 1:1 on letter size paper
a) 81°C/W when
mounted on a 1in2
pad of 2 oz copper
b) 135°C/W when mounted on a
minimum pad .
FDS8949-F085 Dual N-Channel Logic Level PowerTrench® MOSFET
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Typical Characteristics TJ = 25°C unless otherwise noted
Figure 1. On Region Characteristics
0.0 0.5 1.0 1.5 2.0 2.5
0
4
8
12
16
20
VGS = 10V
VGS = 3.0V
VGS = 4.5V
VGS = 3.5V
PULSE DURATION = 300µs
DUTY CYCLE = 20%MAX
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 2. Normalized
048121620
0.5
1.0
1.5
2.0
2.5
3.0
PULSE DURATION = 300µs
DUTY CYCLE = 20%MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT(A)
VGS = 10V
VGS = 4.5V
VGS = 3.0V
VGS = 3.5V
On-Resistance vs Drain
Current and Gate Voltage
Figure 3.
-50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
ID = 6A
VGS = 10V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)
Normalized On Resistance vs Junction
Temperature
Figure 4.
246810
10
20
30
40
50
60
70
PULSE DURATION = 300µs
DUTY CYCLE = 20%MAX
TJ = 125oC
TJ = 25oC
ID = 3.5A
rDS(on), DRAIN TO
SOURCE ON-RESISTANCE (mΩ)
VGS, GATE TO SOURCE VOLTAGE (V)
On-Resistance vs Gate to Source
Voltage
Figure 5. Transfer Characteristics
1.5 2.0 2.5 3.0 3.5 4.0
0
4
8
12
16
20
VDD = 10V
PULSE DURATION = 300µs
DUTY CYCLE = 20%MAX
TJ = -55oC
TJ = 25oC
TJ = 125oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.2 0.4 0.6 0.8 1.0 1.2
1E-3
0.01
0.1
1
10
100
TJ = -55oC
TJ = 25oC
TJ = 125oC
VGS = 0V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Source to Drain Diode Forward
Voltage vs Source Current
FDS8949-F085 Dual N-Channel Logic Level PowerTrench® MOSFET
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Figure 7.
0481216
0
2
4
6
8
10
VDD = 30V
VDD = 10V
VGS, GATE TO SOURCE VOLTAGE(V)
Qg, GATE CHARGE(nC)
VDD = 20V
Gate Charge Characteristics Figure 8.
0.1 1 10
101
102
103
f = 1MHz
VGS = 0V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
40
Capacitance vs Drain to Source Voltage
Figure 9.
10-3 10-2 10-1 100101102103
0.1
1
10
TJ = 25oC
TJ = 125oC
tAV, TIME IN AVALANCHE(ms)
IAS, AVALANCHE CURRENT(A)
Unclamped Inductive Switching
Capability
Figure 10.
25 50 75 100 125 150
0
1
2
3
4
5
6
7
RθJA = 81oC/W
ID, DRAIN CURRENT (A)
TA, Ambient TEMPERATURE (oC)
VGS = 4.5V
VGS = 10V
Maximum Continuous Drain Current vs
Ambient Temperature
Figure 11.
0.01 0.1 1 10 100
0.01
0.1
1
10
100
300
DC
10s
1s
100ms
10ms
1ms
100us
LIMITED BY
PACKAGE
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(on)
ID, DRAIN CURRENT (A)
VDS, DRAIN-SOURCE VOLTAGE (V)
Forward Bias Safe Operating Area Figure 12. Single Pulse Maximum Power
Dissipation
10-4 10-3 10-2 10-1 100101102103
1
10
100
0.7
VGS = 10V
SINGLE PULSE
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (s)
SINGLE PULSE
RθJA = 135°C/W
TA = 25°C
Typical Characteristics TJ = 25°C unless otherwise noted
FDS8949-F085 Dual N-Channel Logic Level PowerTrench® MOSFET
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Figure 13. Transient Thermal Response Curve
10-3 10-2 10-1 100101102103
1E-3
0.01
0.1
1
2DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZθJA
t, RECTANGULAR PULSE DURATION (s)
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
P
(PK)
t
1
t
2
R
θ
JA
(t) = r(t)*R
θ
JA
R
θ
JA
= 135
o
C/W T
J
-T
A
=P*R
θ
JA
DUTY FACTOR: D = t1/t2
Typical Characteristics TJ = 25°C unless otherwise noted
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