General Description
The MAX44267 precision, low-noise, low-drift dual opera-
tional amplifier offers true-zero output that allows the
output to cross zero maximizing the dynamic range of an
ADC and increasing resolution. In addition, the input com-
mon-mode range extends from +13.5V down to -12V. The
MAX44267 integrates charge-pump circuitry that gener-
ates the negative voltage rail in conjunction with external
capacitors. This allows the amplifier to operate from a
single +4.5V to +15V power supply, but it is as effective
as a normal dual-rail ±4.5V to ±15V amplifier. The archi-
tecture eliminates the need for a negative power-supply
rail, saving system cost and size.
The MAX44267 is unity-gain stable with a gain-bandwidth
product of 5MHz. The device features low offset voltage
of 50μV (max), drift of 0.4µV/°C (max), and 200nVP-P
noise from 0.1Hz to 10Hz. The low offset and noise
specifications and wide input common-mode range make
the device ideal for sensor transmitters and interfaces.
Varying the external charge pump capacitors enables the
charge-pump noise to be minimized.
The MAX44267 is part of a family of signal chain ICs
including amplifiers, multiplexers and ADCs. These ICs
eliminate the need for a negative supply to the multi-
plexer, amplifier and ADC, saving space and cost. See
the Typical Application Circuit and Table 1 for more infor-
mation. See the MAX44247 for the same amplifier with
internal charge-pump capacitors in a small 8-pin µMAX®
package.
The MAX44267 is available in a 14-pin TSSOP package
and is specified over the -40°C to +125°C operating tem-
perature range.
Benets and Features
●True Bipolar Output Greater than ±10V from a Single
+15V Supply Eliminates Space and Cost of Negative
Power Supply
• True Zero Output from a Single Supply
●High-Accuracy Sensing Over Temperature
• Low Input VOS: 50μV (max)
• Low 0.4µV/°C (max) of Offset Drift
● 9nV/√Hz Low Input Noise at 1kHz Provides Wide
ADC Dynamic Range
●5MHz Gain-Bandwidth Product Provides Wide
Frequency Input Range
● Low 2.4mA (max) Quiescent Current Enables Lower
Power Dissipation and Cooler Operation
●Integrated EMI Filter Reduces Sensitivity to Motors
and Other High-Frequency Noise Generators
●14-Pin TSSOP Package with External Charge-Pump
Capacitors Enables Noise Optimization
Applications
● PLC Analog I/O Modules
●Sensor Interfaces
●Pressure Sensors
●Bridge Sensors
● Analog Level Shifting/Conditioning
Ordering Information appears at end of data sheet.
19-7455; Rev 0; 11/14
Block Diagram
µMAX is a registered trademark of Maxim Integrated Products, Inc.
14
13
12
11
10
9
8
1
2
3
4
5
6
7
V
DD
CPVDD
OUTB
INB-
GND
INA+
INA-
OUTA
MAX44267
INB+
CPVSS
CNCP
V
SS
CPGND
+
C
FILT
C
HOLD
C
FLY
C
BYPASS
AMPLIFIER B
AMPLIFIER A
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
VDD to GND .......................................................-0.3V to +16.5V
CPVDD to GND .................................................. -0.3V to +16.5V
CP, CN, CPVSS, VSS Input Current ...............................±20mA
Common-Mode Input Voltage.... (-VDD - 0.3V) to (+VDD + 0.3V)
Differential Input Current ..................................................±20mA
Differential Input Voltage (Note 1) .........................................±1V
OUTA, OUTB to GND................ (-VDD - 0.3V) to (+VDD + 0.3V)
Short-Circuit Duration, OUTA, OUTB to either Supply Rail .... 1s
Continuous Power Dissipation (TA = +70°C)
14-Pin TSSOP (derate 10mW/°C above +70°C) ...... 796.8mW
Operating Temperature Range ......................... -40°C to +125°C
Junction Temperature ...................................................... +150°C
Storage Temperature Range .............................-65ºC to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
TSSOP
Junction-to-Ambient Thermal Resistance (θJA) .....100.4°C/W
Junction-to-Case Thermal Resistance (θJC) ...............30°C/W
(Note 2)
(VDD = VCPVDD = 15V, VGND = 0V, VCM = GND, RL = 5kΩ to GND, CFLY = 0.022µF, CHOLD = 0.1µF, CFILT = 0.1µF, TA = -40°C to
+125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
Electrical Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC SPECIFICATIONS
Power-Supply Voltage Input Range VDD Guaranteed by PSRR 4.5 15.5 V
Charge-Pump Supply Voltage Input
Range (Note 4) CPVDD 4.5 15.5 V
Charge-Pump Negative Supply
Output CPVSS
VDD = 15V, RL = ∞
-14.8
V
VDD = 5V, RL = ∞
-4.8
Filtered Negative Supply Output VSS
VDD = 15V, RL = 5kΩ -13 V
VDD = 5V, RL = 5kΩ -3.6
Power-Supply Rejection Ratio PSRR
TA = +25°C 117 137
dB
+4.5V ≤ VDD ≤
+15.5V -40°C ≤ TA ≤ +125°C 112
Total Quiescent Current IDD RL = ∞ TA = +25°C 2.4 3.6 mA
-40°C ≤ TA ≤ +125°C 4.0
Input Common-Mode Range VCM
Guaranteed by
CMRR test
VDD = 15V -12.0
+13.5
V
VDD = 5V -2.0 +3.5
Common-Mode Rejection Ratio CMRR
VDD = 15V,
VCM = -12V to +13.5V
TA = +25°C 138 150 dB
-40°C ≤ TA ≤ +125°C 122
VDD = 5V,
VCM = -2V to +3.5V
TA = +25°C 125 140 dB
-40°C ≤ TA ≤ +125°C 118
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
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Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Note 1: The amplifier inputs are connected by internal back-to-back clamp diodes. In order to minimize noise in the input stage,
current-limiting resistors are not used. If differential input voltages exceeding ±1V are applied, limit input current to ±20mA.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(VDD = VCPVDD = 15V, VGND = 0V, VCM = GND, RL = 5kΩ to GND, CFLY = 0.022µF, CHOLD = 0.1µF, CFILT = 0.1µF, TA = -40°C to
+125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
Note 3: All devices are 100% production tested at TA = +25°C. Temperature limits are guaranteed by design.
Note 4: CPVDD voltage must be equal to VDD voltage. Connect CPVDD to VDD.
Note 5: Parameter is guaranteed by design.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Offset Voltage VOS
TA = +25°C 4 45 µV
-40°C ≤ TA ≤ +125°C 50
Input Offset Voltage Drift (Note 5) TCVOS -40°C ≤ TA ≤ +125°C 0.1 0.4 µV/°C
Input Bias Current IB
TA = +25°C 0.5 1.5 nA
-40°C ≤ TA ≤ +125°C 2.5
Input Offset Current IOS
TA = +25°C 0.3 1.0 nA
-40°C ≤ TA ≤ +125°C 2.0
Open-Loop Gain AVOL
VDD = 15V,
-11V ≤ VOUT ≤ +13.5V
TA = +25°C 136 145
dB
-40°C ≤ TA ≤ +125°C 129
VDD = 5V,
-1.3V ≤ VOUT ≤ +3.5V
TA = +25°C 130 140
-40°C ≤ TA ≤ +125°C 121
Input Resistance RIN 50 MΩ
Maximum Output Current IOUT
Sinking 17 mA
Sourcing 36
Output Voltage Swing High
(VOUT to GND) VOH
VDD = 15V, RL = 5kΩ, both channels driven
13.8 14.8
V
VDD = 5V, RL = 5kΩ, both channels driven
3.8 4.9
Output Voltage Swing Low
(VOUT to GND) VOL
VDD = 15V, RL = 5kΩ, both channels driven -11.3 -12.7 V
VDD = 5V, RL = 5kΩ,both channels driven -1.5 -3.5 V
AC SPECIFICATIONS
Input Voltage-Noise Density eNf = 1kHz 9 nV/√Hz
Input Voltage Noise 0.1Hz < f < 10Hz 200 nVP-P
Input Current-Noise Density iNf = 1kHz 200 fA/√Hz
Gain-Bandwidth Product GBW 5 MHz
Slew Rate SR 3 V/µs
Total Harmonic Distortion THD f = 1kHz, VOUT = 2VP-P, AV = +1V/V -100 dB
Capacitive Loading CLNo sustained oscillation, AV = +1V/V 300 pF
Charge-Pump Frequency fOSC 500 kHz
Charge-Pump Feedthrough 2 mV
Crosstalk Xtalk f = 1kHz -100 dB
Settling Time tS1µs
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
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Electrical Characteristics (continued)
(VDD = VCPVDD = 15V, VGND = VCPGND = 0V, VCM = 0V, CFLY = 0.022µF, CHOLD = 0.1µF, CFILT = 0.1µF, RL = 5kΩ and CL = 10pF to
GND, TA = +25°C, unless otherwise noted.)
2
2.05
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.45
2.5
-50 -25 025 50 75 100 125
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
TOTAL SUPPLY CURRENT vs. TEMPERATURE
toc01
VDD = +5V
VDD = +15V
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
4.5 67.5 910.5 12 13.5 15
IDD (mA)
VDD (V)
TOTAL SUPPLY CURRENT vs. VDD
toc02
-17
-16
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
4.5 67.5 910.5 12 13.5 15
VCPVSS,VSS (V)
VDD (V)
CPVSS AND VSS vs. VDD
toc2b
CPVSS
VSS
OP AMPS, VSS AND
CPVSS UNLOADED
0
10
20
30
40
50
60
-4 -3 -2 -1 01234
PERCENT OCCURRENCE (%)
OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE HISTOGRAM
toc03
-500
-450
-400
-350
-300
-250
-200
-150
-100
-50
0
-50 -25 025 50 75 100 125
INPUT BIAS CURRENT (pA)
TEMPERATURE (°C)
INPUT BIAS CURRENT vs. TEMPERATURE
toc04
IB-
IB+
-15
-14.5
-14
-13.5
-50 -25 025 50 75 100 125
VCPVSS, VSS (V)
TEMPERATURE (°C)
CPVSS AND VSS vs. TEMPERATURE
(VDD = 15V) toc2c
CPVSS
VSS
OP AMPS, VSS AND
CPVSS UNLOADED
-5
-4.5
-4
-3.5
-50 -25 025 50 75 100 125
VCPVSS, VSS (V)
TEMPERATURE (°C)
CPVSS AND VSS vs. TEMPERATURE
(VDD = 5V)
toc2d
CPVSS
VSS
OP AMPS, VSS AND
CPVSS UNLOADED
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
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Typical Operating Characteristics
(VDD = VCPVDD = 15V, VGND = VCPGND = 0V, VCM = 0V, CFLY = 0.022µF, CHOLD = 0.1µF, CFILT = 0.1µF, RL = 5kΩ and CL = 10pF to
GND, TA = +25°C, unless otherwise noted.)
-450
-400
-350
-300
-250
-200
-150
-100
-50
0
50
100
150
-50 -25 025 50 75 100 125
INPUT OFFSET CURRENT (pA)
TEMPERATURE (°C)
INPUT OFFSET CURRENT vs. TEMPERATURE
toc4b
-10
-8
-6
-4
-2
0
2
4
6
8
10
-50 -25 025 50 75 100 125
INPUT OFFSET VOLTAGE (µV)
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE
vs. TEMPERATURE
toc05
1
10
100
1000
110 100 1000 10000 100000
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
INPUT VOLTAGE-NOISE DENSITY
vs. FREQUENCY
toc06
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.01 0.1 110 100 1000 10000
PSRR (dB)
FREQUENCY (kHz)
PSRR vs. FREQUENCY
toc09
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
0.01 0.1 110 100 1000 10000
CMRR (dB)
FREQUENCY (kHz)
VDD = 15V
CMRR vs. FREQUENCY
toc10
10
100
1000
10000
110 100 1000 10000 100000
CURRENT-NOISE DENSITY (fA/√Hz)
FREQUENCY (Hz)
INPUT CURRENT-NOISE DENSITY
vs. FREQUENCY
toc07
100nV/div
toc08
1s/div
0.1Hz TO 10Hz PEAK-TO-PEAK NOISE
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
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Typical Operating Characteristics (continued)
(VDD = VCPVDD = 15V, VGND = VCPGND = 0V, VCM = 0V, CFLY = 0.022µF, CHOLD = 0.1µF, CFILT = 0.1µF, RL = 5kΩ and CL = 10pF to
GND, TA = +25°C, unless otherwise noted.)
-35
-30
-25
-20
-15
-10
-5
0
5
0.01 0.1 110 100 1000 10000 100000
LARGE-SIGNAL GAIN (dB)
FREQUENCY (kHz)
LARGE-SIGNAL GAIN vs. FREQUENCY
toc13
VIN = 2VP-P
GAIN = 1V/V
100mV/div
100mV/div
toc15
1µs/div
VIN
VOUT
SMALL-SIGNAL STEP RESPONSE
(G = -1V/V, VIN = ±100mVPP, CL= 100pF)
100mV/div
100mV/div
toc14
1µs/div
VIN
VOUT
SMALL-SIGNAL STEP RESPONSE
(G = -1V/V, VIN = ±100mVPP, CL= 10pF)
100mV/div
100mV/div
toc16
1µs/div
VIN
VOUT
SMALL-SIGNAL STEP RESPONSE
(G = +1V/V, VIN = ±100mVPP, CL= 10pF)
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
0.01 0.1 110 100 1000 10000
CMRR (dB)
FREQUENCY (kHz)
VDD = 5V
CMRR vs. FREQUENCY
toc11
-35
-30
-25
-20
-15
-10
-5
0
5
0.01 0.1 110 100 1000 10000 100000
SMALL-SIGNAL GAIN (dB)
FREQUENCY (kHz)
SMALL-SIGNAL GAIN vs. FREQUENCY
toc12
VIN = 100mVP-P
GAIN = 1V/V
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
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Typical Operating Characteristics (continued)
(VDD = VCPVDD = 15V, VGND = VCPGND = 0V, VCM = 0V, CFLY = 0.022µF, CHOLD = 0.1µF, CFILT = 0.1µF, RL = 5kΩ and CL = 10pF to
GND, TA = +25°C, unless otherwise noted.)
10V/div
10V/div
toc19
20µs/div
VIN
VOUT
LARGE-SIGNAL STEP RESPONSE
(G = +1V/V, VIN = ±10VPP, CL= 100pF)
100ΩIN SERIES WITH VIN
-2V
toc21
1µs/div
VIN
VOUT
NEGATIVE OVERLOAD RECOVERY
(G = -10V/V, CL= 10pF)
0V
0V
15V
0
10
20
30
40
50
050 100 150 200 250 300 350
PERCENT OVERSHOOT (%)
CAPACITIVE LOAD (pF)
PERCENT OVERSHOOT vs.
CAPACITIVE LOAD
toc20
GAIN = +1V/V,
VIN = ±100mV, 1kHz
RL= 5kΩ
NEGATIVE
POSITIVE
0V
toc22
1µs/div
VIN
VOUT
POSITIVE OVERLOAD RECOVERY
(G = -10V/V, CL= 10pF)
2V
-15V
0V
100mV/div
100mV/div
toc17
1µs/div
VIN
VOUT
SMALL-SIGNAL STEP RESPONSE
(G = +1V/V, VIN = ±100mVPP, CL= 100pF)
10V/div
10V/div
toc18
20µs/div
VIN
VOUT
LARGE-SIGNAL STEP RESPONSE
(G = -1V/V, VIN = ±10VPP, CL= 100pF)
100ΩIN SERIES WITH VIN
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
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Typical Operating Characteristics (continued)
(VDD = VCPVDD = 15V, VGND = VCPGND = 0V, VCM = 0V, CFLY = 0.022µF, CHOLD = 0.1µF, CFILT = 0.1µF, RL = 5kΩ and CL = 10pF to
GND, TA = +25°C, unless otherwise noted.)
1V/div
toc25
100µs/div
TURN-ON TRANSIENT
(VIN_+ = 500mV)
VDD
VOUTA
IDD
5V/div
40mA/div
VOUTB
1V/div
OP AMPS, VSS AND
CPVSS UNLOADED
OP AMPS, VSS AND
CPVSS UNLOADED
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1000 10000 100000
THD+N (dB)
FREQUENCY (Hz)
toc27
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
0
10
20
30
40
50
60
70
80
10 100 1000 10000
EMIRR (dB)
FREQUENCY (MHz)
EMIRR vs. FREQUENCY
toc26
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 5 10 15 20 25 30
THD (dB)
OUTPUT AMPLITUDE (V)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT AMPLITUDE
toc28
G = +1V/V,
f = 1kHz
10V/div
toc23
10µs/div
VIN
VOUT
NO PHASE REVERSAL
(VDD = 15V, G = +1V/V, VIN = 29VP-P)
10V/div
2V/div
toc24
200µs/div
VIN
VOUT
NO PHASE REVERSAL
(VDD = 5V, G = +1V/V, VIN = 9VP-P)
2V/div
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
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Typical Operating Characteristics (continued)
(VDD = VCPVDD = 15V, VGND = VCPGND = 0V, VCM = 0V, CFLY = 0.022µF, CHOLD = 0.1µF, CFILT = 0.1µF, RL = 5kΩ and CL = 10pF to
GND, TA = +25°C, unless otherwise noted.)
0
1
2
3
4
5
6
0 5 10 15 20 25 30 35 40
VOUT HIGH (V)
ISOURCE (mA)
VOUT HIGH vs. OUTPUT SOURCE CURRENT
toc31
VDD = 5V
AMP_ SOURCING ONLY
VOUT_
-5
-4
-3
-2
-1
0
0246810 12 14
VOUT LOW (V)
ISINK (mA)
VOUT LOW vs. OUTPUT SINK CURRENT
toc33
VDD = 5V
AMP A SINKING ONLY
(AMP B NOT SINKING)
VOUTA
VOUTB
-15
-14
-13
-12
-11
-10
0246810 12 14 16 18 20
VOUT LOW (V)
ISINK (mA)
VOUT LOW vs. OUTPUT SINK CURRENT
toc32
VDD = 15V
AMP A SINKING ONLY
(AMP B NOT SINKING)
VOUTA
VOUTB
-13.5
-13.4
-13.3
-13.2
-13.1
-13
-12.9
-12.8
-12.7
-12.6
-12.5
-50 -25 025 50 75 100 125
VOUT LOW (V)
TEMPERATURE (
ᵒ
C)
VOUT LOW vs. TEMPERATURE toc34
AMP B
AMP A
DRIVING BOTH CHANNELS,
VDD = 15V, 5kΩLOAD TO GND per AMP
0
0.5
1
1.5
2
2.5
0.01 0.1 110 100 1000 10000
OUTPUT IMPEDANCE (Ω)
FREQUENCY (kHz)
toc29
OUTPUT IMPEDANCE vs. FREQUENCY
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0 5 10 15 20 25 30 35 40
VOUT HIGH (V)
ISOURCE (mA)
VOUT HIGH vs. OUTPUT SOURCE CURRENT
toc30
VDD = 15V
AMP_ SOURCING ONLY
VOUT_
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
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Typical Operating Characteristics (continued)
(VDD = VCPVDD = 15V, VGND = VCPGND = 0V, VCM = 0V, CFLY = 0.022µF, CHOLD = 0.1µF, CFILT = 0.1µF, RL = 5kΩ and CL = 10pF to
GND, TA = +25°C, unless otherwise noted.)
4.8
4.9
5
5.1
-50 -25 025 50 75 100 125
VOH (V)
TEMPERATURE (
ᵒ
C)
VOUT HIGH vs. TEMPERATURE toc37
AMP B
AMP A
DRIVING BOTH CHANNELS,
VDD = 5V, 5kΩLOAD TO GND per AMP
0.1
1
10
100
100 1000 10000 100000
RISO (Ω)
CAPACITIVE LOAD (pF)
STABILITY vs. CAPACITIVE LOAD
AND ISOLATION RESISTANCE
toc39
STABLE
UNSTABLE
0.001
0.01
0.1
1
10
100
100 1000 10000
RESISTIVE LOAD (kΩ)
CAPACITIVE LOAD (pF)
STABILITY vs. CAPACITIVE LOAD
AND ISOLATION RESISTANCE
toc38
STABLE
UNSTABLE
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.01 0.1 110 100 1000 10000
CROSSTALK (dB)
FREQUENCY (kHz)
CROSSTALK vs. FREQUENCY
toc40
-3.7
-3.6
-3.5
-3.4
-3.3
-50 -25 025 50 75 100 125
VOUT LOW (V)
TEMPERATURE (
ᵒ
C)
VOUT LOW vs. TEMPERATURE toc35
AMP B
AMP A
DRIVING BOTH CHANNELS,
VDD = 5V, 5kΩLOAD TO GND per AMP
14.7
14.8
14.9
15
-50 -25 025 50 75 100 125
VOH (V)
TEMPERATURE (
ᵒ
C)
VOUT HIGH vs. TEMPERATURE toc36
AMP B
AMP A
DRIVING BOTH CHANNELS,
VDD = 15V, 5kΩLOAD TO GND per AMP
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
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Typical Operating Characteristics (continued)
PIN NAME FUNCTION
1 OUTA Channel A Output
2 INA- Channel A Negative Input
3 INA+ Channel A Positive Input
4 GND Ground. Connect GND to a solid ground plane.
5 CPGND Charge-Pump Ground. Connect CPGND to GND.
6 VSS Filtered Negative Supply Output. Bypass VSS with a low-ESR capacitor (CFILT = 1µF) to GND.
7 CP Charge-Pump Positive Capacitor Connection. Capacitor connection only to CN. Do not connect any
voltage on CP or CN. Connect a low-ESR capacitor (CFLY = 0.022µF) between CP and CN.
8 CN Charge-Pump Negative Capacitor Connection. Capacitor connection only to CP. Do not connect any
voltage on CN or CP. Connect a low-ESR capacitor (CFLY = 0.022µF) between CP and CN.
9 CPVSS Charge Pump Negative Supply Output. Bypass CPVSS with a 0.1µF capacitor to CPGND.
10 INB+ Channel B Positive Input
11 INB- Channel B Negative Input
12 OUTB Channel B Output
13 CPVDD Charge-Pump Supply Voltage Input. Connect CPVDD to VDD. Bypass CPVDD with a 0.1µF capacitor to
GND.
14 VDD Device Supply Voltage Input. Bypass VDD with a 0.1µF capacitor to GND.
14
13
12
11
10
9
8
1
2
3
4
5
6
7
V
DD
CPVDD
OUTB
INB-GND
INA+
INA-
OUTA
TOP VIEW
MAX44267
INB+
CPVSS
CNCP
V
SS
CPGND
TSSOP
+
MAX44267 +15V Single-Supply, Dual Op Amp
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Pin Conguration
Pin Description
Detailed Description
The MAX44267 is a high-precision amplifier that provides
less than 50µV of maximum input-referred offset and low
1/f noise. These characteristics are achieved by using
a combination of proprietary auto-zeroing and chopper-
stabilized techniques. This combination of auto-zeroing
and chopping ensures that these amplifiers give all the
benefits of zero-drift amplifiers, while still ensuring low
noise, minimizing chopper spikes, and providing wide
bandwidth.
Common Internal Charge Pump
The MAX44267’s integrated charge pump produces a
negative voltage rail (VSS) that is common to both ampli-
fiers (see Figure 1 for external capacitor connections).
The device consumes a total of 4mA (max) of quiescent
current (including both the op amps and the charge-pump
operation).
The VSS generator acts as a negative supply for the
MAX44267, and has limited sink current capability.
Attempting to load more than its capability will reduce the
negative supply voltage, affecting its driving capabil-
ity when sinking current. Sinking beyond typically 17mA
per channel will result in reduced swing in the negative
direction and increased ripple affecting both outputs and
degrading output accuracy and performance of both ampli-
fiers.
The output V
SS
negative supply is common to both ampli-
fier channels. Loading the output of one channel beyond
the recommended value will affect the second amplifier
channel as mentioned above. The total loading of both
channels must be kept below 17mA. If one channel is
minimally loaded, for example, only sinking 100µA, the
other channel may sink 16.9mA. As shown in Figure 2,
when using V
DD
of +15V the V
SS
output will be around
-13.6V (typ) at no load. As amplifier A is sinking, it causes
the V
SS
rail to rise and this is reflected in V
OUTB
.
Figure 1. External Capacitor Connections Figure 2. VOUT LOW vs. OUTPUT SINK CURRENT
14
13
12
11
10
9
8
1
2
3
4
5
6
7
V
DD
CPVDD
OUTB
INB-
GND
INA+
INA-
OUTA
MAX44267
INB+
CPVSS
CNCP
V
SS
CPGND
+
C
FILT
C
HOLD
C
FLY
C
BYPASS
AMPLIFIER B
AMPLIFIER A
-15
-14
-13
-12
-11
-10
0246810 12 14 16 18 20
VOUT LOW (V)
ISINK (mA)
VOUT LOW vs. OUTPUT SINK CURRENT
VDD = 15V
AMP A SINKING ONLY
(AMP B NOT SINKING)
VOUTA
VOUTB
MAX44267 +15V Single-Supply, Dual Op Amp
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ESD Networks
The MAX44267 output swing can be well below 0V while
all the other circuitry on the board may have 0V as its most
negative terminal. Since almost all modern integrated cir-
cuits protect their inputs with a network of diode clamps to
their power rails, it is possible to discover the driven circuit
is clamping the MAX44267’s output (Figure 3).
Maxim Integrated has many products that have inputs that
can be driven Beyond the Rails: ADCs, multiplexers and cur-
rent-sensing amplifiers. Other circuitry should be designed
such that the MAX44267’s output will not be clamped by
another circuit’s ESD network. A common solution to this
problem is to arrange that the output is level-shifted as well
as amplified or conditioned by the MAX44267. Be sure not
to exceed the absolute maximum ratings on any devices
surrounding the MAX44267 amplifier.
Capacitor Selection
The MAX44267 requires three external capacitors (CFLY,
CHOLD, and CFILT) to generate the VSS negative supply
rail. The charge-pump output resistance is a function of
the ESR of CFLY, CHOLD, and CFILT. To maintain the
lowest output resistance, use capacitors with low ESR.
Flying Capacitor (CFLY)
Increasing the flying capacitor’s value reduces the
output resistance. Above 0.047µF, increasing C
FLY
’s
capacitance has negligible effect because internal switch
resistance and capacitor ESR then dominate the output
resistance.
Output Capacitor (CHOLD)
Increasing the output capacitor’s value reduces the output
ripple voltage. Decreasing its ESR reduces both output
resistance and ripple. Lower capacitance values can be
Figure 3. Possibility of Clamping the MAX44267 Output via Another Circuit’s ESD Network
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
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used with light loads if higher output ripple can be toler-
ated. Refer to the following graphs to estimate the peak-
to-peak ripple for certain sinking current value.
CPVSS Bypass Capacitor
Bypass the incoming supply (CPVSS) to reduce its AC
impedance and the impact of the charge pump’s switching
noise. Connect a minimum of a 0.1µF low-ESR capacitor
from CPVSS to CPGND as close as possible to the IC.
Noise Suppression
Low-frequency noise, inherent in all active devices, is
inversely proportional to frequency. Charges at the oxide-
silicon interface that are trapped-and-released by oxide
and PN junction occur at low frequency more often. The
MAX44267 eliminates the 1/f noise internally, thus making
it an ideal choice for DC or low frequency, high-precision
applications. The 1/f noise appears as a slow varying offset
voltage and is eliminated by the chopping technique used.
Electromagnetic interference (EMI) noise occurs at higher
frequency that results in malfunction or degradation of
electrical equipment. The ICs have an input EMI filter to
avoid the output being affected by radio frequency inter-
ference. The EMI filter composed of passive devices pres-
ents significant higher impedance to higher frequency.
Figure 4. IOUTSINK vs. VSS_RIPPLE (CFLY = 0.022µF, CHOLD =
CFILT = 0.1µF)
Figure 5. IOUTSINK vs. VSS_RIPPLE (CFLY = 0.047µF, CHOLD =
CFILT = 0.1µF)
Figure 6. Total Supply Current vs. ISINK
0
1
2
3
4
5
6
0246810 12 14
VSS_RIPPLE (mVP-P)
ISS_SINK (mA)
V
SS_RIPPLE
vs. ISS OUTPUT SINK CURRENT
(CFLY = 0.022µF)
VDD = VCPVDD = 15V
CHOLD = CFILT = 0.1µF
VSS SINKING CURRENT
VSS_RIPPLE
VOUTA_RIPPLE
VOUTB_RIPPLE
0
5
10
15
20
25
30
0246810 12 14 16 18
IDD (mA)
ISS_SINK (mA)
TOTAL IDD
vs. ISS OUTPUT SINK CURRENT
VDD = VCPVDD = 15V
CFLY =0.022µF
CHOLD = CFILT = 0.1µF
VSS SINKING CURRENT
0
1
2
3
4
5
6
0246810 12 14
VSS_RIPPLE (mVPP)
ISS_SINK (mA)
V
SS_RIPPLE
vs. ISS OUTPUT SINK CURRENT
(CFLY = 0.047µF)
VDD = VCPVDD = 15V
CHOLD = CFILT = 0.1µF
VSS SINKING CURRENT
VSS_RIPPLE
VOUTA_RIPPLE
VOUTB_RIPPLE
MAX44267 +15V Single-Supply, Dual Op Amp
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True Zero Output Architecture
The MAX44267 is unique compared to the majority of
operational amplifiers. The MAX44267 contains an inter-
nal charge pump that generates a negative voltage rail
(VSS), shared by both amplifiers. This allows the amplifier
input and output ranges to extend substantially below 0V,
while powered from only a single positive supply. VSS
output supplies both amplifiers and its output load current.
VSS can be used to power external circuitry but the addi-
tional load current is seen as additional load by the charge
pump. This internally generated negative supply can
cause currents to flow in unexpected paths—especially
through the electrostatic discharge protection networks
found in almost all modern integrated circuits (Figure 7).
Near-Zero Source Impedances
The negative voltage generator has a finite current sink
capability (typically around 15mA for CFLY = 0.022µF,
CHOLD = CFILT = 0.1µF). If the device is overloaded by
the output sink current of one or both amplifiers combined,
it will lose regulation, limiting output swing in the negative
direction. Additionally, if regulation is lost, and the input
is forced towards the negative rail, the MAX44267 can
enter a latchup condition. This latchup is non-destructive,
and the device will recover when the fault conditions are
removed.
The MAX44267 is specified with a 5kΩ load on each out-
put channel. This results in a maximum output load current
that is well below an overload of the generator, and so the
device will not latch up. It is possible to drive even heavier
loads, although the total output sink current (of both chan-
nels combined) should not be allowed to exceed 15mA
peak. (see the V
OUT
Low vs. Output Sink Current graph
in the Typical Operating Characteristics for details). When
driving loads that may approach the output’s limit, it is
recommended that the inputs should be high-impedance
sources or add a protective 5kΩ series resistor.
Figure 7. Possible Latchup Due to Overloading the MAX44267
15V
MAX44267
V
DD
V
SS
V
DD
V
SS
VERY LOW
SOURCE
IMPEDANCE
-5V
ON
AMPLIFIER
BIASING
V
DD
CHARGE PUMP
C
FLY
OUT_
C
FILT
C
HOLD
CN
CP
V
SS
CPVSS
CPVDD
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
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Applications Information
Bridge Measurement Conguration without
Instrumentation Amplier
The MAX44267’s low input offset voltage and low noise
make it ideal for biasing strain gauges (Figure 8). The
strain-gauge bridge is most commonly biased from the
reference source and the output from the bridge is then
at approximately half the reference voltage. In the case
of biasing around ground, a negative supply needs to be
available. Hence, the bridge is biased at twice the refer-
ence voltage and the center is at 0V (to within the offset
voltage of the amplifier X1). Doubling the voltage across
the bridge doubles its sensitivity, but of course, the down-
side is twice the current flows.
Since the bridge’s center is now forced to be at 0V, the
node “ip” must also be at 0V when no strain is applied, to
within the calibration of zero strain of the bridge. Having
controlled the zero bias point, the application can use
the second amplifier within the dual MAX44267 to take
a very large, direct-coupled gain without the usual risk of
common-mode errors causing the output to saturate.
A full bridge, as shown, typically produces a differential
output with a full scale of approximately 0.1% of the bias-
ing voltage. Doubling the biasing voltage yields a doubling
of sensitivity while also removing any common-mode
error for the high-gain amplifier. Assuming that RB3 and
RB2 are configured to decrease their resistance as the
strain increases while RB1 and RB4 increase their resis-
tance, then the full-scale output will be +819.2mV at the
output. Capacitor C1 can be sized to roll of any unwanted
bandwidth and its associated noise. Assuming the bridge
uses resistances of 10kΩ in each leg, the noise will be
about 24nV/√Hz, which is then amplified by 100x, along
with the signal to give 2.4µV. If the bandwidth is kept down
to 100Hz then this is only 24µVRMS or about 300µVP-P
yielding a signal to noise ratio of 68dB. This can of course
be improved by averaging the readings over a suitably
long period of time with an integral number of 60Hz
(50Hz) cycles usually offering both improved resolution
and reduced sensitivity to the 60Hz power system.
Layout Guidelines
The MAX44267 features ultra-low offset voltage and
noise, causing the Seebeck effect error to become sig-
nificant. Therefore, to get optimum performance follow the
following layout guidelines:
Avoid temperature gradients at the junction of two dis-
similar metals. The most common dissimilar metals used
on a PCB are solder to component lead and solder to
board trace. Dissimilar metals create a local thermo-
couple. A variation in temperature across the board can
cause an additional offset due to the Seebeck effect at the
solder junctions. To minimize the Seebeck effect, place
the amplifier away from potential heat sources on the
board, if possible. Orient the resistors such that both the
ends are heated equally. It is good practice to match the
input signal path to ensure that the type and number of
thermoelectric junctions remain the same. For example,
consider using dummy 0Ω resistors oriented such that
the thermoelectric sources due to the real resistors in the
signal path is cancelled. It is recommended to flood the
PCB with ground plane. The ground plane ensures that
heat is distributed uniformly reducing the potential offset
voltage degradation due to Seebeck effect.
Figure 8. Bridge Measurement Configuration without Instrumentation Amplifier
R1
18kΩ
½ MAX44267
V
CC
R2
2kΩ
R3
180kΩ
V
REF
4.096V
RB1
RB2
RB3
RB4
ip
X1
X2
MAX6070
V
OUT
C1
1nF
½ MAX44267
V
CC
V
IN
MAX44267 +15V Single-Supply, Dual Op Amp
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Table 1. Selector Guide for the Typical Operating Circuit
PART NO. FUNCTION VOLTAGE SUPPLY RANGE (V) INPUT VOLTAGE RANGE (V)
MAX44267 Precision amplier +4.5 to +15.5 -12.0 to +13.5
MAX14778 4:1 mux +3 to +5.5 ±25
MAX14762 2-channel switch +3 to +5.5 ±25
MAX11167 16-bit ADC +5 ±5
±V
REF
MAX14778
MUX A
MAX11166
±25V
SOURCES ½ MAX44267
C2
C1
MAX11166
½ MAX44267
C4
MUX B
5V SINGLE SUPPLY
5V
COMPLETE BEYOND-THE-RAILS SIGNAL CHAIN SOLUTION
C3
R1
R2
R3
R6
R4
R5
±25V
SOURCES
±V
REF
5V
MAX44267 +15V Single-Supply, Dual Op Amp
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Typical Application Circuit
+Denotes a lead(Pb)-free/RoHS-compliant package.
PART TEMP RANGE PIN-PACKAGE
MAX44267AUD+ -40°C to + 125°C14 TSSOP
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
14 TSSOP U14+1 21-0066 90-0113
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
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Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Ordering Information
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
011/14 Initial release —
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX44267 +15V Single-Supply, Dual Op Amp
with ±10V Output Range
© 2014 Maxim Integrated Products, Inc.
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19
Revision History
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