PIC16F1719-I/PT - Microchip Technology

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 1

PIC16(L)F1717/8/9

Description:

PIC16(L)F1717/8/9 microcontrollers combine Intelligent Analog integration with low cost and extreme low power (XLP)

to suit a variety of general purpose applications. These 28-pin and 40-pin devices deliver on-chip op amps, Core

Independent Peripherals (CLC, NCO and COG), Peripheral Pin Select and Zero-Cross Detect, providing for increased

design flexibility.

Core Features:

• C Compiler Optimized RISC Architecture

• Only 49 Instructions

• Operating Speed:

- 0-32 MHz clock input

- 125 ns minimum instruction cycle

• Interrupt Capability

• 16-Level Deep Hardware Stack

• Up to Four 8-Bit Timers

• One 16-Bit Timer

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Low-Power Brown-Out Reset (LPBOR)

• Programmable Watchdog Timer (WDT) up to

256s

• Programmable Code Protection

Memory:

• Up to 16 Kwords Flash Program Memory

• Up to 2048 Bytes Data SRAM Memory

• Direct, Indirect and Relative Addressing modes

Operating Characteristics:

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF1717/8/9)

- 2.3V to 5.5V (PIC16F1717/8/9)

• Temperature Range:

- Industrial: -40°C to 85°C

- Extended: -40°C to 125°C

eXtreme Low-Power (XLP) Features:

• Sleep mode: 50 nA @ 1.8V, typical

• Watchdog Timer: 500 nA @ 1.8V, typical

• Secondary Oscillator: 500 nA @ 32 kHz

• Operating Current:

- 8 uA @ 32 kHz, 1.8V, typical

- 32 uA/MHz @ 1.8V, typical

Digital Peripherals:

• Configurable Logic Cell (CLC):

- Integrated combinational and sequential logic

• Complementary Output Generator (COG):

- Rising/falling edge dead-band control/

blanking

• Numerically Controlled Oscillator (NCO):

- Generates true linear frequency control and

increased frequency resolution

- Input Clock: 0 Hz < FNCO < 32 MHz

- Resolution: FNCO/220

• Capture/Compare/PWM (CCP) module

• PWM: Two 10-Bit Pulse-Width Modulators

• Serial Communications:

- SPI, I2C™, RS-232, RS-485, LIN compatible

- Auto-Baud Detect, auto-wake-up on start

• Up to 35 I/O Pins and One Input Pin:

- Individually programmable pull-ups

- Slew rate control

- Interrupt-on-change with edge-select

• Peripheral Pin Select (PPS):

- Enables pin mapping of digital I/O

Intelligent Analog Peripherals:

• Operational Amplifiers:

- Two configurable rail-to-rail op amps

- Selectable internal and external channels

- 2 MHz gain bandwidth product

• High-Speed Comparators:

- Up to two comparators

- 50 ns response time

- Rail-to-rail inputs

• 10-Bit Analog-to-Digital Converter (ADC):

- Up to 28 external channels

- Conversion available during Sleep

- Temperature indicator

• Zero-Cross Detector (ZCD):

- Detect when AC signal on pin crosses

ground

• 8-Bit Digital-to-Analog Converter (DAC):

- Output available externally

- Internal connections to comparators, op

amps, Fixed Voltage Reference (FVR) and

ADC

• Internal Voltage Reference module

Cost Effective 8-Bit Intelligent Analog Flash Microcontrollers

PIC16(L)F1717/8/9

DS40001740A-page 2 Preliminary  2014 Microchip Technology Inc.

Clocking Structure:

• 16 MHz Internal Oscillator Block:

- ±1% at calibration

- Selectable frequency range from 0 to 32 MHz

• 31 kHz Low-Power Internal Oscillator

• External Oscillator Block with:

- Three crystal/resonator modes up to 20 MHz

- Two external clock modes up to 20 MHz

• Fail-Safe Clock Monitor

• Two-Speed Oscillator Start-up

• Oscillator Start-up Timer (OST)

Programming/Debug Features:

• In-Circuit Debug Integrated On-Chip

• Emulation Header for Advanced Debug:

- Provides trace, background debug and up to

32 hardware break points

• In-Circuit Serial Programming™ (ICSP™) via Two

Pins

PIC16(L)F1713/6 Family Types

Device

Data Sheet Index

Program Memory

Flash (words)

Data SRAM

(bytes)

I/Os(2)

10-bit ADC (ch)

5/8-bit DAC

High-Speed/

Comparators

Op Amp

Zero Cross

Timers

(8/16-bit)

CCP

PWM

COG

EUSART

MSSP (I2C™/SPI)

CLC

NCO

PPS

Debug(1)

XLP

PIC16(L)F1713 (1) 4096 512 25 17 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y

PIC16(L)F1716 (1) 8192 1024 17 25 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y

PIC16(L)F1717 (2) 8192 1024 36 28 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y

PIC16(L)F1718 (2) 16384 2048 25 17 1/1 2 2 1 4/1 2211141YI/EY

PIC16(L)F1719 (2) 16384 2048 36 28 1/1 2 2 1 4/1 2211141YI/EY

Note 1: Debugging Methods: (I) – Integrated on Chip; (H) – using Debug Header; E – using Emulation Header.

2: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document.)

1: DS40001726 PIC16(L)F1713/6 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers.

2: DS40001740 PIC16(L)F1717/8/9 Data Sheet, 28/40-Pin Flash, 8-bit Microcontrollers.

Note: For other small form-factor package availability and marking information, please visit

http://www.microchip.com/packaging or contact your local sales office.

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 3

PIC16(L)F1717/8/9

Pin Diagrams

FIGURE 1: 28-PIN SPDIP, SOIC, SSOP

FIGURE 2: 28-PIN (U)QFN

PIC16(L)F1718

VPP/MCLR/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VDD

VSS

14 15

VSS

RA7

RA6

RC0

RC1

RC2

RC3

RC5

RC4

RC7

RC6

RB7

Note: See Tabl e 1 for the pin allocation table.

RC0

RB7

RB6

RB5

RB4

RB0

VDD

VSS

RC7

RC6

RC5

RC4

RE3/MCLR/VPP

RA0

RA1

RA2

RA3

RA4

RA5

VSS

RA7

RA6

RC1

RC2

RC3

PIC16(L)F1718

RB3

RB2

RB1

Note: See Tab le 1 for the pin allocation table.

PIC16(L)F1717/8/9

DS40001740A-page 4 Preliminary  2014 Microchip Technology Inc.

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1718)

I/O(2)

6PDIP,SOIC,

SSOP

QFN, UQFN

ADC

Reference

Op Amp

DAC

Zero Cross

NCO

Interrupt

Pull-up

Basic

RA0 2 27 AN0

CLCIN0(1) IOC Y

RA1 3 28 AN1 OPA1OUT

CLCIN1(1) IOC Y

RA2 4 1 AN2

V5()- DAC1OUT1 IOC Y

RA3 5 2 AN3

V5()+

IOC Y

RA4 6 3 OPA1IN+

T0CKI(1) IOC Y

RA5 7 4 AN4 OPA1IN- DAC2OUT1

nSS(1) IOC Y

RA6 10 7 IOC Y

OSC2

CLKOUT

RA7 9 6 IOC Y

OSC1

CLKIN

RB0 21 18 AN12 ZCD

INT(1)

IOC

RB1 22 19 AN10 OPA2OUT IOC Y

RB2 23 20 AN8 OPA2IN- IOC Y

RB3 24 21 AN9 OPA2IN+ IOC Y

RB4 25 22 AN11 IOC Y

RB5 26 23 AN13

T1G(1) IOC Y

RB6 27 24

CLCIN2(1) IOC Y ICSPCLK

RB7 28 25

DAC1OUT2

DAC2OUT2

CLCIN3(1) IOC Y ICSPDAT

T1CKI(1)

SOSCO

RC1 12 9 SOSCI IOC Y

RC2 13 10 AN14 IOC Y

RC3 14 11 AN15

6&/SCK(1)

IOC Y

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: Alternate outputs are excluded from solid shaded areas.

5: Alternate inputs are excluded from dot shaded areas.

C1IN1+

Comparator

Timers

CCP

PWM

EUSART

CLC

C1IN0-

C2IN0-

C1IN1-

C2IN1-

C1IN0+

C2IN0+

COG

MSSP

C2IN1+

COG1IN(1)

C1IN3-

C2IN3-

C1IN2-

C2IN2-

RC0

IOC

CCP2(1)

CCP1(1)

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 5

PIC16(L)F1717/8/9

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1718) (CONTINUED)

I/O(2)

6PDIP,SOIC,

SSOP

QFN, UQFN

ADC

Reference

Op Amp

DAC

Zero Cross

NCO

Interrupt

Pull-up

Basic

SDI(1)

SDA(1)

RC5 16 13 AN17 IOC Y

RC6 17 14 AN18 IOC Y

RC7 18 15 AN19 IOC Y

RE3 1 26 IOC Y

MCLR

V33

V'' 20 17 V''

85 V66

19 16

OUT(4)

C1OUT

C2OUT

CCP1

CCP2

NCOOUT

PWM3OUT

PWM4OUT

COG1A

COG1B

COG1C

COG1D

SDA(3)

SCK/SCL(3)

SDO

TX/CK

DT(3)

CLC4OUT

CLC3OUT

CLC2OUT

CLC1OUT

IN(5)

T1G

T1CKI

T0CKI

CCP1

CCP2

SDI

SCK/SCL(3)

RX(3)

CLCIN0

CLCIN1

CLCIN2

CLCIN3

INT

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: Alternate outputs are excluded from solid shaded areas.

5: Alternate inputs are excluded from dot shaded areas.

Comparator

Timers

CCP

PWM

COG

MSSP

EUSART

CLC

COG1IN

CK(3)

RX(3)

V66

RC4

AN16

IOC

PIC16(L)F1717/8/9

DS40001740A-page 6 Preliminary  2014 Microchip Technology Inc.

FIGURE 3: 40-PIN PDIP

FIGURE 4: 40-PIN UQFN (5X5)

PIC16L(F)1717/9

VPP/MCLR/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RE0

RE1

RE2

RB6/ICSPCLK

RB5

RB4

RB0

VDD

VSS

RD2

VDD

VSS

RA7

RA6

RC0

RC1

RC2

RC3

RD0

RD1

RC5

RC4

RD3

RD4

RC7

RC6

RD7

RD6

RD5

RB7/ICSPDAT

RB3

RB2

RB1

Note: See Tabl e 2 for the pin allocation table.

RA1

RA0

VPP/MCLR/RE3

RB3

ICSPDAT/RB7

ICSPCLK/RB6

RB5

RB4 RC6

RC5

RC4

RD3

RD2

RD1

RD0

RC3

RC2

RC1

RC0

RA6

RA7

VSS

VDD

RE2

RE1

RE0

RA5

RA4

RC7

RD4

RD5

RD6

RD7

VSS

VDD

RB0

RB1

RB2

PIC16L(F)1717/9

RA3

RA2

Note: See Table 2 for the pin allocation table.

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 7

PIC16(L)F1717/8/9

FIGURE 5: 44-PIN TQFP (10X10)

PIC16(L)F1717/9

RC6

RC5

RC4

RD3

RD2

RD1

RD0

RC3

RC2

RC1

RC0

RA1

RA0

VPP/MCLR/RE3

RB3

ICSPDAT/RB7

ICSPCLK/RB6

RB5

RB4

RA3

RA2

RC7

RD4

RD5

RD6

RD7

VSS

VDD

RB0

RB1

RB2

RA6

RA7

VSS

VDD

RE2

RE1

RE0

RA5

RA4

Note: See Table 2 for the pin allocation table.

PIC16(L)F1717/8/9

DS40001740A-page 8 Preliminary  2014 Microchip Technology Inc.

TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC16(L)F1717/9)

I/O(2)

PDIP

TQFP

UQFN

ADC

Reference

Op Amp

DAC

Zero Cross

NCO

Interrupt

Pullup

Basic

RA0 2 19 17 AN0

CLCIN0(1) IOC Y

RA1 3 20 18 AN1 OPA1OUT

CLCIN1(1) IOC Y

RA2 4 21 19 AN2

V5()- DAC1OUT1 IOC Y

RA3 5 22 20 AN3

V5()+

IOC Y

RA4 6 23 21 OPA1IN+

T0CKI(1) IOC Y

RA5 7 24 22 AN4 OPA1IN- DAC2OUT1

nSS(1) IOC Y

RA6 14 31 29 IOC Y

OSC2

CLKOUT

RA7 13 30 28 IOC Y

OSC1

CLKIN

RB0 33 8 8 AN12 ZCD

INT(1)

IOC

RB1 34 9 9 AN10 OPA2OUT IOC Y

RB2 35 10 10 AN8 OPA2IN- IOC Y

RB3 36 11 11 AN9 OPA2IN+ IOC Y

RB4 37 14 12 AN11 IOC Y

RB5 38 15 13 AN13

T1G(1) IOC Y

RB6 39 16 14

CLCIN2(1) IOC Y ICSPCLK

RB7 40 17 15

DAC1OUT2

DAC2OUT2

CLCIN3(1) IOC Y ICSPDAT

T1CKI

(1)

SOSCO

RC1 16 35 31 SOSCI IOC Y

RC2 17 36 32 AN14 IOC Y

RC3 18 37 33 AN15

6&/SCK(1)

IOC Y

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: Alternate outputs are excluded from solid shaded areas.

5: Alternate inputs are excluded from dot shaded areas.

COG

COG1IN(1)

PWM

Comparator

C2IN1+

C1IN3-

C2IN3-

C1IN2-

C2IN2-

C1IN0-

C2IN0-

C1IN1-

C2IN1-

C1IN0+

C2IN0+

C1IN1+

CLC

EUSART

CCP

CCP2(1)

CCP1(1)

MSSP

Timers

RC0

IOC

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 9

PIC16(L)F1717/8/9

TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC16(L)F1717/9) (CONTINUED)

I/O(2)

PDIP

TQFP

UQFN

ADC

Reference

Op Amp

DAC

Zero Cross

NCO

Interrupt

Pullup

Basic

SDI(1)

SDA(1)

RC5 24 43 39 AN17 IOC Y

RC6 25 44 40 AN18 IOC Y

RC7 26 1 1 AN19 IOC Y

RD0 19 38 34 AN20 Y

RD1 20 39 35 AN21 Y

RD2 21 40 36 AN22 Y

RD3 22 41 37 AN23 Y

RD4 27 2 2 AN24 Y

RD5 28 3 3 AN25 Y

RD6 29 4 4 AN26 Y

RD7 30 5 5 AN27 Y

RE0 8 25 23 AN5 Y

RE1 92624

AN6 Y

RE2 10 27 25 AN7 Y

RE3 1 18 16 IOC Y

MCLR

V33

11 7 7 V''

32 28 26

12 6 6 V66

31 29 27

OUT(4)

C1OUT

C2OUT

CCP1

CCP2

NCOOUT

PWM3OUT

PWM4OUT

COG1A

COG1B

COG1C

COG1D

SDA(3)

SCK/SCL(3)

SDO

TX/CK

DT (3)

CLC4OUT

CLC3OUT

CLC2OUT

CLC1OUT

IN(5)

T1G

T1CKI

T0CKI

CCP1

CCP2

SDI

SCK/SCL(3)

RX (3)

CLCIN0

CLCIN1

CLCIN2

CLCIN3

INT

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: Alternate outputs are excluded from solid shaded areas.

5: Alternate inputs are excluded from dot shaded areas.

IOC

EUSART

CLC

Comparator

Timers

CCP

PWM

COG

V''

V66

RX(3)

CK(3)

MSSP

COG1IN

RC4

AN16

PIC16(L)F1717/8/9

DS40001740A-page 10 Preliminary  2014 Microchip Technology Inc.

Table of Contents

1.0 Device Overview......................................................................................................................................................................... 12

2.0 Enhanced Mid-Range CPU......................................................................................................................................................... 22

3.0 Memory Organization................................................................................................................................................................. 24

4.0 Device Configuration.................................................................................................................................................................. 54

5.0 Resets........................................................................................................................................................................................ 59

6.0 Oscillator Module (with Fail-Safe Clock Monitor)......................................................................................................................... 67

7.0 Interrupts.................................................................................................................................................................................... 85

8.0 Power-Down Mode (Sleep)......................................................................................................................................................... 97

9.0 Watchdog Timer (WDT)............................................................................................................................................................ 101

10.0 Flash Program Memory Control................................................................................................................................................ 105

11.0 I/O Ports.................................................................................................................................................................................... 121

12.0 Peripheral Pin Select (PPS) Module.......................................................................................................................................... 149

13.0 Interrupt-On-Change................................................................................................................................................................ 155

14.0 Fixed Voltage Reference (FVR)................................................................................................................................................ 162

15.0 Temperature Indicator Module.................................................................................................................................................. 165

16.0 Comparator Module.................................................................................................................................................................. 167

17.0 Pulse Width Modulation (PWM)................................................................................................................................................ 176

18.0 Complementary Output Generator (COG) Module.................................................................................................................... 182

19.0 Configurable Logic Cell (CLC).................................................................................................................................................. 212

20.0 Numerically Controlled Oscillator (NCO) Module...................................................................................................................... 227

21.0 Analog-to-Digital Converter (ADC) Module............................................................................................................................... 236

22.0 Operational Amplifier (OPA) Modules....................................................................................................................................... 249

23.0 8-Bit Digital-to-Analog Converter (DAC1) Module..................................................................................................................... 252

24.0 5-Bit Digital-to-Analog Converter (DAC2) Module..................................................................................................................... 255

25.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 259

26.0 Timer0 Module.......................................................................................................................................................................... 263

27.0 Timer1 Module with Gate Control............................................................................................................................................. 266

28.0 Timer2/4/6 Module.................................................................................................................................................................... 277

29.0 Capture/Compare/PWM Modules............................................................................................................................................. 282

30.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................................... 290

31.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)................................................................. 344

32.0 In-Circuit Serial Programming (ICSP™)................................................................................................................................... 374

33.0 Instruction Set Summary........................................................................................................................................................... 376

34.0 Electrical Specifications............................................................................................................................................................ 390

35.0 DC and AC Characteristics Graphs and Charts......................................................................................................................... 424

36.0 Development Support............................................................................................................................................................... 438

37.0 Packaging Information.............................................................................................................................................................. 442

The Microchip Web Site...................................................................................................................................................................... 463

Customer Change Notification Service............................................................................................................................................... 463

Customer Support...............................................................................................................................................................................463

Product Identification System............................................................................................................................................................. 464

Worldwide Sales and Service............................................................................................................................................................. 466

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 11

PIC16(L)F1717/8/9

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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Customer Notification System

PIC16(L)F1717/8/9

DS40001740A-page 12 Preliminary  2014 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

The PIC16(L)F1717/8/9 devices are described within

this data sheet. They are available in the following

package configurations:

• 28-pin SPDIP, SSOP, SOIC, QFN and UQFN

• 40-pin PDIP and UQFN

• 44-pin TQFP

Figure 1-1 and Figure 1-2 show block diagrams of the

PIC16(L)F1717/8/9 devices. Table 1 - 2 shows the

pinout descriptions.

Reference Table 1-1 for peripherals available per device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16(L)F1717

PIC16(L)F1718

PIC16(L)F1719

Analog-to-Digital Converter (ADC) ●●●

Fixed Voltage Reference (FVR) ●●●

Zero-Cross Detection (ZCD) ●●●

Temperature Indicator ●●●

Complementary Output Generator (COG)

COG ●●●

Numerically Controlled Oscillator (NCO)

NCO ●●●

Digital-to-Analog Converter (DAC)

DAC1 ●●●

DAC2 ●●●

Capture/Compare/PWM (CCP/ECCP) Modules

CCP1 ●●●

CCP2 ●●●

Comparators

C1 ●●●

C2 ●●●

Configurable Logic Cell (CLC)

CLC1 ●●●

CLC2 ●●●

CLC3 ●●●

CLC4 ●●●

Enhanced Universal Synchronous/Asynchronous

Receiver/Transmitter (EUSART)

EUSART ●●●

Master Synchronous Serial Ports

MSSP ●●●

Op Amp

Op Amp 1 ●●●

Op Amp 2 ●●●

Pulse-Width Modulator (PWM)

PWM3 ●●●

PWM4 ●●●

Timers

Timer0 ●●●

Timer1 ●●●

Timer2 ●●●

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 13

PIC16(L)F1717/8/9

FIGURE 1-1: PIC16(L)F1718 BLOCK DIAGRAM

PORTA

PORTB

PORTC

Note 1: See applicable chapters for more information on peripherals.

CPU

Program

Flash Memory

RAM

Timing

Generation

LFINTOSC

Oscillator

MCLR

Figure 2-1: Core Block Diagram

CLKIN

CLKOUT

ADC

10-Bit FVR

Temp .

Indicator EUSART

Comparators

MSSPTimer2Timer1Timer0

DACs CCPs

PWMOp Amps

HFINTOSC/

CLCs

COG

ZCD

NCO

PIC16(L)F1717/8/9

DS40001740A-page 14 Preliminary  2014 Microchip Technology Inc.

FIGURE 1-2: PIC16(L)F1717/9 BLOCK DIAGRAM

PORTA

PORTB

PORTC

Note 1: See applicable chapters for more information on peripherals.

CPU

Program

Flash Memory

RAM

Timing

Generation

LFINTOSC

Oscillator

MCLR

Figure 2-1: Core Block Diagram

CLKIN

CLKOUT

ADC

10-Bit FVR

Temp .

Indicator EUSART

Comparators

MSSPTimer2Timer1Timer0

DACs CCPs

PWMOp Amps

HFINTOSC/

CLCs

COG

ZCD

NCO

PORTD

PORTE

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 15

PIC16(L)F1717/8/9

TABLE 1-2: PIC16(L)F1718 PINOUT DESCRIPTION

Name Function Input

Type

Output

Type Description

RA0/AN0/C1IN0-/C2IN0-/

CLCIN0(1) RA0 TTL/ST CMOS General purpose I/O.

AN0 AN — ADC Channel 0 input.

C1IN0- AN — Comparator C2 negative input.

C2IN0- AN — Comparator C3 negative input.

CLCIN0 TTL/ST — Configurable Logic Cell source input.

RA1/AN1/C1IN1-/C2IN1-/

OPA1OUT/CLCIN1(1)

RA1 TTL/ST CMOS General purpose I/O.

AN1 AN — ADC Channel 1 input.

C1IN1- AN — Comparator C1 negative input.

C2IN1- AN — Comparator C2 negative input.

OPA1OUT — AN Operational Amplifier 1 output.

CLCIN1 TTL/ST — Configurable Logic Cell source input.

RA2/AN2/VREF-/C1IN0+/C2IN0+/

DAC1OUT1

RA2 TTL/ST CMOS General purpose I/O.

AN2 AN — ADC Channel 2 input.

VREF- AN — ADC Negative Voltage Reference input.

C1IN0+ AN — Comparator C2 positive input.

C2IN0+ AN — Comparator C3 positive input.

DAC1OUT1 — AN Digital-to-Analog Converter output.

RA3/AN3/VREF+/C1IN1+ RA3 TTL/ST CMOS General purpose I/O.

AN3 AN — ADC Channel 3 input.

VREF+ AN — ADC Voltage Reference input.

C1IN1+ AN — Comparator C1 positive input.

RA4/OPA1IN+/T0CKI(1) RA4 TTL/ST CMOS General purpose I/O.

OPA1IN+ AN — Operational Amplifier 1 non-inverting input.

T0CKI TTL/ST — Timer0 gate input.

RA5/AN4/OPA1IN-/DAC2OUT1/

SS(1)

RA5 TTL/ST CMOS General purpose I/O.

AN4 AN — ADC Channel 4 input.

OPA1IN- AN — Operational Amplifier 1 inverting input.

DAC2OUT1 — AN Digital-to-Analog Converter output.

SS TTL/ST — Slave Select enable input.

RA6/OSC2/CLKOUT RA6 TTL/ST CMOS General purpose I/O.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS FOSC/4 output.

RA7/OSC1/CLKIN RA7 TTL/ST CMOS General purpose I/O.

OSC1 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKIN ST — External clock input (EC mode).

RB0/AN12/C2IN1+/ZCD/

COGIN(1)

RB0 TTL/ST CMOS General purpose I/O.

AN12 AN — ADC Channel 12 input.

C2IN1+ AN — Comparator C2 positive input.

ZCD AN — Zero-Cross Detection Current Source/Sink.

COGIN TTL/ST CMOS Complementary Output Generator input.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C™

HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

PIC16(L)F1717/8/9

DS40001740A-page 16 Preliminary  2014 Microchip Technology Inc.

RB1/AN10/C1IN3-/C2IN3-/

OPA2OUT

RB1 TTL/ST CMOS General purpose I/O.

AN10 AN — ADC Channel 10 input.

C1IN3- AN — Comparator C1 negative input.

C2IN3- AN — Comparator C2 negative input.

OPA2OUT — AN Operational Amplifier 2 output.

RB2/AN8/OPA2IN- RB2 TTL/ST CMOS General purpose I/O.

AN8 AN — ADC Channel 8 input.

OPA2IN- AN — Operational Amplifier 2 inverting input.

RB3/AN9/C1IN2-/C2IN2-/

OPA2IN+

RB3 TTL/ST CMOS General purpose I/O.

AN9 AN — ADC Channel 9 input.

C1IN2- AN — Comparator C1 negative input.

C2IN2- AN — Comparator C2 negative input.

OPA2IN+ AN — Operational Amplifier 2 non-inverting input.

RB4/AN11 RB4 TTL/ST CMOS General purpose I/O.

AN11 AN — ADC Channel 11 input.

RB5/AN13/T1G(1) RB5 TTL/ST CMOS General purpose I/O.

AN13 AN — ADC Channel 13 input.

T1G TTL/ST — Timer1 gate input.

RB6/CLCIN2(1)/ICSPCLK RB6 TTL/ST CMOS General purpose I/O.

CLCIN2 TTL/ST — Configurable Logic Cell source input.

ICSPCLK ST — Serial Programming Clock.

RB7/DAC1OUT2/DAC2OUT2/

CLCIN3(1)/ICSPDAT

RB7 TTL/ST CMOS General purpose I/O.

DAC1OUT2 — AN Digital-to-Analog Converter output.

DAC2OUT2 — AN Digital-to-Analog Converter output.

CLCIN3 TTL/ST — Configurable Logic Cell source input.

ICSPDAT ST CMOS ICSP™ Data I/O.

RC0/T1CKI(1)/SOSCO RC0 TTL/ST CMOS General purpose I/O.

T1CKI TTL/ST — Timer1 clock input.

SOSCO XTAL XTAL Secondary Oscillator Connection.

RC1/SOSCI/CCP2(1) RC1 TTL/ST CMOS General purpose I/O.

SOSCI XTAL XTAL Secondary Oscillator Connection.

CCP2 TTL/ST — Capture input

RC2/AN14/CCP1(1) RC2 TTL/ST CMOS General purpose I/O.

AN14 AN — ADC Channel 14 input.

CCP1 TTL/ST — Capture input

RC3/AN15/SCK(1)/SCL(1) RC3 TTL/ST CMOS General purpose I/O.

AN15 AN — ADC Channel 15 input.

SCK TTL/ST — SPI clock input

SCL I2C™ — I2C™ clock input.

TABLE 1-2: PIC16(L)F1718 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type

Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C™

HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 17

PIC16(L)F1717/8/9

RC4/AN16/SDI(1)/SDA(1) RC4 TTL/ST CMOS General purpose I/O.

AN16 AN — ADC Channel 16 input.

SDI TTL/ST — SPI Data input.

SDA I2C™ — I2C™ Data input.

RC5/AN17 RC5 TTL/ST CMOS General purpose I/O.

AN17 AN — ADC Channel 17 input.

RC6/AN18/CK(1) RC6 TTL/ST CMOS General purpose I/O.

AN16 AN — ADC Channel 16 input.

CK TTL/ST EUSART synchronous clock.

RC7/AN19/RX(1) RC7 TTL/ST CMOS General purpose I/O.

AN18 AN — ADC Channel 18 input.

RX TTL/ST — EUSART receive.

RE3/MCLR/VPP RE3 TTL/ST — General purpose input.

MCLR ST — Master clear input.

VPP HV — Programming enable.

VDD VDD Power — Positive supply.

VSS VSS Power — Ground reference.

OUT(2) C1OUT CMOS Comparator 1 output.

C2OUT CMOS Comparator 2 output.

CCP1 CMOS Compare/PWM1 output.

CCP2 CMOS Compare/PWM2 output.

NCO1OUT CMOS Numerically controlled oscillator output.

PWM3OUT CMOS PWM3 output.

PWM4OUT CMOS PWM4 output.

COG1A CMOS Complementary output generator output A.

COG1B CMOS Complementary output generator output B.

COG1C CMOS Complementary output generator output C.

COG1D CMOS Complementary output generator output D.

SDA(3) OD I2C™ Data output.

SCK CMOS SPI clock output.

SCL(3) OD I2C™ clock output.

SDO CMOS SPI data output.

TX/CK CMOS EUSART asynchronous TX data/synchronous clock out.

DT(3) CMOS EUSART synchronous data output.

CLC1OUT CMOS Configurable Logic Cell 1 output.

CLC2OUT CMOS Configurable Logic Cell 2 output.

CLC3OUT CMOS Configurable Logic Cell 3 output.

CLC4OUT CMOS Configurable Logic Cell 4 output.

TABLE 1-2: PIC16(L)F1718 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type

Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C™

HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

PIC16(L)F1717/8/9

DS40001740A-page 18 Preliminary  2014 Microchip Technology Inc.

TABLE 1-3: PIC16(L)F1717/9 PINOUT DESCRIPTION

Name Function Input

Type

Output

Type Description

RA0/AN0/C1IN0-/C2IN0-/

CLCIN0(1) RA0 TTL/ST CMOS General purpose I/O.

AN0 AN — ADC Channel 0 input.

C1IN0- AN — Comparator C2 negative input.

C2IN0- AN — Comparator C3 negative input.

CLCIN0 TTL/ST — Configurable Logic Cell source input.

RA1/AN1/C1IN1-/C2IN1-/

OPA1OUT/CLCIN1(1)

RA1 TTL/ST CMOS General purpose I/O.

AN1 AN — ADC Channel 1 input.

C1IN1- AN — Comparator C1 negative input.

C2IN1- AN — Comparator C2 negative input.

OPA1OUT — AN Operational Amplifier 1 output.

CLCIN1 TTL/ST — Configurable Logic Cell source input.

RA2/AN2/VREF-/C1IN0+/C2IN0+/

DAC1OUT1

RA2 TTL/ST CMOS General purpose I/O.

AN2 AN — ADC Channel 2 input.

VREF- AN — ADC Negative Voltage Reference input.

C1IN0+ AN — Comparator C2 positive input.

C2IN0+ AN — Comparator C3 positive input.

DAC1OUT1 — AN Digital-to-Analog Converter output.

RA3/AN3/VREF+/C1IN1+ RA3 TTL/ST CMOS General purpose I/O.

AN3 AN — ADC Channel 3 input.

VREF+ AN — ADC Voltage Reference input.

C1IN1+ AN — Comparator C1 positive input.

RA4/OPA1IN+/T0CKI(1) RA4 TTL/ST CMOS General purpose I/O.

OPA1IN+ AN — Operational Amplifier 1 non-inverting input.

T0CKI TTL/ST — Timer0 gate input.

RA5/AN4/OPA1IN-/DAC2OUT1/

SS(1)

RA5 TTL/ST CMOS General purpose I/O.

AN4 AN — ADC Channel 4 input.

OPA1IN- AN — Operational Amplifier 1 inverting input.

DAC2OUT1 — AN Digital-to-Analog Converter output.

SS — — Slave Select enable input.

RA6/OSC2/CLKOUT RA6 TTL/ST CMOS General purpose I/O.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS FOSC/4 output.

RA7/OSC1/CLKIN RA7 TTL/ST CMOS General purpose I/O.

OSC1 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKIN ST — External clock input (EC mode).

RB0/AN12/C2IN1+/ZCD/

COGIN(1)

RB0 TTL/ST CMOS General purpose I/O.

AN12 AN — ADC Channel 12 input.

C2IN1+ AN — Comparator C2 positive input.

ZCD AN — Zero-Cross Detection Current Source/Sink.

COGIN TTL/ST — Complementary Output Generator input.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C™

HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 19

PIC16(L)F1717/8/9

RB1/AN10/C1IN3-/C2IN3-/

OPA2OUT

RB1 TTL/ST CMOS General purpose I/O.

AN10 AN — ADC Channel 10 input.

C1IN3- AN — Comparator C1 negative input.

C2IN3- AN — Comparator C2 negative input.

OPA2OUT — AN Operational Amplifier 2 output.

RB2/AN8/OPA2IN- RB2 TTL/ST CMOS General purpose I/O.

AN8 AN — ADC Channel 8 input.

OPA2IN- AN — Operational Amplifier 2 inverting input.

RB3/AN9/C1IN2-/C2IN2-/

OPA2IN+

RB3 TTL/ST CMOS General purpose I/O.

AN9 AN — ADC Channel 9 input.

C1IN2- AN — Comparator C1 negative input.

C2IN2- AN — Comparator C2 negative input.

OPA2IN+ AN — Operational Amplifier 2 non-inverting input.

RB4/AN11 RB4 TTL/ST CMOS General purpose I/O.

AN11 AN — ADC Channel 11 input.

RB5/AN13/T1G(1) RB5 TTL/ST CMOS General purpose I/O.

AN13 AN — ADC Channel 13 input.

T1G TTL/ST — Timer1 gate input.

RB6/CLCIN2(1)/ICSPCLK RB6 TTL/ST CMOS General purpose I/O.

CLCIN2 TTL/ST — Configurable Logic Cell source input.

ICSPCLK ST — Serial Programming Clock.

RB7/DAC1OUT2/DAC2OUT2/

CLCIN3(1)/ICSPDAT

RB7 TTL/ST CMOS General purpose I/O.

DAC1OUT2 — AN Digital-to-Analog Converter output.

DAC2OUT2 — AN Digital-to-Analog Converter output.

CLCIN3 TTL/ST — Configurable Logic Cell source input.

ICSPDAT ST CMOS ICSP™ Data I/O.

RC0/T1CKI(1)/SOSCO RC0 TTL/ST CMOS General purpose I/O.

T1CKI ST — Timer1 clock input.

SOSCO XTAL XTAL Secondary Oscillator Connection.

RC1/SOSCI/CCP2(1) RC1 TTL/ST CMOS General purpose I/O.

SOSCI XTAL XTAL Secondary Oscillator Connection.

CCP2 TTL/ST — Capture input.

RC2/AN14/CCP1(1) RC2 TTL/ST CMOS General purpose I/O.

AN14 AN — ADC Channel 14 input.

CCP1 TTL/ST — Capture input.

RC3/AN15/SCK(1)/SCL(1) RC3 TTL/ST CMOS General purpose I/O.

AN15 AN — ADC Channel 15 input.

SCK TTL/ST — SPI clock input.

SCL I2C™ OD I2C™ clock.

TABLE 1-3: PIC16(L)F1717/9 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type

Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C™

HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

PIC16(L)F1717/8/9

DS40001740A-page 20 Preliminary  2014 Microchip Technology Inc.

RC4/AN16/SDI(1)/SDA(1) RC4 TTL/ST CMOS General purpose I/O.

AN16 AN — ADC Channel 16 input.

SDI TTL/ST — SPI Data input.

SDA(3) I2C™ — I2C™ Data input.

RC5/AN17 RC5 TTL/ST CMOS General purpose I/O.

AN17 AN — ADC Channel 17 input.

RC6/AN18/CK(1) RC6 TTL/ST CMOS General purpose I/O.

AN16 AN — ADC Channel 16 input.

CK TTL/ST EUSART synchronous clock.

RC7/AN19/RX(1) RC7 TTL/ST CMOS General purpose I/O.

AN19 AN — ADC Channel 19 input.

RX TTL/ST — EUSART receive.

RDO/AN20 RD0 TTL/ST CMOS General purpose I/O.

AN20 AN — ADC Channel 20 input.

RD1/AN21 RD1 TTL/ST CMOS General purpose I/O.

AN21 AN — ADC Channel 21 input.

RD2/AN22 RD2 TTL/ST CMOS General purpose I/O.

AN22 AN — ADC Channel 22 input.

RD3/AN23 RD3 TTL/ST CMOS General purpose I/O.

AN23 AN — ADC Channel 23 input.

RD4/AN24 RD4 TTL/ST CMOS General purpose I/O.

AN24 AN — ADC Channel 24 input.

RD5/AN25 RD5 TTL/ST CMOS General purpose I/O.

AN25 AN — ADC Channel 25 input.

RD6/AN26 RD6 TTL/ST CMOS General purpose I/O.

AN26 AN — ADC Channel 26 input.

RD7/AN27 RD7 TTL/ST CMOS General purpose I/O.

AN27 AN — ADC Channel 27 input.

RE0/AN5 RE0 TTL/ST CMOS General purpose I/O.

AN5 AN — ADC Channel 5 input.

RE1/AN6 RE1 TTL/ST CMOS General purpose I/O.

AN6 AN — ADC Channel 6 input.

RE2/AN7 RE2 TTL/ST CMOS General purpose I/O.

AN7 AN — ADC Channel 7 input.

RE3/MCLR/VPP RE3 TTL/ST — General purpose input.

MCLR ST — Master clear input.

VPP HV — Programming voltage.

VDD VDD Power — Positive supply.

VSS VSS Power — Ground reference.

TABLE 1-3: PIC16(L)F1717/9 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type

Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C™

HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 21

PIC16(L)F1717/8/9

OUT(2) C1OUT CMOS Comparator 1 output.

C2OUT CMOS Comparator 2 output.

CCP1 CMOS Compare/PWM1 output.

CCP2 CMOS Compare/PWM2 output.

NCO1OUT CMOS Numerically controlled oscillator output.

PWM3OUT CMOS PWM3 output.

PWM4OUT CMOS PWM4 output.

COG1A CMOS Complementary output generator output A.

COG1B CMOS Complementary output generator output B.

COG1C CMOS Complementary output generator output C.

COG1D CMOS Complementary output generator output D.

SDA(3) OD I2C™ Data output.

SCK CMOS SPI clock output.

SCL(3) OD I2C™ clock output.

SDO CMOS SPI data output.

TX/CK CMOS EUSART asynchronous TX data/synchronous clock out.

DT(3) CMOS EUSART synchronous data output.

CLC1OUT CMOS Configurable Logic Cell 1 output.

CLC2OUT CMOS Configurable Logic Cell 2 output.

CLC3OUT CMOS Configurable Logic Cell 3 output.

CLC4OUT CMOS Configurable Logic Cell 4 output.

TABLE 1-3: PIC16(L)F1717/9 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type

Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C™

HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.

2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with

the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

PIC16(L)F1717/8/9

DS40001740A-page 22 Preliminary  2014 Microchip Technology Inc.

2.0 ENHANCED MID-RANGE CPU

This family of devices contains an enhanced mid-range

8-bit CPU core. The CPU has 49 instructions. Interrupt

capability includes automatic context saving. The

hardware stack is 16 levels deep and has Overflow and

Underflow Reset capability. Direct, Indirect and

Relative addressing modes are available. Two File

Select Registers (FSRs) provide the ability to read

program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

FIGURE 2-1: CORE BLOCK DIAGRAM

Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

VDD

Brown-out

Reset

VSS

Internal

Oscillator

Block

Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

VDD

VSS

Internal

Oscillator

Block

15 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr 7

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

VDD

VSS

Internal

Oscillator

Block

RAM

FSR regFSR reg

FSR1 Reg

MUX

Program Memory

Read (PMR)

FSR regFSR reg

BSR Reg

ConfigurationConfigurationConfiguration

Flash

Program

Memory

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 23

PIC16(L)F1717/8/9

2.1 Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 7.5 “Automatic Context Saving”

for more information.

2.2 16-Level Stack with Overflow and

Underflow

These devices have a hardware stack memory 15 bits

wide and 16 words deep. A Stack Overflow or

Underflow will set the appropriate bit (STKOVF or

STKUNF) in the PCON register, and if enabled, will

cause a software Reset. See Section 3.5 “Stack” for

more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers and program memory,

which allows one Data Pointer for all memory. When an

FSR points to program memory, there is one additional

instruction cycle in instructions using INDF to allow the

data to be fetched. General purpose memory can now

also be addressed linearly, providing the ability to

access contiguous data larger than 80 bytes. There are

also new instructions to support the FSRs. See

Section 3.6 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 33.0 “Instruction Set Summary” for more

details.

PIC16(L)F1717/8/9

DS40001740A-page 24 Preliminary  2014 Microchip Technology Inc.

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

-Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

The following features are associated with access and

control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program

counter capable of addressing a 32K x 14 program

memory space. Table 3-1 shows the memory sizes

implemented for the PIC16(L)F1717/8/9 family.

Accessing a location above these boundaries will cause

a wrap-around within the implemented memory space.

The Reset vector is at 0000h and the interrupt vector is

at 0004h (see Figure 3-1).

Note 1: The method to access Flash memory

through the PMCON registers is described

in Section 10.0 “Flash Program Memory

Control”.

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC16(L)F1717 8,192 1FFFh

PIC16(L)F1718/9 16,384 3FFFh

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 25

PIC16(L)F1717/8/9

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR

PIC16(L)F1717

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR

PIC16(L)F1718/9

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh

1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

Page 2

Page 3

17FFh

1800h

1FFFh

2000h

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh

1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

Page 2

Page 3

Page 4

Page 5

Page 6

Page 7

1FFFh

2000h

17FFh

1800h

27FFh

2800h

2FFFh

3000h

37FFh

3800h

3FFFh

4000h

PIC16(L)F1717/8/9

DS40001740A-page 26 Preliminary  2014 Microchip Technology Inc.

3.1.1 READING PROGRAM MEMORY AS

DATA

There are two methods of accessing constants in

program memory. The first method is to use tables of

RETLW instructions. The second method is to set an

FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very

simple to implement. If your code must remain portable

with previous generations of microcontrollers, then the

BRW instruction is not available, so the older table read

method must be used.

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by

setting bit 7 of the FSRxH register and reading the

matching INDFx register. The MOVIW instruction will

place the lower eight bits of the addressed word in the

W register. Writes to the program memory cannot be

performed via the INDF registers. Instructions that

access the program memory via the FSR require one

extra instruction cycle to complete. Example 3-2

demonstrates accessing the program memory via an

FSR.

The high directive will set bit<7> if a label points to a

location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks

with 128 bytes in a bank. Each bank consists of (see

Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented

memory will read as ‘0’. All data memory can be

accessed either directly (via instructions that use the

file registers) or indirectly via the two File Select

Registers (FSR). See Section 3.6 “Indirect

Addressing” for more information.

Data memory uses a 12-bit address. The upper five bits

of the address define the Bank address and the lower

seven bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERS

The core registers contain the registers that directly

affect the basic operation. The core registers occupy

the first 12 addresses of every data memory bank

(addresses x00h/x08h through x0Bh/x8Bh). These

registers are listed below in Ta bl e 3 -2 . For detailed

information, see Tabl e 3 -11.

TABLE 3-2: CORE REGISTERS

constants

BRW ;Add Index in W to

;program counter to

;select data

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

call constants

;… THE CONSTANT IS IN W

constants

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW LOW constants

MOVWF FSR1L

MOVLW HIGH constants

MOVWF FSR1H

MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

Addresses BANKx

x00h or x80h INDF0

x01h or x81h INDF1

x02h or x82h PCL

x03h or x83h STATUS

x04h or x84h FSR0L

x05h or x85h FSR0H

x06h or x86h FSR1L

x07h or x87h FSR1H

x08h or x88h BSR

x09h or x89h WREG

x0Ah or x8Ah PCLATH

x0Bh or x8Bh INTCON

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PIC16(L)F1717/8/9

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• The arithmetic status of the ALU

• The Reset status

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 33.0

“Instruction Set Summary”).

Note: The C and DC bits operate as Borrow and

Digit Borrow out bits, respectively, in

subtraction.

PIC16(L)F1717/8/9

DS40001740A-page 28 Preliminary  2014 Microchip Technology Inc.

3.3 Register Definitions: Status

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —TOPD ZDC

(1) C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT Time-out occurred

bit 3 PD: Power-Down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand.

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 29

PIC16(L)F1717/8/9

3.3.1 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by

the application to control the desired operation of

peripheral functions in the device. The Special Function

Registers occupy the 20 bytes after the core registers of

every data memory bank (addresses x0Ch/x8Ch

through x1Fh/x9Fh). The registers associated with the

operation of the peripherals are described in the

appropriate peripheral chapter of this data sheet.

3.3.2 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory

bank. The Special Function Registers occupy the 20

bytes after the core registers of every data memory

bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.3.2.1 Linear Access to GPR

The general purpose RAM can be accessed in a

non-banked method via the FSRs. This can simplify

access to large memory structures. See Section 3.6.2

“Linear Data Memory” for more information.

3.3.3 COMMON RAM

There are 16 bytes of common RAM accessible from all

banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

3.3.4 DEVICE MEMORY MAPS

The memory maps for the device family are as shown

in Table 3-3 through Tabl e 3- 1 0.

0Bh

0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

PIC16(L)F1717/8/9

DS40001740A-page 30 Preliminary  2014 Microchip Technology Inc.

TABLE 3-3: PIC16(L)F1718 MEMORY MAP (BANKS 0-7)

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: Unimplemented on PIC16LF1717/8/9.

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Tabl e 3- 2 )

080h

Core Registers

(Tabl e 3- 2 )

100h

Core Registers

(Table 3-2)

180h

Core Registers

(Table 3-2)

200h

Core Registers

(Table 3-2)

280h

Core Registers

(Table 3-2)

300h

Core Registers

(Table 3-2)

380h

Core Registers

(Table 3-2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh

00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA

00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB

00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC

00Fh —08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

010h PORTE 090h TRISE 110h —190h— 210h WPUE 290h — 310h — 390h INLVLE

011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP

012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN

013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF

014h —094h— 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h — 314h — 394h IOCBP

015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h — 315h — 395h IOCBN

016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h IOCBF

017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h SSP1CON3 297h — 317h — 397h IOCCP

018h T1CON 098h OSCTUNE 118h DAC1CON0 198h —218h— 298h CCPR2L 318h — 398h IOCCN

019h T1GCON 099h OSCCON 119h DAC1CON1 199h RC1REG 219h — 299h CCPR2H 319h — 399h IOCCF

01Ah TMR2 09Ah OSCSTAT 11Ah DAC2CON0 19Ah TX1REG 21Ah — 29Ah CCP2CON 31Ah —39Ah—

01Bh PR2 09Bh ADRESL 11Bh DAC2CON1 19Bh SP1BRGL 21Bh —29Bh—31Bh—39Bh—

01Ch T2CON 09Ch ADRESH 11Ch ZCD1CON 19Ch SP1BRGH 21Ch — 29Ch — 31Ch — 39Ch —

01Dh — 09Dh ADCON0 11Dh — 19Dh RC1STA 21Dh — 29Dh — 31Dh — 39Dh IOCEP

01Eh — 09Eh ADCON1 11Eh — 19Eh TX1STA 21Eh — 29Eh CCPTMRS 31Eh —39EhIOCEN

01Fh — 09Fh ADCON2 11Fh — 19Fh BAUD1CON 21Fh —29Fh—31Fh—39FhIOCEF

020h

General

Purpose

80 Bytes

0A0h

General

Purpose

80 Bytes

120h

General

Purpose

80 Bytes

1A0h

General

Purpose

80 Bytes

220h

General

Purpose

80 Bytes

2A0h

General

Purpose

80 Bytes

320h

General

Purpose

80 Bytes

3A0h

General

Purpose

80 Bytes

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

070h

Common RAM

70h – 7Fh

0F0h

Accesses

70h – 7Fh

170h

Accesses

70h – 7Fh

1F0h

Accesses

70h – 7Fh

270h

Accesses

70h – 7Fh

2F0h

Accesses

70h – 7Fh

370h

Accesses

70h – 7Fh

3F0h

Accesses

70h – 7Fh

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

 2014 Microchip Technology Inc. Preliminary DS40001740A-page 31

PIC16(L)F1717/8/9

TABLE 3-4: PIC16(L)F1717/9 MEMORY MAP (BANKS 0-7)

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: Unimplemented on PIC16LF1717/8/9.

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Tabl e 3- 2 )

080h

Core Registers

(Tabl e 3- 2 )

100h

Core Registers

(Table 3-2)

180h

Core Registers

(Table 3-2)

200h

Core Registers

(Table 3-2)

280h

Core Registers

(Table 3-2)

300h

Core Registers

(Table 3-2)

380h

Core Registers

(Table 3-2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh

00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA

00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB

00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC

00Fh PORTD 08Fh TRISD 10Fh LATD 18Fh ANSELD 20Fh WPUD 28Fh ODCOND 30Fh SLRCOND 38Fh INLVLE

010h PORTE 090h TRISE 110h LATE 190h ANSELE 210h WPUE 290h ODCONE 310h SLRCONE 390h INLVLE