Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Features
zHigh-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
zNonvolatile program and data memories
64K - 256KBytes of in-system self-programmable flash
4K - 8KBytes boot section
2K - 4KBytes EEPROM
4K - 16KBytes internal SRAM
zPeripheral features
Four-channel DMA controller
Eight-channel event system
Seven 16-bit timer/counters
zFour timer/counters with four output compare or input capture channels
zThree timer/counters with two output compare or input capture channels
zHigh resolution extension on all timer/counters
zAdvanced waveform extension (AWeX) on one timer/counter
One USB device interface
zUSB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
z32 Endpoints with full configuration flexibility
Seven USARTs with IrDA support for one USART
Two two-wire interfaces with dual address match (I2C and SMBus compatible)
Three serial peripheral interfaces (SPIs)
AES and DES crypto engine
CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator
16-bit real time counter (RTC) with separate oscillator
Two sixteen-channel, 12-bit, 2msps Analog to Digital Converters
One two-channel, 12-bit, 1msps Digital to Analog Converter
Four Analog Comparators with window compare function, and current
sources
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power
oscillator
QTouch® library support
zCapacitive touch buttons, sliders and wheels
zSpecial microcontroller features
Power-on reset and programmable brown-out detection
Internal and external clock options with PLL and prescaler
Programmable multilevel interrupt controller
Five sleep modes
8/16-bit Atmel XMEGA A3U Microcontroller
ATxmega256A3U / ATxmega192A3U /
ATxmega128A3U / ATxmega64A3U
DATASHEET
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Programming and debug interfaces
zJTAG (IEEE 1149.1 compliant) interface, including boundary scan
zPDI (program and debug interface)
zI/O and packages
50 Programmable I/O pins
64-lead TQFP
64-pad QFN
zOperating voltage
1.6 – 3.6V
zOperating frequency
0 – 12MHz from 1.6V
0 – 32MHz from 2.7V
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1. Ordering Information
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
Ordering code Flash (bytes)
EEPROM
(bytes)
SRAM
(bytes) Speed (MHz)
Power
supply
Package
(1)(2)(3) Temp.
ATxmega256A3U-AU 256K + 8K 4K 16K
32 1.6 - 3.6V
64A
-40°C - 85°C
ATxmega256A3U-AUR(4) 256K + 8K 4K 16K
ATxmega192A3U-AU 192K + 8K 2K 16K
ATxmega192A3U-AUR(4) 192K + 8K 2K 16K
ATxmega128A3U-AU 128K + 8K 2K 8K
ATxmega128A3U-AUR(4) 128K + 8K 2K 8K
ATxmega64A3U-AU 64K + 4K 2K 4K
ATxmega64A3U-AUR(4) 64K + 4K 2K 4K
ATxmega256A3U-MH 256K + 8K 4K 16K
64M2
ATxmega256A3U-MHR(4) 256K + 8K 4K 16K
ATxmega192A3U-MH 192K + 8K 2K 16K
ATxmega192A3U-MHR(4) 192K + 8K 2K 16K
ATxmega128A3U-MH 128K + 8K 2K 8K
ATxmega128A3U-MHR(4) 128K + 8K 2K 8K
ATxmega64A3U-MH 64K + 4K 2K 4K
ATxmega64A3U-MHR(4) 64K + 4K 2K 4K
ATxmega256A3U-AN 256K + 8K 4K 16K
32 1.6 - 3.6V
64A
-40°C - 105°C
ATxmega256A3U-ANR(4) 256K + 8K 4K 16K
ATxmega192A3U-AN 192K + 8K 2K 16K
ATxmega192A3U-ANR(4) 192K + 8K 2K 16K
ATxmega128A3U-AN 128K + 8K 2K 8K
ATxmega128A3U-ANR(4) 128K + 8K 2K 8K
ATxmega64A3U-AN 64K + 4K 2K 4K
ATxmega64A3U-ANR(4) 64K + 4K 2K 4K
ATxmega256A3U-MN 256K + 8K 4K 16K
64M2
ATxmega256A3U-MNR(4) 256K + 8K 4K 16K
ATxmega192A3U-MN 192K + 8K 2K 16K
ATxmega192A3U-MHR(4) 192K + 8K 2K 16K
ATxmega128A3U-MN 128K + 8K 2K 8K
ATxmega128A3U-MNR(4) 128K + 8K 2K 8K
ATxmega64A3U-MN 64K + 4K 2K 4K
ATxmega64A3U-MNR(4) 64K + 4K 2K 4K
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3. For packaging information, see “Packaging information” on page 71.
4. Tape and Reel.
Typical Applications
Package Type
64A 64-lead, 14 x 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)
64M2 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, 7.65mm exposed pad, quad flat no-lead package (QFN)
Industrial control Climate control Low power battery applications
Factory automation RF and ZigBee®Power tools
Building control USB connectivity HVAC
Board control Sensor control Utility metering
White goods Optical Medical applications
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2. Pinout/Block Diagram
Figure 2-1. Block diagram and pinout.
Note: 1. For full details on pinout and alternate pin functions refer to “Pinout and Pin Functions” on page 59.
1
2
3
4
64
63
62
61
60
59
58
VCC
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
GND
VCC
AVCC
GND
PB0
PB1
PB3
PB2
PB7
PB5
PB4
PB6
PA7
PA6
PA0
PA1
PA2
PA3
PA4
PA5
RESET/PDI
PDI
PR0
PR1
VCC
GND
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VCC
GND
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
VCC
GND
Digital function
Analog function / Oscillators
Programming, debug, test
External clock / Crystal pins
General Purpose I /O
Ground
Power
Power
Supervision
Port A
EVENT ROUTING NETWORK
DMA
Controller
BUS
matrix
SRAMFLASH
ADC
AC0:1
OCD
Port EPort D
Prog/Debug
Interface
EEPROM
Port C
TC0:1
Event System
Controller
Watchdog
Timer
Internal
oscillators
OSC/CLK
Control
Real Time
Counter
Interrupt
Controller
DATA BUS
DATA BUS
Port R
USART0:1
TWI
SPI
TC0:1
USART0:1
SPI
TC0:1
USART0:1
TWI
Port B
ADC
DAC
AC0:1
AREF
JTAG
AREF
Sleep
Controller
Reset
Controller
Internal
references
IRCOM
USB
Port F
TC0:1
USART0
CPU
SPI
XOSC
TOSC
Crypto /
CRC
Watchdog
oscillator
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3. Overview
The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers
based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR
XMEGA device achieves throughputs CPU approaching one million instructions per second (MIPS) per
megahertz, allowing the system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are
directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a
single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs many times faster than conventional single-accumulator or CISC based microcontrollers.
The AVR XMEGA A3U devices provide the following features: in-system programmable flash with read-while-
write capabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and
programmable multilevel interrupt controller, 50 general purpose I/O lines, 16-bit real-time counter (RTC); seven
flexible, 16-bit timer/counters with compare and PWM channels; seven USARTs; two two-wire serial interfaces
(TWIs); one full speed USB 2.0 interface; three serial peripheral interfaces (SPIs); AES and DES cryptographic
engine; two 16-channel, 12-bit ADCs with programmable gain; one 2-channel 12-bit DAC; four analog
comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate
internal oscillators with PLL and prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available.
The devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for boundary
scan, on-chip debug and programming.
The ATx devices have five software selectable power saving modes. The idle mode stops the CPU while
allowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue
functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling
all other functions until the next TWI, USB resume, or pin-change interrupt, or reset. In power-save mode, the
asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest
of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the
device is sleeping. This allows very fast startup from the external crystal, combined with low power
consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run.
To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be
stopped in active mode and idle sleep mode.
Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into
AVR microcontrollers.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash
memory can be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the
device can use any interface to download the application program to the flash memory. The boot loader
software in the boot flash section will continue to run while the application flash section is updated, providing
true read-while-write operation. By combining an 8/16-bit RISC CPU with in-system, self-programmable flash,
the AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost effective solution for
many embedded applications.
All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
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3.1 Block Diagram
Figure 3-1. XMEGA A3U block diagram.
Power
Supervision
POR/BOD &
RESET
PORT A (8)
PORT B (8)
DMA
Controller
SRAM
ADCA
ACA
DACB
ADCB
ACB
OCD
PDI
PA[0..7]
PB[0..7]/
JTAG
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
Prog/Debug
Controller
VCC
GND
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Real Time
Counter
Event System
Controller
JTAG
AREFA
AREFB
PDI_DATA
RESET/
PDI_CLK
PORT B
Sleep
Controller
DES
CRC
PORT C (8)
PC[0..7]
TCC0:1
USARTC0:1
TWIC
SPIC
PD[0..7] PE[0..7]
PORT D (8)
TCD0:1
USARTD0:1
SPID
TCE0:1
USARTE0:1
TWIE
SPIE
PORT E (8)
AES
USB
PORT R (2)
XTAL1
XTAL2
PR[0..1]
DATA BUS
NVM Controller
MORPEEhsalF
IRCOM
BUS Matrix
CPU
TOSC1
TOSC2
TCF0
USARTF0
PF[0..7]
PORT F (8)
EVENT ROUTING NETWORK
To Clock
Generator
Int. Refs.
Tempref
Digital function
Analog function
Programming, debug, test
Oscillator/Crystal/Clock
General Purpose I/O
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4. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
4.1 Recommended reading
zAtmel AVR XMEGA AU manual
zXMEGA application notes
This device data sheet only contains part specific information with a short description of each peripheral and
module. The XMEGA AU manual describes the modules and peripherals in depth. The XMEGA application
notes contain example code and show applied use of the modules and peripherals.
All documentations are available from www.atmel.com/avr.
5. Capacitive touch sensing
The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel
AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully
debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for
unambiguous detection of key events. The QTouch library includes support for the QTouch and QMatrix
acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR
microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then
calling the touch sensing APIs to retrieve the channel information and determine the touch sensor states.
The QTouch library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the QTouch library
user guide - also available for download from the Atmel website.
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6. AVR CPU
6.1 Features
z8/16-bit, high-performance Atmel AVR RISC CPU
142 instructions
Hardware multiplier
z32x8-bit registers directly connected to the ALU
zStack in RAM
zStack pointer accessible in I/O memory space
zDirect addressing of up to 16MB of program memory and 16MB of data memory
zTrue 16/24-bit access to 16/24-bit I/O registers
zEfficient support for 8-, 16-, and 32-bit arithmetic
zConfiguration change protection of system-critical features
6.2 Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code
and perform all calculations. The CPU is able to access memories, perform calculations, control peripherals,
and execute the program in the flash memory. Interrupt handling is described in a separate section, refer to
“Interrupts and Programmable Multilevel Interrupt Controller” on page 30.
6.3 Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate
memories and buses for program and data. Instructions in the program memory are executed with single-level
pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory.
This enables instructions to be executed on every clock cycle. For details of all AVR instructions, refer to
http://www.atmel.com/avr.
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Figure 6-1. Block diagram of the AVR CPU architecture.
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a
constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic
operation, the status register is updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers
all have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between
registers or between a register and an immediate. Six of the 32 registers can be used as three 16-bit address
pointers for program and data space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different
memory spaces.
The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can
be memory mapped in the data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as
the I/O memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from
0x00 to 0x3F. The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here
must be accessed as data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five
different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.
The program memory is divided in two sections, the application program section and the boot program section.
Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for
self-programming of the application flash memory must reside in the boot program section. The application
section contains an application table section with separate lock bits for write and read/write protection. The
application table section can be used for safe storing of nonvolatile data in the program memory.
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6.4 ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a
constant and a register. Single-register operations can also be executed. The ALU operates in direct connection
with all 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed and the result is stored in the register file. After
an arithmetic or logic operation, the status register is updated to reflect information about the result of the
operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The
hardware multiplier supports signed and unsigned multiplication and fractional format.
6.4.1 Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports
different variations of signed and unsigned integer and fractional numbers:
zMultiplication of unsigned integers
zMultiplication of signed integers
zMultiplication of a signed integer with an unsigned integer
zMultiplication of unsigned fractional numbers
zMultiplication of signed fractional numbers
zMultiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
6.5 Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The
program counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the
whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-
bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the
general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the
SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is
read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas.
The data SRAM can easily be accessed through the five different addressing modes supported in the AVR
CPU.
6.6 Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or
logic instruction. This information can be used for altering program flow in order to perform conditional
operations. Note that the status register is updated after all ALU operations, as specified in the instruction set
reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in
faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning
from an interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
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6.7 Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for
storing temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented
as two 8-bit registers that are accessible in the I/O memory space. Data are pushed and popped from the stack
using the PUSH and POP instructions. The stack grows from a higher memory location to a lower memory
location. This implies that pushing data onto the stack decreases the SP, and popping data off the stack
increases the SP. The SP is automatically loaded after reset, and the initial value is the highest address of the
internal SRAM. If the SP is changed, it must be set to point above address 0x2000, and it must be defined
before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return
address can be two or three bytes, depending on program memory size of the device. For devices with 128KB
or less of program memory, the return address is two bytes, and hence the stack pointer is
decremented/incremented by two. For devices with more than 128KB of program memory, the return address is
three bytes, and hence the SP is decremented/incremented by three. The return address is popped off the stack
when returning from interrupts using the RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented
by one when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable
interrupts for up to four instructions or until the next I/O memory write.
After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-3 on page 16.
6.8 Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The
register file supports the following input/output schemes:
zOne 8-bit output operand and one 8-bit result input
zTwo 8-bit output operands and one 8-bit result input
zTwo 8-bit output operands and one 16-bit result input
zOne 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling
efficient address calculations. One of these address pointers can also be used as an address pointer for lookup
tables in flash program memory.
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7. Memories
7.1 Features
zFlash program memory
One linear address space
In-system programmable
Self-programming and boot loader support
Application section for application code
Application table section for application code or data storage
Boot section for application code or boot loader code
Separate read/write protection lock bits for all sections
Built in fast CRC check of a selectable flash program memory section
zData memory
One linear address space
Single-cycle access from CPU
SRAM
EEPROM
zByte and page accessible
zOptional memory mapping for direct load and store
I/O memory
zConfiguration and status registers for all peripherals and modules
z16 bit-accessible general purpose registers for global variables or flags
Bus arbitration
zDeterministic priority handling between CPU, DMA controller, and other bus masters
Separate buses for SRAM, EEPROM and I/O memory
zSimultaneous bus access for CPU and DMA controller
zProduction signature row memory for factory programmed data
ID for each microcontroller device type
Serial number for each device
Calibration bytes for factory calibrated peripherals
zUser signature row
One flash page in size
Can be read and written from software
Content is kept after chip erase
7.2 Overview
The Atmel AVR architecture has two main memory spaces, the program memory and the data memory.
Executable code can reside only in the program memory, while data can be stored in the program memory and
the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All
memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be
locked for further write and read/write operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions,
and can only be written by an external programmer.
The available memory size configurations are shown in “Ordering Information” on page 3. In addition, each
device has a Flash memory signature row for calibration data, device identification, serial number etc.
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7.3 Flash Program Memory
The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program
storage. The flash memory can be accessed for read and write from an external programmer through the PDI or
from application software running in the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is
organized in two main sections, the application section and the boot loader section. The sizes of the different
sections are fixed, but device-dependent. These two sections have separate lock bits, and can have different
levels of protection. The store program memory (SPM) instruction, which is used to write to the flash from the
application software, will only operate when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe
storage of nonvolatile data in the program memory.
Table 7-1. Flash Program Memory (Hexadecimal address).
7.3.1 Application Section
The Application section is the section of the flash that is used for storing the executable application code. The
protection level for the application section can be selected by the boot lock bits for this section. The application
section can not store any boot loader code since the SPM instruction cannot be executed from the application
section.
7.3.2 Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing
data. The size is identical to the boot loader section. The protection level for the application table section can be
selected by the boot lock bits for this section. The possibilities for different protection levels on the application
section and the application table section enable safe parameter storage in the program memory. If this section
is not used for data, application code can reside here.
7.3.3 Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located
in the boot loader section because the SPM instruction can only initiate programming when executing from this
section. The SPM instruction can access the entire flash, including the boot loader section itself. The protection
level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot
loader software, application code can be stored here.
Word Address
ATxmega256A3U ATxmega192A3U ATxmega128A3U ATxmega64A3U
0000
Application Section
(256K/192K/128K/64K)
...
1EFFF / 16FFF / 37FF / 77FF
1F000 / 17000 / EFFF / 7800 Application Table Section
(8K/8K/8K/4K)
1FFFF / 17FFF / F000 / 7FFF
20000 / 18000 / 10000 / 8000 Boot Section
(8K/8K/8K/4K)
20FFF/ 18FFF/ 10FFF/ 87FF
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7.3.4 Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration
data for functions such as oscillators and analog modules. Some of the calibration values will be automatically
loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the
signature row and written to the corresponding peripheral registers from software. For details on calibration
conditions, refer to “Electrical Characteristics” on page 73.
The production signature row also contains an ID that identifies each microcontroller device type and a serial
number for each manufactured device. The serial number consists of the production lot number, wafer number,
and wafer coordinates for the device. The device ID for the available devices is shown in Table 7-2.
The production signature row cannot be written or erased, but it can be read from application software and
external programmers.
Table 7-2. Device ID bytes for Atmel AVR XMEGA A3U devices.
7.3.5 User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application
software and external programmers. It is one flash page in size, and is meant for static user parameter storage,
such as calibration data, custom serial number, identification numbers, random number seeds, etc. This section
is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. This
ensures parameter storage during multiple program/erase operations and on-chip debug sessions.
7.4 Fuses and Lock bits
The fuses are used to configure important system functions, and can only be written from an external
programmer. The application software can read the fuses. The fuses are used to configure reset sources such
as brownout detector and watchdog, startup configuration, JTAG enable, and JTAG user ID.
The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access
should be blocked). Lock bits can be written by external programmers and application software, but only to
stricter protection levels. Chip erase is the only way to erase the lock bits. To ensure that flash contents are
protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the
value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
7.5 Data Memory
The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external
memory if available. The data memory is organized as one continuous memory section, see Table 7-3 on page
16. To simplify development, I/O Memory, EEPROM and SRAM will always have the same start addresses for
all Atmel AVR XMEGA devices.
Device Device ID bytes
Byte 2 Byte 1 Byte 0
ATxmega64A3U 42 96 1E
ATxmega128A3U 42 97 1E
ATxmega192A3U 44 97 1E
ATxmega256A3U 42 98 1E
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Table 7-3. Data memory map (Hexadecimal address).
7.6 EEPROM
XMEGA AU devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data
space (default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and
page access. Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading.
When doing this, EEPROM is accessible using load and store instructions. Memory mapped EEPROM will
always start at hexadecimal address 0x1000.
7.7 I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through
I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD)
instructions, which are used to transfer data between the 32 registers in the register file and the I/O memory.
The IN and OUT instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the
address range 0x00 - 0x1F, single-cycle instructions for manipulation and checking of individual bits are
available.
The I/O memory address for all peripherals and modules in XMEGA A3U is shown in the “Peripheral Module
Address Map” on page 64.
7.7.1 General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be
used for storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and
SBIC instructions.
Byte Address ATxmega192A3U Byte Address ATxmega128A3U Byte Address ATxmega64A3U
0
I/O Registers (4K)
0
I/O Registers (4K)
0
I/O Registers (4K)
FFF FFF FFF
1000
EEPROM (2K)
1000
EEPROM (2K)
1000
EEPROM (2K)
17FF 17FF 17FF
RESERVED RESERVED RESERVED
2000 Internal
SRAM (16K)
2000
Internal SRAM (8K)
2000
Internal SRAM (4K)
5FFF 3FFF 2FFF
Byte Address ATxmega256A3U
0
I/O Registers (4K)
FFF
1000
EEPROM (4K)
13FF
RESERVED
2000 Internal
SRAM (16K)
27FF
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7.8 Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA
controller read and DMA controller write, etc.) can access different memory sections at the same time.
7.9 Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a
read from SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page
load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every
second cycle. Refer to the instruction summary for more details on instructions and instruction timing.
7.10 Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the
device type. A separate register contains the revision number of the device.
7.11 JTAG Disable
It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG
access to the device until the next device reset or until JTAG is enabled again from the application software. As
long as JTAG is disabled, the I/O pins required for JTAG can be used as normal I/O pins.
7.12 I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to
lock the I/O register related to the clock system, the event system, and the advanced waveform extensions. As
long as the lock is enabled, all related I/O registers are locked and they can not be written from the application
software. The lock registers themselves are protected by the configuration change protection mechanism.
7.13 Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible
for the flash and byte accessible for the EEPROM.
Table 7-4 on page 17 shows the Flash Program Memory organization and Program Counter (PC) size. Flash
write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a
time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address
(FPAGE) give the page number and the least significant address bits (FWORD) give the word in the page.
Table 7-4. Number of words and pages in the flash.
Table 7-5 on page 18 shows EEPROM memory organization for the Atmel AVR XMEGA A3U devices.
EEEPROM write and erase operations can be performed one page or one byte at a time, while reading the
EEPROM is done one byte at a time. For EEPROM access the NVM address register (ADDR[m:n]) is used for
Devices PC size Flash size Page Size FWORD FPAGE Application Boot
bits bytes words Size No of
pages Size No of
pages
ATxmega64A3U 16 64K + 4K 128 Z[7:1] Z[16:8] 64K 256 4K 16
ATxmega128A3U 17 128K + 8K 256 Z[8:1] Z[17:9] 128K 256 8K 16
ATxmega192A3U 17 192K + 8K 256 Z[8:1] Z[17:9] 192K 384 8K 16
ATxmega256A3U 18 256K + 8K 256 Z[8:1] Z[18:9] 256K 512 8K 16
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addressing. The most significant bits in the address (E2PAGE) give the page number and the least significant
address bits (E2BYTE) give the byte in the page.
Table 7-5. Number of bytes and pages in the EEPROM.
Devices EEPROM Page Size E2BYTE E2PAGE No of Pages
Size bytes
ATxmega64A3U 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega128A3U 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega192A3U 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega256A3U 4K 32 ADDR[4:0] ADDR[11:5] 128
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8. DMAC – Direct Memory Access Controller
8.1 Features
zAllows high speed data transfers with minimal CPU intervention
from data memory to data memory
from data memory to peripheral
from peripheral to data memory
from peripheral to peripheral
zFour DMA channels with separate
transfer triggers
interrupt vectors
addressing modes
zProgrammable channel priority
zFrom 1 byte to 16MB of data in a single transaction
Up to 64KB block transfers with repeat
1, 2, 4, or 8 byte burst transfers
zMultiple addressing modes
Static
Incremental
Decremental
zOptional reload of source and destination addresses at the end of each
Burst
Block
Transaction
zOptional interrupt on end of transaction
zOptional connection to CRC generator for CRC on DMA data
8.2 Overview
The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals,
and thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention,
and frees up CPU time. The four DMA channels enable up to four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly
between peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer
of data to/from communication modules. The DMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size
from 1 byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to
16MB. Source and destination addressing can be static, incremental or decremental. Automatic reload of
source and/or destination addresses can be done after each burst or block transfer, or when a transaction is
complete. Application software, peripherals, and events can trigger DMA transfers.
The four DMA channels have individual configuration and control settings. This include source, destination,
transfer triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be
generated when a transaction is complete or when the DMA controller detects an error on a DMA channel.
To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer
when the first is finished, and vice versa.
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9. Event System
9.1 Features
zSystem for direct peripheral-to-peripheral communication and signaling
zPeripherals can directly send, receive, and react to peripheral events
CPU and DMA controller independent operation
100% predictable signal timing
Short and guaranteed response time
zEight event channels for up to eight different and parallel signal routing configurations
zEvents can be sent and/or used by most peripherals, clock system, and software
zAdditional functions include
Quadrature decoders
Digital filtering of I/O pin state
zWorks in active mode and idle sleep mode
9.2 Overview
The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in
one peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable
system for short and predictable response times between peripherals. It allows for autonomous peripheral
control and interaction without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful
tool for reducing the complexity, size and execution time of application code. It also allows for synchronized
timing of actions in several peripheral modules.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the
event routing network. How events are routed and used by the peripherals is configured in software.
Figure 9-1 on page 21 shows a basic diagram of all connected peripherals. The event system can directly
connect together analog and digital converters, analog comparators, I/O port pins, the real-time counter,
timer/counters, IR communication module (IRCOM), and USB interface. It can also be used to trigger DMA
transactions (DMA controller). Events can also be generated from software and the peripheral clock.
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Figure 9-1. Event system overview and connected peripherals.
The event routing network consists of eight software-configurable multiplexers that control how events are
routed and used. These are called event channels, and allow for up to eight parallel event routing
configurations. The maximum routing latency is two peripheral clock cycles. The event system works in both
active mode and idle sleep mode.
DAC
Timer /
Counters
USB
ADC
Real Time
Counter
Port pins
CPU /
Software
DMA
Controller
IRCOM
Event Routing Network
Event
System
Controller
clkPER
Prescaler
AC
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10. System Clock and Clock options
10.1 Features
zFast start-up time
zSafe run-time clock switching
zInternal oscillators:
32MHz run-time calibrated and tuneable oscillator
2MHz run-time calibrated oscillator
32.768kHz calibrated oscillator
32kHz ultra low power (ULP) oscillator with 1kHz output
zExternal clock options
0.4MHz - 16MHz crystal oscillator
32.768kHz crystal oscillator
External clock
zPLL with 20MHz - 128MHz output frequency
Internal and external clock options and 1x to 31x multiplication
Lock detector
zClock prescalers with 1x to 2048x division
zFast peripheral clocks running at two and four times the CPU clock
zAutomatic run-time calibration of internal oscillators
zExternal oscillator and PLL lock failure detection with optional non-maskable interrupt
10.2 Overview
Atmel AVR XMEGA A3U devices have a flexible clock system supporting a large number of clock sources. It
incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-
frequency phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock
frequencies. A calibration feature (DFLL) is available, and can be used for automatic run-time calibration of the
internal oscillators to remove frequency drift over voltage and temperature. An oscillator failure monitor can be
enabled to issue a non-maskable interrupt and switch to the internal oscillator if the external oscillator or PLL
fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the
device will always start up running from the 2MHz internal oscillator. During normal operation, the system clock
source and prescalers can be changed from software at any time.
Figure 10-1 on page 23 presents the principal clock system in the XMEGA A3U family of devices. Not all of the
clocks need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep
modes and power reduction registers, as described in “Power Management and Sleep Modes” on page 25.
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Figure 10-1. The clock system, clock sources and clock distribution.
10.3 Clock Sources
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the
clock sources can be directly enabled and disabled from software, while others are automatically enabled or
disabled, depending on peripheral settings. After reset, the device starts up running from the 2MHz internal
oscillator. The other clock sources, DFLLs and PLL, are turned off by default.
The internal oscillators do not require any external components to run. For details on characteristics and
accuracy of the internal oscillators, refer to the device datasheet.
10.3.1 32kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a
very low power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler
Real Time
Counter Peripherals RAM AVR CPU Non-Volatile
Memory
Watchdog
Timer
Brown-out
Detector
System Clock Prescalers
USB
Prescaler
System Clock Multiplexer
(SCLKSEL)
PLLSRC
RTCSRC
DIV32
32kHz
Int. ULP
32.768kHz
Int. OSC
32.768kHz
TOSC
2MHz
Int. Osc
32MHz
Int. Osc
0.4 – 16MHz
XTAL
DIV32
DIV32
DIV4
XOSCSEL
PLL
USBSRC
TOSC1
TOSC2
XTAL1
XTAL2
clk
SYS
clk
RTC
clk
PER2
clk
PER
clk
CPU
clk
PER4
clk
USB
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that provides a 1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for
any part of the device. This oscillator can be selected as the clock source for the RTC.
10.3.2 32.768kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default
frequency close to its nominal frequency. The calibration register can also be written from software for run-time
calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a
32.768kHz output and a 1.024kHz output.
10.3.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated
low frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This
oscillator can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.
10.3.4 0.4 - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 -
16MHz.
10.3.5 2MHz Run-time Calibrated Internal Oscillator
The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated
during production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the
oscillator accuracy.
10.3.6 32MHz Run-time Calibrated Internal Oscillator
The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production
to provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be
enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and
optimize the oscillator accuracy. This oscillator can also be adjusted and calibrated to any frequency between
30MHz and 55MHz. The production signature row contains 48MHz calibration values intended used when the
oscillator is used a full-speed USB clock source.
10.3.7 External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic
resonator. XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated
to driving a 32.768kHz crystal oscillator.
10.3.8 PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a
user-selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range
of output frequencies from all clock sources.
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11. Power Management and Sleep Modes
11.1 Features
zPower management for adjusting power consumption and functions
zFive sleep modes
Idle
Power down
Power save
Standby
Extended standby
zPower reduction register to disable clock and turn off unused peripherals in active and idle modes
11.2 Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application
requirements. This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing
application code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is
used to wake the device again. The application code decides which sleep mode to enter and when. Interrupts
from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active
mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software.
When this is done, the current state of the peripheral is frozen, and there is no power consumption from that
peripheral. This reduces the power consumption in active mode and idle sleep modes and enables much more
fine-tuned power management than sleep modes alone.
11.3 Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power.
XMEGA microcontrollers have five different sleep modes tuned to match the typical functional stages during
application execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are
used to wake the device from sleep, and the available interrupt wake-up sources are dependent on the
configured sleep mode. When an enabled interrupt occurs, the device will wake up and execute the interrupt
service routine before continuing normal program execution from the first instruction after the SLEEP
instruction. If other, higher priority interrupts are pending when the wake-up occurs, their interrupt service
routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt
is executed. After wake-up, the CPU is halted for four cycles before execution starts.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the
device will reset, start up, and execute from the reset vector.
11.3.1 Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be
completed), but all peripherals, including the interrupt controller, event system and DMA controller are kept
running. Any enabled interrupt will wake the device.
11.3.2 Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation
only of asynchronous modules that do not require a running clock. The only interrupts that can wake up the
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MCU are the two-wire interface address match interrupt, asynchronous port interrupts, and the USB resume
interrupt.
11.3.3 Power-save Mode
Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it
will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match
interrupt.
11.3.4 Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept
running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.
11.3.5 Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock
sources are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
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12. System Control and Reset
12.1 Features
zReset the microcontroller and set it to initial state when a reset source goes active
zMultiple reset sources that cover different situations
Power-on reset
External reset
Watchdog reset
Brownout reset
PDI reset
Software reset
zAsynchronous operation
No running system clock in the device is required for reset
zReset status register for reading the reset source from the application code
12.2 Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontroller operates below its power supply rating.
If a reset source goes active, the device enters and is kept in reset until all reset sources have released their
reset. The I/O pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O
registers are set to their initial values. The SRAM content is kept. However, if the device accesses the SRAM
when a reset occurs, the content of the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device
starts running from the reset vector address. By default, this is the lowest program memory address, 0, but it is
possible to move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The
software reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and
shows which sources have issued a reset since the last power-on.
12.3 Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the
request is active. When all reset requests are released, the device will go through three stages before the
device starts running again:
zReset counter delay
zOscillator startup
zOscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
12.4 Reset Sources
12.4.1 Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises
and reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.
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12.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level
during chip erase and when the PDI is enabled.
12.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the
RESET pin is driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period,
tEXT. The reset will be held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
12.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not
reset from the software within a programmable timeout period, a watchdog reset will be given. The watchdog
reset is active for one to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog
Timer” on page 29.
12.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in
the reset control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not
possible to execute any instruction from when a software reset is requested until it is issued.
12.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during
external programming and debugging. This reset source is accessible only from external debuggers and
programmers.
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13. WDT – Watchdog Timer
13.1 Features
zIssues a device reset if the timer is not reset before its timeout period
zAsynchronous operation from dedicated oscillator
z1kHz output of the 32kHz ultra low power oscillator
z11 selectable timeout periods, from 8ms to 8s
zTwo operation modes:
Normal mode
Window mode
zConfiguration lock to prevent unwanted changes
13.2 Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to
recover from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a
predefined timeout period, and is constantly running when enabled. If the WDT is not reset within the timeout
period, it will issue a microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset)
instruction from the application code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which
WDT must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be
issued. Compared to the normal mode, this can also catch situations where a code error causes constant WDR
execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-
independent clock source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident.
For increased safety, a fuse for locking the WDT settings is also available.
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14. Interrupts and Programmable Multilevel Interrupt Controller
14.1 Features
zShort and predictable interrupt response time
zSeparate interrupt configuration and vector address for each interrupt
zProgrammable multilevel interrupt controller
Interrupt prioritizing according to level and vector address
Three selectable interrupt levels for all interrupts: low, medium and high
Selectable, round-robin priority scheme within low-level interrupts
Non-maskable interrupts for critical functions
zInterrupt vectors optionally placed in the application section or the boot loader section
14.2 Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals
can have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled
and configured, it will generate an interrupt request when the interrupt condition is present. The programmable
multilevel interrupt controller (PMIC) controls the handling and prioritizing of interrupt requests. When an
interrupt request is acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and
the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high.
Interrupts are prioritized according to their level and their interrupt vector address. Medium-level interrupts will
interrupt low-level interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt
handlers. Within each level, the interrupt priority is decided from the interrupt vector address, where the lowest
interrupt vector address has the highest interrupt priority. Low-level interrupts have an optional round-robin
scheduling scheme to ensure that all interrupts are serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
14.3 Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific
interrupts in each peripheral. The base addresses for the Atmel AVR XMEGA A3U devices are shown in Table
14-1. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the
XMEGA AU manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in
Table 14-1. The program address is the word address.
Table 14-1. Reset and interrupt vectors.
Program address
(base address) Source Interrupt description
0x000 RESET
0x002 OSCF_INT_vect Crystal oscillator failure interrupt vector (NMI)
0x004 PORTC_INT_base Port C interrupt base
0x008 PORTR_INT_base Port R interrupt base
0x00C DMA_INT_base DMA controller interrupt base
0x014 RTC_INT_base Real Time Counter Interrupt base
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0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base
0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base
0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base
0x030 SPIC_INT_vect SPI on port C Interrupt vector
0x032 USARTC0_INT_base USART 0 on port C Interrupt base
0x038 USARTC1_INT_base USART 1 on port C Interrupt base
0x03E AES_INT_vect AES Interrupt vector
0x040 NVM_INT_base Non-Volatile Memory Interrupt base
0x044 PORTB_INT_base Port B Interrupt base
0x048 ACB_INT_base Analog Comparator on Port B Interrupt base
0x04E ADCB_INT_base Analog to Digital Converter on Port B Interrupt base
0x056 PORTE_INT_base Port E INT base
0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base
0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base
0x06A TCE1_INT_base Timer/Counter 1 on port E Interrupt base
0x072 SPIE_INT_vect SPI on port E Interrupt vector
0x074 USARTE0_INT_base USART 0 on port E Interrupt base
0x07A USARTE1_INT_base USART 1 on port E Interrupt base
0x080 PORTD_INT_base Port D Interrupt base
0x084 PORTA_INT_base Port A Interrupt base
0x088 ACA_INT_base Analog Comparator on Port A Interrupt base
0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base
0x09A TCD0_INT_base Timer/Counter 0 on port D Interrupt base
0x0A6 TCD1_INT_base Timer/Counter 1 on port D Interrupt base
0x0AE SPID_INT_vector SPI D Interrupt vector
0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base
0x0B6 USARTD1_INT_base USART 1 on port D Interrupt base
0x0D0 PORTF_INT_base Port F Interrupt base
0x0D8 TCF0_INT_base Timer/Counter 0 on port F Interrupt base
0x0EE USARTF0_INT_base USART 0 on port F Interrupt base
0x0FA USB_INT_base USB on port D Interrupt base
Program address
(base address) Source Interrupt description
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15. I/O Ports
15.1 Features
z50 general purpose input and output pins with individual configuration
zOutput driver with configurable driver and pull settings:
Totem-pole
Wired-AND
Wired-OR
Bus-keeper
Inverted I/O
zInput with synchronous and/or asynchronous sensing with interrupts and events
Sense both edges
Sense rising edges
Sense falling edges
Sense low level
zOptional pull-up and pull-down resistor on input and Wired-OR/AND configurations
zOptional slew rate control
zAsynchronous pin change sensing that can wake the device from all sleep modes
zTwo port interrupts with pin masking per I/O port
zEfficient and safe access to port pins
Hardware read-modify-write through dedicated toggle/clear/set registers
Configuration of multiple pins in a single operation
Mapping of port registers into bit-accessible I/O memory space
zPeripheral clocks output on port pin
zReal-time counter clock output to port pin
zEvent channels can be output on port pin
zRemapping of digital peripheral pin functions
Selectable USART, SPI, and timer/counter input/output pin locations
15.2 Overview
One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with
configurable driver and pull settings. They also implement synchronous and asynchronous input sensing with
interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin
change can wake the device from all sleep modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation.
The pins have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or
pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the
direction of any other pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have
both the peripheral clock and the real-time clock output to a port pin, and available for external use. The same
applies to events from the event system that can be used to synchronize and control external functions. Other
digital peripherals, such as USART, SPI, and timer/counters, can be remapped to selectable pin locations in
order to optimize pin-out versus application needs.
The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTF and PORTR.
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15.3 Output Driver
All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate
limitation to reduce electromagnetic emission.
15.3.1 Push-pull
Figure 15-1. I/O configuration - Totem-pole.
15.3.2 Pull-down
Figure 15-2. I/O configuration - Totem-pole with pull-down (on input).
15.3.3 Pull-up
Figure 15-3. I/O configuration - Totem-pole with pull-up (on input).
INn
OUTn
DIRn
Pn
INn
OUTn
DIRn
Pn
INn
OUTn
DIRn
Pn
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15.3.4 Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the
last level was ‘1’, and pull-down if the last level was ‘0’.
Figure 15-4. I/O configuration - Totem-pole with bus-keeper.
15.3.5 Others
Figure 15-5. Output configuration - Wired-OR with optional pull-down.
Figure 15-6. I/O configuration - Wired-AND with optional pull-up.
INn
OUTn
DIRn
Pn
INn
OUTn
Pn
INn
OUTn
Pn
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15.4 Input sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the
configuration is shown in Figure 15-7.
Figure 15-7. Input sensing system overview.
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
15.5 Alternate Port Functions
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate
function is enabled, it might override the normal port pin function or pin value. This happens when other
peripherals that require pins are enabled or configured to use pins. If and how a peripheral will override and use
pins is described in the section for that peripheral. “Pinout and Pin Functions” on page 59 shows which modules
on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin.
DQ
R
NVERTED I/O
Interrupt
Control
DQ
R
Pxn Synchronizer
INn EDGE
DETECT
Synchronous sensing
EDGE
DETECT
Asynchronous sensing
IRQ
Synchronous
Events
Asynchronou
Events
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16. TC0/1 – 16-bit Timer/Counter Type 0 and 1
16.1 Features
zSeven 16-bit timer/counters
Four timer/counters of type 0
Three timer/counters of type 1
Split-mode enabling two 8-bit timer/counter from each timer/counter type 0
z32-bit Timer/Counter support by cascading two timer/counters
zUp to four compare or capture (CC) channels
Four CC channels for timer/counters of type 0
Two CC channels for timer/counters of type 1
zDouble buffered timer period setting
zDouble buffered capture or compare channels
zWaveform generation:
Frequency generation
Single-slope pulse width modulation
Dual-slope pulse width modulation
zInput capture:
Input capture with noise cancelling
Frequency capture
Pulse width capture
32-bit input capture
zTimer overflow and error interrupts/events
zOne compare match or input capture interrupt/event per CC channel
zCan be used with event system for:
Quadrature decoding
Count and direction control
Capture
zCan be used with DMA and to trigger DMA transactions
zHigh-resolution extension
Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)
zAdvanced waveform extension:
Low- and high-side output with programmable dead-time insertion (DTI)
zEvent controlled fault protection for safe disabling of drivers
16.2 Overview
Atmel AVR XMEGA devices have a set of seven flexible 16-bit Timer/Counters (TC). Their capabilities include
accurate program execution timing, frequency and waveform generation, and input capture with time and
frequency measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter
with optional 32-bit capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter
can be used to count clock cycles or events. It has direction control and period setting that can be used for
timing. The CC channels can be used together with the base counter to do compare match control, frequency
generation, and pulse width waveform modulation, as well as various input capture operations. A timer/counter
can be configured for either capture or compare functions, but cannot perform both at the same time.
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A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event
system. The event system can also be used for direction control and capture trigger or to synchronize
operations.
There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and
timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for
timer/counter 0. Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with
four compare channels each.
Some timer/counters have extensions to enable more specialized waveform and frequency generation. The
advanced waveform extension (AWeX) is intended for motor control and other power control applications. It
enables low- and high-side output with dead-time insertion, as well as fault protection for disabling and shutting
down external drivers. It can also generate a synchronized bit pattern across the port pins.
The advanced waveform extension can be enabled to provide extra and more advanced features for the
Timer/Counter. This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on
page 39 for more details.
The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight
times by using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res –
High Resolution Extension” on page 40 for more details.
Figure 16-1. Overview of a Timer/Counter and closely related peripherals.
PORTC, PORTD and PORTE each has one Timer/Counter 0 and one Timer/Counter1. PORTF has one
Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1, TCE0, TCE1 and TCF0,
respectively.
AWeX
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
Waveform
Generation
Buffer
Comparator
Hi-Res
Fault
Protection
Capture
Control
Base Counter
Counter
Control Logic
Timer Period
Prescaler
Dead-Time
Insertion
Pattern
Generation
clkPER4
PORT
Event
System
clkPER
Timer/Counter
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17. TC2 - Timer/Counter Type 2
17.1 Features
zEight eight-bit timer/counters
Four Low-byte timer/counter
Four High-byte timer/counter
zUp to eight compare channels in each Timer/Counter 2
Four compare channels for the low-byte timer/counter
Four compare channels for the high-byte timer/counter
zWaveform generation
Single slope pulse width modulation
zTimer underflow interrupts/events
zOne compare match interrupt/event per compare channel for the low-byte timer/counter
zCan be used with the event system for count control
zCan be used to trigger DMA transactions
17.2 Overview
There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a
system of two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse
width modulation (PWM) channels with individually controlled duty cycles, and is intended for applications that
require a high number of PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte
timer/counter, respectively. The difference between them is that only the low-byte timer/counter can be used to
generate compare match interrupts, events and DMA triggers. The two eight-bit timer/counters have a shared
clock source and separate period and compare settings. They can be clocked and timed from the peripheral
clock, with optional prescaling, or from the event system. The counters are always counting down.
PORTC, PORTD, PORTE and PORTF each has one Timer/Counter 2. Notation of these are TCC2
(Time/Counter C2), TCD2, TCE2 and TCF2, respectively.
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18. AWeX – Advanced Waveform Extension
18.1 Features
zWaveform output with complementary output from each compare channel
zFour dead-time insertion (DTI) units
8-bit resolution
Separate high and low side dead-time setting
Double buffered dead time
Optionally halts timer during dead-time insertion
zPattern generation unit creating synchronised bit pattern across the port pins
Double buffered pattern generation
Optional distribution of one compare channel output across the port pins
zEvent controlled fault protection for instant and predictable fault triggering
18.2 Overview
The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform
generation (WG) modes. It is primarily intended for use with different types of motor control and other power
control applications. It enables low- and high side output with dead-time insertion and fault protection for
disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port
pins.
Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs
when any AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that
generates the non-inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion
between LS and HS switching. The DTI output will override the normal port value according to the port override
setting.
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In
addition, the WG output from compare channel A can be distributed to and override all the port pins. When the
pattern generator unit is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will
disable the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in
the selection of fault triggers.
The AWeX is available for TCC0. The notation of this is AWEXC.
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19. Hi-Res – High Resolution Extension
19.1 Features
zIncreases waveform generator resolution up to 8x (three bits)
zSupports frequency, single-slope PWM, and dual-slope PWM generation
zSupports the AWeX when this is used for the same timer/counter
19.2 Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output
from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or
dual-slope PWM generation. It can also be used with the AWeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so
the peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-
res extension is enabled.
There are four hi-res extensions that each can be enabled for each timer/counters pair on PORTC, PORTD,
PORTE and PORTF. The notation of these are HIRESC, HIRESD, HIRESE and HIRESF, respectively.
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20. RTC – 16-bit Real-Time Counter
20.1 Features
z16-bit resolution
zSelectable clock source
32.768kHz external crystal
External clock
32.768kHz internal oscillator
32kHz internal ULP oscillator
zProgrammable 10-bit clock prescaling
zOne compare register
zOne period register
zClear counter on period overflow
zOptional interrupt/event on overflow and compare match
20.2 Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep
modes, to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular
intervals.
The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the
configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the
RTC needs a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the
32.768kHz internal oscillator or the 32kHz internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches
the counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock
source, the maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a
resolution of 1s, the maximum timeout period is more than18 hours (65536 seconds). The RTC can give a
compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt
and/or event when it equals the period register value.
Figure 20-1. Real-time counter overview.
32.768kHz Crystal Osc
32.768kHz Int. Osc
TOSC1
TOSC2
External Clock
DIV32
DIV32
32kHz int ULP (DIV32)
RTCSRC
10-bit
prescaler
clkRTC
CNT
PER
COMP
=
=
”match”/
Compare
TOP/
Overflow
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21. USB – Universal Serial Bus Interface
21.1 Features
zOne USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
zIntegrated on-chip USB transceiver, no external components needed
z16 endpoint addresses with full endpoint flexibility for up to 31 endpoints
One input endpoint per endpoint address
One output endpoint per endpoint address
zEndpoint address transfer type selectable to
Control transfers
Interrupt transfers
Bulk transfers
Isochronous transfers
zConfigurable data payload size per endpoint, up to 1023 bytes
zEndpoint configuration and data buffers located in internal SRAM
Configurable location for endpoint configuration data
Configurable location for each endpoint's data buffer
zBuilt-in direct memory access (DMA) to internal SRAM for:
Endpoint configurations
Reading and writing endpoint data
zPing-pong operation for higher throughput and double buffered operation
Input and output endpoint data buffers used in a single direction
CPU/DMA controller can update data buffer during transfer
zMultipacket transfer for reduced interrupt load and software intervention
Data payload exceeding maximum packet size is transferred in one continuous transfer
No interrupts or software interaction on packet transaction level
zTransaction complete FIFO for workflow management when using multiple endpoints
Tracks all completed transactions in a first-come, first-served work queue
zClock selection independent of system clock source and selection
zMinimum 1.5MHz CPU clock required for low speed USB operation
zMinimum 12MHz CPU clock required for full speed operation
zConnection to event system
zOn chip debug possibilities during USB transactions
21.2 Overview
The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for
a total of 31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and
can be configured for any of the four transfer types; control, interrupt, bulk, or isochronous. The data payload
size is also selectable, and it supports data payloads up to 1023 bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the
configuration for each endpoint address and the data buffer for each endpoint. The memory locations used for
endpoint configurations and data buffers are fully configurable. The amount of memory allocated is fully
dynamic, according to the number of endpoints in use and the configuration of these. The USB module has
built-in direct memory access (DMA), and will read/write data from/to the SRAM when a USB transaction takes
place.
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To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input
and output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one
data buffer while the USB module writes/reads the others, and vice versa. This gives double buffered
communication.
Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be
transferred as multiple packets without software intervention. This reduces the CPU intervention and the
interrupts needed for USB transfers.
For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is
idle and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller
from any sleep mode.
PORTD has one USB. Notation of this is USB.
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22. TWI – Two-Wire Interface
22.1 Features
zTwo Identical two-wire interface peripherals
zBidirectional, two-wire communication interface
Phillips I2C compatible
System Management Bus (SMBus) compatible
zBus master and slave operation supported
Slave operation
Single bus master operation
Bus master in multi-master bus environment
Multi-master arbitration
zFlexible slave address match functions
7-bit and general call address recognition in hardware
10-bit addressing supported
Address mask register for dual address match or address range masking
Optional software address recognition for unlimited number of addresses
zSlave can operate in all sleep modes, including power-down
zSlave address match can wake device from all sleep modes
z100kHz and 400kHz bus frequency support
zSlew-rate limited output drivers
zInput filter for bus noise and spike suppression
zSupport arbitration between start/repeated start and data bit (SMBus)
zSlave arbitration allows support for address resolve protocol (ARP) (SMBus)
22.2 Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System
Management Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up
resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by
addressing a slave on the bus and telling whether it wants to transmit or receive data. One bus can have many
slaves and one or several masters that can take control of the bus. An arbitration process handles priority if
more than one master tries to transmit data at the same time. Mechanisms for resolving bus contention are
inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from
each other, and can be enabled and configured separately. The master module supports multi-master bus
operation and arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is
supported. Quick command and smart mode can be enabled to auto-trigger operations and reduce software
complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit
addressing is also supported. A dedicated address mask register can act as a second address match register or
as a register for address range masking. The slave continues to operate in all sleep modes, including power-
down mode. This enables the slave to wake up the device from all sleep modes on TWI address match. It is
possible to disable the address matching to let this be handled in software instead.
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The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors,
collision, and clock hold on the bus are also detected and indicated in separate status flags available in both
master and slave modes.
It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an
external TWI bus driver. This can be used for applications where the device operates from a different VCC
voltage than used by the TWI bus.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
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23. SPI – Serial Peripheral Interface
23.1 Features
zThree Identical SPI peripherals
zFull-duplex, three-wire synchronous data transfer
zMaster or slave operation
zLsb first or msb first data transfer
zEight programmable bit rates
zInterrupt flag at the end of transmission
zWrite collision flag to indicate data collision
zWake up from idle sleep mode
zDouble speed master mode
23.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four
pins. It allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between
several microcontrollers. The SPI supports full-duplex communication.
A device connected to the bus must act as a master or slave. The master initiates and controls all data
transactions.
PORTC, PORTD, and PORTE each has one SPI. Notation of these peripherals are SPIC, SPID, and SPIE
respectivel
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24. USART
24.1 Features
zSeven identical USART peripherals
zFull-duplex operation
zAsynchronous or synchronous operation
Synchronous clock rates up to 1/2 of the device clock frequency
Asynchronous clock rates up to 1/8 of the device clock frequency
zSupports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
zFractional baud rate generator
Can generate desired baud rate from any system clock frequency
No need for external oscillator with certain frequencies
zBuilt-in error detection and correction schemes
Odd or even parity generation and parity check
Data overrun and framing error detection
Noise filtering includes false start bit detection and digital low-pass filter
zSeparate interrupts for
Transmit complete
Transmit data register empty
Receive complete
zMultiprocessor communication mode
Addressing scheme to address a specific devices on a multidevice bus
Enable unaddressed devices to automatically ignore all frames
zMaster SPI mode
Double buffered operation
Operation up to 1/2 of the peripheral clock frequency
zIRCOM module for IrDA compliant pulse modulation/demodulation
24.2 Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible
serial communication module. The USART supports full-duplex communication and asynchronous and
synchronous operation. The USART can be configured to operate in SPI master mode and used for SPI
communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards.
The USART is buffered in both directions, enabling continued data transmission without any delay between
frames. Separate interrupts for receive and transmit complete enable fully interrupt driven communication.
Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd
parity generation and parity check can also be enabled.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART
baud rates from any system clock frequencies. This removes the need to use an external crystal oscillator with
a specific frequency to achieve a required baud rate. It also supports external clock input in synchronous slave
operation.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and
receive buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are
identical in both modes. The registers are used in both modes, but their functionality differs for some control
settings.
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An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2Kbps.
PORTC, PORTD, and PORTE each has two USARTs, while PORTF has one USART only. Notation of these
peripherals are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0, USARTE1 and USARTF0,
respectively.
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25. IRCOM – IR Communication Module
25.1 Features
zPulse modulation/demodulation for infrared communication
zIrDA compatible for baud rates up to 115.2Kbps
zSelectable pulse modulation scheme
3/16 of the baud rate period
Fixed pulse period, 8-bit programmable
Pulse modulation disabled
zBuilt-in filtering
zCan be connected to and used by any USART
25.2 Overview
Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for
baud rates up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for
that USART.
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26. AES and DES Crypto Engine
26.1 Features
zData Encryption Standard (DES) CPU instruction
zAdvanced Encryption Standard (AES) crypto module
zDES Instruction
Encryption and decryption
DES supported
Encryption/decryption in 16 CPU clock cycles per 8-byte block
zAES crypto module
Encryption and decryption
Supports 128-bit keys
Supports XOR data load mode to the state memory
Encryption/decryption in 375 clock cycles per 16-byte block
26.2 Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used
standards for cryptography. These are supported through an AES peripheral module and a DES CPU
instruction, and the communication interfaces and the CPU can use these for fast, encrypted communication
and secure data storage.
DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into
the register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block.
The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and
data must be loaded into the key and state memory in the module before encryption/decryption is started. It
takes 375 peripheral clock cycles before the encryption/decryption is done. The encrypted/encrypted data can
then be read out, and an optional interrupt can be generated. The AES crypto module also has DMA support
with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when
the state memory is fully loaded.
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27. CRC – Cyclic Redundancy Check Generator
27.1 Features
zCyclic redundancy check (CRC) generation and checking for
Communication data
Program or data in flash memory
Data in SRAM and I/O memory space
zIntegrated with flash memory, DMA controller and CPU
Continuous CRC on data going through a DMA channel
Automatic CRC of the complete or a selectable range of the flash memory
CPU can load data to the CRC generator through the I/O interface
zCRC polynomial software selectable to
CRC-16 (CRC-CCITT)
CRC-32 (IEEE 802.3)
zZero remainder detection
27.2 Overview
A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in
data, and it is commonly used to determine the correctness of a data transmission, and data present in the data
and program memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit
output that can be appended to the data and used as a checksum. When the same data are later received or
read, the device or application repeats the calculation. If the new CRC result does not match the one calculated
earlier, the block contains a data error. The application will then detect this and may take a corrective action,
such as requesting the data to be sent again or simply not using the incorrect data.
Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer
than n bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of
all longer error bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC
polynomials; CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3).
zCRC-16:
zCRC-32:
Polynomial: x16+x12+x5+1
Hex value: 0x1021
Polynomial: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
Hex value: 0x04C11DB7
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28. ADC – 12-bit Analog to Digital Converter
28.1 Features
zTwo Analog to Digital Converters (ADCs)
z12-bit resolution
zUp to two million samples per second
Two inputs can be sampled simultaneously using ADC and 1x gain stage
Four inputs can be sampled within 1.5µs
Down to 2.5µs conversion time with 8-bit resolution
Down to 3.5µs conversion time with 12-bit resolution
zDifferential and single-ended input
Up to 16 single-ended inputs
16x4 differential inputs without gain
8x4 differential input with gain
zBuilt-in differential gain stage
1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options
zSingle, continuous and scan conversion options
zFour internal inputs
Internal temperature sensor
DAC output
AVCC voltage divided by 10
1.1V bandgap voltage
zFour conversion channels with individual input control and result registers
Enable four parallel configurations and results
zInternal and external reference options
zCompare function for accurate monitoring of user defined thresholds
zOptional event triggered conversion for accurate timing
zOptional DMA transfer of conversion results
zOptional interrupt/event on compare result
28.2 Overview
The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting
up to two million samples per second (msps). The input selection is flexible, and both single-ended and
differential measurements can be done. For differential measurements, an optional gain stage is available to
increase the dynamic range. In addition, several internal signal inputs are available. The ADC can provide both
signed and unsigned results.
This is a pipelined ADC that consists of several consecutive stages. The pipelined design allows a high sample
rate at a low system clock frequency. It also means that a new input can be sampled and a new ADC conversion
started while other ADC conversions are still ongoing. This removes dependencies between sample rate and
propagation delay.
The ADC has four conversion channels (0-3) with individual input selection, result registers, and conversion
start control. The ADC can then keep and use four parallel configurations and results, and this will ease use for
applications with high data throughput or for multiple modules using the ADC independently. It is possible to use
DMA to move ADC results directly to memory or peripherals when conversions are done.
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Both internal and external reference voltages can be used. An integrated temperature sensor is available for
use with the ADC. The output from the DAC, AVCC/10 and the bandgap voltage can also be measured by the
ADC.
The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software
intervention required.
Figure 28-1. ADC overview.
Two inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold
circuits, and the gain stage has 1x gain setting. Four inputs can be sampled within 1.5µs without any
intervention by the application.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay)
from 3.5µs for 12-bit to 2.5µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation
when the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively.
CH1 Result
CH0 Result
CH2 Result
Compare
<
>Threshold
(Int Req)
Internal 1.00V
Internal AVCC/1.6V
AREFA
AREFB
VINP
VINN
Internal
signals
Internal AVCC/2
Internal
signals
CH3 Result
ADC0
ADC7
ADC4
ADC7
ADC0
ADC3
•
•
•
Int. signals
Int. signals
Reference
Voltage
½x - 64x
•
•
•
•
•
•
ADC0
ADC11
•
•
•
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29. DAC – 12-bit Digital to Analog Converter
29.1 Features
zOne Digital to Analog Converter (DAC)
z12-bit resolution
zTwo independent, continuous-drive output channels
zUp to one million samples per second conversion rate per DAC channel
zBuilt-in calibration that removes:
Offset error
Gain error
zMultiple conversion trigger sources
On new available data
Events from the event system
zHigh drive capabilities and support for
Resistive loads
Capacitive loads
Combined resistive and capacitive loads
zInternal and external reference options
zDAC output available as input to analog comparator and ADC
zLow-power mode, with reduced drive strength
zOptional DMA transfer of data
29.2 Overview
The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with
12-bit resolution, and is capable of converting up to one million samples per second (msps) on each channel.
The built-in calibration system can remove offset and gain error when loaded with calibration values from
software.
Figure 29-1. DAC overview.
DAC0
DAC1
CTRLA
CH1DATA
CH0DATA
Trigger
Trigger
Internal Output
enable
Enable
Internal 1.00V
AREFA
AREFB
Reference
selection
AVCC
Output
Driver
Output
Driver
D
A
T
A
Int.
driver
D
A
T
A
CTRLB
DMA req
(Data Empty)
DMA req
(Data Empty)
Select
12
12
Select
Enable
To
AC/ADC
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A DAC conversion is automatically started when new data to be converted are available. Events from the event
system can also be used to trigger a conversion, and this enables synchronized and timed conversions between
the DAC and other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the
DAC.
The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, aswell as loads
which combine both. A low-power mode is available, which will reduce the drive strength of the output. Internal
and external voltage references can be used. The DAC output is also internally available for use as input to the
analog comparator or ADC.
PORTB has one DAC. Notation of this peripheral is DACB.
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30. AC – Analog Comparator
30.1 Features
zFour Analog Comparators (AC)
zSelectable propagation delay versus current consumption
zSelectable hysteresis
No
Small
Large
zAnalog comparator output available on pin
zFlexible input selection
All pins on the port
Output from the DAC
Bandgap reference voltage
A 64-level programmable voltage scaler of the internal AVCC voltage
zInterrupt and event generation on:
Rising edge
Falling edge
Toggle
zWindow function interrupt and event generation on:
Signal above window
Signal inside window
Signal below window
zConstant current source with configurable output pin selection
30.2 Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The analog comparator may be configured to generate interrupt requests and/or events upon
several different combinations of input change.
Two important properties of the analog comparator’s dynamic behavior are: hysteresis and propagation delay.
Both of these parameters may be adjusted in order to achieve the optimal operation for each application.
The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage
scaler. The analog comparator output state can also be output on a pin for use by external devices.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for
example, external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0)
and analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they
can be set in window mode to compare a signal to a voltage range instead of a voltage level.
PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.
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Figure 30-1. Analog comparator overview.
The window function is realized by connecting the external inputs of the two analog comparators in a pair as
shown in Figure 30-2.
Figure 30-2. Analog comparator window function.
ACnMUXCTRL ACnCTRL
Interrupt
Mode
Enable
Enable
Hysteresis
Hysteresis
AC1OUT
WINCTRL
Interrupt
Sensititivity
Control
&
Window
Function
Events
Interrupts
AC0OUT
Pin Input
Pin Input
Pin Input
Pin Input
Voltage
Scaler
DAC
Bandgap
+
-
+
-
AC0
+
-
AC1
+
-
Input signal
Upper limit of window
Lower limit of window
Interrupt
sensitivity
control
Interrupts
Events
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31. Programming and Debugging
31.1 Features
zProgramming
External programming through PDI or JTAG interfaces
zMinimal protocol overhead for fast operation
zBuilt-in error detection and handling for reliable operation
Boot loader support for programming through any communication interface
zDebugging
Nonintrusive, real-time, on-chip debug system
No software or hardware resources required from device except pin connection
Program flow control
zGo, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
Unlimited number of user program breakpoints
Unlimited number of user data breakpoints, break on:
zData location read, write, or both read and write
zData location content equal or not equal to a value
zData location content is greater or smaller than a value
zData location content is within or outside a range
No limitation on device clock frequency
zProgram and Debug Interface (PDI)
Two-pin interface for external programming and debugging
Uses the Reset pin and a dedicated pin
No I/O pins required during programming or debugging
zJTAG interface
Four-pin, IEEE Std. 1149.1 compliant interface for programming and debugging
Boundary scan capabilities according to IEEE Std. 1149.1 (JTAG)
31.2 Overview
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip
debugging of a device.
The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and
the user signature row.
Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not
require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it
offers complete program flow control and support for an unlimited number of program and complex data
breakpoints. Application debug can be done from a C or other high-level language source code level, as well as
from an assembler and disassembler level.
Programming and debugging can be done through two physical interfaces. The primary one is the PDI physical
layer, which is available on all devices. This is a two-pin interface that uses the Reset pin for the clock input
(PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). A JTAG interface is also
available on most devices, and this can be used for programming and debugging through the four-pin JTAG
interface. The JTAG interface is IEEE Std. 1149.1 compliant, and supports boundary scan. Any external
programmer or on-chip debugger/emulator can be directly connected to either of these interfaces. Unless
otherwise stated, all references to the PDI assume access through the PDI physical layer.
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32. Pinout and Pin Functions
The device pinout is shown in “Pinout/Block Diagram” on page 5. In addition to general purpose I/O
functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and
connected to the actual pin. Only one of the pin functions can be used at time.
32.1 Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
32.1.1 Operation/Power Supply
32.1.2 Port Interrupt functions
32.1.3 Analog functions
32.1.4 Timer/Counter and AWEX functions
32.1.5 Communication functions
VCC Digital supply voltage
AVCC Analog supply voltage
GND Ground
SYNC Port pin with full synchronous and limited asynchronous interrupt function
ASYNC Port pin with full synchronous and full asynchronous interrupt function
ACn Analog Comparator input pin n
ACnOUT Analog Comparator n Output
ADCn Analog to Digital Converter input pin n
DACn Digital to Analog Converter output pin n
AREF Analog Reference input pin
OCnxLS Output Compare Channel x Low Side for Timer/Counter n
OCnxHS Output Compare Channel x High Side for Timer/Counter n
SCL Serial Clock for TWI
SDA Serial Data for TWI
SCLIN Serial Clock In for TWI when external driver interface is enabled
SCLOUT Serial Clock Out for TWI when external driver interface is enabled
SDAIN Serial Data In for TWI when external driver interface is enabled
SDAOUT Serial Data Out for TWI when external driver interface is enabled
XCKn Transfer Clock for USART n
RXDn Receiver Data for USART n
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32.1.6 Oscillators, Clock and Event
32.1.7 Debug/System functions
TXDn Transmitter Data for USART n
SS Slave Select for SPI
MOSI Master Out Slave In for SPI
MISO Master In Slave Out for SPI
SCK Serial Clock for SPI
D- Data- for USB
D+ Data+ for USB
TOSCn Timer Oscillator pin n
XTALn Input/Output for Oscillator pin n
CLKOUT Peripheral Clock Output
EVOUT Event Channel Output
RTCOUT RTC Clock Source Output
RESET Reset pin
PDI_CLK Program and Debug Interface Clock pin
PDI_DATA Program and Debug Interface Data pin
TCK JTAG Test Clock
TDI JTAG Test Data In
TDO JTAG Test Data Out
TMS JTAG Test Mode Select
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32.2 Alternate Pin Functions
The tables below show the primary/default function for each pin on a port in the first column, the pin number in
the second column, and then all alternate pin functions in the remaining columns. The head row shows what
peripheral that enable and use the alternate pin functions.
For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted
under the first table where this apply.
Table 32-1. Port A - alternate functions.
Table 32-2. Port B - alternate functions.
PORTA PIN# INTERRUPT ADCAPOS/
GAINPOS
ADCA
NEG
ADCA
GAINNEG
ACA
POS
ACA
NEG
ACA
OUT
REFA
GND 60
AVCC 61
PA0 62 SYNC ADC0 ADC0 AC0 AC0 AREF
PA1 63 SYNC ADC1 ADC1 AC1 AC1
PA2 64 SYNC/
ASYNC ADC2 ADC2 AC2
PA3 1SYNC ADC3 ADC3 AC3 AC3
PA4 2SYNC ADC4 ADC4 AC4
PA5 3SYNC ADC5 ADC5 AC5 AC5
PA6 4SYNC ADC6 ADC6 AC6 AC1OUT
PA7 5SYNC ADC7 ADC7 AC7 AC0OUT
PORTB PIN# INTERRUPT ADCAPOS/
GAINPOS
ADCBPOS/
GAINPOS
ADCB
NEG
ADCB
GAINNEG
ACB
POS
ACB
NEG
ACBOUT DACB REFB JTAG
PB0 6SYNC ADC8 ADC0 ADC0 AC0 AC0 AREF
PB1 7SYNC ADC9 ADC1 ADC1 AC1 AC1
PB2 8SYNC/
ASYNC ADC10 ADC2 ADC2 AC2 DAC0
PB3 9SYNC ADC11 ADC3 ADC3 AC3 AC3 DAC1
PB4 10 SYNC ADC12 ADC4 ADC4 AC4 TMS
PB5 11 SYNC ADC13 ADC5 ADC5 AC5 AC5 TDI
PB6 12 SYNC ADC14 ADC6 ADC6 AC6 AC1OUT TCK
PB7 13 SYNC ADC15 ADC7 ADC7 AC7 AC0OUT TDO
GND 14
VCC 15
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Table 32-3. Port C - alternate functions.
Notes: 1. Pin mapping of all TC0 can optionally be moved to high nibble of port.
2. If TC0 is configured as TC2 all eight pins can be used for PWM output.
3. Pin mapping of all USART0 can optionally be moved to high nibble of port.
4. Pins MOSI and SCK for all SPI can optionally be swapped.
5. CLKOUT can optionally be moved between port C, D and E and be on pin 4 or 7.
6. EVOUT can optionally be moved between port C, D and E and be on pin 4 or 7.
Table 32-4. Port D - alternate functions.
Notes: 1. Pin mapping of all TC0 can optionally be moved to high nibble of port.
2. If TC0 is configured as TC2 all eight pins can be used for PWM output.
3. Pin mapping of all USART0 can optionally be moved to high nibble of port.
4. Pins MOSI and SCK for all SPI can optionally be swapped.
5. CLKOUT can optionally be moved between port C, D and E and be on pin 4 or 7.
6. EVOUT can optionally be moved between port C, D and E and be on pin 4 or 7.
PORTC PIN# INTERRUPT TCC0
(1)(2)
AWEXC TCC1 USART
C0 (3)
USART
C1
SPIC
(4) TWIC
TWIC
w/ext
driver
CLOCKOUT
(5)
EVENTOUT
(6)
PC0 16 SYNC OC0A OC0ALS SDA SDAIN
PC1 17 SYNC OC0B OC0AHS XCK0 SCL SCLIN
PC2 18 SYNC/
ASYNC OC0C OC0BLS RXD0 SDAOUT
PC3 19 SYNC OC0D OC0BHS TXD0 SCLOUT
PC4 20 SYNC OC0CLS OC1A SS
PC5 21 SYNC OC0CHS OC1B XCK1 MOSI
PC6 22 SYNC OC0DLS RXD1 MISO RTCOUT
PC7 23 SYNC OC0DHS TXD1 SCK clkPER EVOUT
GND 24
VCC 25
PORT D PIN # INTERRUPT TCD0 TCD1 USBD USARTD0 USARTD1 SPID CLOCKOUT EVENTOUT
PD0 26 SYNC OC0A
PD1 27 SYNC OC0B XCK0
PD2 28 SYNC/ASYNC OC0C RXD0
PD3 29 SYNC OC0D TXD0
PD4 30 SYNC OC1A SS
PD5 31 SYNC OC1B XCK1 MOSI
PD6 32 SYNC D- RXD1 MISO
PD7 33 SYNC D+ TXD1 SCK clkPER EVOUT
GND 34
VCC 35
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Table 32-5. Port E - alternate functions.
Notes: 1. Pin mapping of all TC0 can optionally be moved to high nibble of port.
2. If TC0 is configured as TC2 all eight pins can be used for PWM output.
3. Pin mapping of all USART0 can optionally be moved to high nibble of port.
4. Pins MOSI and SCK for all SPI can optionally be swapped.
5. CLKOUT can optionally be moved between port C, D and E and be on pin 4 or 7.
6. EVOUT can optionally be moved between port C, D and E and be on pin 4 or 7.
Table 32-6. Port F - alternate functions.
Table 32-7. Port R - alternate functions.
PORTE PIN # INTERRUPT TCE0 TCE1 USART
E0
USART
E1
SPIE TWIE
TWIE
w/ext
driver
TOSC CLOCKOUT EVENTOUT
PE0 36 SYNC OC0A SDA SDAIN
PE1 37 SYNC OC0B XCK0 SCL SCLIN
PE2 38 SYNC/ASYNC OC0C RXD0 SDAOUT
PE3 39 SYNC OC0D TXD0 SCLOUT
PE4 40 SYNC OC1A SS
PE5 41 SYNC OC1B XCK1 MOSI
PE6 42 SYNC RXD1 MISO TOSC2
PE7 43 SYNC TXD1 SCK TOSC1 clkPER EVOUT
GND 44
VCC 45
PORTF PIN# INTERRUPT TCF0 USARTF0
PF0 46 SYNC OC0A
PF1 47 SYNC OC0B XCK0
PF2 48 SYNC/ASYNC OC0C RXD0
PF3 49 SYNC OC0D TXD0
PF4 50 SYNC
PF5 51 SYNC
GND 52
VCC 53
PF6 54 SYNC
PF7 55 SYNC
PORTR PIN# INTERRUPT PDI XTAL
PDI 56 PDI_DATA
RESET 57 PDI_CLOCK
PR0 58 SYNC XTAL2
PR1 59 SYNC XTAL1
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33. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in Atmel AVR XMEGA A3U. For
complete register description and summary for each peripheral module, refer to the XMEGA AU manual.
Table 33-1. Peripheral module address map.
Base address Name Description
0x0000 GPIO General Purpose IO Registers
0x0010 VPORT0 Virtual Port 0
0x0014 VPORT1 Virtual Port 1
0x0018 VPORT2 Virtual Port 2
0x001C VPORT3 Virtual Port 2
0x0030 CPU CPU
0x0040 CLK Clock Control
0x0048 SLEEP Sleep Controller
0x0050 OSC Oscillator Control
0x0060 DFLLRC32M DFLL for the 32MHz Internal RC Oscillator
0x0068 DFLLRC2M DFLL for the 2MHz RC Oscillator
0x0070 PR Power Reduction
0x0078 RST Reset Controller
0x0080 WDT Watch-Dog Timer
0x0090 MCU MCU Control
0x00A0 PMIC Programmable MUltilevel Interrupt Controller
0x00B0 PORTCFG Port Configuration
0x00C0 AES AES Module
0x00D0 CRC CRC Module
0x0100 DMA DMA Module
0x0180 EVSYS Event System
0x01C0 NVM Non Volatile Memory (NVM) Controller
0x0200 ADCA Analog to Digital Converter on port A
0x0240 ADCB Analog to Digital Converter on port B
0x0320 DACB Digital to Analog Converter on port B
0x0380 ACA Analog Comparator pair on port A
0x0390 ACB Analog Comparator pair on port B
0x0400 RTC Real Time Counter
0x0480 TWIC Two Wire Interface on port C
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0x04A0 TWIE Two Wire Interface on port E
0x04C0 USB Universal Serial Bus Interface
0x0600 PORTA Port A
0x0620 PORTB Port B
0x0640 PORTC Port C
0x0660 PORTD Port D
0x0680 PORTE Port E
0x06A0 PORTF Port F
0x07E0 PORTR Port R
0x0800 TCC0 Timer/Counter 0 on port C
0x0840 TCC1 Timer/Counter 1 on port C
0x0880 AWEXC Advanced Waveform Extension on port C
0x0890 HIRESC High Resolution Extension on port C
0x08A0 USARTC0 USART 0 on port C
0x08B0 USARTC1 USART 1 on port C
0x08C0 SPIC Serial Peripheral Interface on port C
0x08F8 IRCOM Infrared Communication Module
0x0900 TCD0 Timer/Counter 0 on port D
0x0940 TCD1 Timer/Counter 1 on port D
0x0990 HIRESD High Resolution Extension on port D
0x09A0 USARTD0 USART 0 on port D
0x09B0 USARTD1 USART 1 on port D
0x09C0 SPID Serial Peripheral Interface on port D
0x0A00 TCE0 Timer/Counter 0 on port E
0x0A90 HIRESE High Resolution Extension on port E
0x0AA0 USARTE0 USART 0 on port E
0x0AB0 USARTE1 USART 1 on port E
0x0AC0 SPIE Serial Peripheral Interface on port E
0x0B00 TCF0 Timer/Counter 0 on port F
Base address Name Description
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34. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
Arithmetic and Logic Instructions
ADD Rd, Rr Add without Carry Rd ←Rd + Rr Z,C,N,V,S,H 1
ADC Rd, Rr Add with Carry Rd ←Rd + Rr + C Z,C,N,V,S,H 1
ADIW Rd, K Add Immediate to Word Rd ←Rd + 1:Rd + K Z,C,N,V,S 2
SUB Rd, Rr Subtract without Carry Rd ←Rd - Rr Z,C,N,V,S,H 1
SUBI Rd, K Subtract Immediate Rd ←Rd - K Z,C,N,V,S,H 1
SBC Rd, Rr Subtract with Carry Rd ←Rd - Rr - C Z,C,N,V,S,H 1
SBCI Rd, K Subtract Immediate with Carry Rd ←Rd - K - C Z,C,N,V,S,H 1
SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd ←Rd + 1:Rd - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Rd ←Rd • Rr Z,N,V,S 1
ANDI Rd, K Logical AND with Immediate Rd ←Rd • K Z,N,V,S 1
OR Rd, Rr Logical OR Rd ←Rd v Rr Z,N,V,S 1
ORI Rd, K Logical OR with Immediate Rd ←Rd v K Z,N,V,S 1
EOR Rd, Rr Exclusive OR Rd ←Rd ⊕ Rr Z,N,V,S 1
COM Rd One’s Complement Rd ←$FF - Rd Z,C,N,V,S 1
NEG Rd Two’s Complement Rd ←$00 - Rd Z,C,N,V,S,H 1
SBR Rd,K Set Bit(s) in Register Rd ←Rd v K Z,N,V,S 1
CBR Rd,K Clear Bit(s) in Register Rd ←Rd • ($FFh - K) Z,N,V,S 1
INC Rd Increment Rd ←Rd + 1 Z,N,V,S 1
DEC Rd Decrement Rd ←Rd - 1 Z,N,V,S 1
TST Rd Test for Zero or Minus Rd ←Rd • Rd Z,N,V,S 1
CLR Rd Clear Register Rd ←Rd ⊕ Rd Z,N,V,S 1
SER Rd Set Register Rd ←$FF None 1
MUL Rd,Rr Multiply Unsigned R1:R0 ←Rd x Rr (UU) Z,C 2
MULS Rd,Rr Multiply Signed R1:R0 ←Rd x Rr (SS) Z,C 2
MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 ←Rd x Rr (SU) Z,C 2
FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 ←Rd x Rr<<1 (UU) Z,C 2
FMULS Rd,Rr Fractional Multiply Signed R1:R0 ←Rd x Rr<<1 (SS) Z,C 2
FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ←Rd x Rr<<1 (SU) Z,C 2
DES KData Encryption if (H = 0) then R15:R0
else if (H = 1) then R15:R0
←
←
Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
1/2
Branch instructions
RJMP kRelative Jump PC ←PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC(15:0)
PC(21:16)
←
←
Z,
0
None 2
EIJMP Extended Indirect Jump to (Z) PC(15:0)
PC(21:16)
←
←
Z,
EIND
None 2
JMP kJump PC ←kNone 3
RCALL kRelative Call Subroutine PC ←PC + k + 1 None 2 / 3 (1)
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ICALL Indirect Call to (Z) PC(15:0)
PC(21:16)
←
←
Z,
0
None 2 / 3 (1)
EICALL Extended Indirect Call to (Z) PC(15:0)
PC(21:16)
←
←
Z,
EIND
None 3 (1)
CALL kcall Subroutine PC ←kNone 3 / 4 (1)
RET Subroutine Return PC ←STACK None 4 / 5 (1)
RETI Interrupt Return PC ←STACK I4 / 5 (1)
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ←PC + 2 or 3 None 1 / 2 / 3
CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1
CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1
CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ←PC + 2 or 3 None 1 / 2 / 3
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ←PC + 2 or 3 None 1 / 2 / 3
SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ←PC + 2 or 3 None 2 / 3 / 4
SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC ←PC + 2 or 3 None 2 / 3 / 4
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC + k + 1 None 1 / 2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC + k + 1 None 1 / 2
BREQ k Branch if Equal if (Z = 1) then PC ←PC + k + 1 None 1 / 2
BRNE k Branch if Not Equal if (Z = 0) then PC ←PC + k + 1 None 1 / 2
BRCS k Branch if Carry Set if (C = 1) then PC ←PC + k + 1 None 1 / 2
BRCC k Branch if Carry Cleared if (C = 0) then PC ←PC + k + 1 None 1 / 2
BRSH k Branch if Same or Higher if (C = 0) then PC ←PC + k + 1 None 1 / 2
BRLO k Branch if Lower if (C = 1) then PC ←PC + k + 1 None 1 / 2
BRMI k Branch if Minus if (N = 1) then PC ←PC + k + 1 None 1 / 2
BRPL k Branch if Plus if (N = 0) then PC ←PC + k + 1 None 1 / 2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ←PC + k + 1 None 1 / 2
BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ←PC + k + 1 None 1 / 2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ←PC + k + 1 None 1 / 2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ←PC + k + 1 None 1 / 2
BRTS k Branch if T Flag Set if (T = 1) then PC ←PC + k + 1 None 1 / 2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ←PC + k + 1 None 1 / 2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ←PC + k + 1 None 1 / 2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ←PC + k + 1 None 1 / 2
BRIE k Branch if Interrupt Enabled if (I = 1) then PC ←PC + k + 1 None 1 / 2
BRID k Branch if Interrupt Disabled if (I = 0) then PC ←PC + k + 1 None 1 / 2
Data transfer instructions
MOV Rd, Rr Copy Register Rd ←Rr None 1
MOVW Rd, Rr Copy Register Pair Rd+1:Rd ←Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd ←KNone 1
Mnemonics Operands Description Operation Flags #Clocks
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LDS Rd, k Load Direct from data space Rd ←(k) None 2 (1)(2)
LD Rd, X Load Indirect Rd ←(X) None 1 (1)(2)
LD Rd, X+ Load Indirect and Post-Increment Rd
X
←
←
(X)
X + 1
None 1 (1)(2)
LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1,
Rd ← (X)
←
←
X - 1
(X)
None 2 (1)(2)
LD Rd, Y Load Indirect Rd ← (Y) ←(Y) None 1 (1)(2)
LD Rd, Y+ Load Indirect and Post-Increment Rd
Y
←
←
(Y)
Y + 1
None 1 (1)(2)
LD Rd, -Y Load Indirect and Pre-Decrement Y
Rd
←
←
Y - 1
(Y)
None 2 (1)(2)
LDD Rd, Y+q Load Indirect with Displacement Rd ←(Y + q) None 2 (1)(2)
LD Rd, Z Load Indirect Rd ←(Z) None 1 (1)(2)
LD Rd, Z+ Load Indirect and Post-Increment Rd
Z
←
←
(Z),
Z+1
None 1 (1)(2)
LD Rd, -Z Load Indirect and Pre-Decrement Z
Rd
←
←
Z - 1,
(Z)
None 2 (1)(2)
LDD Rd, Z+q Load Indirect with Displacement Rd ←(Z + q) None 2 (1)(2)
STS k, Rr Store Direct to Data Space (k) ←Rd None 2 (1)
ST X, Rr Store Indirect (X) ←Rr None 1 (1)
ST X+, Rr Store Indirect and Post-Increment (X)
X
←
←
Rr,
X + 1
None 1 (1)
ST -X, Rr Store Indirect and Pre-Decrement X
(X)
←
←
X - 1,
Rr
None 2 (1)
ST Y, R r Store Indirect (Y) ←Rr None 1 (1)
ST Y+, Rr Store Indirect and Post-Increment (Y)
Y
←
←
Rr,
Y + 1
None 1 (1)
ST -Y, Rr Store Indirect and Pre-Decrement Y
(Y)
←
←
Y - 1,
Rr
None 2 (1)
STD Y+q, Rr Store Indirect with Displacement (Y + q) ←Rr None 2 (1)
ST Z, Rr Store Indirect (Z) ←Rr None 1 (1)
ST Z+, Rr Store Indirect and Post-Increment (Z)
Z
←
←
Rr
Z + 1
None 1 (1)
ST -Z, Rr Store Indirect and Pre-Decrement Z←Z - 1 None 2 (1)
STD Z+q,Rr Store Indirect with Displacement (Z + q) ←Rr None 2 (1)
LPM Load Program Memory R0 ←(Z) None 3
LPM Rd, Z Load Program Memory Rd ←(Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Increment Rd
Z
←
←
(Z),
Z + 1
None 3
ELPM Extended Load Program Memory R0 ←(RAMPZ:Z) None 3
ELPM Rd, Z Extended Load Program Memory Rd ←(RAMPZ:Z) None 3
ELPM Rd, Z+ Extended Load Program Memory and Post-
Increment
Rd
Z
←
←
(RAMPZ:Z),
Z + 1
None 3
SPM Store Program Memory (RAMPZ:Z) ←R1:R0 None -
SPM Z+ Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
Z
←
←
R1:R0,
Z + 2
None -
Mnemonics Operands Description Operation Flags #Clocks
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IN Rd, A In From I/O Location Rd ←I/O(A) None 1
OUT A, Rr Out To I/O Location I/O(A) ←Rr None 1
PUSH Rr Push Register on Stack STACK ←Rr None 1 (1)
POP Rd Pop Register from Stack Rd ←STACK None 2 (1)
XCH Z, Rd Exchange RAM location Tem p
Rd
(Z)
←
←
←
Rd,
(Z),
Tem p
None 2
LAS Z, Rd Load and Set RAM location Temp
Rd
(Z)
←
←
←
Rd,
(Z),
Tem p v ( Z)
None 2
LAC Z, Rd Load and Clear RAM location Tem p
Rd
(Z)
←
←
←
Rd,
(Z),
($FFh – Rd) z (Z)
None 2
LAT Z, Rd Load and Toggle RAM location Te mp
Rd
(Z)
←
←
←
Rd,
(Z),
Tem p ⊕ (Z)
None 2
Bit and bit-test instructions
LSL Rd Logical Shift Left Rd(n+1)
Rd(0)
C
←
←
←
Rd(n),
0,
Rd(7)
Z,C,N,V,H 1
LSR Rd Logical Shift Right Rd(n)
Rd(7)
C
←
←
←
Rd(n+1),
0,
Rd(0)
Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)
Rd(n+1)
C
←
←
←
C,
Rd(n),
Rd(7)
Z,C,N,V,H 1
ROR Rd Rotate Right Through Carry Rd(7)
Rd(n)
C
←
←
←
C,
Rd(n+1),
Rd(0)
Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ←Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0) ↔Rd(7..4) None 1
BSET sFlag Set SREG(s) ←1SREG(s) 1
BCLR sFlag Clear SREG(s) ←0SREG(s) 1
SBI A, b Set Bit in I/O Register I/O(A, b) ←1None 1
CBI A, b Clear Bit in I/O Register I/O(A, b) ←0None 1
BST Rr, b Bit Store from Register to T T←Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ←TNone 1
SEC Set Carry C←1 C 1
CLC Clear Carry C←0 C 1
SEN Set Negative Flag N←1 N 1
CLN Clear Negative Flag N←0 N 1
SEZ Set Zero Flag Z←1 Z 1
CLZ Clear Zero Flag Z←0 Z 1
SEI Global Interrupt Enable I←1 I 1
CLI Global Interrupt Disable I←0 I 1
SES Set Signed Test Flag S←1 S 1
CLS Clear Signed Test Flag S←0 S 1
Mnemonics Operands Description Operation Flags #Clocks
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Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
SEV Set Two’s Complement Overflow V←1 V 1
CLV Clear Two’s Complement Overflow V←0 V 1
SET Set T in SREG T←1 T 1
CLT Clear T in SREG T←0 T 1
SEH Set Half Carry Flag in SREG H←1 H 1
CLH Clear Half Carry Flag in SREG H←0 H 1
MCU control instructions
BREAK Break (See specific descr. for BREAK) None 1
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep) None 1
WDR Watchdog Reset (see specific descr. for WDR) None 1
Mnemonics Operands Description Operation Flags #Clocks
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35. Packaging information
35.1 64A
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO. REV.
64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness,
0.8mm Lead Pitch, Thin Prole Plastic Quad Flat Package (TQFP) C
64A
2010-10-20
PIN 1 IDENTIFIER
0°~7°
PIN 1
L
C
A1 A2 A
D1
D
e
E1 E
B
COMMON DIMENSIONS
(Unit of measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes:
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 15.75 16.00 16.25
D1 13.90 14.00 14.10 Note 2
E 15.75 16.00 16.25
E1 13.90 14.00 14.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
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35.2 64M2
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO. REV.
64M2, 64-pad, 9 x 9 x 1.0mm Bod y, Lead Pitch 0.50mm , F
64M2
2014-05-30
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
A1 – 0.02 0.05
b
0.18 0.25 0.30
D
D2
7.50 7.65 7.80
8.90 9.00 9.10
8.90 9.00 9.10
E
E2
7.50 7.65 7.80
e
0.50 BSC
L 0.35 0.40
0.45
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D
E
Marked Pin# 1 ID
SEATING PLANE
A1
C
A
C
0.08
1
2
3
K0.20 0.27 0.40
2. Dimension and tolerance conform to ASMEY14.5M-1994.
0.20 REF
A3
A3
E2
D2
be
Pin #1 Corner
L
Pin #1
Triangle
Pin #1
Chamfer
(C 0.30)
Option A
Option B
Pin #1
Notch
(0.20 R)
Option C
K
K
Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
7.65mm Exposed Pad, Package (QFN)
Quad Flat No Lead
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36. Electrical Characteristics
All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and
maximum values are valid across operating temperature and voltage unless other conditions are given.
Note: For devices that are not available yet, preliminary values in this datasheet are based on simulations, and/or
characterization of similar AVR XMEGA microcontrollers. After the device is characterized the final values will be
available, hence existing values can change. Missing minimum and maximum values will be available after the
device is characterized.
36.1 ATxmega64A3U
36.1.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 36-1 under may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or other conditions beyond those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 36-1. Absolute maximum ratings.
36.1.2 General Operating Ratings
The device must operate within the ratings listed in Table 36-2 in order for all other electrical characteristics and
typical characteristics of the device to be valid.
Table 36-2. General operating conditions.
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power Supply Voltage -0.3 4 V
IVCC Current into a VCC pin 200 mA
IGND Current out of a Gnd pin 200 mA
VPIN
Pin voltage with respect to
Gnd and VCC
-0.5 VCC+0.5 V
IPIN I/O pin sink/source current -25 25 mA
TAStorage temperature -65 150 °C
TjJunction temperature 150 °C
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power Supply Voltage 1.60 3.6 V
AVCC Analog Supply Voltage 1.60 3.6 V
TATemperature range
85 °C -40 85
°C
105 °C -40 105
TjJunction temperature
85°C -40 105
°C
105°C -40 125
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Table 36-3. Operating voltage and frequency.
The maximum CPU clock frequency depends on VCC. As shown in Figure 36-1 the Frequency vs. VCC curve is
linear between 1.8V < VCC <2.7V.
Figure 36-1. Maximum Frequency vs. VCC.
Symbol Parameter Condition Min. Typ. Max. Units
ClkCPU CPU clock frequency
VCC = 1.6V 012
MHz
VCC = 1.8V 012
VCC = 2.7V 032
VCC = 3.6V 032
1.8
12
32
MHz
V
2.7 3.6
1.6
Safe Operating Area
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36.1.3 Current consumption
Table 36-4. Current consumption for active mode and sleep modes.
Notes: 1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Active Power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 50
µA
VCC = 3.0V 125
1MHz, Ext. Clk
VCC = 1.8V 250
VCC = 3.0V 520
2MHz, Ext. Clk
VCC = 1.8V 450 550
VCC = 3.0V
0.9 1.4
mA
32MHz, Ext. Clk 9.5 15
Idle Power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 3.0
µA
VCC = 3.0V 4.8
1MHz, Ext. Clk
VCC = 1.8V 75
VCC = 3.0V 140
2MHz, Ext. Clk
VCC = 1.8V 145 250
VCC = 3.0V
275 450
32MHz, Ext. Clk 4.4 7.0 mA
Power-down power
consumption
T = 25°C
VCC = 3.0V
0.1 1.0
µA
T = 85°C 1.6 5.0
T = 105°C 1.6 7
WDT and Sampled BOD enabled,
T = 25°C
VCC = 3.0V
1.3 3.0
WDT and Sampled BOD enabled,
T = 85°C 2.5 7.0
WDT and Sampled BOD enabled,
T = 105°C 2.5 8
Power-save power
consumption (2)
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
VCC = 1.8V 1.2
µA
VCC = 3.0V 1.3
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
VCC = 1.8V 0.6 2
VCC = 3.0V 0.7 2
RTC from low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V 0.8 3
VCC = 3.0V 1.0 3
Reset power consumption Current through RESET pin
substracted VCC = 3.0V 150 µA
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Table 36-5. Current consumption for modules and peripherals.
Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external
clock without prescaling, T = 25°C unless other conditions are given.
Symbol Parameter Condition(1) Min. Typ. Max. Units
ICC
ULP oscillator 1.0 µA
32.768kHz int. oscillator 26 µA
2MHz int. oscillator
85
µA
DFLL enabled with 32.768kHz int. osc. as reference 115
32MHz int. oscillator
270
µA
DFLL enabled with 32.768kHz int. osc. as reference 460
PLL 20x multiplication factor,
32MHz int. osc. DIV4 as reference 220 µA
Watchdog Timer 1µA
BOD
Continuous mode 138
µA
Sampled mode, includes ULP oscillator 1.2
Internal 1.0V reference 100 µA
Temperature sensor 95 µA
ADC 250ksps
VREF = Ext ref
3.0
mA
CURRLIMIT = LOW 2.6
CURRLIMIT = MEDIUM 2.1
CURRLIMIT = HIGH 1.6
DAC
250ksps
VREF = Ext ref
No load
Normal mode 1.9
mA
Low Power mode 1.1
AC
High Speed Mode 330
µA
Low Power Mode 130
DMA 615KBps between I/O registers and SRAM 115 µA
Timer/Counter 16 µA
USART Rx and Tx enabled, 9600 BAUD 2.5 µA
Flash memory and EEPROM programming 4mA
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36.1.4 Wake-up time from sleep modes
Table 36-6. Device wake-up time from sleep modes with various system clock sources.
Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-2. All peripherals and modules
start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 36-2. Wake-up time definition.
Symbol Parameter Condition Min. Typ. (1) Max. Units
twakeup
Wake-up time from Idle,
Standby, and Extended Standby
mode
External 2MHz clock 2
µs
32.768kHz internal oscillator 120
2MHz internal oscillator 2
32MHz internal oscillator 0.2
Wake-up time from Power-save
and Power-down mode
External 2MHz clock 4.5
µs
32.768kHz internal oscillator 320
2MHz internal oscillator 9
32MHz internal oscillator 5
Wakeup request
Clock output
Wakeup time
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36.1.5 I/O Pin Characteristics
The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and
output voltage limits reflect or exceed this specification.
Table 36-7. I/O pin characteristics.
Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
Symbol Parameter Condition Min. Typ. Max. Units
IOH (1)/
IOL (2) I/O pin source/sink current -20 20 mA
VIH High Level Input Voltage
VCC = 2.7 - 3.6V 2 VCC+0.3
VVCC = 2.0 - 2.7V 0.7*VCC VCC+0.3
VCC = 1.6 - 2.0V 0.8*VCC VCC+0.3
VIL Low Level Input Voltage
VCC = 2.7- 3.6V -0.3 0.8
VVCC = 2.0 - 2.7V -0.3 0.3*VCC
VCC = 1.6 - 2.0V -0.3 0.2*VCC
VOH High Level Output Voltage
VCC = 3.0 - 3.6V IOH = -2mA 2.4 0.94*VCC
V
VCC = 2.3 - 2.7V
IOH = -1mA 2.0 0.96*VCC
IOH = -2mA 1.7 0.92*VCC
VCC = 3.3V IOH = -8mA 2.6 2.9
VCC = 3.0V IOH = -6mA 2.1 2.6
VCC = 1.8V IOH = -2mA 1.4 1.6
VOL Low Level Output Voltage
VCC = 3.0 - 3.6V IOL = 2mA 0.05*VCC 0.4
V
VCC = 2.3 - 2.7V
IOL = 1mA 0.03*VCC 0.4
IOL = 2mA 0.06*VCC 0.7
VCC = 3.3V IOL = 15mA 0.4 0.76
VCC = 3.0V IOL = 10mA 0.3 0.64
VCC = 1.8V IOL = 5mA 0.3 0.46
IIN Input Leakage Current T = 25°C <0.01 0.1 µA
RPPull/Buss keeper Resistor 27 kΩ
trRise time No load
4
ns
slew rate limitation 7
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36.1.6 ADC characteristics
Table 36-8. Power supply, reference and input range.
Table 36-9. Clock and timing.
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC- 0.3 VCC+ 0.3 V
VREF Reference voltage 1AVCC- 0.6 V
Rin Input resistance Switched 5.0 kΩ
Csample Input capacitance Switched 5.0 pF
RAREF Reference input resistance (leakage only) >10 MΩ
CAREF Reference input capacitance Static load 7pF
VIN Input range -0.1 AVCC+0.1 V
Conversion range Differential mode, Vinp - Vinn -VREF VREF V
VIN Conversion range Single ended unsigned mode, Vinp -ΔV VREF-ΔV V
∆VFixed offset voltage 190 LSB
Symbol Parameter Condition Min. Typ. Max. Units
ClkADC ADC Clock frequency
Maximum is 1/4 of Peripheral clock
frequency 100 2000
kHz
Measuring internal signals 100 125
fADC Sample rate
Current limitation (CURRLIMIT) off 100 2000
ksps
CURRLIMIT = LOW 100 1500
CURRLIMIT = MEDIUM 100 1000
CURRLIMIT = HIGH 100 500
Sampling Time 1/2 ClkADC cycle 0.25 5µs
Conversion time (latency) (RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12 5 8 ClkADC
cycles
Start-up time ADC clock cycles 12 24 ClkADC
cycles
ADC settling time
After changing reference or input mode 7 7 ClkADC
cycles
After ADC flush 1 1
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Table 36-10. Accuracy characteristics.
Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 36-11. Gain stage characteristics.
Symbol Parameter Condition (2) Min. Typ. Max. Units
RES Resolution Programmable to 8 or 12 bit 812 12 Bits
INL (1) Integral non-linearity
500ksps
VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2
lsb
All VREF ±1.5 ±3
2000ksps
VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2
All VREF ±1.5 ±3
DNL (1) Differential non-linearity guaranteed monotonic <±0.8 <±1 lsb
Offset Error
-1 mV
Temperature drift <0.01 mV/K
Operating voltage drift <0.6 mV/V
Gain Error
Differential
mode
External reference -1
mV
AVCC/1.6 10
AVCC/2.0 8
Bandgap ±5
Temperature drift <0.02 mV/K
Operating voltage drift <0.5 mV/V
Noise Differential mode, shorted input
2msps, VCC = 3.6V, ClkPER = 16MHz 0.4 mV
rms
Symbol Parameter Condition Min. Typ. Max. Units
Rin Input resistance Switched in normal mode 4.0 kΩ
Csample Input capacitance Switched in normal mode 4.4 pF
Signal range Gain stage output 0 VCC- 0.6 V
Propagation delay ADC conversion rate 1ClkADC
cycles
Sample rate Same as ADC 100 1000 kHz
INL (1) Integral Non-Linearity 500ksps All gain
settings ±1.5 ±4 lsb
Gain Error
1x gain, normal mode -0.8
%8x gain, normal mode -2.5
64x gain, normal mode -3.5
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Note: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
36.1.7 DAC Characteristics
Table 36-12. Power supply, reference and output range.
Table 36-13. Clock and timing.
Offset Error,
input referred
1x gain, normal mode -2
mV8x gain, normal mode -5
64x gain, normal mode -4
Noise
1x gain, normal mode
VCC = 3.6V
Ext. VREF
0.5
mV
rms
8x gain, normal mode 1.5
64x gain, normal mode 11
Symbol Parameter Condition Min. Typ. Max. Units
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC- 0.3 VCC+ 0.3
AVREF External reference voltage 1.0 VCC- 0.6 V
Rchannel DC output impedance 50 Ω
Linear output voltage range 0.15 AVCC-0.15 V
RAREF Reference input resistance >10 MΩ
CAREF Reference input capacitance Static load 7pF
Minimum Resistance load 1 kΩ
Maximum capacitance load
100 pF
1000Ω serial resistance 1nF
Output sink/source
Operating within accuracy specification AVCC/1000
mA
Safe operation 10
Symbol Parameter Condition Min. Typ. Max. Units
fDAC Conversion rate Cload=100pF,
maximum step size
Normal mode 01000
ksps
Low power mode 0500
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Table 36-14. Accuracy characteristics.
Note: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.
36.1.8 Analog Comparator Characteristics
Table 36-15. Analog Comparator characteristics.
Symbol Parameter Condition Min. Typ. Max. Units
RES Input Resolution 12 Bits
INL (1) Integral non-linearity
VREF= Ext 1.0V
VCC = 1.6V ±2.0 ±3
lsb
VCC = 3.6V ±1.5 ±2.5
VREF=AVCC
VCC = 1.6V ±2.0 ±4
VCC = 3.6V ±1.5 ±4
VREF=INT1V
VCC = 1.6V ±5.0
VCC = 3.6V ±5.0
DNL (1) Differential non-linearity
VREF=Ext 1.0V
VCC = 1.6V ±1.5 3
lsb
VCC = 3.6V ±0.6 1.5
VREF=AVCC
VCC = 1.6V ±1.0 3.5
VCC = 3.6V ±0.6 1.5
VREF=INT1V
VCC = 1.6V ±4.5
VCC = 3.6V ±4.5
Gain error After calibration <4 lsb
Gain calibration step size 4lsb
Gain calibration drift VREF= Ext 1.0V <0.2 mV/K
Offset error After calibration <1 lsb
Offset calibration step size 1
Symbol Parameter Condition Min. Typ. Max. Units
Voff Input Offset Voltage <±10 mV
Ilk Input Leakage Current <1 nA
Input voltage range -0.1 AVCC V
AC startup time 100 µs
Vhys1 Hysteresis, None 0mV
Vhys2 Hysteresis, Small
mode = High Speed (HS) 13
mV
mode = Low Power (LP) 30
Vhys3 Hysteresis, Large
mode = HS 30
mV
mode = LP 60
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36.1.9 Bandgap and Internal 1.0V Reference Characteristics
Table 36-16. Bandgap and Internal 1.0V reference characteristics.
36.1.10 Brownout Detection Characteristics
Table 36-17. Brownout detection characteristics.
tdelay Propagation delay
mode = HS
VCC = 3.0V,
T= 85°C 60 90
ns
VCC = 1.6V - 3.6V
30
mode = LP 160
64-Level Voltage Scaler Integral non-linearity (INL) 0.3 0.5 lsb
Symbol Parameter Condition Min. Typ. Max. Units
Symbol Parameter Condition Min. Typ. Max. Units
Startup time
As reference for ADC or DAC 1 ClkPER + 2.5µs
µs
As input voltage to ADC and AC 1.5
Bandgap voltage 1.1 V
INT1V Internal 1.00V reference T= 85°C, after calibration 0.99 11.01 V
Variation over voltage and temperature Relative to T= 85°C, VCC = 3.0V ±1.0 %
Symbol Parameter Condition Min. Typ. Max. Units
VBOT
BOD level 0 falling VCC 1.60 1.62 1.72
V
BOD level 1 falling VCC 1.8
BOD level 2 falling VCC 2.0
BOD level 3 falling VCC 2.2
BOD level 4 falling VCC 2.4
BOD level 5 falling VCC 2.6
BOD level 6 falling VCC 2.8
BOD level 7 falling VCC 3.0
tBOD Detection time
Continuous mode 0.4
µs
Sampled mode 1000
VHYST Hysteresis 1.6 %
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36.1.11 External Reset Characteristics
Table 36-18. External reset characteristics.
36.1.12 Power-on Reset Characteristics
Table 36-19. Power-on reset characteristics.
Note: 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
36.1.13 Flash and EEPROM Memory Characteristics
Table 36-20. Endurance and data retention.
Symbol Parameter Condition Min. Typ. Max. Units
tEXT Minimum reset pulse width 95 1000 ns
VRST
Reset threshold voltage (VIH)
VCC = 2.7 - 3.6V 0.60*VCC
V
VCC = 1.6 - 2.7V 0.70*VCC
Reset threshold voltage (VIL)
VCC = 2.7 - 3.6V 0.40*VCC
VCC = 1.6 - 2.7V 0.30*VCC
RRST Reset pin Pull-up Resistor 25 kΩ
Symbol Parameter Condition Min. Typ. Max. Units
VPOT- (1) POR threshold voltage falling VCC
VCC falls faster than 1V/ms 0.4 1.0
V
VCC falls at 1V/ms or slower 0.8 1.0
VPOT+ POR threshold voltage rising VCC 1.3 1.59 V
Symbol Parameter Condition Min. Typ. Max. Units
Flash
Write/Erase cycles
25°C 10K
Cycle85°C 10K
105°C 2K
Data retention
25°C 100
Year85°C 25
105°C 10
EEPROM
Write/Erase cycles
25°C 100K
Cycle85°C 100K
105°C 30K
Data retention
25°C 100
Year85°C 25
105°C 10
85
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Table 36-21. Programming time.
Notes: 1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
36.1.14 Clock and Oscillator Characteristics
36.1.14.1 Calibrated 32.768kHz Internal Oscillator characteristics
Table 36-22. 32.768kHz internal oscillator characteristics.
36.1.14.2 Calibrated 2MHz RC Internal Oscillator characteristics
Table 36-23. 2MHz internal oscillator characteristics.
Symbol Parameter Condition Min. Typ. (1) Max. Units
Chip Erase 64KB Flash, EEPROM (2) and SRAM Erase 55 ms
Application Erase Section erase 6ms
Flash
Page Erase 4
msPage Write 4
Atomic Page Erase and Write 8
EEPROM
Page Erase 4
msPage Write 4
Atomic Page Erase and Write 8
Symbol Parameter Condition Min. Typ. Max. Units
Frequency 32.768 kHz
Factory calibration accuracy T = 85°C, VCC = 3.0V -0.5 0.5 %
User calibration accuracy -0.5 0.5 %
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 1.8 2.2 MHz
Factory calibrated frequency 2.0 MHz
Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5 %
User calibration accuracy -0.2 0.2 %
DFLL calibration stepsize 0.22 %
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36.1.14.3 Calibrated and tunable 32MHz internal oscillator characteristics
Table 36-24. 32MHz internal oscillator characteristics.
36.1.14.4 32kHz Internal ULP Oscillator characteristics
Table 36-25. 32kHz internal ULP oscillator characteristics.
36.1.14.5 Internal Phase Locked Loop (PLL) characteristics
Table 36-26. Internal PLL characteristics.
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 30 55 MHz
Factory calibrated frequency 32 MHz
Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5 %
User calibration accuracy -0.2 0.2 %
DFLL calibration step size 0.23 %
Symbol Parameter Condition Min. Typ. Max. Units
Output frequency 32 kHz
Accuracy -30 30 %
Symbo
lParameter Condition Min. Typ. Max. Units
fIN Input Frequency Output frequency must be within fOUT 0.4 64 MHz
fOUT Output frequency (1) VCC= 1.6 - 1.8V 20 48
MHz
VCC= 2.7 - 3.6V 20 128
Start-up time 25 µs
Re-lock time 25 µs
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36.1.14.6 External clock characteristics
Figure 36-3. External clock drive waveform
Table 36-27. External clock used as system clock without prescaling.
Note: 1. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
tCH
tCL
tCK
tCH
VIL1
VIH1
tCR tCF
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (1) VCC = 1.6 - 1.8V 012
MHz
VCC = 2.7 - 3.6V 032
tCK Clock Period
VCC = 1.6 - 1.8V 83.3
ns
VCC = 2.7 - 3.6V 31.5
tCH Clock High Time
VCC = 1.6 - 1.8V 30.0
ns
VCC = 2.7 - 3.6V 12.5
tCL Clock Low Time
VCC = 1.6 - 1.8V 30.0
ns
VCC = 2.7 - 3.6V 12.5
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
ns
VCC = 2.7 - 3.6V 3
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
ns
VCC = 2.7 - 3.6V 3
ΔtCK Change in period from one clock cycle to the next 10 %
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Table 36-28. External clock with prescaler (1)for system clock.
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
36.1.14.7 External 16MHz crystal oscillator and XOSC characteristics
Table 36-29. External 16MHz crystal oscillator and XOSC characteristics..
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (2) VCC = 1.6 - 1.8V 090
MHz
VCC = 2.7 - 3.6V 0142
tCK Clock Period
VCC = 1.6 - 1.8V 11
ns
VCC = 2.7 - 3.6V 7
tCH Clock High Time
VCC = 1.6 - 1.8V 4.5
ns
VCC = 2.7 - 3.6V 2.4
tCL Clock Low Time
VCC = 1.6 - 1.8V 4.5
ns
VCC = 2.7 - 3.6V 2.4
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
ns
VCC = 2.7 - 3.6V 1.0
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
ns
VCC = 2.7 - 3.6V 1.0
ΔtCK Change in period from one clock cycle to the next 10 %
Symbol Parameter Condition Min. Typ. Max. Units
Cycle to cycle jitter
XOSCPWR=0
FRQRANGE=0 <10
nsFRQRANGE=1, 2, or 3 <1
XOSCPWR=1 <1
Long term jitter
XOSCPWR=0
FRQRANGE=0 <6
nsFRQRANGE=1, 2, or 3 <0.5
XOSCPWR=1 <0.5
Frequency error
XOSCPWR=0
FRQRANGE=0 <0.1
%
FRQRANGE=1 <0.05
FRQRANGE=2 or 3 <0.005
XOSCPWR=1 <0.005
Duty cycle
XOSCPWR=0
FRQRANGE=0 40
%
FRQRANGE=1 42
FRQRANGE=2 or 3 45
XOSCPWR=1 48
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Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
RQ
Negative impedance
(1)
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF 2.4k
Ω
1MHz crystal, CL=20pF 8.7k
2MHz crystal, CL=20pF 2.1k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
2MHz crystal 4.2k
8MHz crystal 250
9MHz crystal 195
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
8MHz crystal 360
9MHz crystal 285
12MHz crystal 155
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
9MHz crystal 365
12MHz crystal 200
16MHz crystal 105
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
9MHz crystal 435
12MHz crystal 235
16MHz crystal 125
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
9MHz crystal 495
12MHz crystal 270
16MHz crystal 145
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal 305
16MHz crystal 160
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal 380
16MHz crystal 205
ESR SF = Safety factor min(RQ)/SF kΩ
CXTAL1
Parasitic
capacitance XTAL1
pin
5.2 pF
CXTAL2
Parasitic
capacitance XTAL2
pin
6.8 pF
CLOAD
Parasitic
capacitance load 2.95 pF
Symbol Parameter Condition Min. Typ. Max. Units
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36.1.14.8 External 32.768kHz crystal oscillator and TOSC characteristics
Table 36-30. External 32.768kHz crystal oscillator and TOSC characteristics.
Note: 1. See Figure 36-4 for definition.
Figure 36-4. TOSC input capacitance.
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when
oscillating without external capacitors.
Symbol Parameter Condition Min. Typ. Max. Units
ESR/R1 Recommended crystal equivalent
series resistance (ESR)
Crystal load capacitance 6.5pF 60
kΩ
Crystal load capacitance 9.0pF 35
CTOSC1 Parasitic capacitance TOSC1 pin 4.2 pF
CTOSC2 Parasitic capacitance TOSC2 pin 4.3 pF
Recommended safety factor capacitance load matched to
crystal specification 3
C
L1
C
L2
2CS
O
T
1
CS
O
TDevice internal
External
32.768kHz crystal
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36.1.15 SPI Characteristics
Figure 36-5. SPI timing requirements in master mode.
Figure 36-6. SPI timing requirements in slave mode.
MSB LSB
BSLBSM
t
MOS
t
MIS
t
MIH
t
SCKW
t
SCK
t
MOH
t
MOH
t
SCKF
t
SCKR
t
SCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB LSB
BSLBSM
t
SIS
t
SIH
t
SSCKW
t
SSCKW
t
SSCK
t
SSH
t
SOSSH
t
SCKR
t
SCKF
t
SOS
t
SSS
t
SOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
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Table 36-31. SPI timing characteristics and requirements.
Symbol Parameter Condition Min. Typ. Max. Units
tSCK SCK Period Master (See Table 21-4 in
XMEGA AU Manual)
ns
tSCKW SCK high/low width Master 0.5*SCK
tSCKR SCK Rise time Master 2.7
tSCKF SCK Fall time Master 2.7
tMIS MISO setup to SCK Master 11
tMIH MISO hold after SCK Master 0
tMOS MOSI setup SCK Master 0.5*tSCK
tMOH MOSI hold after SCK Master 1
tSSCK Slave SCK Period Slave 4*t ClkPER
tSSCKW SCK high/low width Slave 2*t ClkPER
tSSCKR SCK Rise time Slave 1600
tSSCKF SCK Fall time Slave 1600
tSIS MOSI setup to SCK Slave 3
tSIH MOSI hold after SCK Slave tsck
tSSS SS setup to SCK Slave 20
tSSH SS hold after SCK Slave 20
tSOS MISO setup SCK Slave 8
tSOH MISO hold after SCK Slave 13
tSOSS MISO setup after SS low Slave 11
tSOSH MISO hold after SS high Slave 8
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36.1.16 Two-Wire Interface Characteristics
Table 36-32 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR
XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols
refer to Figure 36-7.
Figure 36-7. Two-wire interface bus timing.
Table 36-32. Two-wire interface characteristics.
tHD;STA
tof
SDA
SCL
tLOW
tHIGH
tSU;STA
tBUF
tr
tHD;DAT tSU;DAT tSU;STO
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input High Voltage 0.7*VCC VCC+0.5 V
VIL Input Low Voltage -0.5 0.3*VCC V
Vhys Hysteresis of Schmitt Trigger Inputs 0.05*VCC (1) 0 V
VOL Output Low Voltage 3mA, sink current 00.4 V
trRise Time for both SDA and SCL 20+0.1Cb (1)(2) 0ns
tof Output Fall Time from VIHmin to VILmax 10pF < Cb < 400pF (2) 20+0.1Cb (1)(2) 300 ns
tSP Spikes Suppressed by Input Filter 050 ns
IIInput Current for each I/O Pin 0.1VCC < VI < 0.9VCC -10 10 µA
CICapacitance for each I/O Pin 10 pF
fSCL SCL Clock Frequency fPER (3)>max(10fSCL, 250kHz) 0400 kHz
RPValue of Pull-up resistor
fSCL ≤ 100kHz
Ω
fSCL > 100kHz
tHD;STA Hold Time (repeated) START condition
fSCL ≤ 100kHz 4.0
µs
fSCL > 100kHz 0.6
tLOW Low Period of SCL Clock
fSCL ≤ 100kHz 4.7
µs
fSCL > 100kHz 1.3
tHIGH High Period of SCL Clock
fSCL ≤ 100kHz 4.0
µs
fSCL > 100kHz 0.6
VCC 0.4V–
3mA
----------------------------
100ns
Cb
---------------
300ns
Cb
---------------
94
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Notes: 1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
tSU;STA
Set-up time for a repeated START
condition
fSCL ≤ 100kHz 4.7
µs
fSCL > 100kHz 0.6
tHD;DAT Data hold time
fSCL ≤ 100kHz 03.45
µs
fSCL > 100kHz 00.9
tSU;DAT Data setup time
fSCL ≤ 100kHz 250
ns
fSCL > 100kHz 100
tSU;STO Setup time for STOP condition
fSCL ≤ 100kHz 4.0
µs
fSCL > 100kHz 0.6
tBUF
Bus free time between a STOP and
START condition
fSCL ≤ 100kHz 4.7
µs
fSCL > 100kHz 1.3
Symbol Parameter Condition Min. Typ. Max. Units
95
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36.2 ATxmega128A3U
36.2.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 36-1 under may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or other conditions beyond those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 36-33. Absolute maximum ratings.
36.2.2 General Operating Ratings
The device must operate within the ratings listed in Table 36-2 in order for all other electrical characteristics and
typical characteristics of the device to be valid.
Table 36-34. General operating conditions.
Table 36-35. Operating voltage and frequency.
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power Supply Voltage -0.3 4 V
IVCC Current into a VCC pin 200 mA
IGND Current out of a Gnd pin 200 mA
VPIN
Pin voltage with respect to
Gnd and VCC
-0.5 VCC+0.5 V
IPIN I/O pin sink/source current -25 25 mA
TAStorage temperature -65 150 °C
TjJunction temperature 150 °C
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power Supply Voltage 1.60 3.6 V
AVCC Analog Supply Voltage 1.60 3.6 V
TATemperature range
85 °C -40 85
°C
105 °C -40 105
TjJunction temperature
85°C -40 105
°C
105°C -40 125
Symbol Parameter Condition Min. Typ. Max. Units
ClkCPU CPU clock frequency
VCC = 1.6V 012
MHz
VCC = 1.8V 012
VCC = 2.7V 032
VCC = 3.6V 032
97
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36.2.3 Current consumption
Table 36-36. Current consumption for active mode and sleep modes.
Notes: 1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Active Power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 60
µA
VCC = 3.0V 140
1MHz, Ext. Clk
VCC = 1.8V 280
VCC = 3.0V 600
2MHz, Ext. Clk
VCC = 1.8V 510 600
VCC = 3.0V
1.1 1.5
mA
32MHz, Ext. Clk 10.5 15
Idle Power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 4.3
µA
VCC = 3.0V 4.8
1MHz, Ext. Clk
VCC = 1.8V 78
VCC = 3.0V 147
2MHz, Ext. Clk
VCC = 1.8V 156 250
VCC = 3.0V
293 600
32MHz, Ext. Clk 4.7 7mA
Power-down power
consumption
T = 25°C
VCC = 3.0V
0.1 1.0
µA
T = 85°C 1.75 5.0
T= 105°C 4 8
WDT and Sampled BOD enabled,
T = 25°C
VCC = 3.0V
1.2 3.0
WDT and Sampled BOD enabled,
T = 85°C 3.1 7
WDT and Sampled BOD enabled,
T = 105°C 5.3 10
Power-save power
consumption (2)
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
VCC = 1.8V 1.2
µA
VCC = 3.0V 1.3
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
VCC = 1.8V 0.5 2
VCC = 3.0V 0.7 2
RTC from low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V 0.9 3
VCC = 3.0V 1.2 3.5
Reset power consumption Current through RESET pin
substracted VCC = 3.0V 150 µA
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Table 36-37. Current consumption for modules and peripherals.
Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at
VCC = 3.0V, ClkSYS = 1MHz external clock without prescaling, T = 25°C unless other conditions are givenAll parameters
measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock without
prescaling, T = 25°C unless other conditions are given.
Symbol Parameter Condition(1) Min. Typ. Max. Units
ICC
ULP oscillator 1.0 µA
32.768kHz int. oscillator 27 µA
2MHz int. oscillator
85
µA
DFLL enabled with 32.768kHz int. osc. as reference 115
32MHz int. oscillator
270
µA
DFLL enabled with 32.768kHz int. osc. as reference 460
PLL 20x multiplication factor,
32MHz int. osc. DIV4 as reference 220 µA
Watchdog Timer 1µA
BOD
Continuous mode 138
µA
Sampled mode, includes ULP oscillator 1.2
Internal 1.0V reference 100 µA
Temperature sensor 95 µA
ADC 250ksps
VREF = Ext ref
3.0
mA
CURRLIMIT = LOW 2.6
CURRLIMIT = MEDIUM 2.1
CURRLIMIT = HIGH 1.6
DAC
250ksps
VREF = Ext ref
No load
Normal mode 1.9
mA
Low Power mode 1.1
AC
High Speed Mode 330
µA
Low Power Mode 130
DMA 615KBps between I/O registers and SRAM 115 µA
Timer/Counter 16 µA
USART Rx and Tx enabled, 9600 BAUD 2.5 µA
Flash memory and EEPROM programming 4mA
99
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36.2.4 Wake-up time from sleep modes
Table 36-38. Device wake-up time from sleep modes with various system clock sources.
Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-2. All peripherals and modules
start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 36-9. Wake-up time definition.
Symbol Parameter Condition Min. Typ. (1) Max. Units
twakeup
Wake-up time from Idle,
Standby, and Extended Standby
mode
External 2MHz clock 2
µs
32.768kHz internal oscillator 120
2MHz internal oscillator 2
32MHz internal oscillator 0.2
Wake-up time from Power-save
and Power-down mode
External 2MHz clock 4.5
µs
32.768kHz internal oscillator 320
2MHz internal oscillator 9
32MHz internal oscillator 5
Wakeup request
Clock output
Wakeup time
100
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36.2.5 I/O Pin Characteristics
The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and
output voltage limits reflect or exceed this specification.
Table 36-39. I/O pin characteristics.
Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
Symbol Parameter Condition Min. Typ. Max. Units
IOH (1)/
IOL (2) I/O pin source/sink current -20 20 mA
VIH High Level Input Voltage
VCC = 2.7 - 3.6V 2 VCC+0.3
VVCC = 2.0 - 2.7V 0.7*VCC VCC+0.3
VCC = 1.6 - 2.0V 0.8*VCC VCC+0.3
VIL Low Level Input Voltage
VCC = 2.7- 3.6V -0.3 0.8
VVCC = 2.0 - 2.7V -0.3 0.2*VCC
VCC = 1.6 - 2.0V -0.3 0.2*VCC
VOH High Level Output Voltage
VCC = 3.0 - 3.6V IOH = -2mA 2.4 0.19
V
VCC = 2.3 - 2.7V
IOH = -1mA 2.0 2.44
IOH = -2mA 1.7 2.37
VCC = 3.3V IOH = -8mA 2.6 2.9
VCC = 3.0V IOH = -6mA 2.1 2.6
VCC = 1.8V IOH = -2mA 1.4 1.6
VOL Low Level Output Voltage
VCC = 3.0 - 3.6V IOL = 2mA 0.05 0.4
V
VCC = 2.3 - 2.7V
IOL = 1mA 0.03 0.4
IOL = 2mA 0.05 0.7
VCC = 3.3V IOL = 15mA 0.4 0.76
VCC = 3.0V IOL = 10mA 0.3 0.64
VCC = 1.8V IOL = 5mA 0.2 0.46
IIN Input Leakage Current T = 25°C <0.01 0.1 µA
RPPull/Buss keeper Resistor 27 kΩ
trRise time No load
4
ns
slew rate limitation 7
101
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36.2.6 ADC characteristics
Table 36-40. Power supply, reference and input range.
Table 36-41. Clock and timing.
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC- 0.3 VCC+ 0.3 V
VREF Reference voltage 1AVCC- 0.6 V
Rin Input resistance Switched 5.0 kΩ
Csample Input capacitance Switched 5.0 pF
RAREF Reference input resistance (leakage only) >10 MΩ
CAREF Reference input capacitance Static load 7pF
VIN Input range -0.1 AVCC+0.1 V
Conversion range Differential mode, Vinp - Vinn -VREF VREF V
VIN Conversion range Single ended unsigned mode, Vinp -ΔV VREF-ΔV V
∆VFixed offset voltage 190 LSB
Symbol Parameter Condition Min. Typ. Max. Units
ClkADC ADC Clock frequency
Maximum is 1/4 of Peripheral clock
frequency 100 2000
kHz
Measuring internal signals 100 125
fADC Sample rate
Current limitation (CURRLIMIT) off 100 2000
ksps
CURRLIMIT = LOW 100 1500
CURRLIMIT = MEDIUM 100 1000
CURRLIMIT = HIGH 100 500
Sampling Time 1/2 ClkADC cycle 0.25 5µs
Conversion time (latency) (RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12 5 8 ClkADC
cycles
Start-up time ADC clock cycles 12 24 ClkADC
cycles
ADC settling time
After changing reference or input mode 7 7 ClkADC
cycles
After ADC flush 1 1
102
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Table 36-42. Accuracy characteristics.
Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 36-43. Gain stage characteristics.
Symbol Parameter Condition (2) Min. Typ. Max. Units
RES Resolution Programmable to 8 or 12 bit 812 12 Bits
INL (1) Integral non-linearity
500ksps
VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2
lsb
All VREF ±1.5 ±3
2000ksps
VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2
All VREF ±1.5 ±3
DNL (1) Differential non-linearity guaranteed monotonic <±0.8 <±1 lsb
Offset Error
-1 mV
Temperature drift <0.01 mV/K
Operating voltage drift <0.6 mV/V
Gain Error
Differential
mode
External reference -1
mV
AVCC/1.6 10
AVCC/2.0 8
Bandgap ±5
Temperature drift <0.02 mV/K
Operating voltage drift <0.5 mV/V
Noise Differential mode, shorted input
2msps, VCC = 3.6V, ClkPER = 16MHz 0.4 mV
rms
Symbol Parameter Condition Min. Typ. Max. Units
Rin Input resistance Switched in normal mode 4.0 kΩ
Csample Input capacitance Switched in normal mode 4.4 pF
Signal range Gain stage output 0 VCC- 0.6 V
Propagation delay ADC conversion rate 1ClkADC
cycles
Sample rate Same as ADC 100 1000 kHz
INL (1) Integral Non-Linearity 500ksps All gain
settings ±1.5 ±4 lsb
Gain Error
1x gain, normal mode -0.8
%8x gain, normal mode -2.5
64x gain, normal mode -3.5
103
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Note: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
36.2.7 DAC Characteristics
Table 36-44. Power supply, reference and output range.
Table 36-45. Clock and timing.
Offset Error,
input referred
1x gain, normal mode -2
mV8x gain, normal mode -5
64x gain, normal mode -4
Noise
1x gain, normal mode
VCC = 3.6V
Ext. VREF
0.5
mV
rms
8x gain, normal mode 1.5
64x gain, normal mode 11
Symbol Parameter Condition Min. Typ. Max. Units
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC- 0.3 VCC+ 0.3
AVREF External reference voltage 1.0 VCC- 0.6 V
Rchannel DC output impedance 50 Ω
Linear output voltage range 0.15 AVCC-0.15 V
RAREF Reference input resistance >10 MΩ
CAREF Reference input capacitance Static load 7pF
Minimum Resistance load 1 kΩ
Maximum capacitance load
100 pF
1000Ω serial resistance 1nF
Output sink/source
Operating within accuracy specification AVCC/1000
mA
Safe operation 10
Symbol Parameter Condition Min. Typ. Max. Units
fDAC Conversion rate Cload=100pF,
maximum step size
Normal mode 01000
ksps
Low power mode 0500
104
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Table 36-46. Accuracy characteristics.
Note: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.
36.2.8 Analog Comparator Characteristics
Table 36-47. Analog Comparator characteristics.
Symbol Parameter Condition Min. Typ. Max. Units
RES Input Resolution 12 Bits
INL (1) Integral non-linearity
VREF= Ext 1.0V
VCC = 1.6V ±2.0 ±3
lsb
VCC = 3.6V ±1.5 ±2.5
VREF=AVCC
VCC = 1.6V ±2.0 ±4
VCC = 3.6V ±1.5 ±4
VREF=INT1V
VCC = 1.6V ±5.0
VCC = 3.6V ±5.0
DNL (1) Differential non-linearity
VREF=Ext 1.0V
VCC = 1.6V ±1.5 3
lsb
VCC = 3.6V ±0.6 1.5
VREF=AVCC
VCC = 1.6V ±1.0 3.5
VCC = 3.6V ±0.6 1.5
VREF=INT1V
VCC = 1.6V ±4.5
VCC = 3.6V ±4.5
Gain error After calibration <4 lsb
Gain calibration step size 4lsb
Gain calibration drift VREF= Ext 1.0V <0.2 mV/K
Offset error After calibration <1 lsb
Offset calibration step size 1
Symbol Parameter Condition Min. Typ. Max. Units
Voff Input Offset Voltage <±10 mV
Ilk Input Leakage Current <1 nA
Input voltage range -0.1 AVCC V
AC startup time 100 µs
Vhys1 Hysteresis, None 0mV
Vhys2 Hysteresis, Small
mode = High Speed (HS) 13
mV
mode = Low Power (LP) 30
Vhys3 Hysteresis, Large
mode = HS 30
mV
mode = LP 60
105
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36.2.9 Bandgap and Internal 1.0V Reference Characteristics
Table 36-48. Bandgap and Internal 1.0V reference characteristics.
36.2.10 Brownout Detection Characteristics
Table 36-49. Brownout detection characteristics.
tdelay Propagation delay
mode = HS
VCC = 3.0V, T= 85°C 90 100
ns
VCC = 1.6V - 3.6V
95
mode = LP 200 500
64-Level Voltage Scaler Integral non-linearity (INL) 0.5 1.0 lsb
Symbol Parameter Condition Min. Typ. Max. Units
Symbol Parameter Condition Min. Typ. Max. Units
Startup time
As reference for ADC or DAC 1 ClkPER + 2.5µs
µs
As input voltage to ADC and AC 1.5
Bandgap voltage 1.1 V
INT1V Internal 1.00V reference T= 85°C, after calibration 0.99 11.01
Variation over voltage and temperature Relative to T= 85°C, VCC = 3.0V ±1.0 %
Symbol Parameter Condition Min. Typ. Max. Units
VBOT
BOD level 0 falling VCC 1.60 1.62 1.72
V
BOD level 1 falling VCC 1.8
BOD level 2 falling VCC 2.0
BOD level 3 falling VCC 2.2
BOD level 4 falling VCC 2.4
BOD level 5 falling VCC 2.6
BOD level 6 falling VCC 2.8
BOD level 7 falling VCC 3.0
tBOD Detection time
Continuous mode 0.4
µs
Sampled mode 1000
VHYST Hysteresis 1.6 %
106
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36.2.11 External Reset Characteristics
Table 36-50. External reset characteristics.
36.2.12 Power-on Reset Characteristics
Table 36-51. Power-on reset characteristics.
Note: 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
36.2.13 Flash and EEPROM Memory Characteristics
Table 36-52. Endurance and data retention.
Symbol Parameter Condition Min. Typ. Max. Units
tEXT Minimum reset pulse width 95 1000 ns
VRST
Reset threshold voltage (VIH)
VCC = 3.0 - 3.6V 0.50*VCC
V
VCC = 2.3 - 2.7V 0.40*VCC
Reset threshold voltage (VIL)
VCC = 3.0 - 3.6V 0.50*VCC
VCC = 2.3 - 2.7V 0.40*VCC
RRST Reset pin Pull-up Resistor 25 kΩ
Symbol Parameter Condition Min. Typ. Max. Units
VPOT- (1) POR threshold voltage falling VCC
VCC falls faster than 1V/ms 0.4 1.0
V
VCC falls at 1V/ms or slower 0.8 1.3
VPOT+ POR threshold voltage rising VCC 1.3 1.59 V
Symbol Parameter Condition Min. Typ. Max. Units
Flash
Write/Erase cycles
25°C 10K
Cycle85°C 10K
105°C 2K
Data retention
25°C 100
Year85°C 25
105°C 10
EEPROM
Write/Erase cycles
25°C 100K
Cycle85°C 100K
105°C 30K
Data retention
25°C 100
Year85°C 25
105°C 10
107
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Table 36-53. Programming time.
Notes: 1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
36.2.14 Clock and Oscillator Characteristics
36.2.14.1 Calibrated 32.768kHz Internal Oscillator characteristics
Table 36-54. 32.768kHz internal oscillator characteristics.
36.2.14.2 Calibrated 2MHz RC Internal Oscillator characteristics
Table 36-55. 2MHz internal oscillator characteristics.
Symbol Parameter Condition Min. Typ. (1) Max. Units
Chip Erase 128KB Flash, EEPROM (2) and SRAM Erase 75 ms
Application Erase Section erase 6ms
Flash
Page Erase 4
msPage Write 4
Atomic Page Erase and Write 8
EEPROM
Page Erase 4
msPage Write 4
Atomic Page Erase and Write 8
Symbol Parameter Condition Min. Typ. Max. Units
Frequency 32.768 kHz
Factory calibration accuracy T = 85°C, VCC = 3.0V -0.5 0.5 %
User calibration accuracy -0.5 0.5 %
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 1.8 2.2 MHz
Factory calibrated frequency 2.0 MHz
Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5 %
User calibration accuracy -0.2 0.2 %
DFLL calibration stepsize 0.22 %
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36.2.14.3 Calibrated and tunable 32MHz internal oscillator characteristics
Table 36-56. 32MHz internal oscillator characteristics.
36.2.14.4 32kHz Internal ULP Oscillator characteristics
Table 36-57. 32kHz internal ULP oscillator characteristics.
36.2.14.5 Internal Phase Locked Loop (PLL) characteristics
Table 36-58. Internal PLL characteristics.
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 30 55 MHz
Factory calibrated frequency 32 MHz
Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5 %
User calibration accuracy -0.2 0.2 %
DFLL calibration step size 0.23 %
Symbol Parameter Condition Min. Typ. Max. Units
Output frequency 32 kHz
Accuracy -30 30 %
Symbo
lParameter Condition Min. Typ. Max. Units
fIN Input Frequency Output frequency must be within fOUT 0.4 64 MHz
fOUT Output frequency (1) VCC= 1.6 - 1.8V 20 48
MHz
VCC= 2.7 - 3.6V 20 128
Start-up time 25 µs
Re-lock time 25 µs
109
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36.2.14.6 External clock characteristics
Figure 36-10. External clock drive waveform
Table 36-59. External clock used as system clock without prescaling.
Note: 1. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
tCH
tCL
tCK
tCH
VIL1
VIH1
tCR tCF
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (1) VCC = 1.6 - 1.8V 012
MHz
VCC = 2.7 - 3.6V 032
tCK Clock Period
VCC = 1.6 - 1.8V 83.3
ns
VCC = 2.7 - 3.6V 31.5
tCH Clock High Time
VCC = 1.6 - 1.8V 30.0
ns
VCC = 2.7 - 3.6V 12.5
tCL Clock Low Time
VCC = 1.6 - 1.8V 30.0
ns
VCC = 2.7 - 3.6V 12.5
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
ns
VCC = 2.7 - 3.6V 3
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
ns
VCC = 2.7 - 3.6V 3
ΔtCK Change in period from one clock cycle to the next 10 %
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Table 36-60. External clock with prescaler (1)for system clock.
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
36.2.14.7 External 16MHz crystal oscillator and XOSC characteristics
Table 36-61. External 16MHz crystal oscillator and XOSC characteristics..
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (2) VCC = 1.6 - 1.8V 090
MHz
VCC = 2.7 - 3.6V 0142
tCK Clock Period
VCC = 1.6 - 1.8V 11
ns
VCC = 2.7 - 3.6V 7
tCH Clock High Time
VCC = 1.6 - 1.8V 4.5
ns
VCC = 2.7 - 3.6V 2.4
tCL Clock Low Time
VCC = 1.6 - 1.8V 4.5
ns
VCC = 2.7 - 3.6V 2.4
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
ns
VCC = 2.7 - 3.6V 1.0
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
ns
VCC = 2.7 - 3.6V 1.0
ΔtCK Change in period from one clock cycle to the next 10 %
Symbol Parameter Condition Min. Typ. Max. Units
Cycle to cycle jitter
XOSCPWR=0
FRQRANGE=0 <10
nsFRQRANGE=1, 2, or 3 <1
XOSCPWR=1 <1
Long term jitter
XOSCPWR=0
FRQRANGE=0 <6
nsFRQRANGE=1, 2, or 3 <0.5
XOSCPWR=1 <0.5
Frequency error
XOSCPWR=0
FRQRANGE=0 <0.1
%
FRQRANGE=1 <0.05
FRQRANGE=2 or 3 <0.005
XOSCPWR=1 <0.005
Duty cycle
XOSCPWR=0
FRQRANGE=0 40
%
FRQRANGE=1 42
FRQRANGE=2 or 3 45
XOSCPWR=1 48
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Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
RQ
Negative
impedance (1)
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF 2.4k
Ω
1MHz crystal, CL=20pF 8.7k
2MHz crystal, CL=20pF 2.1k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
2MHz crystal 4.2k
8MHz crystal 250
9MHz crystal 195
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
8MHz crystal 360
9MHz crystal 285
12MHz crystal 155
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
9MHz crystal 365
12MHz crystal 200
16MHz crystal 105
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
9MHz crystal 435
12MHz crystal 235
16MHz crystal 125
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
9MHz crystal 495
12MHz crystal 270
16MHz crystal 145
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal 305
16MHz crystal 160
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal 380
16MHz crystal 205
ESR SF = Safety factor min(RQ)/SF kΩ
CXTAL1
Parasitic
capacitance XTAL1
pin
5.2 pF
CXTAL2
Parasitic
capacitance XTAL2
pin
6.8 pF
CLOAD
Parasitic
capacitance load 2.95 pF
Symbol Parameter Condition Min. Typ. Max. Units
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36.2.14.8 External 32.768kHz crystal oscillator and TOSC characteristics
Table 36-62. External 32.768kHz crystal oscillator and TOSC characteristics.
Note: 1. See Figure 36-4 for definition.
Figure 36-11. TOSC input capacitance.
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when
oscillating without external capacitors.
Symbol Parameter Condition Min. Typ. Max. Units
ESR/R1 Recommended crystal equivalent
series resistance (ESR)
Crystal load capacitance 6.5pF 60
kΩ
Crystal load capacitance 9.0pF 35
CTOSC1 Parasitic capacitance TOSC1 pin 4.2 pF
CTOSC2 Parasitic capacitance TOSC2 pin 4.3 pF
Recommended safety factor capacitance load matched to
crystal specification 3
C
L1
C
L2
2CS
O
T
1
CS
O
TDevice internal
External
32.768kHz crystal
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36.2.15 SPI Characteristics
Figure 36-12. SPI timing requirements in master mode.
Figure 36-13. SPI timing requirements in slave mode.
MSB LSB
BSLBSM
t
MOS
t
MIS
t
MIH
t
SCKW
t
SCK
t
MOH
t
MOH
t
SCKF
t
SCKR
t
SCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB LSB
BSLBSM
t
SIS
t
SIH
t
SSCKW
t
SSCKW
t
SSCK
t
SSH
t
SOSSH
t
SCKR
t
SCKF
t
SOS
t
SSS
t
SOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
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Table 36-63. SPI timing characteristics and requirements.
Symbol Parameter Condition Min. Typ. Max. Units
tSCK SCK Period Master (See Table 21-4 in
XMEGA AU Manual)
ns
tSCKW SCK high/low width Master 0.5*SCK
tSCKR SCK Rise time Master 2.7
tSCKF SCK Fall time Master 2.7
tMIS MISO setup to SCK Master 11
tMIH MISO hold after SCK Master 0
tMOS MOSI setup SCK Master 0.5*tSCK
tMOH MOSI hold after SCK Master 1
tSSCK Slave SCK Period Slave >4*t ClkPER
tSSCKW SCK high/low width Slave >2*t ClkPER
tSSCKR SCK Rise time Slave 1600
tSSCKF SCK Fall time Slave 1600
tSIS MOSI setup to SCK Slave 3
tSIH MOSI hold after SCK Slave tSCK
tSSS SS setup to SCK Slave 20
tSSH SS hold after SCK Slave 20
tSOS MISO setup SCK Slave 8
tSOH MISO hold after SCK Slave 13
tSOSS MISO setup after SS low Slave 11
tSOSH MISO hold after SS high Slave 8
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36.2.16 Two-Wire Interface Characteristics
Table 36-32 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR
XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols
refer to Figure 36-7.
Figure 36-14. Two-wire interface bus timing.
Table 36-64. Two-wire interface characteristics.
tHD;STA
tof
SDA
SCL
tLOW
tHIGH
tSU;STA
tBUF
tr
tHD;DAT tSU;DAT tSU;STO
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input High Voltage 0.7*VCC VCC+0.5 V
VIL Input Low Voltage -0.5 0.3*VCC V
Vhys Hysteresis of Schmitt Trigger Inputs 0.05*VCC (1) 0 V
VOL Output Low Voltage 3mA, sink current 00.4 V
trRise Time for both SDA and SCL 20+0.1Cb (1)(2) 0ns
tof Output Fall Time from VIHmin to VILmax 10pF < Cb < 400pF (2) 20+0.1Cb (1)(2) 300 ns
tSP Spikes Suppressed by Input Filter 050 ns
IIInput Current for each I/O Pin 0.1VCC < VI < 0.9VCC -10 10 µA
CICapacitance for each I/O Pin 10 pF
fSCL SCL Clock Frequency fPER (3)>max(10fSCL, 250kHz) 0400 kHz
RPValue of Pull-up resistor
fSCL ≤ 100kHz
Ω
fSCL > 100kHz
tHD;STA Hold Time (repeated) START condition
fSCL ≤ 100kHz 4.0
µs
fSCL > 100kHz 0.6
tLOW Low Period of SCL Clock
fSCL ≤ 100kHz 4.7
µs
fSCL > 100kHz 1.3
tHIGH High Period of SCL Clock
fSCL ≤ 100kHz 4.0
µs
fSCL > 100kHz 0.6
VCC 0.4V–
3mA
----------------------------
100ns
Cb
---------------
300ns
Cb
---------------
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Notes: 1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
tSU;STA
Set-up time for a repeated START
condition
fSCL ≤ 100kHz 4.7
µs
fSCL > 100kHz 0.6
tHD;DAT Data hold time
fSCL ≤ 100kHz 03.5
µs
fSCL > 100kHz 00.9
tSU;DAT Data setup time
fSCL ≤ 100kHz 250
ns
fSCL > 100kHz 100
tSU;STO Setup time for STOP condition
fSCL ≤ 100kHz 4.0
µs
fSCL > 100kHz 0.6
tBUF
Bus free time between a STOP and
START condition
fSCL ≤ 100kHz 4.7
µs
fSCL > 100kHz 1.3
Symbol Parameter Condition Min. Typ. Max. Units
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36.3 ATxmega192A3U
36.3.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 36-1 under may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or other conditions beyond those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 36-65. Absolute maximum ratings.
36.3.2 General Operating Ratings
The device must operate within the ratings listed in Table 36-2 in order for all other electrical characteristics and
typical characteristics of the device to be valid.
Table 36-66. General operating conditions.
Table 36-67. Operating voltage and frequency.
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power Supply Voltage -0.3 4 V
IVCC Current into a VCC pin 200 mA
IGND Current out of a Gnd pin 200 mA
VPIN
Pin voltage with respect to
Gnd and VCC
-0.5 VCC+0.5 V
IPIN I/O pin sink/source current -25 25 mA
TAStorage temperature -65 150 °C
TjJunction temperature 150 °C
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power Supply Voltage 1.60 3.6 V
AVCC Analog Supply Voltage 1.60 3.6 V
TATemperature range
85 °C -40 85
°C
105 °C -40 105
TjJunction temperature
85°C -40 105
°C
105°C -40 125
Symbol Parameter Condition Min. Typ. Max. Units
ClkCPU CPU clock frequency
VCC = 1.6V 012
MHz
VCC = 1.8V 012
VCC = 2.7V 032
VCC = 3.6V 032
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36.3.3 Current consumption
Table 36-68. Current consumption for active mode and sleep modes.
Notes: 1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Active Power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 60
µA
VCC = 3.0V 140
1MHz, Ext. Clk
VCC = 1.8V 260
VCC = 3.0V 600
2MHz, Ext. Clk
VCC = 1.8V 510 600
VCC = 3.0V
1.1 1.5
mA
32MHz, Ext. Clk 10.6 15
Idle Power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 4.3
µA
VCC = 3.0V 4.8
1MHz, Ext. Clk
VCC = 1.8V 78
VCC = 3.0V 150
2MHz, Ext. Clk
VCC = 1.8V 150 350
VCC = 3.0V
290 600
32MHz, Ext. Clk 4.7 7.0 mA
Power-down power
consumption
T = 25°C
VCC = 3.0V
0.1 1.0
µA
T = 85°C 1.8 5.0
T = 105°C 6.5 17
WDT and Sampled BOD enabled,
T = 25°C
VCC = 3.0V
1.3 3.0
WDT and Sampled BOD enabled,
T = 85°C 3.1 7.0
WDT and Sampled BOD enabled,
T = 105°C 7.3 20
Power-save power
consumption (2)
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
VCC = 1.8V 1.2
µA
VCC = 3.0V 1.3
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
VCC = 1.8V 0.6 2
VCC = 3.0V 0.7 2
RTC from low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V 0.8 3
VCC = 3.0V 1.0 3
Reset power consumption Current through RESET pin
substracted VCC = 3.0V 250 µA
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Table 36-69. Current consumption for modules and peripherals.
Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at
VCC = 3.0V, ClkSYS = 1MHz external clock without prescaling, T = 25°C unless other conditions are givenAll parameters
measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock without
prescaling, T = 25°C unless other conditions are given.
Symbol Parameter Condition(1) Min. Typ. Max. Units
ICC
ULP oscillator 1.0 µA
32.768kHz int. oscillator 27 µA
2MHz int. oscillator
85
µA
DFLL enabled with 32.768kHz int. osc. as reference 115
32MHz int. oscillator
270
µA
DFLL enabled with 32.768kHz int. osc. as reference 460
PLL 20x multiplication factor,
32MHz int. osc. DIV4 as reference 220 µA
Watchdog Timer 1µA
BOD
Continuous mode 138
µA
Sampled mode, includes ULP oscillator 1.2
Internal 1.0V reference 100 µA
Temperature sensor 95 µA
ADC 250ksps
VREF = Ext ref
3.0
mA
CURRLIMIT = LOW 2.6
CURRLIMIT = MEDIUM 2.1
CURRLIMIT = HIGH 1.6
DAC
250ksps
VREF = Ext ref
No load
Normal mode 1.9
mA
Low Power mode 1.1
AC
High Speed Mode 330
µA
Low Power Mode 130
DMA 615KBps between I/O registers and SRAM 115 µA
Timer/Counter 16 µA
USART Rx and Tx enabled, 9600 BAUD 2.5 µA
Flash memory and EEPROM programming 4mA
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36.3.4 Wake-up time from sleep modes
Table 36-70. Device wake-up time from sleep modes with various system clock sources.
Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-2. All peripherals and modules
start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 36-16. Wake-up time definition.
Symbol Parameter Condition Min. Typ. (1) Max. Units
twakeup
Wake-up time from Idle,
Standby, and Extended Standby
mode
External 2MHz clock 2
µs
32.768kHz internal oscillator 120
2MHz internal oscillator 2
32MHz internal oscillator 0.2
Wake-up time from Power-save
and Power-down mode
External 2MHz clock 4.5
µs
32.768kHz internal oscillator 320
2MHz internal oscillator 9
32MHz internal oscillator 5
Wakeup request
Clock output
Wakeup time
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36.3.5 I/O Pin Characteristics
The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and
output voltage limits reflect or exceed this specification.
Table 36-71. I/O pin characteristics.
Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
Symbol Parameter Condition Min. Typ. Max. Units
IOH (1)/
IOL (2) I/O pin source/sink current -20 20 mA
VIH High Level Input Voltage
VCC = 2.7 - 3.6V 2 VCC+0.3
VVCC = 2.0 - 2.7V 0.7*VCC VCC+0.3
VCC = 1.6 - 2.0V 0.8*VCC VCC+0.3
VIL Low Level Input Voltage
VCC = 2.7- 3.6V -0.3 0.8
VVCC = 2.0 - 2.7V -0.3 0.3*VCC
VCC = 1.6 - 2.0V -0.3 0.2*VCC
VOH High Level Output Voltage
VCC = 3.0 - 3.6V IOH = -2mA 2.4 0.94*VCC
V
VCC = 2.3 - 2.7V
IOH = -1mA 2.0 0.96*VCC
IOH = -2mA 1.7 0.92*VCC
VCC = 3.3V IOH = -8mA 2.6 2.9
VCC = 3.0V IOH = -6mA 2.1 2.6
VCC = 1.8V IOH = -2mA 1.4 1.6
VOL Low Level Output Voltage
VCC = 3.0 - 3.6V IOL = 2mA 0.05*VCC 0.4
V
VCC = 2.3 - 2.7V
IOL = 1mA 0.03*VCC 0.4
IOL = 2mA 0.06*VCC 0.7
VCC = 3.3V IOL = 15mA 0.4 0.76
VCC = 3.0V IOL = 10mA 0.3 0.64
VCC = 1.8V IOL = 5mA 0.3 0.46
IIN Input Leakage Current T = 25°C <0.001 0.1 µA
RPPull/Buss keeper Resistor 27 kΩ
trRise time No load
4
ns
slew rate limitation 7
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36.3.6 ADC characteristics
Table 36-72. Power supply, reference and input range.
Table 36-73. Clock and timing.
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC- 0.3 VCC+ 0.3 V
VREF Reference voltage 1AVCC- 0.6 V
Rin Input resistance Switched 4.0 kΩ
Csample Input capacitance Switched 4.4 pF
RAREF Reference input resistance (leakage only) >10 MΩ
CAREF Reference input capacitance Static load 7pF
VIN Input range -0.1 AVCC+0.1 V
Conversion range Differential mode, Vinp - Vinn -VREF VREF V
VIN Conversion range Single ended unsigned mode, Vinp -ΔV VREF-ΔV V
∆VFixed offset voltage 190 LSB
Symbol Parameter Condition Min. Typ. Max. Units
ClkADC ADC Clock frequency
Maximum is 1/4 of Peripheral clock
frequency 100 2000
kHz
Measuring internal signals 100 125
fADC Sample rate
Current limitation (CURRLIMIT) off 100 2000
ksps
CURRLIMIT = LOW 100 1500
CURRLIMIT = MEDIUM 100 1000
CURRLIMIT = HIGH 100 500
Sampling Time 1/2 ClkADC cycle 0.25 5µs
Conversion time (latency) (RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12 5 8 ClkADC
cycles
Start-up time ADC clock cycles 12 24 ClkADC
cycles
ADC settling time
After changing reference or input mode 7 7 ClkADC
cycles
After ADC flush 1 1
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Table 36-74. Accuracy characteristics.
Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 36-75. Gain stage characteristics.
Symbol Parameter Condition (2) Min. Typ. Max. Units
RES Resolution Programmable to 8 or 12 bit 812 12 Bits
INL (1) Integral non-linearity
500ksps
VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2
lsb
All VREF ±1.5 ±3
2000ksps
VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2
All VREF ±1.5 ±3
DNL (1) Differential non-linearity guaranteed monotonic <±0.8 <±1 lsb
Offset Error
-1 mV
Temperature drift <0.01 mV/K
Operating voltage drift <0.6 mV/V
Gain Error
Differential
mode
External reference -1
mV
AVCC/1.6 10
AVCC/2.0 8
Bandgap ±5
Temperature drift <0.02 mV/K
Operating voltage drift <0.5 mV/V
Noise Differential mode, shorted input
2msps, VCC = 3.6V, ClkPER = 16MHz 0.4 mV
rms
Symbol Parameter Condition Min. Typ. Max. Units
Rin Input resistance Switched in normal mode 4.0 kΩ
Csample Input capacitance Switched in normal mode 4.4 pF
Signal range Gain stage output 0 VCC- 0.6 V
Propagation delay ADC conversion rate 1ClkADC
cycles
Sample rate Same as ADC 100 1000 kHz
INL (1) Integral Non-Linearity 500ksps All gain
settings ±1.5 ±4 lsb
Gain Error
1x gain, normal mode -0.8
%8x gain, normal mode -2.5
64x gain, normal mode -3.5
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Note: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
36.3.7 DAC Characteristics
Table 36-76. Power supply, reference and output range.
Table 36-77. Clock and timing.
Offset Error,
input referred
1x gain, normal mode -2
mV8x gain, normal mode -5
64x gain, normal mode -4
Noise
1x gain, normal mode
VCC = 3.6V
Ext. VREF
0.5
mV
rms
8x gain, normal mode 1.5
64x gain, normal mode 11
Symbol Parameter Condition Min. Typ. Max. Units
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC- 0.3 VCC+ 0.3
AVREF External reference voltage 1.0 VCC- 0.6 V
Rchannel DC output impedance 50 Ω
Linear output voltage range 0.15 AVCC-0.15 V
RAREF Reference input resistance >10 MΩ
CAREF Reference input capacitance Static load 7pF
Minimum Resistance load 1 kΩ
Maximum capacitance load
100 pF
1000Ω serial resistance 1nF
Output sink/source
Operating within accuracy specification AVCC/1000
mA
Safe operation 10
Symbol Parameter Condition Min. Typ. Max. Units
fDAC Conversion rate Cload=100pF,
maximum step size
Normal mode 01000
ksps
Low power mode 0500
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Table 36-78. Accuracy characteristics.
Note: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.
36.3.8 Analog Comparator Characteristics
Table 36-79. Analog Comparator characteristics.
Symbol Parameter Condition Min. Typ. Max. Units
RES Input Resolution 12 Bits
INL (1) Integral non-linearity
VREF= Ext 1.0V
VCC = 1.6V ±2.0 ±3
lsb
VCC = 3.6V ±1.5 ±2.5
VREF=AVCC
VCC = 1.6V ±2.0 ±4
VCC = 3.6V ±1.5 ±4
VREF=INT1V
VCC = 1.6V ±5.0
VCC = 3.6V ±5.0
DNL (1) Differential non-linearity
VREF=Ext 1.0V
VCC = 1.6V ±1.5 3
lsb
VCC = 3.6V ±0.6 1.5
VREF=AVCC
VCC = 1.6V ±1.0 3.5
VCC = 3.6V ±0.6 1.5
VREF=INT1V
VCC = 1.6V ±4.5
VCC = 3.6V ±4.5
Gain error After calibration <4 lsb
Gain calibration step size 4lsb
Gain calibration drift VREF= Ext 1.0V <0.2 mV/K
Offset error After calibration <1 lsb
Offset calibration step size 1
Symbol Parameter Condition Min. Typ. Max. Units
Voff Input Offset Voltage <±10 mV
Ilk Input Leakage Current <1 nA
Input voltage range -0.1 AVCC V
AC startup time 100 µs
Vhys1 Hysteresis, None 0mV
Vhys2 Hysteresis, Small
mode = High Speed (HS) 13
mV
mode = Low Power (LP) 30
Vhys3 Hysteresis, Large
mode = HS 30
mV
mode = LP 60
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36.3.9 Bandgap and Internal 1.0V Reference Characteristics
Table 36-80. Bandgap and Internal 1.0V reference characteristics.
36.3.10 Brownout Detection Characteristics
Table 36-81. Brownout detection characteristics.
tdelay Propagation delay
VCC = 3.0V, T= 85°C mode = HS 30 90
ns
mode = HS 30
VCC = 3.0V, T= 85°C mode = LP 130 500
mode = LP 130
64-Level Voltage Scaler Integral non-linearity (INL) 0.3 0.5 lsb
Symbol Parameter Condition Min. Typ. Max. Units
Symbol Parameter Condition Min. Typ. Max. Units
Startup time
As reference for ADC or DAC 1 ClkPER + 2.5µs
µs
As input voltage to ADC and AC 1.5
Bandgap voltage 1.1 V
INT1V Internal 1.00V reference T= 85°C, after calibration 0.99 11.01 mV
Variation over voltage and temperature Relative to T= 85°C, VCC = 3.0V ±1.0 %
Symbol Parameter Condition Min. Typ. Max. Units
VBOT
BOD level 0 falling VCC 1.60 1.62 1.72
V
BOD level 1 falling VCC 1.8
BOD level 2 falling VCC 2.0
BOD level 3 falling VCC 2.2
BOD level 4 falling VCC 2.4
BOD level 5 falling VCC 2.6
BOD level 6 falling VCC 2.8
BOD level 7 falling VCC 3.0
tBOD Detection time
Continuous mode 0.4
µs
Sampled mode 1000
VHYST Hysteresis 1.6 %
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36.3.11 External Reset Characteristics
Table 36-82. External reset characteristics.
36.3.12 Power-on Reset Characteristics
Table 36-83. Power-on reset characteristics.
Note: 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
36.3.13 Flash and EEPROM Memory Characteristics
Table 36-84. Endurance and data retention.
Symbol Parameter Condition Min. Typ. Max. Units
tEXT Minimum reset pulse width 95 1000 ns
VRST
Reset threshold voltage (VIH)
VCC = 2.7 - 3.6V 0.60*VCC
V
VCC = 1.6 - 2.7V 0.70*VCC
Reset threshold voltage (VIL)
VCC = 2.7 - 3.6V 0.40*VCC
VCC = 1.6 - 2.7V 0.30*VCC
RRST Reset pin Pull-up Resistor 25 kΩ
Symbol Parameter Condition Min. Typ. Max. Units
VPOT- (1) POR threshold voltage falling VCC
VCC falls faster than 1V/ms 0.4 1.0
V
VCC falls at 1V/ms or slower 0.8 1.0
VPOT+ POR threshold voltage rising VCC 1.3 1.59 V
Symbol Parameter Condition Min. Typ. Max. Units
Flash
Write/Erase cycles
25°C 10K
Cycle85°C 10K
105°C 2K
Data retention
25°C 100
Year85°C 25
105°C 10
EEPROM
Write/Erase cycles
25°C 100K
Cycle85°C 100K
105°C 30K
Data retention
25°C 100
Year85°C 25
105°C 10
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Table 36-85. Programming time.
Notes: 1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
36.3.14 Clock and Oscillator Characteristics
36.3.14.1 Calibrated 32.768kHz Internal Oscillator characteristics
Table 36-86. 32.768kHz internal oscillator characteristics.
36.3.14.2 Calibrated 2MHz RC Internal Oscillator characteristics
Table 36-87. 2MHz internal oscillator characteristics.
Symbol Parameter Condition Min. Typ. (1) Max. Units
Chip Erase 192KB Flash, EEPROM (2) and SRAM Erase 90 ms
Application Erase Section erase 6ms
Flash
Page Erase 4
msPage Write 4
Atomic Page Erase and Write 8
EEPROM
Page Erase 4
msPage Write 4
Atomic Page Erase and Write 8
Symbol Parameter Condition Min. Typ. Max. Units
Frequency 32.768 kHz
Factory calibration accuracy T = 85°C, VCC = 3.0V -0.5 0.5 %
User calibration accuracy -0.5 0.5 %
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 1.8 2.2 MHz
Factory calibrated frequency 2.0 MHz
Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5 %
User calibration accuracy -0.2 0.2 %
DFLL calibration stepsize 0.22 %
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36.3.14.3 Calibrated and tunable 32MHz internal oscillator characteristics
Table 36-88. 32MHz internal oscillator characteristics.
36.3.14.4 32kHz Internal ULP Oscillator characteristics
Table 36-89. 32kHz internal ULP oscillator characteristics.
36.3.14.5 Internal Phase Locked Loop (PLL) characteristics
Table 36-90. Internal PLL characteristics.
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 30 55 MHz
Factory calibrated frequency 32 MHz
Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5 %
User calibration accuracy -0.2 0.2 %
DFLL calibration step size 0.23 %
Symbol Parameter Condition Min. Typ. Max. Units
Output frequency 32 kHz
Accuracy -30 30 %
Symbo
lParameter Condition Min. Typ. Max. Units
fIN Input Frequency Output frequency must be within fOUT 0.4 64 MHz
fOUT Output frequency (1) VCC= 1.6 - 1.8V 20 48
MHz
VCC= 2.7 - 3.6V 20 128
Start-up time 25 µs
Re-lock time 25 µs
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36.3.14.6 External clock characteristics
Figure 36-17. External clock drive waveform
Table 36-91. External clock used as system clock without prescaling.
Note: 1. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
tCH
tCL
tCK
tCH
VIL1
VIH1
tCR tCF
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (1) VCC = 1.6 - 1.8V 012
MHz
VCC = 2.7 - 3.6V 032
tCK Clock Period
VCC = 1.6 - 1.8V 83.3
ns
VCC = 2.7 - 3.6V 31.5
tCH Clock High Time
VCC = 1.6 - 1.8V 30.0
ns
VCC = 2.7 - 3.6V 12.5
tCL Clock Low Time
VCC = 1.6 - 1.8V 30.0
ns
VCC = 2.7 - 3.6V 12.5
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
ns
VCC = 2.7 - 3.6V 3
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
ns
VCC = 2.7 - 3.6V 3
ΔtCK Change in period from one clock cycle to the next 10 %
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Table 36-92. External clock with prescaler (1)for system clock.
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
36.3.14.7 External 16MHz crystal oscillator and XOSC characteristics
Table 36-93. External 16MHz crystal oscillator and XOSC characteristics..
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (2) VCC = 1.6 - 1.8V 090
MHz
VCC = 2.7 - 3.6V 0142
tCK Clock Period
VCC = 1.6 - 1.8V 11
ns
VCC = 2.7 - 3.6V 7
tCH Clock High Time
VCC = 1.6 - 1.8V 4.5
ns
VCC = 2.7 - 3.6V 2.4
tCL Clock Low Time
VCC = 1.6 - 1.8V 4.5
ns
VCC = 2.7 - 3.6V 2.4
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
ns
VCC = 2.7 - 3.6V 1.0
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
ns
VCC = 2.7 - 3.6V 1.0
ΔtCK Change in period from one clock cycle to the next 10 %
Symbol Parameter Condition Min. Typ. Max. Units
Cycle to cycle jitter
XOSCPWR=0
FRQRANGE=0 <10
nsFRQRANGE=1, 2, or 3 <1
XOSCPWR=1 <1
Long term jitter
XOSCPWR=0
FRQRANGE=0 <6
nsFRQRANGE=1, 2, or 3 <0.5
XOSCPWR=1 <0.5
Frequency error
XOSCPWR=0
FRQRANGE=0 <0.1
%
FRQRANGE=1 <0.05
FRQRANGE=2 or 3 <0.005
XOSCPWR=1 <0.005
Duty cycle
XOSCPWR=0
FRQRANGE=0 40
%
FRQRANGE=1 42
FRQRANGE=2 or 3 45
XOSCPWR=1 48
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Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
RQ
Negative
impedance (1)
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF 2.4k
Ω
1MHz crystal, CL=20pF 8.7k
2MHz crystal, CL=20pF 2.1k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
2MHz crystal 4.2k
8MHz crystal 250
9MHz crystal 195
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
8MHz crystal 360
9MHz crystal 285
12MHz crystal 155
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
9MHz crystal 365
12MHz crystal 200
16MHz crystal 105
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
9MHz crystal 435
12MHz crystal 235
16MHz crystal 125
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
9MHz crystal 495
12MHz crystal 270
16MHz crystal 145
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal 305
16MHz crystal 160
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal 380
16MHz crystal 205
ESR SF = Safety factor min(RQ)/SF kΩ
CXTAL1
Parasitic
capacitance XTAL1
pin
5.2 pF
CXTAL2
Parasitic
capacitance XTAL2
pin
6.8 pF
CLOAD
Parasitic
capacitance load 2.95 pF
Symbol Parameter Condition Min. Typ. Max. Units
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36.3.14.8 External 32.768kHz crystal oscillator and TOSC characteristics
Table 36-94. External 32.768kHz crystal oscillator and TOSC characteristics.
Note: 1. See Figure 36-4 for definition.
Figure 36-18. TOSC input capacitance.
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when
oscillating without external capacitors.
Symbol Parameter Condition Min. Typ. Max. Units
ESR/R1 Recommended crystal equivalent
series resistance (ESR)
Crystal load capacitance 6.5pF 60
kΩ
Crystal load capacitance 9.0pF 35
CTOSC1 Parasitic capacitance TOSC1 pin 4.2 pF
CTOSC2 Parasitic capacitance TOSC2 pin 4.3 pF
Recommended safety factor capacitance load matched to
crystal specification 3
C
L1
C
L2
2CS
O
T
1
CS
O
TDevice internal
External
32.768kHz crystal
135
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36.3.15 SPI Characteristics
Figure 36-19. SPI timing requirements in master mode.
Figure 36-20. SPI timing requirements in slave mode.
MSB LSB
BSLBSM
t
MOS
t
MIS
t
MIH
t
SCKW
t
SCK
t
MOH
t
MOH
t
SCKF
t
SCKR
t
SCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB LSB
BSLBSM
t
SIS
t
SIH
t
SSCKW
t
SSCKW
t
SSCK
t
SSH
t
SOSSH
t
SCKR
t
SCKF
t
SOS
t
SSS
t
SOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
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Table 36-95. SPI timing characteristics and requirements.
Symbol Parameter Condition Min. Typ. Max. Units
tSCK SCK Period Master (See Table 21-4 in
XMEGA AU Manual)
ns
tSCKW SCK high/low width Master 0.5*SCK
tSCKR SCK Rise time Master 2.7
tSCKF SCK Fall time Master 2.7
tMIS MISO setup to SCK Master 10
tMIH MISO hold after SCK Master 10
tMOS MOSI setup SCK Master 0.5*SCK
tMOH MOSI hold after SCK Master 1
tSSCK Slave SCK Period Slave 4*t ClkPER
tSSCKW SCK high/low width Slave 2*t ClkPER
tSSCKR SCK Rise time Slave 1600
tSSCKF SCK Fall time Slave 1600
tSIS MOSI setup to SCK Slave 3
tSIH MOSI hold after SCK Slave t ClkPER
tSSS SS setup to SCK Slave 21
tSSH SS hold after SCK Slave 20
tSOS MISO setup SCK Slave 8
tSOH MISO hold after SCK Slave 13
tSOSS MISO setup after SS low Slave 11
tSOSH MISO hold after SS high Slave 8
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36.3.16 Two-Wire Interface Characteristics
Table 36-32 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR
XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols
refer to Figure 36-7.
Figure 36-21. Two-wire interface bus timing.
Table 36-96. Two-wire interface characteristics.
tHD;STA
tof
SDA
SCL
tLOW
tHIGH
tSU;STA
tBUF
tr
tHD;DAT tSU;DAT tSU;STO
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input High Voltage 0.7*VCC VCC+0.5 V
VIL Input Low Voltage -0.5 0.3*VCC V
Vhys Hysteresis of Schmitt Trigger Inputs 0.05*VCC (1) V
VOL Output Low Voltage 3mA, sink current 00.4 V
trRise Time for both SDA and SCL 20+0.1Cb (1)(2) 300 ns
tof Output Fall Time from VIHmin to VILmax 10pF < Cb < 400pF (2) 20+0.1Cb (1)(2) 250 ns
tSP Spikes Suppressed by Input Filter 050 ns
IIInput Current for each I/O Pin 0.1VCC < VI < 0.9VCC -10 10 µA
CICapacitance for each I/O Pin 10 pF
fSCL SCL Clock Frequency fPER (3)>max(10fSCL, 250kHz) 0400 kHz
RPValue of Pull-up resistor
fSCL ≤ 100kHz
Ω
fSCL > 100kHz
tHD;STA Hold Time (repeated) START condition
fSCL ≤ 100kHz 4.0
µs
fSCL > 100kHz 0.6
tLOW Low Period of SCL Clock
fSCL ≤ 100kHz 4.7
µs
fSCL > 100kHz 1.3
tHIGH High Period of SCL Clock
fSCL ≤ 100kHz 4.0
µs
fSCL > 100kHz 0.6
VCC 0.4V–
3mA
----------------------------
100ns
Cb
---------------
300ns
Cb
---------------
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Notes: 1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
tSU;STA
Set-up time for a repeated START
condition
fSCL ≤ 100kHz 4.7
µs
fSCL > 100kHz 0.6
tHD;DAT Data hold time
fSCL ≤ 100kHz 03.45
µs
fSCL > 100kHz 00.9
tSU;DAT Data setup time
fSCL ≤ 100kHz 250
ns
fSCL > 100kHz 100
tSU;STO Setup time for STOP condition
fSCL ≤ 100kHz 4.0
µs
fSCL > 100kHz 0.6
tBUF
Bus free time between a STOP and
START condition
fSCL ≤ 100kHz 4.7
µs
fSCL > 100kHz 1.3
Symbol Parameter Condition Min. Typ. Max. Units
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36.4 ATxmega256A3U
36.4.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 36-1 under may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or other conditions beyond those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 36-97. Absolute maximum ratings.
36.4.2 General Operating Ratings
The device must operate within the ratings listed in Table 36-2 in order for all other electrical characteristics and
typical characteristics of the device to be valid.
Table 36-98. General operating conditions.
Table 36-99. Operating voltage and frequency.
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power Supply Voltage -0.3 4 V
IVCC Current into a VCC pin 200 mA
IGND Current out of a Gnd pin 200 mA
VPIN
Pin voltage with respect to
Gnd and VCC
-0.5 VCC+0.5 V
IPIN I/O pin sink/source current -25 25 mA
TAStorage temperature -65 150 °C
TjJunction temperature 150 °C
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power Supply Voltage 1.60 3.6 V
AVCC Analog Supply Voltage 1.60 3.6 V
TATemperature range
85 °C -40 85
°C
105 °C -40 105
TjJunction temperature
85°C -40 105
°C
105°C -40 125
Symbol Parameter Condition Min. Typ. Max. Units
ClkCPU CPU clock frequency
VCC = 1.6V 012
MHz
VCC = 1.8V 012
VCC = 2.7V 032
VCC = 3.6V 032
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36.4.3 Current consumption
Table 36-100. Current consumption for active mode and sleep modes.
Notes: 1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Active Power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 60
µA
VCC = 3.0V 140
1MHz, Ext. Clk
VCC = 1.8V 280
VCC = 3.0V 600
2MHz, Ext. Clk
VCC = 1.8V 510 500
VCC = 3.0V
1.1 1.5
mA
32MHz, Ext. Clk 10.6 15
Idle Power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 4.3
µA
VCC = 3.0V 4.8
1MHz, Ext. Clk
VCC = 1.8V 78
VCC = 3.0V 150
2MHz, Ext. Clk
VCC = 1.8V 150 350
VCC = 3.0V
290 600
32MHz, Ext. Clk 4.7 7.0 mA
Power-down power
consumption
T = 25°C
VCC = 3.0V
0.1 1.0
µA
T = 85°C 1.8 5.0
T = 105°C 6.5 17
WDT and Sampled BOD enabled,
T = 25°C
VCC = 3.0V
1.3 3.0
WDT and Sampled BOD enabled,
T = 85°C 3.1 7.0
WDT and Sampled BOD enabled,
T = 105°C 7.3 20
Power-save power
consumption (2)
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
VCC = 1.8V 1.2
µA
VCC = 3.0V 1.3
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
VCC = 1.8V 0.6 2
VCC = 3.0V 0.7 2
RTC from low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V 0.8 3
VCC = 3.0V 1.0 3
Reset power consumption Current through RESET pin
substracted VCC = 3.0V 250 µA
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Table 36-101. Current consumption for modules and peripherals.
Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at
VCC = 3.0V, ClkSYS = 1MHz external clock without prescaling, T = 25°C unless other conditions are givenAll parameters
measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock without
prescaling, T = 25°C unless other conditions are given.
Symbol Parameter Condition(1) Min. Typ. Max. Units
ICC
ULP oscillator 1.0 µA
32.768kHz int. oscillator 27 µA
2MHz int. oscillator
85
µA
DFLL enabled with 32.768kHz int. osc. as reference 115
32MHz int. oscillator
270
µA
DFLL enabled with 32.768kHz int. osc. as reference 460
PLL 20x multiplication factor,
32MHz int. osc. DIV4 as reference 220 µA
Watchdog Timer 1µA
BOD
Continuous mode 138
µA
Sampled mode, includes ULP oscillator 1.2
Internal 1.0V reference 100 µA
Temperature sensor 95 µA
ADC 250ksps
VREF = Ext ref
3.0
mA
CURRLIMIT = LOW 2.6
CURRLIMIT = MEDIUM 2.1
CURRLIMIT = HIGH 1.6
DAC
250ksps
VREF = Ext ref
No load
Normal mode 1.9
mA
Low Power mode 1.1
AC
High Speed Mode 330
µA
Low Power Mode 130
DMA 615KBps between I/O registers and SRAM 115 µA
Timer/Counter 16 µA
USART Rx and Tx enabled, 9600 BAUD 2.5 µA
Flash memory and EEPROM programming 4mA
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36.4.4 Wake-up time from sleep modes
Table 36-102. Device wake-up time from sleep modes with various system clock sources.
Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-2. All peripherals and modules
start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 36-23. Wake-up time definition.
Symbol Parameter Condition Min. Typ. (1) Max. Units
twakeup
Wake-up time from Idle,
Standby, and Extended Standby
mode
External 2MHz clock 2
µs
32.768kHz internal oscillator 120
2MHz internal oscillator 2
32MHz internal oscillator 0.2
Wake-up time from Power-save
and Power-down mode
External 2MHz clock 4.5
µs
32.768kHz internal oscillator 320
2MHz internal oscillator 9
32MHz internal oscillator 5
Wakeup request
Clock output
Wakeup time
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36.4.5 I/O Pin Characteristics
The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and
output voltage limits reflect or exceed this specification.
Table 36-103. I/O pin characteristics.
Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
Symbol Parameter Condition Min. Typ. Max. Units
IOH (1)/
IOL (2) I/O pin source/sink current -20 20 mA
VIH High Level Input Voltage
VCC = 2.7 - 3.6V 2 VCC+0.3
VVCC = 2.0 - 2.7V 0.7*VCC VCC+0.3
VCC = 1.6 - 2.0V 0.8*VCC VCC+0.3
VIL Low Level Input Voltage
VCC = 2.7- 3.6V -0.3 0.8
VVCC = 2.0 - 2.7V -0.3 0.3*VCC
VCC = 1.6 - 2.0V -0.3 0.2*VCC
VOH High Level Output Voltage
VCC = 3.0 - 3.6V IOH = -2mA 2.4 0.94*VCC
V
VCC = 2.3 - 2.7V
IOH = -1mA 2.0 0.96*VCC
IOH = -2mA 1.7 0.92*VCC
VCC = 3.3V IOH = -8mA 2.6 2.9
VCC = 3.0V IOH = -6mA 2.1 2.6
VCC = 1.8V IOH = -2mA 1.4 1.6
VOL Low Level Output Voltage
VCC = 3.0 - 3.6V IOL = 2mA 0.05*VCC 0.4
V
VCC = 2.3 - 2.7V
IOL = 1mA 0.03*VCC 0.4
IOL = 2mA 0.06*VCC 0.7
VCC = 3.3V IOL = 15mA 0.4 0.76
VCC = 3.0V IOL = 10mA 0.3 0.64
VCC = 1.8V IOL = 5mA 0.3 0.46
IIN Input Leakage Current T = 25°C <0.001 0.1 µA
RPPull/Buss keeper Resistor 27 kΩ
trRise time No load
4
ns
slew rate limitation 7
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36.4.6 ADC characteristics
Table 36-104. Power supply, reference and input range.
Table 36-105. Clock and timing.
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC- 0.3 VCC+ 0.3 V
VREF Reference voltage 1AVCC- 0.6 V
Rin Input resistance Switched 4.0 kΩ
Csample Input capacitance Switched 4.4 pF
RAREF Reference input resistance (leakage only) >10 MΩ
CAREF Reference input capacitance Static load 7pF
VIN Input range -0.1 AVCC+0.1 V
Conversion range Differential mode, Vinp - Vinn -VREF VREF V
VIN Conversion range Single ended unsigned mode, Vinp -ΔV VREF-ΔV V
∆VFixed offset voltage 190 LSB
Symbol Parameter Condition Min. Typ. Max. Units
ClkADC ADC Clock frequency
Maximum is 1/4 of Peripheral clock
frequency 100 2000
kHz
Measuring internal signals 100 125
fADC Sample rate
Current limitation (CURRLIMIT) off 100 2000
ksps
CURRLIMIT = LOW 100 1500
CURRLIMIT = MEDIUM 100 1000
CURRLIMIT = HIGH 100 500
Sampling Time 1/2 ClkADC cycle 0.25 5µs
Conversion time (latency) (RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12 5 8 ClkADC
cycles
Start-up time ADC clock cycles 12 24 ClkADC
cycles
ADC settling time
After changing reference or input mode 7 7 ClkADC
cycles
After ADC flush 1 1
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Table 36-106. Accuracy characteristics.
Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 36-107. Gain stage characteristics.
Symbol Parameter Condition (2) Min. Typ. Max. Units
RES Resolution Programmable to 8 or 12 bit 812 12 Bits
INL (1) Integral non-linearity
500ksps
VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2
lsb
All VREF ±1.5 ±3
2000ksps
VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2
All VREF ±1.5 ±3
DNL (1) Differential non-linearity guaranteed monotonic <±0.8 <±1 lsb
Offset Error
-1 mV
Temperature drift <0.01 mV/K
Operating voltage drift <0.6 mV/V
Gain Error
Differential
mode
External reference -1
mV
AVCC/1.6 10
AVCC/2.0 8
Bandgap ±5
Temperature drift <0.02 mV/K
Operating voltage drift <0.5 mV/V
Noise Differential mode, shorted input
2msps, VCC = 3.6V, ClkPER = 16MHz 0.4 mV
rms
Symbol Parameter Condition Min. Typ. Max. Units
Rin Input resistance Switched in normal mode 4.0 kΩ
Csample Input capacitance Switched in normal mode 4.4 pF
Signal range Gain stage output 0 VCC- 0.6 V
Propagation delay ADC conversion rate 1ClkADC
cycles
Sample rate Same as ADC 100 1000 kHz
INL (1) Integral Non-Linearity 500ksps All gain
settings ±1.5 ±4 lsb
Gain Error
1x gain, normal mode -0.8
%8x gain, normal mode -2.5
64x gain, normal mode -3.5
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Note: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
36.4.7 DAC Characteristics
Table 36-108. Power supply, reference and output range.
Table 36-109. Clock and timing.
Offset Error,
input referred
1x gain, normal mode -2
mV8x gain, normal mode -5
64x gain, normal mode -4
Noise
1x gain, normal mode
VCC = 3.6V
Ext. VREF
0.5
mV
rms
8x gain, normal mode 1.5
64x gain, normal mode 11
Symbol Parameter Condition Min. Typ. Max. Units
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC- 0.3 VCC+ 0.3
AVREF External reference voltage 1.0 VCC- 0.6 V
Rchannel DC output impedance 50 Ω
Linear output voltage range 0.15 AVCC-0.15 V
RAREF Reference input resistance >10 MΩ
CAREF Reference input capacitance Static load 7pF
Minimum Resistance load 1 kΩ
Maximum capacitance load
100 pF
1000Ω serial resistance 1nF
Output sink/source
Operating within accuracy specification AVCC/1000
mA
Safe operation 10
Symbol Parameter Condition Min. Typ. Max. Units
fDAC Conversion rate Cload=100pF,
maximum step size
Normal mode 01000
ksps
Low power mode 0500
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Table 36-110. Accuracy characteristics.
Note: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.
36.4.8 Analog Comparator Characteristics
Table 36-111. Analog Comparator characteristics.
Symbol Parameter Condition Min. Typ. Max. Units
RES Input Resolution 12 Bits
INL (1) Integral non-linearity
VREF= Ext 1.0V
VCC = 1.6V ±2.0 ±3
lsb
VCC = 3.6V ±1.5 ±2.5
VREF=AVCC
VCC = 1.6V ±2.0 ±4
VCC = 3.6V ±1.5 ±4
VREF=INT1V
VCC = 1.6V ±5.0
VCC = 3.6V ±5.0
DNL (1) Differential non-linearity
VREF=Ext 1.0V
VCC = 1.6V ±1.5 3
lsb
VCC = 3.6V ±0.6 1.5
VREF=AVCC
VCC = 1.6V ±1.0 3.5
VCC = 3.6V ±0.6 1.5
VREF=INT1V
VCC = 1.6V ±4.5
VCC = 3.6V ±4.5
Gain error After calibration <4 lsb
Gain calibration step size 4lsb
Gain calibration drift VREF= Ext 1.0V <0.2 mV/K
Offset error After calibration <1 lsb
Offset calibration step size 1
Symbol Parameter Condition Min. Typ. Max. Units
Voff Input Offset Voltage <±10 mV
Ilk Input Leakage Current <1 nA
Input voltage range -0.1 AVCC V
AC startup time 100 µs
Vhys1 Hysteresis, None 0mV
Vhys2 Hysteresis, Small
mode = High Speed (HS) 13
mV
mode = Low Power (LP) 30
Vhys3 Hysteresis, Large
mode = HS 30
mV
mode = LP 60
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36.4.9 Bandgap and Internal 1.0V Reference Characteristics
Table 36-112. Bandgap and Internal 1.0V reference characteristics.
36.4.10 Brownout Detection Characteristics
Table 36-113. Brownout detection characteristics.
tdelay Propagation delay
VCC = 3.0V, T= 85°C mode = HS 30 90
ns
mode = HS 30
VCC = 3.0V, T= 85°C mode = LP 130 500
mode = LP 130
64-Level Voltage Scaler Integral non-linearity (INL) 0.3 0.5 lsb
Symbol Parameter Condition Min. Typ. Max. Units
Symbol Parameter Condition Min. Typ. Max. Units
Startup time
As reference for ADC or DAC 1 ClkPER + 2.5µs
µs
As input voltage to ADC and AC 1.5
Bandgap voltage 1.1 V
INT1V Internal 1.00V reference T= 85°C, after calibration 0.99 11.01 V
Variation over voltage and temperature Relative to T= 85°C, VCC = 3.0V ±1.0 %
Symbol Parameter Condition Min. Typ. Max. Units
VBOT
BOD level 0 falling VCC 1.60 1.62 1.72
V
BOD level 1 falling VCC 1.8
BOD level 2 falling VCC 2.0
BOD level 3 falling VCC 2.2
BOD level 4 falling VCC 2.4
BOD level 5 falling VCC 2.6
BOD level 6 falling VCC 2.8
BOD level 7 falling VCC 3.0
tBOD Detection time
Continuous mode 0.4
µs
Sampled mode 1000
VHYST Hysteresis 1.6 %
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36.4.11 External Reset Characteristics
Table 36-114. External reset characteristics.
36.4.12 Power-on Reset Characteristics
Table 36-115. Power-on reset characteristics.
Note: 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
36.4.13 Flash and EEPROM Memory Characteristics
Table 36-116. Endurance and data retention.
Symbol Parameter Condition Min. Typ. Max. Units
tEXT Minimum reset pulse width 95 1000 ns
VRST
Reset threshold voltage (VIH)
VCC = 2.7 - 3.6V 0.60*VCC
V
VCC = 1.6 - 2.7V 0.70*VCC
Reset threshold voltage (VIL)
VCC = 2.7 - 3.6V 0.40*VCC
VCC = 1.6 - 2.7V 0.30*VCC
RRST Reset pin Pull-up Resistor 25 kΩ
Symbol Parameter Condition Min. Typ. Max. Units
VPOT- (1) POR threshold voltage falling VCC
VCC falls faster than 1V/ms 0.4 1.0
V
VCC falls at 1V/ms or slower 0.8 1.0
VPOT+ POR threshold voltage rising VCC 1.3 1.59 V
Symbol Parameter Condition Min. Typ. Max. Units
Flash
Write/Erase cycles
25°C 10K
Cycle85°C 10K
105°C 2K
Data retention
25°C 100
Year85°C 25
105°C 10
EEPROM
Write/Erase cycles
25°C 100K
Cycle85°C 100K
105°C 30K
Data retention
25°C 100
Year85°C 25
105°C 10
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Table 36-117. Programming time.
Notes: 1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
36.4.14 Clock and Oscillator Characteristics
36.4.14.1 Calibrated 32.768kHz Internal Oscillator characteristics
Table 36-118. 32.768kHz internal oscillator characteristics.
36.4.14.2 Calibrated 2MHz RC Internal Oscillator characteristics
Table 36-119. 2MHz internal oscillator characteristics.
Symbol Parameter Condition Min. Typ. (1) Max. Units
Chip Erase 256KB Flash, EEPROM (2) and SRAM Erase 105 ms
Application Erase Section erase 6ms
Flash
Page Erase 4
msPage Write 4
Atomic Page Erase and Write 8
EEPROM
Page Erase 4
msPage Write 4
Atomic Page Erase and Write 8
Symbol Parameter Condition Min. Typ. Max. Units
Frequency 32.768 kHz
Factory calibration accuracy T = 85°C, VCC = 3.0V -0.5 0.5 %
User calibration accuracy -0.5 0.5 ms
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 1.8 2.2 MHz
Factory calibrated frequency 2.0 MHz
Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5 %
User calibration accuracy -0.2 0.2 %
DFLL calibration stepsize 0.22 %
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36.4.14.3 Calibrated and tunable 32MHz internal oscillator characteristics
Table 36-120. 32MHz internal oscillator characteristics.
36.4.14.4 32kHz Internal ULP Oscillator characteristics
Table 36-121. 32kHz internal ULP oscillator characteristics.
36.4.14.5 Internal Phase Locked Loop (PLL) characteristics
Table 36-122. Internal PLL characteristics.
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 30 55 MHz
Factory calibrated frequency 32 MHz
Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5 %
User calibration accuracy -0.2 0.2 %
DFLL calibration step size 0.23 %
Symbol Parameter Condition Min. Typ. Max. Units
Output frequency 32 kHz
Accuracy -30 30 %
Symbo
lParameter Condition Min. Typ. Max. Units
fIN Input Frequency Output frequency must be within fOUT 0.4 64 MHz
fOUT Output frequency (1) VCC= 1.6 - 1.8V 20 48
MHz
VCC= 2.7 - 3.6V 20 128
Start-up time 25 µs
Re-lock time 25 µs
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36.4.14.6 External clock characteristics
Figure 36-24. External clock drive waveform
Table 36-123. External clock used as system clock without prescaling.
Note: 1. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
tCH
tCL
tCK
tCH
VIL1
VIH1
tCR tCF
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (1) VCC = 1.6 - 1.8V 012
MHz
VCC = 2.7 - 3.6V 032
tCK Clock Period
VCC = 1.6 - 1.8V 83.3
ns
VCC = 2.7 - 3.6V 31.5
tCH Clock High Time
VCC = 1.6 - 1.8V 30.0
ns
VCC = 2.7 - 3.6V 12.5
tCL Clock Low Time
VCC = 1.6 - 1.8V 30.0
ns
VCC = 2.7 - 3.6V 12.5
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
ns
VCC = 2.7 - 3.6V 3
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
ns
VCC = 2.7 - 3.6V 3
ΔtCK Change in period from one clock cycle to the next 10 %
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Table 36-124. External clock with prescaler (1)for system clock.
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
36.4.14.7 External 16MHz crystal oscillator and XOSC characteristics
Table 36-125. External 16MHz crystal oscillator and XOSC characteristics..
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (2) VCC = 1.6 - 1.8V 090
MHz
VCC = 2.7 - 3.6V 0142
tCK Clock Period
VCC = 1.6 - 1.8V 11
ns
VCC = 2.7 - 3.6V 7
tCH Clock High Time
VCC = 1.6 - 1.8V 4.5
ns
VCC = 2.7 - 3.6V 2.4
tCL Clock Low Time
VCC = 1.6 - 1.8V 4.5
ns
VCC = 2.7 - 3.6V 2.4
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
ns
VCC = 2.7 - 3.6V 1.0
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
ns
VCC = 2.7 - 3.6V 1.0
ΔtCK Change in period from one clock cycle to the next 10 %
Symbol Parameter Condition Min. Typ. Max. Units
Cycle to cycle jitter
XOSCPWR=0
FRQRANGE=0 <10
nsFRQRANGE=1, 2, or 3 <1
XOSCPWR=1 <1
Long term jitter
XOSCPWR=0
FRQRANGE=0 <6
nsFRQRANGE=1, 2, or 3 <0.5
XOSCPWR=1 <0.5
Frequency error
XOSCPWR=0
FRQRANGE=0 <0.1
%
FRQRANGE=1 <0.05
FRQRANGE=2 or 3 <0.005
XOSCPWR=1 <0.005
Duty cycle
XOSCPWR=0
FRQRANGE=0 40
%
FRQRANGE=1 42
FRQRANGE=2 or 3 45
XOSCPWR=1 48
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Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
RQ
Negative impedance
(1)
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF 2.4k
Ω
1MHz crystal, CL=20pF 8.7k
2MHz crystal, CL=20pF 2.1k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
2MHz crystal 4.2k
8MHz crystal 250
9MHz crystal 195
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
8MHz crystal 360
9MHz crystal 285
12MHz crystal 155
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
9MHz crystal 365
12MHz crystal 200
16MHz crystal 105
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
9MHz crystal 435
12MHz crystal 235
16MHz crystal 125
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
9MHz crystal 495
12MHz crystal 270
16MHz crystal 145
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal 305
16MHz crystal 160
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal 380
16MHz crystal 205
ESR SF = Safety factor min(RQ)/SF kΩ
CXTAL1
Parasitic
capacitance XTAL1
pin
5.2 pF
CXTAL2
Parasitic
capacitance XTAL2
pin
6.8 pF
CLOAD
Parasitic
capacitance load 2.95 pF
Symbol Parameter Condition Min. Typ. Max. Units
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36.4.14.8 External 32.768kHz crystal oscillator and TOSC characteristics
Table 36-126. External 32.768kHz crystal oscillator and TOSC characteristics.
Note: 1. See Figure 36-4 for definition.
Figure 36-25. TOSC input capacitance.
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when
oscillating without external capacitors.
Symbol Parameter Condition Min. Typ. Max. Units
ESR/R1 Recommended crystal equivalent
series resistance (ESR)
Crystal load capacitance 6.5pF 60
kΩ
Crystal load capacitance 9.0pF 35
CTOSC1 Parasitic capacitance TOSC1 pin 4.2 pF
CTOSC2 Parasitic capacitance TOSC2 pin 4.3 pF
Recommended safety factor capacitance load matched to
crystal specification 3
C
L1
C
L2
2CS
O
T
1
CS
O
TDevice internal
External
32.768kHz crystal
157
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36.4.15 SPI Characteristics
Figure 36-26. SPI timing requirements in master mode.
Figure 36-27. SPI timing requirements in slave mode.
MSB LSB
BSLBSM
t
MOS
t
MIS
t
MIH
t
SCKW
t
SCK
t
MOH
t
MOH
t
SCKF
t
SCKR
t
SCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB LSB
BSLBSM
t
SIS
t
SIH
t
SSCKW
t
SSCKW
t
SSCK
t
SSH
t
SOSSH
t
SCKR
t
SCKF
t
SOS
t
SSS
t
SOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
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Table 36-127. SPI timing characteristics and requirements.
Symbol Parameter Condition Min. Typ. Max. Units
tSCK SCK Period Master (See Table 21-4 in
XMEGA AU Manual)
ns
tSCKW SCK high/low width Master 0.5*SCK
tSCKR SCK Rise time Master 2.7
tSCKF SCK Fall time Master 2.7
tMIS MISO setup to SCK Master 10
tMIH MISO hold after SCK Master 10
tMOS MOSI setup SCK Master 0.5*SCK
tMOH MOSI hold after SCK Master 1
tSSCK Slave SCK Period Slave 4*t ClkPER
tSSCKW SCK high/low width Slave 2*t ClkPER
tSSCKR SCK Rise time Slave 1600
tSSCKF SCK Fall time Slave 1600
tSIS MOSI setup to SCK Slave 3
tSIH MOSI hold after SCK Slave t ClkPER
tSSS SS setup to SCK Slave 21
tSSH SS hold after SCK Slave 20
tSOS MISO setup SCK Slave 8
tSOH MISO hold after SCK Slave 13
tSOSS MISO setup after SS low Slave 11
tSOSH MISO hold after SS high Slave 8
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36.4.16 Two-Wire Interface Characteristics
Table 36-32 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR
XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols
refer to Figure 36-7.
Figure 36-28. Two-wire interface bus timing.
Table 36-128. Two-wire interface characteristics.
tHD;STA
tof
SDA
SCL
tLOW
tHIGH
tSU;STA
tBUF
tr
tHD;DAT tSU;DAT tSU;STO
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input High Voltage 0.7*VCC VCC+0.5 V
VIL Input Low Voltage -0.5 0.3*VCC V
Vhys Hysteresis of Schmitt Trigger Inputs 0.05*VCC (1) V
VOL Output Low Voltage 3mA, sink current 00.4 V
trRise Time for both SDA and SCL 20+0.1Cb (1)(2) 300 ns
tof Output Fall Time from VIHmin to VILmax 10pF < Cb < 400pF (2) 20+0.1Cb (1)(2) 250 ns
tSP Spikes Suppressed by Input Filter 050 ns
IIInput Current for each I/O Pin 0.1VCC < VI < 0.9VCC -10 10 µA
CICapacitance for each I/O Pin 10 pF
fSCL SCL Clock Frequency fPER (3)>max(10fSCL, 250kHz) 0400 kHz
RPValue of Pull-up resistor
fSCL ≤ 100kHz
Ω
fSCL > 100kHz
tHD;STA Hold Time (repeated) START condition
fSCL ≤ 100kHz 4.0
µs
fSCL > 100kHz 0.6
tLOW Low Period of SCL Clock
fSCL ≤ 100kHz 4.7
µs
fSCL > 100kHz 1.3
tHIGH High Period of SCL Clock
fSCL ≤ 100kHz 4.0
µs
fSCL > 100kHz 0.6
VCC 0.4V–
3mA
----------------------------
100ns
Cb
---------------
300ns
Cb
---------------
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Notes: 1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
tSU;STA
Set-up time for a repeated START
condition
fSCL ≤ 100kHz 4.7
µs
fSCL > 100kHz 0.6
tHD;DAT Data hold time
fSCL ≤ 100kHz 03.45
µs
fSCL > 100kHz 00.9
tSU;DAT Data setup time
fSCL ≤ 100kHz 250
ns
fSCL > 100kHz 100
tSU;STO Setup time for STOP condition
fSCL ≤ 100kHz 4.0
µs
fSCL > 100kHz 0.6
tBUF
Bus free time between a STOP and
START condition
fSCL ≤ 100kHz 4.7
µs
fSCL > 100kHz 1.3
Symbol Parameter Condition Min. Typ. Max. Units
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37. Typical Characteristics
37.1 ATxmega64A3U
37.1.1 Current consumption
37.1.1.1 Active mode supply current
Figure 37-1. Active supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
Figure 37-2. Active supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
0
100
200
300
400
500
600
700
0 0.2 0.4 0.6 0.8 1
I
CC
[µA]
Frequency [MHz]
3.6 V
3.0 V
2.7 V
1.8 V
1.6 V
0
2
4
6
8
10
12
14
0 4 8 121620242832
I
CC
[mA]
Frequency [MHz]
2.2 V
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Figure 37-3. Active mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
Figure 37-4. Active mode supply current vs. VCC.
fSYS = 1MHz external clock.
105
85
25
-40
50
70
90
110
130
150
170
190
210
230
250
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC
[µA]
VCC
[V]
Temp [°C]
200
270
340
410
480
550
620
690
760
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC
[µA]
VCC
[V]
40°C
25°C
85°C
105°C
-
163
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Figure 37-5. Active mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
Figure 37-6. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
400
525
650
775
900
1025
1150
1275
1400
1525
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC
[µA]
VCC
[V]
40°C
25°C
85°C
105°C
-
1400
1900
2400
2900
3400
3900
4400
4900
5400
5900
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC
[µA]
VCC
[V]
40°C
25°C
85°C
105°C
-
164
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Figure 37-7. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator.
37.1.1.2 Idle mode supply current
Figure 37-8. Idle mode supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
8000
8700
9400
10100
10800
11500
12200
12900
13600
14300
2.7 2.8 2.9 3 3,1 3.2 3.3 3.4 3.5 3.6
ICC
[A]
VCC
[V]
40°C
25°C
85°C
105°C
-
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
0
20
40
60
80
100
120
140
160
180
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
I
CC
[µA]
Frequency [MHz]
165
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-9. Idle mode supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
Figure 37-10. Idle mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
3.6 V
3.0 V
2.7 V
1.8 V
1.6 V
0 4 8 121620242832
ICC [mA]
Frequency [MHz]
2.2 V
6
5
4
3
2
1
0
25
°C
27
28
29
30
31
32
33
34
35
36
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC
[µA]
VCC[V ]
-40
°C
105
°C
85
°C
166
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-11. Idle mode supply current vs. VCC.
fSYS = 1MHz external clock.
Figure 37-12. Idle mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
60
75
90
105
120
135
150
165
180
195
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC[µA]
VCC
[V]
40°C
25°C
85°C
105°C
-
180
220
260
300
340
380
420
460
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC[µA]
VCC[V ]
40°C
25°C
85°C
105°C
-
167
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-13. Idle mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
Figure 37-14. Idle mode current vs. VCC.
fSYS = 32MHz internal oscillator.
700
900
1100
1300
1500
1700
1900
2100
2300
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
I
CC
[µA]
V
CC
[V]
40°C
25°C
85°C
105°C
-
3800
4050
4300
4550
4800
5050
5300
5550
5800
6050
6300
2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
ICC [µA]
VCC [V]
40°C
25°C
85°C
105°C
-
168
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.1.1.3 Power-down mode supply current
Figure 37-15. Power-down mode supply current vs. VCC.
All functions disabled.
Figure 37-16. Power-down mode supply current vs. VCC.
Watchdog and sampled BOD enabled.
105
85
25
- 40
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
I
CC
[µA]
VCC [V]
Temp [°C]
105
85
25
-40
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.6 1.8 2 2.2 2.4 2..6 2.8 3 3.2 3.4 3.6
ICC
[µA]
VCC[V ]
Temp [°C]
169
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.1.1.4 Power-save mode supply current
Figure 37-17. Power-save mode supply current vs. VCC.
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.
37.1.1.5 Standby mode supply current
Figure 37-18. Standby supply current vs. VCC.
Standby, fSYS =1MHz.
Normal Mode
Low-Power Mode
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
Icc [µA]
Vcc [V]
RTC from 1kHz output of 32.768kHz TOSC
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
I
CC
[uA]
V
CC
[V]
105°C
85°C
25°C
-40°C
170
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-19. Standby supply current vs. VCC.
25°C, running from different crystal oscillators.
37.1.2 I/O Pin Characteristics
37.1.2.1 Pull-up
Figure 37-20. I/O pin pull-up resistor current vs. input voltage.
VCC = 1.8V.
16MHz
12MHz
8MHz
2MHz
0.454MHz
160
200
240
280
320
360
400
440
480
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Icc [µA]
Vcc [V]
,y
105
85
25
-
40
0
8
16
24
32
40
48
56
64
72
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7
I[µA]
V
PIN
[V]
Temp [°C]
PIN
171
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-21. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.0V.
Figure 37-22. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.3V.
105
85
25
-
40
0
15
30
45
60
75
90
105
120
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
IPIN
[µA]
VPIN
[V]
Temp [°C]
105
85
25
-
40
0
15
30
45
60
75
90
105
120
135
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.4
IPIN [µA]
VPIN[V ]
Temp [°C]
172
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.1.2.2 Output Voltage vs. Sink/Source Current
Figure 37-23. I/O pin output voltage vs. source current.
VCC = 1.8V.
Figure 37-24. I/O pin output voltage vs. source current.
VCC = 3.0V.
105
85
25
-40
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
-10-9-8-7-6-5-4-3-2-1 0
VPIN
[V]
IPIN [mA]
Temp [°C]
105
85
25
-40
0.5
0.8
1.1
1.4
1.7
2.0
2.3
2.6
2.9
3.2
-30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0
VPIN
[V]
IPIN [mA]
Temp [°C]
173
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-25. I/O pin output voltage vs. source current.
VCC = 3.3V.
Figure 37-26. I/O pin output voltage vs. source current.
105
85
25
-40
0.5
0.8
1.1
1.4
1.7
2.0
2.3
2.6
2.9
3.2
3.5
-30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0
VPIN[V ]
IPIN [mA]
Temp [°C]
3.6 V
3.3 V
3.0 V
2.7 V
1.8 V
1.6 V
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
-24 -21 -18 -15 -12 -9 -6 -3 0
V
PIN
[V]
I
PIN
[mA]
174
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-27. I/O pin output voltage vs. sink current.
VCC = 1.8V.
Figure 37-28. I/O pin output voltage vs. sink current.
VCC = 3.0V.
-40
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 2 4 6 8 101214161820
VPIN
[V]
IPIN
[mA]
25
85
105
Temp [°C]
105
85
25
- 40
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 3 6 9 12 15 18 21 24 27 30
VPIN
[V]
IPIN [mA]
Temp [°C]
175
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-29. I/O pin output voltage vs. sink current.
VCC = 3.3V.
Figure 37-30. I/O pin output voltage vs. sink current.
105
85
25
-40
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 3 6 9 12 15 18 21 24 27 30
VPIN[V ]
IPIN
[mA]
Temp [°C]
3.6 V
3.3 V
3.0 V
2.7 V
0.0
0.2
0.3
0.5
0.6
0.8
0.9
1.1
1.2
1.4
1.5
0 3 6 9 12 15 18 21 24 27 30
V
PIN
[V]
I
PIN
[mA]
1.6 V 1.8 V
176
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.1.2.3 Thresholds and Hysteresis
Figure 37-31. I/O pin input threshold voltage vs. VCC.
T = 25°C.
Figure 37-32. I/O pin input threshold voltage vs. VCC.
VIH I/O pin read as “1”.
VIL
VIH
0.50
0.65
0.80
0.95
1.10
1.25
1.40
1.55
1.70
1.85
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
THR ESH OLD
[V]
VCC [V]
105
85
25
40
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VTHR E S HOLD [V]
VCC [V]
Temp [°C]
177
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-33. I/O pin input threshold voltage vs. VCC.
VIL I/O pin read as “0”.
Figure 37-34. I/O pin input hysteresis vs. VCC.
105
85
25
-40
0.50
0.65
0.80
0.95
1.10
1.25
1.40
1.55
1.70
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VTHR E S HOLD [V]
VCC [V]
Temp [°C]
105
85
25
-40
0.12
0.15
0.18
0.21
0.24
0.27
0.3
0.33
0.36
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
HYSTERESIS[V ]
VCC
[V]
Temp [°C]
178
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.1.3 ADC Characteristics
Figure 37-35. INL error vs. external VREF.
T = 25
°
C, VCC = 3.6V, external reference.
Figure 37-36. INL error vs. sample rate.
T = 25
°
C, VCC = 2.7V, VREF = 1.0V external.
Single-ended unsigned mode
Single-ended signed mode
Dif f erential mode
0.0
0.5
1.0
1.5
2.0
2.5
3.0
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
INL[LSB]
VREF [V]
Single-ended unsigned mode
Single-ended signed mode
Dif f erential mode
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
500 650 800 950 1100 1250 1400 1550 1700 1850 2000
INL[LSB]
ADC sample rate [ksps]
179
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-37. INL error vs. input code.
Figure 37-38. DNL error vs. external VREF.
T = 25
°
C, VCC = 3.6V, external reference.
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
INL [LSB]
2.0
1.5
1.0
0.5
0.0
-0.5
-0.1
-1.5
-2.0
Single_ended unsigned mode
Single-ended signed mode
Dif f erential mode
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.01.21.41.61.82.02.22.42.62.83.0
DNL [LSB]
VREF [V]
180
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-39. DNL error vs. sample rate.
T = 25
°
C, VCC = 2.7V, VREF = 1.0V external.
Figure 37-40. DNL error vs. input code.
Single-ended unsigned mode
Single-ended signed mode
Dif f erential mode
0.2
0.3
0.3
0.4
0.4
0.5
0.5
500 650 800 950 1100 1250 1400 1550 1700 1850 2000
DNL [LSB]
ADC sample rate [ksps]
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
DNL [LSB]
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
181
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-41. Gain error vs. VREF.
T = 25
°
C, VCC = 3.6V, ADC sampling speed = 500ksps.
Figure 37-42. Gain error vs. VCC.
T = 25
°
C, VREF = external 1.0V, ADC sampling speed = 500ksps.
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0
1
2
3
4
5
6
7
8
9
10
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 30
Gain Error [mV]
VREF [V]
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Noise [mV RMS]
Vcc [V]
182
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-43. Offset error vs. VREF.
T = 25
°
C, VCC = 3.6V, ADC sampling speed = 500ksps.
Figure 37-44. Gain error vs. temperature.
VCC = 2.7V, VREF = external 1.0V.
Dif f erential mode
-1.20
-1.15
-1.10
-1.05
-1.00
-0.95
-0.90
-0.85
-0.80
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Offset Error [mV]
VREF [V]
S ingle E nded
Unsigned
Single Ended Signed
Differential Signed
0
1
2
3
4
5
6
7
8
-60 -40 -20 0 20 40 60 80 100 120
Gain Error [mV]
Temperature [°C ]
183
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-45. Offset error vs. VCC.
T = 25
°
C, VREF = external 1.0V, ADC sampling speed = 500ksps.
Figure 37-46. Noise vs. VREF.
T = 25
°
C, VCC = 3.6V, ADC sampling speed = 500ksps.
Dif f erential mode
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Offset Error [mV]
Vcc [V]
Single-ended unsigned mode
Single-ended signed mode
Dif f erential mode
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.01.21.41.61.82.02.22.42.62.83.0
Noise [mV RMS]
VREF [V]
184
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-47. Noise vs. VCC.
T = 25
°
C, VREF = external 1.0V, ADC sampling speed = 500ksps.
37.1.4 DAC Characteristics
Figure 37-48. DAC INL error vs. VREF.
VCC = 3.6V.
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Noise [mV RMS]
Vcc [V]
105
85
25
-40
0
0.5
1
1.5
2
2.5
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
DAC INL [LSB]
[V]
Temp [°C]
REF
V
185
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-49. DNL error vs. VREF.
T = 25
°
C, VCC = 3.6V.
Figure 37-50. DAC noise vs. temperature.
VCC = 3.3V, VREF = 2.0V.
105
85
25
-40
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
DAC DNL [LSB]
VREF [V]
Temp [°C]
0.165
0.170
0.175
0.180
0.185
0.190
0.195
0.200
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Noise[mV R MS]
Temperature [°C]
186
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.1.5 Analog Comparator Characteristics
Figure 37-51. Analog comparator hysteresis vs. VCC
High-speed, small hysteresis.
Figure 37-52. Analog comparator hysteresis vs. VCC.
Low power, small hysteresis.
105
85
25
-40
15
16
17
18
19
20
21
22
23
24
25
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VHYST
[mV]
VCC
[V]
Temp [°C]
105
85
25
-40
20
22
24
26
28
30
32
34
36
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST [mV ]
VCC
[V]
Temp [°C]
187
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-53. Analog comparator hysteresis vs. VCC.
High-speed mode, large hysteresis.
Figure 37-54. Analog comparator hysteresis vs. VCC.
Low power, large hysteresis.
105
85
25
-
40
27
29
31
33
35
37
39
41
43
45
47
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
HYST [mV ]
VCC
[V]
Temp [°C]
105
85
25
-40
46
49
52
55
58
61
64
67
70
73
76
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST[mV]
V
CC [V]
Temp [°C]
188
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-55. Analog comparator current source vs. calibration value.
Temperature = 25°C.
Figure 37-56. Analog comparator current source vs. calibration value.
VCC = 3.0V.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
1
2
3
4
5
6
7
8
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I
CURRENTSOURCE
[µA]
CURRCALIBA[3..0]
105
85
25
-
40
3.5
3.9
4.3
4.7
5.1
5.5
5.9
6.3
6.7
0246810121416
ICURRENTSOURCE[µA]
CURRCALIBA[3...0]
Temp [°C]
189
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-57. Voltage scaler INL vs. SCALEFAC.
T = 25
°
C, VCC = 3.0V.
37.1.6 Internal 1.0V reference Characteristics
Figure 37-58. ADC/DAC Internal 1.0V reference vs. temperature.
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0 8 16 24 32 40 48 56 64
INL [LSB]
SCALEFAC
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
0.999
1.001
1.002
1.004
1.005
1.007
1.008
1.010
1.011
-45 -30 -15 0 15 30 45 60 75 90 105
Bandgap Voltage [V]
Temperature [°
C]
190
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.1.7 BOD Characteristics
Figure 37-59. BOD thresholds vs. temperature.
BOD level = 1.6V.
Figure 37-60. BOD thresholds vs. temperature.
BOD level = 3.0V.
Rising Vcc
Falling Vcc
1.626
1.629
1.632
1.635
1.638
1.641
1.644
1.647
1.650
1.653
-45 -30 -15 0 15 30 45 60 75 90 105
V
BOT[V ]
Temperature [
°C ]
p
BOD Level = 1.6V
Rising Vcc
Falling Vcc
3.01
3.02
3.03
3.04
3.05
3.06
3.07
3.08
-45 -30 -15 0 15 30 45 60 75 90 105
V
BOT[V]
Temperature [
°C ]
191
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.1.8 External Reset Characteristics
Figure 37-61. Minimum Reset pin pulse width vs. VCC.
Figure 37-62. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 1.8V.
105
85
25
-40
85
90
95
100
105
110
115
120
125
130
135
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
tRST[ns ]
VCC[V]
Temp [°C]
105
85
25
-
40
0
8
16
24
32
40
48
56
64
72
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
IRESET
[µA]
VRESET[V ]
Temp [°C]
192
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-63. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.0V.
Figure 37-64. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.3V.
105
85
25
-
40
0
15
30
45
60
75
90
105
120
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
IRESET [µA]
VRESET
[V]
Temp [°C]
105
85
25
-
40
0
15
30
45
60
75
90
105
120
135
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3
IRESET
[µA]
VRESET[V]
Temp [°C
193
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-65. Reset pin input threshold voltage vs. VCC.
VIH - Reset pin read as “1”.
Figure 37-66. Reset pin input threshold voltage vs. VCC.
VIL - Reset pin read as “0”.
105
85
25
-40
1.00
1.15
1.30
1.45
1.60
1.75
1.90
2.05
2.20
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VTHR E S HOLD [V ]
VCC[V ]
Temp [°C]
105
85
25
-40
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
THR E S HOLD [V ]
VCC[V ]
Temp [°C]
194
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.1.9 Power-on Reset Characteristics
Figure 37-67. Power-on reset current consumption vs. VCC.
BOD level = 3.0V, enabled in continuous mode.
105
85
25
-
40
0
75
150
225
300
375
450
525
600
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
ICC[uA]
VCC
[V]
Temp [°C]
195
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.1.10 Oscillator Characteristics
37.1.10.1 Ultra Low-Power internal oscillator
Figure 37-68. Ultra Low-Power internal oscillator frequency vs. temperature.
37.1.10.2 32.768kHz Internal Oscillator
Figure 37-69. 32.768kHz internal oscillator frequency vs. temperature.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [kHz]
Temperature [ °C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.0
32.1
32.2
32.3
32.4
32.5
32.6
32,7
32.8
32.9
33.0
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [kHz]
Temperature [°C]
196
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-70. 32.768kHz internal oscillator frequency vs. calibration value.
VCC = 3.0V, T = 25°C.
37.1.10.3 2MHz Internal Oscillator
Figure 37-71. 2MHz internal oscillator frequency vs. temperature.
DFLL disabled.
22
25
28
31
34
37
40
43
46
49
0 26 52 78 104 130 156 182 208 234 260
Frequency [kHz]
RC32KCAL[7..0]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
1.96
1.98
2.00
2.02
2.04
2.06
2.08
2.10
2.12
2.14
2.16
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
197
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-72. 2MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
Figure 37-73. 2MHz internal oscillator CALA calibration step size.
VCC = 3V.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
1.960
1.965
1.970
1.975
1.980
1.985
1.990
1.995
2.000
2.005
2.010
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
105
85
25
-40
0.15
0.17
0.19
0.21
0.23
0.25
0.27
0.29
0.31
0.33
0 163248648096112128
Frequency Step size [%]
CALA
Temp [°C]
198
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.1.10.4 32MHz Internal Oscillator
Figure 37-74. 32MHz internal oscillator frequency vs. temperature.
DFLL disabled.
Figure 37-75. 32MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
1.8 V
1.6 V
31.25
31.35
31.45
31.55
31.65
31.75
31.85
31.95
32.05
32.15
32.25
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
199
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-76. 32MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
Figure 37-77. 32MHz internal oscillator frequency vs. CALB calibration value.
VCC = 3.0V.
105
85
25
-40
0.08
0.13
0.18
0.23
0.28
0.33
0.38
0.43
0.48
0 163248648096112128
Frequency S tep S ize [%]
CALA
Temp [°C]
105
85
25
- 40
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
0 8 16 24 32 40 48 56 64
Frequency Step size [%]
CALB
Temp [°C]
200
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.1.10.5 32MHz internal oscillator calibrated to 48MHz
Figure 37-78. 48MHz internal oscillator frequency vs. temperature.
DFLL disabled.
Figure 37-79. 48MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
46.4
47.2
48.0
48.8
49.6
50.4
51.2
52.0
52.8
53.6
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
46.900
47.050
47.200
47.350
47.500
47.650
47.800
47.950
48.100
48,250
48.400
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
201
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-80. 48MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
37.1.11 Two-Wire Interface characteristics
Figure 37-81. SDA hold time vs. Vcc.
105
85
25
-40
0.12
0.15
0.18
0.21
0.24
0.27
0.30
0.33
0.36
0163248648096112
128
Frequency Step size [%]
CALA
Temp [°C]
105
85
25
-40
260
265
270
275
280
285
290
295
300
2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Holdtime [ns]
Vcc [V]
Temp [°C]
202
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-82. SDA hold time vs. supply voltage.
37.1.12 PDI characteristics
Figure 37-83. Maximum PDI frequency vs. VCC.
3
2
1
0
50
100
150
200
250
300
350
400
450
500
2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
VCC
[V]
Hold time [ns]
105
85
25
-40
10
14
18
22
26
30
34
38
42
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Maximum Frequency [MHz]
VCC[V]
Temp [°C]
203
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2 ATxmega128A3U
37.2.1 Current consumption
37.2.1.1 Active mode supply current
Figure 37-84. Active supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
Figure 37-85. Active supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
0
100
200
300
400
500
600
700
800
900
1000
0 0.2 0.4 0.6 0.8 1
I
CC
[µA]
Frequency [MHz]
3.6 V
3.0 V
2.7 V
1.8 V
1.6 V
0
2
4
6
8
10
12
14
0 4 8 121620242832
I
CC
[mA]
Frequency [MHz]
2.2 V
204
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-86. Active mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
Figure 37-87. Active mode supply current vs. VCC.
fSYS = 1MHz external clock.
105
85
25
-40
100
140
180
220
260
300
340
380
420
460
1.6 1.8 2 2.2 2,4 2.6 2.8 3 3.2 3.4 3.6
ICC
[µA]
VCC[V]
Temp [°C]
105
85
25
-40
260
340
420
500
580
660
740
820
900
980
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC[µA]
VCC [V]
Temp [°C]
205
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-88. Active mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
Figure 37-89. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
105
85
25
-40
500
625
750
875
1000
1125
1250
1375
1500
1625
1750
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC[µA]
VCC[V]
Temp [°C]
105
85
25
-40
1500
2000
2500
3000
3500
4000
4500
5000
5500
6000
6500
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC
[µA]
VCC [V]
Temp [°C]
206
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-90. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator.
37.2.1.2 Idle mode supply current
Figure 37-91. Idle mode supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
105
85
25
-40
9000
9700
10400
11100
11800
12500
13200
13900
14600
15300
2.72.82.9 3 3.13.23.33.43.53.6
ICC [µA]
VCC [V]
Temp [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
0
30
60
90
120
150
180
00.20.40.60.81
I
CC
[µA]
Frequency [MHz]
207
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-92. Idle mode supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
Figure 37-93. Idle mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
3.6 V
3.0 V
2.7 V
1.8 V
1.6 V
0
1
2
3
4
5
6
0 4 8 121620242832
I
CC
[mA]
Frequency [MHz]
2.2 V
105
85
25
-40
27
28
29
30
31
32
33
34
35
36
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
VCC [V]
Temp [°C]
208
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-94. Idle mode supply current vs. VCC.
fSYS = 1MHz external clock.
Figure 37-95. Idle mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
105
85
25
-40
65
77
89
101
113
125
137
149
161
173
185
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
VCC [V]
Temp [°C]
105
85
25
-40
180
210
240
270
300
330
360
390
420
450
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
VCC [V]
Temp [°C]
209
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-96. Idle mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
Figure 37-97. Idle mode current vs. VCC.
fSYS = 32MHz internal oscillator.
105
85
25
-40
700
880
1060
1240
1420
1600
1780
1960
2140
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
V
CC [V]
Temp [°C]
105
85
25
-
40
3900
4150
4400
4650
4900
5150
5400
5650
5900
6150
2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
ICC [µA]
VCC
[V]
Temp [°C]
210
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2.1.3 Power-down mode supply current
Figure 37-98. Power-down mode supply current vs. VCC.
All functions disabled.
Figure 37-99. Power-down mode supply current vs. VCC.
Watchdog and sampled BOD enabled.
105
85
25
-40
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
VCC [V]
Temp [°C]
105
85
25
-40
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
5.50
6.00
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
VCC [V]
Temp [°C]
211
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2.1.4 Power-save mode supply current
Figure 37-100. Power-save mode supply current vs. VCC.
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.
37.2.1.5 Standby mode supply current
Figure 37-101. Standby supply current vs. VCC.
Standby, fSYS =1MHz.
Normal mode
Low-power mode
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
V
CC
[V]
I
CC
[µA]
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
I
CC
[uA]
V
CC
[V]
105°C
85°C
25°C
-40°C
212
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-102. Standby supply current vs. VCC.
25°C, running from different crystal oscillators.
37.2.2 I/O Pin Characteristics
37.2.2.1 Pull-up
Figure 37-103. I/O pin pull-up resistor current vs. input voltage.
VCC = 1.8V.
16MHz
12MHz
8MHz
2MHz
0.454MHz
150
200
250
300
350
400
450
500
V
CC
[V]
I
CC
[µA]
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
105
85
25
-40
0
8
16
24
32
40
48
56
64
72
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
IPIN [µA]
VPIN [V]
Temp [°C]
213
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-104. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.0V.
Figure 37-105. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.3V.
105
85
25
-40
0
15
30
45
60
75
90
105
120
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
IPIN [µA]
VPIN [V]
Temp [°C]
105
85
25
-
40
0
20
40
60
80
100
120
140
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3
IPIN [µA]
VPIN [V]
Temp [°C]
214
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2.2.2 Output Voltage vs. Sink/Source Current
Figure 37-106. I/O pin output voltage vs. source current.
VCC = 1.8V.
Figure 37-107. I/O pin output voltage vs. source current.
VCC = 3.0V.
105
85
25
-40
0.50
0.65
0.80
0.95
1.10
1.25
1.40
1.55
1.70
1.85
-9 -8 -7 -6 -5 -4 -3 -2 -1 0
VPIN [V]
IPIN [mA]
Temp [°C]
105
8525-40
0.5
0.8
1.1
1.4
1.7
2.0
2.3
2.6
2.9
3.2
-30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0
VPIN [V]
IPIN [mA]
Temp [°C]
215
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-108. I/O pin output voltage vs. source current.
VCC = 3.3V.
Figure 37-109. I/O pin output voltage vs. source current.
10585
25
-40
0.5
0.8
1.1
1.4
1.7
2.0
2.3
2.6
2.9
3.2
3.5
-33 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0
VPIN [V ]
IPIN [mA]
Temp [°C]
3.6 V
3.0 V
2.7 V
1.8 V
1.6 V
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-20 -15 -10 -5 0
V
PIN
[V]
I
PIN
[mA]
216
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-110. I/O pin output voltage vs. sink current.
VCC = 1.8V.
Figure 37-111. I/O pin output voltage vs. sink current.
VCC = 3.0V.
105
85
25
-40
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
02468101214
16
VPIN [V]
IPIN [mA]
Temp [°C]
105
85
25
-40
0.00
0.12
0.24
0.36
0.48
0.60
0.72
0.84
0.96
1.08
0 3 6 9 12 15 18 21 24 27 30 33
V
PIN
[V]
I
PIN
[mA]
Temp [°C]
217
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-112. I/O pin output voltage vs. sink current.
VCC = 3.3V.
Figure 37-113. I/O pin output voltage vs. sink current.
105
85
25
-40
0.00
0.12
0.24
0.36
0.48
0.60
0.72
0.84
0.96
1.08
0 3 6 9 12 15 18 21 24 27 30 33
VPIN [V]
IPIN [mA]
Temp [°C]
3.6 V
3.3 V
3.0 V
2.7 V
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
0 3 6 9 12 15 18 21 24 27 30
V
PIN
[V]
I
PIN
[mA]
1.6 V 1.8 V
218
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2.2.3 Thresholds and Hysteresis
Figure 37-114. I/O pin input threshold voltage vs. VCC.
T = 25°C.
Figure 37-115. I/O pin input threshold voltage vs. VCC.
VIH I/O pin read as “1”.
VIL
VIH
0.50
0.65
0.80
0.95
1.10
1.25
1.40
1.55
1.70
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
THR ESH OLD
[V]
V
CC
[V]
105
85
25
-40
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VTHR E S HOLD [V ]
VCC [V]
Temp [°C]
219
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-116. I/O pin input threshold voltage vs. VCC.
VIL I/O pin read as “0”.
Figure 37-117. I/O pin input hysteresis vs. VCC.
105
85
25
-40
0.50
0.65
0.80
0.95
1.10
1.25
1.40
1.55
1.70
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
THR E SHOLD
[V]
V
CC
[V]
Temp [°C]
105
85
25
-40
0.100
0.125
0.150
0.175
0.200
0.225
0.250
0.275
0.300
0.325
0.350
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
HYST
[V]
V
CC
[V]
Temp [°C]
220
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2.3 ADC Characteristics
Figure 37-118. INL error vs. external VREF.
T = 25
°
C, VCC = 3.6V, external reference.
Figure 37-119. INL error vs. sample rate.
T = 25
°
C, VCC = 3.6V, VREF = 3.0V external.
Single-ended unsigned mode
Single-ended signed mode
Dif f erential mode
0.0
0.5
1.0
1.5
2.0
2.5
3.0
1.01.21.41.61.82.02.22.42.62.83.0
INL [LSB]
Vref [V]
Single-ended unsigned mode
Single-ended signed mode
Dif f erential mode
0
0.5
1
1.5
2
2.5
3
500 650 800 950 1100 1250 1400 1550 1700 1850 2000
INL[LSB]
ADC sample rate [ksps]
221
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-120. INL error vs. input code.
Figure 37-121. DNL error vs. external VREF.
T = 25
°
C, VCC = 3.6V, external reference.
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
INL [LSB]
2.0
1.5
1.0
0.5
0.0
-0.5
-0.1
-1.5
-2.0
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.35
0.45
0.55
0.65
0.75
0.85
0.95
1.05
1.15
1.01.21.41.61.82.02.22.42.62.83.0
DNL [LSB]
Vref [V]
222
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-122. DNL error vs. sample rate.
T = 25
°
C, VCC = 3.6V, VREF = 3.0V external.
Figure 37-123. DNL error vs. input code.
Single-ended unsigned mode
Single-ended signed mode
Dif f erential mode
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
500 650 800 950 1100 1250 1400 1550 1700 1850 2000
DNL [LSB]
ADC sampling rate [kSps]
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
DNL [LSB]
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
223
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-124. Gain error vs. VREF.
T = 25
°
C, VCC = 3.6V, ADC sampling speed = 500ksps.
Figure 37-125. Gain error vs. VCC.
T = 25
°
C, VREF = external 1.0V, ADC sampling speed = 500ksps.
Single-ended unsigned mode
Single-ended signed mode
Dif f erential mode
-5
-4
-3
-2
-1
0
1
2
3
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Gain Error [mV]
Vref [V]
Single-ended unsigned mode
Single-ended signed mode
Dif f erential mode
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Gain Error [mV]
Vcc [V]
224
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-126. Offset error vs. VREF.
T = 25
°
C, VCC = 3.6V, ADC sampling speed = 500ksps.
Figure 37-127. Gain error vs. temperature.
VCC = 2.7V, VREF = external 1.0V.
Dif f erential mode
-1.6
-1.5
-1.4
-1.3
-1.2
-1.1
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Offset[mV]
Vref[V]
Single Ended Signed
Differential Signed
-1
0
1
2
3
4
5
6
-60 -40 -200 20406080 100 120
Gain Error [mV]
Temperature [ºC]
225
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-128. Offset error vs. VCC.
T = 25
°
C, VREF = external 1.0V, ADC sampling speed = 500ksps.
Figure 37-129. Noise vs. VREF.
T = 25
°
C, VCC = 3.6V, ADC sampling speed = 500ksps.
Differential mode
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Offset Erro r [mV]
Vcc [V]
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.2
0.3
0.3
0.4
0.4
0.5
0.5
0.6
0.6
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Noise [mV RMS]
Vref [V]
226
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-130. Noise vs. VCC.
T = 25
°
C, VREF = external 1.0V, ADC sampling speed = 500ksps.
37.2.4 DAC Characteristics
Figure 37-131. DAC INL error vs. VREF.
VCC = 3.6V.
Single-ended unsigned mode
Single-ended signed mode
Dif f erential signed
0.2
0.3
0.3
0.4
0.4
0.5
0.5
0.6
0.6
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Noise [mV RMS]
Vcc [V]
Roo m temperature, Vref External 1.0V, ADC sampling speed 500kS/s
105
85
25
-40
0
0.5
1
1.5
2
2.5
3
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
INL [LS B]
VREF [V]
Temp [°C]
227
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-132. DNL error vs. VREF.
T = 25
°
C, VCC = 3.6V.
Figure 37-133. DAC noise vs. temperature.
VCC = 3.0V, VREF = 2.0V.
105
85
25
-40
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
11.522.533.5
DAC DNL [LSB]
VREF [V]
Temp [°C]
0.16
0.165
0.17
0.175
0.18
0.185
0.19
0.195
0.2
-45-35-25-15-5 5 152535455565758595105
Noise[mV R MS]
Temperature [ºC]
228
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2.5 Analog Comparator Characteristics
Figure 37-134. Analog comparator hysteresis vs. VCC.
High-speed, small hysteresis.
Figure 37-135. Analog comparator hysteresis vs. VCC.
Low power, small hysteresis.
-40°C
25°C
85°C
105°C
4
5
6
7
8
9
10
11
12
13
14
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST [mV]
V
CC
[V]
-40°C
25°C
85°C
105°C
12
14
16
18
20
22
24
26
28
30
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST[mV]
V
CC [V]
229
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-136. Analog comparator hysteresis vs. VCC
High-speed mode, large hysteresis.
Figure 37-137. Analog comparator hysteresis vs. VCC.
Low power, large hysteresis.
-40°C
25°C
85°C
105°C
14
16
18
20
22
24
26
28
30
32
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VHYST[mV]
V
CC [V]
-40°C
25°C
85°C
105°C
32
36
40
44
48
52
56
60
64
68
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST [mV]
V
CC [V]
230
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-138. Analog comparator current source vs. calibration value.
Temperature = 25°C.
Figure 37-139. Analog comparator current source vs. calibration value.
VCC = 3.0V.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
1.8
2.6
3.4
4.2
5
5.8
6.6
7.4
8.2
0246810121416
I
CURRENTSOURCE
[µA]
CURRCALIBA[3..0]
105
85
25
-40
3.5
3.8
4.1
4.4
4.7
5
5.3
5.6
5.9
6.2
6.5
0246810121416
I
CURRENTSOURCE
[µA]
CURRCALIBA[3...0]
Temp [°C]
231
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-140. Voltage scaler INL vs. SCALEFAC.
T = 25
°
C, VCC = 3.0V.
37.2.6 Internal 1.0V reference Characteristics
Figure 37-141. ADC/DAC Internal 1.0V reference vs. temperature.
-0.09
-0.06
-0.03
0
0.03
0.06
0.09
0.12
0.15
0 8 16 24 32 40 48 56 64
INL [LSB]
SCALEFAC
p
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
0.9986
0.9992
0.9998
1.0004
1.0010
1.0016
1.0022
1.0028
1.0034
1.0040
1.0046
-45 -30 -15 0 15 30 45 60 75 90 105
Bandgap Voltage [V]
Temperature [°C]
232
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2.7 BOD Characteristics
Figure 37-142. BOD thresholds vs. temperature.
BOD level = 1.6V.
Figure 37-143. BOD thresholds vs. temperature.
BOD level = 3.0V.
Rising Vcc
Falling Vcc
1.631
1.632
1.634
1.635
1.637
1.638
1.640
1.641
1.643
1.644
-45 -30 -15 0 15 30 45 60 75 90 105
VBOT [V]
Temperature [°C]
Rising Vcc
F alling V c c
3.010
3.020
3.030
3.040
3.050
3.060
3.070
3.080
3.090
-45 -30 -15 0 15 30 45 60 75 90 105
V
BOT
[V]
Temperature [°
C]
233
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2.8 External Reset Characteristics
Figure 37-144. Minimum Reset pin pulse width vs. VCC.
Figure 37-145. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 1.8V.
105
85
25
-40
80
87
94
101
108
115
122
129
136
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
t
RST
[ns ]
VCC [V]
Temp [°C]
105
85
25
-40
0
10
20
30
40
50
60
70
80
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
I
RESET
[µA]
V
RESET
[V]
Temp [°C]
234
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-146. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.0V.
Figure 37-147. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.3V.
105
85
25
-40
0
15
30
45
60
75
90
105
120
135
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
I
RESET
[µA]
VRESET[V]
Temp [°C]
105
25
-
40
0
18
36
54
72
90
108
126
144
0.00 0.35 0.70 1.05 1.40 1.75 2.10 2.45 2.80 3.15 3.50
IRESET [µA]
VRESET
[V]
85
Temp [°C]
235
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-148. Reset pin input threshold voltage vs. VCC.
VIH - Reset pin read as “1”.
Figure 37-149. Reset pin input threshold voltage vs. VCC.
VIL - Reset pin read as “0”.
105
85
25
-40
1.00
1.15
1.30
1.45
1.60
1.75
1.90
2.05
2.20
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
THRESHOLD
[V]
V
CC
[V]
Temp [°C]
105
85
25
-40
0.50
0.65
0.80
0.95
1.10
1.25
1.40
1.55
1.70
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
THR E SHOLD
[V]
V
CC
[V]
Temp [°C]
236
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2.9 Power-on Reset Characteristics
Figure 37-150. Power-on reset current consumption vs. VCC.
BOD level = 3.0V, enabled in continuous mode.
1.055
1.060
1.065
1.070
1.075
1.080
1.085
1.090
1.095
-45 -30 -15 0 15 30 45 60 75 90 105
VPOT
-[V]
Temperature [°C]
Falling Vcc
237
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2.10 Oscillator Characteristics
37.2.10.1 Ultra Low-Power internal oscillator
Figure 37-151. Ultra Low-Power internal oscillator frequency vs. temperature.
37.2.10.2 32.768kHz Internal Oscillator
Figure 37-152. 32.768kHz internal oscillator frequency vs. temperature.
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
38.5
39.0
39.5
40.0
40.5
41.0
41.5
42.0
42.5
43.0
43.5
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [kHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.35
32.41
32.47
32.53
32.59
32.65
32.71
32.77
32.83
32.89
32.95
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
238
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-153. 32.768kHz internal oscillator frequency vs. calibration value.
VCC = 3.0V, T = 25°C.
37.2.10.3 2MHz Internal Oscillator
Figure 37-154. 2MHz internal oscillator frequency vs. temperature.
DFLL disabled.
22
25
28
31
34
37
40
43
46
49
0 30 60 90 120 150 180 210 240 270
Frequency [kHz]
RC32KCAL[7..0]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
1.975
1.990
2.005
2.020
2.035
2.050
2.065
2.080
2.095
2.110
2.125
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
239
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-155. 2MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
Figure 37-156. 2MHz internal oscillator CALA calibration step size.
VCC = 3V.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
1.978
1.982
1.986
1.990
1.994
1.998
2.002
2.006
2.010
2.014
2.018
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
105
85
25
-40
0.13
0.15
0.17
0.19
0.21
0.23
0.25
0.27
0.29
0 15 30 45 60 75 90 105 120 135
Frequency Step Size [%]
CALA
Temp [°C]
240
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2.10.4 32MHz Internal Oscillator
Figure 37-157. 32MHz internal oscillator frequency vs. temperature.
DFLL disabled.
Figure 37-158. 32MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
31.4
31.8
32.2
32.6
33.0
33.4
33.8
34.2
34.6
35.0
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
31.70
31.75
31.80
31.85
31.90
31.95
32.00
32.05
32.10
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
241
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-159. 32MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
Figure 37-160. 32MHz internal oscillator frequency vs. CALB calibration value.
VCC = 3.0V.
105
85
25
-40
0.07
0.10
0.13
0.16
0.19
0.22
0.25
0.28
0.31
0.34
0 153045607590105120135
Frequency Step Size [%]
CALA
Temp [°C]
105
85
25
-40
0.80
1.05
1.30
1.55
1.80
2.05
2.30
2.55
2.80
0 8 16 24 32 40 48 56 64
Frequency S tep S ize [% ]
CALB
Temp [°C]
242
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.2.10.5 32MHz internal oscillator calibrated to 48MHz
Figure 37-161. 48MHz internal oscillator frequency vs. temperature.
DFLL disabled.
Figure 37-162. 48MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
46.8
47.4
48.0
48.6
49.2
49.8
50.4
51.0
51.6
52.2
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
47.4
47.5
47.6
47.7
47.8
47.9
48
48.1
48.2
48.3
-45 -30 -15 0 15 30 45 60 75 90 105
Frequency [MHz]
Temperature [°C]
243
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-163. 48MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
37.2.11 Two-Wire Interface characteristics
Figure 37-164. SDA hold time vs. Vcc.
105
85
25
-40
0.07
0.10
0.13
0.16
0.19
0.22
0.25
0.28
0.31
0.34
0 153045607590105120135
Frequency Step Size [%]
CALA
Temp [°C]
105
85
25
-
40
260
265
270
275
280
285
290
295
300
2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Holdtime [ns]
Vcc [V]
Tem p [ °C ]
244
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-165. SDA hold time vs. supply voltage.
37.2.12 PDI characteristics
Figure 37-166. Maximum PDI frequency vs. VCC.
3
2
1
0
50
100
150
200
250
300
350
400
450
500
2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
VCC [V]
Hold time [ns]
105
85
25
-40
12.0
14.5
17.0
19.5
22.0
24.5
27.0
29.5
32.0
34.5
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Maximum Frequency [MHz]
VCC[V ]
Temp [°C]
245
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3 ATxmega192A3U
37.3.1 Current consumption
37.3.1.1 Active mode supply current
Figure 37-167. Active supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
Figure 37-168. Active supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
3.3V
3.0V
2.7V
2.2V
1.8V
100
200
300
400
500
600
700
800
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency [MHz]
I
CC
[µA]
3.3V
3.0V
2.7V
0
2
4
6
8
10
12
14
0 4 8 121620242832
Frequency [MHz]
I
CC
[mA]
2.2V
1.8V
246
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-169. Active mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
Figure 37-170. Active mode supply current vs. VCC.
fSYS = 1MHz external clock.
105°C
85°C
25°C
-40°C
50
75
100
125
150
175
200
225
250
1.6 2.1 2.6 3.1 3.6
ICC [µA]
VCC[V]
105°C
85°C
25°C
-40°C
200
260
320
380
440
500
560
620
680
740
800
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
VCC [V]
247
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-171. Active mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
Figure 37-172. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
105°C
85°C
25°C
- 40°C
450
600
750
900
1050
1200
1350
1500
1650
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
V
CC [V]
105°C
85°C
25°C
-40°C
1500
2000
2500
3000
3500
4000
4500
5000
5500
6000
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
I
CC[µA]
VCC[V ]
248
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-173. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator.
37.3.1.2 Idle mode supply current
Figure 37-174. Idle mode supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
105°C
85°C
25°C
-40°C
8800
9600
10400
11200
12000
12800
13600
14400
15200
2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
I
CC
[µA]
V
CC
[V]
3.3V
3.0V
2.7V
2.2V
1.8V
0
20
40
60
80
100
120
140
160
180
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency [MHz]
I
CC
[µA]
249
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-175. Idle mode supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
Figure 37-176. Idle mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
3.3V
3.0V
2.7V
0
1
2
3
4
5
6
0 4 8 121620242832
Frequency [MHz]
I
CC
[mA]
1.8V
2.2V
105°C
85°C
25°C
-40°C
28
29
30
31
32
33
34
35
36
37
38
39
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
V
CC [V]
250
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-177. Idle mode supply current vs. VCC.
fSYS = 1MHz external clock.
Figure 37-178. Idle mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
105°C
85°C
25°C
- 40°C
65
85
105
125
145
165
185
205
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
V
CC [V]
.
105°C
85°C
25°C
- 40°C
190
240
290
340
390
440
490
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
V
CC [V]
251
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-179. Idle mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
Figure 37-180. Idle mode current vs. VCC.
fSYS = 32MHz internal oscillator.
105°C
85°C
25°C
-40°C
700
900
1100
1300
1500
1700
1900
2100
2300
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
V
CC[V]
SYS p
105°C
85°C
25°C
-40°C
4000
4300
4600
4900
5200
5500
5800
6100
6400
6700
2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
ICC [µA]
V
CC [V]
252
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3.1.3 Power-down mode supply current
Figure 37-181. Power-down mode supply current vs. VCC.
All functions disabled.
Figure 37-182. Power-down mode supply current vs. VCC.
Watchdog and sampled BOD enabled.
105°C
85°C
25°C
-40°C
0
1
2
3
4
5
6
7
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
VCC
105°C
85°C
35°C
40°C
0
1
2
3
4
5
6
7
8
1.6 2.1 2.6 3.1 3.6
I
CC
[µA]
VCC [V]
253
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3.1.4 Power-save mode supply current
Figure 37-183. Power-save mode supply current vs. VCC.
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.
37.3.1.5 Standby mode supply current
Figure 37-184. Standby supply current vs. VCC.
Standby, fSYS =1MHz.
Normal mode
Low-power mode
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
V
CC
[V]
I
CC
[µA]
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
I
CC
[uA]
V
CC
[V]
105°C
85°C
25°C
-40°C
254
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-185. Standby supply current vs. VCC.
25°C, running from different crystal oscillators.
37.3.2 I/O Pin Characteristics
37.3.2.1 Pull-up
Figure 37-186. I/O pin pull-up resistor current vs. input voltage.
VCC = 1.8V.
16MHz
12MHz
8MHz
2MHz
0.454MHz
150
200
250
300
350
400
450
500
V
CC
[V]
I
CC
[µA]
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
105°C
85°C
25°C
-40°C
0
7
14
21
28
35
42
49
56
63
70
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
IPIN [µA]
V
PIN [V]
255
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-187. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.0V.
Figure 37-188. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.3V.
105°C
85°C
25°C
-40°C
0
13
26
39
52
65
78
91
104
117
130
00.511.522.53
IPIN [µA]
V
PIN [V]
CC
105°C
85°C 25°C
-40°C
0
14
28
42
56
70
84
98
112
126
140
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3
IPIN [µA]
V
PIN [V]
256
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3.2.2 Output Voltage vs. Sink/Source Current
Figure 37-189. I/O pin output voltage vs. source current.
VCC = 1.8V.
Figure 37-190. I/O pin output voltage vs. source current.
VCC = 3.0V.
105 °C
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-10-9-8-7-6-5-4-3-2-1
V
PIN [V]
IPIN[mA]
105°C 85°C
25°C -40°C
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
-30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0
V
PIN[V]
IPIN[mA]
257
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-191. I/O pin output voltage vs. source current.
VCC = 3.3V.
Figure 37-192. I/O pin output voltage vs. source current.
105°C
85°C
25°C
-40°C
0
0.5
1
1.5
2
2.5
3
3.5
-33 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0
V
PIN [V]
IPIN[mA]
3.6V
3.3V
2.7V
2.2V
1.8V
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0
I
PIN
[mA]
V
PIN
[V]
258
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-193. I/O pin output voltage vs. sink current.
VCC = 1.8V.
Figure 37-194. I/O pin output voltage vs. sink current.
VCC = 3.0V.
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0 2 4 6 8 101214161820
VPIN
[V]
IPIN [mA]
40°C
85°C
25°C
105°C
105°C
85°C
25°C
-40°C
0
0.2
0.4
0.6
0.8
1
1.2
0 3 6 9 12 15 18 21 24 27 30 33
V
PIN[V
IPIN [mA]
259
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-195. I/O pin output voltage vs. sink current.
VCC = 3.3V.
Figure 37-196. I/O pin output voltage vs. sink current.
105°C
85°C
25°C
-40°C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 3 6 9 12 15 18 21 24 27 30 33
VPIN[V
IPIN[mA]
V
CC 3.3 V
3.6V
3.3V
2.7V
2.2V
0
0.3
0.6
0.9
1.2
1.5
0 5 10 15 20 25
IPIN [mA]
V
PIN
[V]
1.8V
260
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3.2.3 Thresholds and Hysteresis
Figure 37-197. I/O pin input threshold voltage vs. VCC.
T = 25°C.
Figure 37-198. I/O pin input threshold voltage vs. VCC.
VIH I/O pin read as “1”.
VIL
VIH
0.50
0.65
0.80
0.95
1.10
1.25
1.40
1.55
1.70
1.85
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VCC [V]
V
Threshold
[V]
105°C
85°C
25°C
-40°C
0.7
0.8
0.9
1
1.1
1,2
1.3
1.4
1.5
1.6
1.7
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vthres hold [V]
VCC [V]
261
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-199. I/O pin input threshold voltage vs. VCC.
VIL I/O pin read as “0”.
Figure 37-200. I/O pin input hysteresis vs. VCC .
105°C
85°C
25°C
-40°C
0.5
0.7
0.9
1,1
1.3
1.5
1.7
1.6 .,8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vthre s hold [V]
VCC [V]
105°C
85°C
25°C
-40°C
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vthres hold [V]
VCC[V ]
262
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3.3 ADC Characteristics
Figure 37-201. INL error vs. external VREF.
T = 25
°
C, VCC = 3.6V, external reference.
Figure 37-202. INL error vs. sample rate.
T = 25
°
C, VCC = 3.6V, VREF = 3.0V external.
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
VREF [V]
INL [LSB]
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
ADC sample rate [ksps]
INL [LSB]
500 650 800 950 1100 1250 1400 1550 1700 1850 2000
263
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-203. INL error vs. input code.
Figure 37-204. DNL error vs. external VREF.
T = 25
°
C, VCC = 3.6V, external reference.
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
INL [LSB]
Single-ended unsigned mode
Single-endedsigned mode
Differential mode
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
V
REF
[V]
DNL [LSB]
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
264
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-205. DNL error vs. sample rate.
T = 25
°
C, VCC = 3.6V, VREF = 3.0V external.
Figure 37-206. DNL error vs. input code.
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
Sampling speed [MS/s]
DNL [LSB]
0.50 0.65 0.80 0.95 1.10 1.25 1.40 1.55 1.70 1.85 2.00
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
0 512 1024 1536 2048 2560 3072 3584 4096
ADC Input Code
DNL [LSB]
265
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-207. Gain error vs. VREF.
T = 25
°
C, VCC = 3.6V, ADC sampling speed = 500ksps.
Figure 37-208. Gain error vs. VCC.
T = 25
°
C, VREF = external 1.0V, ADC sampling speed = 500ksps.
Single-ended unsigned mode
Single-ended signed mode
Differential mode
-10
-8
-6
-4
-2
0
2
4
V
REF
[V]
Gain error [mV]
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Single-ended unsigned mode
Single-ended signed mode
Differential mode
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
V
CC
[V]
Gain Error [mV]
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
266
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-209. Offset error vs. VREF.
T = 25
°
C, VCC = 3.6V, ADC sampling speed = 500ksps.
Figure 37-210. Gain error vs. temperature.
VCC = 2.7V, VREF = external 1.0V .
Differential mode
-1.6
-1.5
-1.4
-1.3
-1.2
-1.1
VREF
[V]
Offset [mV]
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Single Ended
Unsigned
Single Ended Signed
Differential Signed
0
1
2
3
4
5
6
7
8
9
-60 -40 -20 0 20 40 60 80 100 120 140
Gain Error [mV]
Temperature [°C]
267
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-211. Offset error vs. VCC.
T = 25
°
C, VREF = external 1.0V, ADC sampling speed = 500ksps.
Figure 37-212. Noise vs. VREF.
T = 25
°
C, VCC = 3.6V, ADC sampling speed = 500ksps.
Differential mode
-1.2
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
VCC
[V]
Offset error [mV]
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
p, ,pgp
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.40
0.55
0.70
0.85
1.00
1.15
1.30
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
Noise [mV RMS]
268
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-213. Noise vs. VCC.
T = 25
°
C, VREF = external 1.0V, ADC sampling speed = 500ksps.
37.3.4 DAC Characteristics
Figure 37-214. DAC INL error vs. VREF.
VCC = 3.6V.
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
CC
[V]
Noise [mV RMS]
105°C
85°C
25°C
-40°C
0
0.5
1
1.5
2
2.5
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
DAC INL [LSB]
VREF[V]
269
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-215. DNL error vs. VREF.
T = 25
°
C, VCC = 3.6V.
Figure 37-216. DAC noise vs. temperature.
VCC = 3.3V, VREF = 2.0V.
105°C
85°C
25°C
-40°C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
DAC DNL [LSB]
VREF [V]
DAC_Linearity
0.1
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.2
-40 -20 0 20 40 60 80 100 120 140
Noise[mV R MS]
Temperature [°C]
270
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3.5 Analog Comparator Characteristics
Figure 37-217. Analog comparator hysteresis vs. VCC.
High-speed, small hysteresis.
Figure 37-218. Analog comparator hysteresis vs. VCC.
Low power, small hysteresis.
40°C
25°C
85°C
105°C
4
5
6
7
8
9
10
11
12
13
14
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VHYST [mV]
V
CC [V]
40°C
25°C
85°C
105°C
12
14
16
18
20
22
24
26
28
30
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VHYST [mV]
V
CC [V]
271
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-219. Analog comparator hysteresis vs. VCC.
High-speed mode, large hysteresis.
Figure 37-220. Analog comparator hysteresis vs. VCC.
Low power, large hysteresis.
40°C
25°C
85°C
105°C
14
16
18
20
22
24
26
28
30
32
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VHYST [mV]
V
CC[V]
40°C
25°C
85°C
105°C
32
36
40
44
48
52
56
60
64
68
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST [mV]
V
CC[V]
272
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-221. Analog comparator current source vs. calibration value.
Temperature = 25°C.
Figure 37-222. Analog comparator current source vs. calibration value.
VCC = 3.0V.
3.3V
3.0V
2.7V
2.2V
1.8V
2
3
4
5
6
7
8
0123456789101112131415
CALIB[3...0]
ICURRENT SOURCE [µA]
105°C
85°C
25°C
-40°C
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0123456789101112131415
ICURRENT SOURCE [µA]
CALIB[3..0]
273
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-223. Voltage scaler INL vs. SCALEFAC.
T = 25
°
C, VCC = 3.0V.
37.3.6 Internal 1.0V reference Characteristics
Figure 37-224. ADC/DAC Internal 1.0V reference vs. temperature.
25°C
-0.100
-0.075
-0.050
-0.025
0
0.025
0.050
0.075
0.100
0 10203040506070
SCALEFAC
INL [LSB]
3.6 V
3.0 V
2.7 V
2.2 V
1.6 V
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
1.006
-40 -25 -10 5 20 35 50 65 80 95 110
Bandgap Voltage [V]
Temperature [°C]
274
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3.7 BOD Characteristics
Figure 37-225. BOD thresholds vs. temperature.
BOD level = 1.6V.
Figure 37-226. BOD thresholds vs. temperature.
BOD level = 3.0V.
Rising Vcc
Falling Vcc
1.618
1.62
1.622
1.624
1.626
1.628
1.63
1.632
-40 -25 -10 5 20 35 50 65 80 95 110
V
BOT[V]
T [°C]
Rising Vcc
Falling Vcc
3.01
3.02
3.03
3.04
3.05
3.06
3.07
3.08
-40 -25 -10 5 20 35 50 65 80 95 110
V
BOT[V]
Temperature [°C]
275
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3.8 External Reset Characteristics
Figure 37-227. Minimum Reset pin pulse width vs. VCC.
Figure 37-228. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 1.8V.
105°C
85°C
25°C
40°C
92
97
102
107
112
117
122
127
132
137
142
147
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
tRST[n s ]
V
CC [V
105 °C
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
70
80
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
IRESET[µA]
V
RESET[V]
276
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-229. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.0V.
Figure 37-230. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.3V.
105°C
85°C
25°C
-40°C
0
13
26
39
52
65
78
91
104
117
130
0 0.5 1 1.5 2 2.5 3
IRESET [µA]
V
RESET [V]
105°C
-40°C
0
14
28
42
56
70
84
98
112
126
140
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3
IRESET[µA]
V
RESET [V]
85°C
25°C
277
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-231. Reset pin input threshold voltage vs. VCC
VIH - Reset pin read as “1”.
Figure 37-232. Reset pin input threshold voltage vs. VCC.
VIL - Reset pin read as “0”.
105°C
85°C
25°C
-40°C
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
thre s hold [V]
V
CC[V]
105°C
85°C
25°C
-40°C
0.4
0.6
0.8
1
1,2
1.4
1.6
1.8
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
thre s hol d[V]
V
CC [V]
278
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3.9 Power-on Reset Characteristics
Figure 37-233. Power-on reset current consumption vs. VCC.
BOD level = 3.0V, enabled in continuous mode.
105°C
85°C
25°C
-40°C
0
100
200
300
400
500
600
700
800
900
1000
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
ICC [µA]
VCC[V]
279
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3.10 Oscillator Characteristics
37.3.10.1 Ultra Low-Power internal oscillator
Figure 37-234. Ultra Low-Power internal oscillator frequency vs. temperature.
37.3.10.2 32.768kHz Internal Oscillator
Figure 37-235. 32.768kHz internal oscillator frequency vs. temperature.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
27.5
28
28.5
29
29.5
30
30.5
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [kHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.36
32.42
32.48
32.54
32.60
32.66
32.72
32.78
32.84
32.90
32.96
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [kHz]
Temperature [°C]
280
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-236. 32.768kHz internal oscillator frequency vs. calibration value.
VCC = 3.0V, T = 25°C.
37.3.10.3 2MHz Internal Oscillator
Figure 37-237. 2MHz internal oscillator frequency vs. temperature.
DFLL disabled.
20
25
30
35
40
45
50
0 50 100 150 200 250 300
RC32KCAL[7..0]
Frequency [kHz]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
1.95
1.98
2.01
2.04
2.07
2.1
2.13
2.16
2.19
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [MHz]
Temperature [°C]
281
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-238. 2MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
Figure 37-239. 2MHz internal oscillator CALA calibration step size.
VCC = 3V.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
1.975
1.980
1.985
1.990
1.995
2.000
2.005
2.010
2.015
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [MHz]
Temperature [°C]
105°C
85°C
25°C
-40°C
0.13
0.16
0.19
0.22
0.25
0.28
0.31
0.34
0.37
0.40
0 20 40 60 80 100 120 140
Step size [%]
CALA
282
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3.10.4 32MHz Internal Oscillator
Figure 37-240. 32MHz internal oscillator frequency vs. temperature.
DFLL disabled.
Figure 37-241. 32MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
30.5
31.5
32.5
33.5
34.5
35.5
36.5
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [MHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
31.5
31.6
31.7
31.8
31.9
32.0
32.1
32.2
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [MHz]
Temperature [°C]
283
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-242. 32MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
Figure 37-243. 32MHz internal oscillator frequency vs. CALB calibration value.
VCC = 3.0V.
105°C
85°C
25°C
-40°C
0.15
0.18
0.21
0.24
0.27
0.30
0.33
0.36
0.39
0.42
0 20 40 60 80 100 120 140
Step size %
CALA
105°C
85°C
25°C
-40°C
0.50
0.80
1.10
1.40
1.70
2.00
2.30
2.60
2.90
0 8 16 24 32 40 48 56 64
S tep s ize [%]
DFLLR C32MCALB
284
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.3.10.5 32MHz internal oscillator calibrated to 48MHz
Figure 37-244. 48MHz internal oscillator frequency vs. temperature.
DFLL disabled.
Figure 37-245. 48MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
46
47
48
49
50
51
52
53
54
55
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [MHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
47.4
47.5
47.6
47.7
47.8
47.9
48.0
48.1
48.2
48.3
48.4
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [MHz]
Temperature [°C]
285
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-246. 48MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
37.3.11 Two-Wire Interface characteristics
Figure 37-247. SDA hold time vs. Vcc.
105°C
85°C
25°C
40°C
0.12
0.15
0.18
0.21
0.24
0.27
0.30
0.33
0.36
0.39
0.42
0 20 40 60 80 100 120 140
Step size %
CALA
105
85
25
-40
260
265
270
275
280
285
290
295
300
2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Holdtime [ns]
Vcc [V]
Temp [°C]
286
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-248. SDA hold time vs. supply voltage.
37.3.12 PDI characteristics
Figure 37-249. Maximum PDI frequency vs. VCC.
3
2
1
0
50
100
150
200
250
300
350
400
450
500
V
CC
[V]
Hold time [ns]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
105°C
85°C
25°C
-40°C
10
15
20
25
30
35
40
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
fMAX [MHz]
V
CC [V]
287
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.4 ATxmega256A3U
37.4.1 Current consumption
37.4.1.1 Active mode supply current
Figure 37-250. Active supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
Figure 37-251. Active supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
0
75
150
225
300
375
450
525
600
675
750
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
I
CC
[uA]
Frequency [MHz]
3.6 V
3.0 V
2.7 V
1.8 V
1.6 V
0
1500
3000
4500
6000
7500
9000
10500
12000
13500
15000
0 4 8 121620242832
ICC [uA]
Frequency [MHz]
2.2 V
288
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-252. Active mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
Figure 37-253. Active mode supply current vs. VCC.
fSYS = 1MHz external clock.
105°C
85°C
25°C
-40°C
50
75
100
125
150
175
200
225
250
1.6 2.1 2.6 3.1 3.6
ICC [µA]
VCC[V]
105°C
85°C
25°C
-40°C
200
260
320
380
440
500
560
620
680
740
800
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
VCC [V]
289
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-254. Active mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
Figure 37-255. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
105°C
85°C
25°C
- 40°C
450
600
750
900
1050
1200
1350
1500
1650
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
V
CC [V]
105°C
85°C
25°C
-40°C
1500
2000
2500
3000
3500
4000
4500
5000
5500
6000
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
I
CC[µA]
VCC[V ]
290
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-256. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator.
37.4.1.2 Idle mode supply current
Figure 37-257. Idle mode supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
105°C
85°C
25°C
-40°C
8800
9600
10400
11200
12000
12800
13600
14400
15200
2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
I
CC
[µA]
V
CC
[V]
3.3V
3.0V
2.7V
2.2V
1.8V
0
20
40
60
80
100
120
140
160
180
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency [MHz]
I
CC
[µA]
291
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-258. Idle mode supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
Figure 37-259. Idle mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
3.3V
3.0V
2.7V
0
1
2
3
4
5
6
0 4 8 121620242832
Frequency [MHz]
I
CC
[mA]
1.8V
2.2V
105°C
85°C
25°C
-40°C
28
29
30
31
32
33
34
35
36
37
38
39
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
V
CC [V]
292
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-260. Idle mode supply current vs. VCC.
fSYS = 1MHz external clock.
Figure 37-261. Idle mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
105°C
85°C
25°C
- 40°C
65
85
105
125
145
165
185
205
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
V
CC [V]
.
105°C
85°C
25°C
- 40°C
450
600
750
900
1050
1200
1350
1500
1650
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
V
CC [V]
293
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-262. Idle mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
Figure 37-263. Idle mode current vs. VCC.
fSYS = 32MHz internal oscillator.
105°C
85°C
25°C
-40°C
700
900
1100
1300
1500
1700
1900
2100
2300
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
V
CC[V]
105°C
85°C
25°C
-40°C
8800
9600
10400
11200
12000
12800
13600
14400
15200
2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
I
CC
[µA]
V
CC
[V]
294
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.4.1.3 Power-down mode supply current
Figure 37-264. Power-down mode supply current vs. VCC.
All functions disabled.
Figure 37-265. Power-down mode supply current vs. VCC.
Watchdog and sampled BOD enabled.
105°C
85°C
25°C
-40°C
0
1
2
3
4
5
6
7
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
ICC [µA]
VCC
105°C
85°C
35°C
40°C
0
1
2
3
4
5
6
7
8
1.6 2.1 2.6 3.1 3.6
ICC [µA]
VCC [V]
295
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.4.1.4 Power-save mode supply current
Figure 37-266. Power-save mode supply current vs. VCC.
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.
37.4.1.5 Standby mode supply current
Figure 37-267. Standby supply current vs. VCC.
Standby, fSYS =1MHz.
Normal mode
Low-power mode
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
V
CC
[V]
I
CC
[µA]
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
I
CC
[uA]
VCC [V]
105°C
85°C
25°C
-40°C
296
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-268. Standby supply current vs. VCC.
25°C, running from different crystal oscillators.
37.4.2 I/O Pin Characteristics
37.4.2.1 Pull-up
Figure 37-269. I/O pin pull-up resistor current vs. input voltage.
VCC = 1.8V.
16MHz
12MHz
8MHz
2MHz
0.454MHz
150
200
250
300
350
400
450
500
V
CC
[V]
I
CC
[µA]
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
105°C
85°C
25°C
-40°C
0
7
14
21
28
35
42
49
56
63
70
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
IPIN [µA]
V
PIN [V]
297
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-270. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.0V.
Figure 37-271. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.3V.
105°C
85°C
25°C
-40°C
0
13
26
39
52
65
78
91
104
117
130
00.511.522.53
IPIN [µA]
V
PIN [V]
CC
105°C
85°C 25°C
-40°C
0
14
28
42
56
70
84
98
112
126
140
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3
IPIN [µA]
V
PIN [V]
298
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.4.2.2 Output Voltage vs. Sink/Source Current
Figure 37-272. I/O pin output voltage vs. source current.
VCC = 1.8V.
Figure 37-273. I/O pin output voltage vs. source current.
VCC = 3.0V.
105 °C
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-10-9-8-7-6-5-4-3-2-1
V
PIN [V]
IPIN[mA]
105°C 85°C
25°C -40°C
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
-30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0
V
PIN[V]
IPIN[mA]
299
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-274. I/O pin output voltage vs. source current.
VCC = 3.3V.
Figure 37-275. I/O pin output voltage vs. source current.
105°C
85°C
25°C
-40°C
0
0.5
1
1.5
2
2.5
3
3.5
-33 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0
V
PIN [V]
IPIN[mA]
3.6V
3.3V
2.7V
2.2V
1.8V
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0
I
PIN
[mA]
V
PIN
[V]
300
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-276. I/O pin output voltage vs. sink current.
VCC = 1.8V.
Figure 37-277. I/O pin output voltage vs. sink current.
VCC = 3.0V.
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0 2 4 6 8 101214161820
VPIN
[V]
IPIN [mA]
40°C
85°C
25°C
105°C
105°C
85°C
25°C
-40°C
0
0.2
0.4
0.6
0.8
1
1.2
0 3 6 9 12 15 18 21 24 27 30 33
V
PIN[V
IPIN [mA]
301
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-278. I/O pin output voltage vs. sink current.
VCC = 3.3V.
Figure 37-279. I/O pin output voltage vs. sink current.
105°C
85°C
25°C
-40°C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 3 6 9 12 15 18 21 24 27 30 33
V
PIN
[V
I
PIN
[mA]
3.6V
3.3V
2.7V
2.2V
0
0.3
0.6
0.9
1.2
1.5
0 5 10 15 20 25
I
PIN
[mA]
V
PIN
[V]
1.8V
302
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.4.2.3 Thresholds and Hysteresis
Figure 37-280. I/O pin input threshold voltage vs. VCC.
T = 25°C.
Figure 37-281. I/O pin input threshold voltage vs. VCC.
VIH I/O pin read as “1”.
VIL
VIH
0.50
0.65
0.80
0.95
1.10
1.25
1.40
1.55
1.70
1.85
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
CC
[V]
VThreshold
[V]
105°C
85°C
25°C
-40°C
0.7
0.8
0.9
1
1.1
1,2
1.3
1.4
1.5
1.6
1.7
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vthre s hold [V]
V
CC
[V]
303
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-282. I/O pin input threshold voltage vs. VCC.
VIL I/O pin read as “0”.
Figure 37-283. I/O pin input hysteresis vs. VCC.
105°C
85°C
25°C
-40°C
0.5
0.7
0.9
1,1
1.3
1.5
1.7
1.6 .,8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
thre s hold
[V]
V
CC
[V]
105°C
85°C
25°C
-40°C
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vthres hold [V]
VCC[V ]
304
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.4.3 ADC Characteristics
Figure 37-284. INL error vs. external VREF.
T = 25
°
C, VCC = 3.6V, external reference.
Figure 37-285. INL error vs. sample rate.
T = 25
°
C, VCC = 3.6V, VREF = 3.0V external.
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
VREF [V]
INL [LSB]
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
ADC sample rate [ksps]
INL [LSB]
500 650 800 950 1100 1250 1400 1550 1700 1850 2000
305
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-286. INL error vs. input code.
Figure 37-287. DNL error vs. external VREF.
T = 25
°
C, VCC = 3.6V, external reference.
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
INL [LSB]
Single-ended unsigned mode
Single-endedsigned mode
Differential mode
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
V
REF
[V]
DNL [LSB]
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
306
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-288. DNL error vs. sample rate.
T = 25
°
C, VCC = 3.6V, VREF = 3.0V external.
Figure 37-289. DNL error vs. input code.
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
Sampling speed [MS/s]
DNL [LSB]
0.50 0.65 0.80 0.95 1.10 1.25 1.40 1.55 1.70 1.85 2.00
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
0 512 1024 1536 2048 2560 3072 3584 4096
ADC Input Code
DNL [LSB]
307
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-290. Gain error vs. VREF.
T = 25
°
C, VCC = 3.6V, ADC sampling speed = 500ksps.
Figure 37-291. Gain error vs. VCC.
T = 25
°
C, VREF = external 1.0V, ADC sampling speed = 500ksps.
Single-ended unsigned mode
Single-ended signed mode
Differential mode
-10
-8
-6
-4
-2
0
2
4
V
REF
[V]
Gain error [mV]
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Single-ended unsigned mode
Single-ended signed mode
Differential mode
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
V
CC
[V]
Gain Error [mV]
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
308
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-292. Offset error vs. VREF.
T = 25
°
C, VCC = 3.6V, ADC sampling speed = 500ksps.
Figure 37-293. Gain error vs. temperature.
VCC = 3.0V, VREF = external 2.0V.
Differential mode
-1.6
-1.5
-1.4
-1.3
-1.2
-1.1
VREF
[V]
Offset [mV]
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Single Ended
Unsigned
Single Ended Signed
Differential Signed
0
1
2
3
4
5
6
7
8
9
-60 -40 -20 0 20 40 60 80 100 120 140
Gain Error [mV]
Temperature [°C ]
309
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-294. Offset error vs. VCC.
T = 25
°
C, VREF = external 1.0V, ADC sampling speed = 500ksps.
Figure 37-295. Noise vs. VREF.
T = 25
°
C, VCC = 3.6V, ADC sampling speed = 500ksps.
Differential mode
-1.2
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
V
CC
[V]
Offset error [mV]
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.40
0.55
0.70
0.85
1.00
1.15
1.30
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VREF
[V]
Noise [mV RMS]
310
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-296. Noise vs. VCC.
T = 25
°
C, VREF = external 1.0V, ADC sampling speed = 500ksps.
37.4.4 DAC Characteristics
Figure 37-297. DAC INL error vs. VREF.
VCC = 3.6V.
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
CC
[V]
Noise [mV RMS]
105°C
85°C
25°C
-40°C
0
0.5
1
1.5
2
2.5
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
DAC INL [LSB]
V
REF
[V]
311
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-298. DNL error vs. VREF.
T = 25
°
C, VCC = 3.6V.
Figure 37-299. DAC noise vs. temperature.
VCC = 3.0V, VREF = 2.4V.
105°C
85°C
25°C
-40°C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
DAC DNL [LSB]
V
REF
[V]
DAC_Linearity
0.1
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.2
-40 -20 0 20 40 60 80 100 120 140
Noise[mV R MS]
Temperature [°C]
312
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.4.5 Analog Comparator Characteristics
Figure 37-300. Analog comparator hysteresis vs. VCC
High-speed, small hysteresis.
Figure 37-301. Analog comparator hysteresis vs. VCC
Low power, small hysteresis.
40°C
25°C
85°C
105°C
4
5
6
7
8
9
10
11
12
13
14
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VHYST [mV]
V
CC [V]
40°C
25°C
85°C
105°C
12
14
16
18
20
22
24
26
28
30
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VHYST [mV]
V
CC [V]
313
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-302. Analog comparator hysteresis vs. VCC.
High-speed mode, large hysteresis.
Figure 37-303. Analog comparator hysteresis vs. VCC.
Low power, large hysteresis.
40°C
25°C
85°C
105°C
14
16
18
20
22
24
26
28
30
32
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VHYST [mV]
V
CC[V]
40°C
25°C
85°C
105°C
32
36
40
44
48
52
56
60
64
68
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST [mV]
V
CC[V]
314
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-304. Analog comparator current source vs. calibration value.
Temperature = 25°C.
Figure 37-305. Analog comparator current source vs. calibration value.
VCC = 3.0V.
3.3V
3.0V
2.7V
2.2V
1.8V
2
3
4
5
6
7
8
0123456789101112131415
CALIB[3...0]
I
CURRENT SOURCE
[µA]
85°C
25°C
-40°C
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0123456789101112131415
CALIB[3..0]
I [µA]
315
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-306. Voltage scaler INL vs. SCALEFAC.
T = 25
°
C, VCC = 3.0V.
37.4.6 Internal 1.0V reference Characteristics
Figure 37-307. ADC/DAC Internal 1.0V reference vs. temperature
25°C
-0.100
-0.075
-0.050
-0.025
0
0.025
0.050
0.075
0.100
0 10203040506070
SCALEFAC
INL [LSB]
3.6 V
3.0 V
2.7 V
2.2 V
1.6 V
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
1.006
-40 -25 -10 5 20 35 50 65 80 95 110
Bandgap Voltage [V]
Temperature [°C]
316
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.4.7 BOD Characteristics
Figure 37-308. BOD thresholds vs. temperature.
BOD level = 1.6V.
Figure 37-309. BOD thresholds vs. temperature.
BOD level = 3.0V.
Rising Vc
Falling Vc
1.618
1.62
1.622
1.624
1.626
1.628
1.63
1.632
-40 -25 -10 5 20 35 50 65 80 95 110
V
BOT[V]
T [°C]
Rising Vc
Falling Vc
3.01
3.02
3.03
3.04
3.05
3.06
3.07
3.08
-40 -25 -10 5 20 35 50 65 80 95 110
V
BOT[V]
Temperature [°C]
317
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.4.8 External Reset Characteristics
Figure 37-310. Minimum Reset pin pulse width vs. VCC.
Figure 37-311. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 1.8V.
105°C
85°C
25°C
40°C
92
97
102
107
112
117
122
127
132
137
142
147
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
tRST[n s ]
V
CC [V
105 °C
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
70
80
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
IRESET[µA]
V
RESET[V]
V
CC= 1.8 V
318
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-312. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.0V.
Figure 37-313. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.3V.
105°C
85°C
25°C
-40°C
0
13
26
39
52
65
78
91
104
117
130
0 0.5 1 1.5 2 2.5 3
IRESET [µA]
V
RESET [V]
105°C
-40°C
0
14
28
42
56
70
84
98
112
126
140
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3
IRESET[µA]
V
RESET [V]
85°C
25°C
319
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-314. Reset pin input threshold voltage vs. VCC.
VIH - Reset pin read as “1”.
Figure 37-315. Reset pin input threshold voltage vs. VCC.
VIL - Reset pin read as “0”.
105°C
85°C
25°C
-40°C
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
thre s hold [V]
V
CC[V]
105°C
85°C
25°C
-40°C
0.4
0.6
0.8
1
1,2
1.4
1.6
1.8
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
thre s hol d[V]
V
CC [V]
320
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.4.9 Power-on Reset Characteristics
Figure 37-316. Power-on reset current consumption vs. VCC.
BOD level = 3.0V, enabled in continuous mode.
105°C
85°C
25°C
-40°C
0
100
200
300
400
500
600
700
800
900
1000
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
ICC [µA]
VCC[V]
321
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
37.4.10 Oscillator Characteristics
37.4.10.1 Ultra Low-Power internal oscillator
Figure 37-317. Ultra Low-Power internal oscillator frequency vs. temperature.
37.4.10.2 32.768kHz Internal Oscillator
Figure 37-318. 32.768kHz internal oscillator frequency vs. temperature.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
27.5
28
28.5
29
29.5
30
30.5
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [kHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.36
32.42
32.48
32.54
32.60
32.66
32.72
32.78
32.84
32.90
32.96
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [kHz]
Temperature [°C]
322
XMEGA A3U [DATASHEET]
Atmel-8386E-AVR-XMEGA A3U-Datasheet_09/2014
Figure 37-319. 32.768kHz internal oscillator frequency vs. calibration value.
VCC = 3.0V, T = 25°C.
37.4.10.3 2MHz Internal Oscillator
Figure 37-320. 2MHz internal oscillator frequency vs. temperature.
DFLL disabled.
20
25
30
35
40
45
50
0 50 100 150 200 250 300
RC32KCAL[7..0]
Frequency [kHz]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
1.95
1.98
2.01
2.04
2.07
2.1
2.13
2.16
2.19
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [MHz]
Temperature [°C]
323
XMEGA A3U [DATASHEET]
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Figure 37-321. 2MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
Figure 37-322. 2MHz internal oscillator CALA calibration step size.
VCC = 3V.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
1.975
1.980
1.985
1.990
1.995
2.000
2.005
2.010
2.015
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [MHz]
Temperature [°C]
105°C
85°C
25°C
-40°C
0.13
0.16
0.19
0.22
0.25
0.28
0.31
0.34
0.37
0.40
0 20 40 60 80 100 120 140
Step size [%]
CALA
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37.4.10.4 32MHz Internal Oscillator
Figure 37-323. 32MHz internal oscillator frequency vs. temperature.
DFLL disabled.
Figure 37-324. 32MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
30.5
31.5
32.5
33.5
34.5
35.5
36.5
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [MHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
31.5
31.6
31.7
31.8
31.9
32.0
32.1
32.2
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [MHz]
Temperature [°C]
325
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Figure 37-325. 32MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
Figure 37-326. 32MHz internal oscillator frequency vs. CALB calibration value.
VCC = 3.0V.
105°C
85°C
25°C
-40°C
0.15
0.18
0.21
0.24
0.27
0.30
0.33
0.36
0.39
0.42
0 20 40 60 80 100 120 140
Step size %
CALA
105°C
85°C
25°C
-40°C
0.50
0.80
1.10
1.40
1.70
2.00
2.30
2.60
2.90
0 8 16 24 32 40 48 56 64
S tep s ize [%]
DFLLR C32MCALB
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37.4.10.5 32MHz internal oscillator calibrated to 48MHz
Figure 37-327. 48MHz internal oscillator frequency vs. temperature.
DFLL disabled.
Figure 37-328. 48MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
46
47
48
49
50
51
52
53
54
55
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [MHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
47.4
47.5
47.6
47.7
47.8
47.9
48.0
48.1
48.2
48.3
48.4
-40 -25 -10 5 20 35 50 65 80 95 110
Frequency [MHz]
Temperature [°C]
327
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Figure 37-329. 48MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
37.4.11 Two-Wire Interface characteristics
Figure 37-330. SDA hold time vs. VCC.
105°C
85°C
25°C
40°C
0.12
0.15
0.18
0.21
0.24
0.27
0.30
0.33
0.36
0.39
0.42
0 20 40 60 80 100 120 140
Step size %
CALA
105
85
25
-40
260
265
270
275
280
285
290
295
300
2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Holdtime [ns]
Vcc [V]
Temp [°C]
328
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Figure 37-331. SDA hold time vs. supply voltage.
37.4.12 PDI characteristics
Figure 37-332. Maximum PDI frequency vs. VCC.
3
2
1
0
50
100
150
200
250
300
350
400
450
500
V
CC
[V]
Hold time [ns]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
105°C
85°C
25°C
-40°C
10
15
20
25
30
35
40
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
fMAX [MHz]
V
CC [V]
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38. Errata
38.1 ATxmega64A3U, ATxmega128A3U, ATxmega192A3U, ATxmega256A3U
38.1.1 Rev. G
zThe DAC Channel 1 has not been calibrated in the Xmega devices released prior to April 2012.
zAWeX fault protection restore is not done correct in Pattern Generation Mode.
1. AWeX fault protection restore is not done correct in Pattern Generation Mode
When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN
is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode
(CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation
Mode (PGM), OUTOVEN should instead have been restored according to the DTLSBUF register.
Problem fix/Workaround
Problem fix/Workaround
For CWCM no workaround is required.
For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set cor-
rect OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable
the correct outputs again.
For PGM in cycle-by-cycle mode there is no workaround.
38.1.2 Rev. A-F
Not sampled.
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39. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision
in this section are referring to the document revision.
39.1 8386E – 09/2014
39.2 8386D – 03/2014
39.3 8386C – 02/2013
1. Updated “Ordering Information” on page 3:
Added Ordering information for ATxmega64A3U/128a3U/192A3U/256A3U @ 105°C
Updated “Electrical Characteristics” on page 73 and onwards concerning “Power Consumption” and
“Endurance and data retention” for ATxmega64A3U/128a3U/192A3U/256A3U @ 105°C
2. Updated “Typical Characteristics” on page 161 and onwards for
ATxmega64A3U/128a3U/192A3U/256A3U @ 105°C
3. Corrected values for Active Current Consumption for 192A3U in Table 36-68 on page 119 and for
256A3U in Table 36-100 on page 141.
4Updated plots for Active supply current for 192A3U in Figure 37-167 on page 245 and Figure 37-168
on page 245
5Updated plots for Active supply current for 256A3U in Figure 37-251 on page 287 and Figure 37-252
on page 288
6. Corrected values for Bootloader start and end address for 128A3U in Table 7-1 on page 14.
7. Changed Vcc to AVcc in Section 28. “ADC – 12-bit Analog to Digital Converter” on page 52and in
Section 30.1 “Features” on page 56.
8. Changed unit notation for parameter tSU;DAT to ns in Table 36-32 on page 93, Table 36-64 on page 115,
Table 36-96 on page 137 and Table 36-128 on page 159.
9. Added information in Section 38. “Errata” on page 329 on missing calibration of DAC channel 1.
1. Updated “Port A - alternate functions.” on page 61:
Removed ACDP POS from the Table 32-1 on page 61
2. Updated “Port B - alternate functions.” on page 61:
ACDB POS changed to ADCB POS/GAINPOS in the Table 32-2 on page 61
1. Updated the datasheet using the Atmel new datasheet template.
2. Added column for TWI with external driver interface for Port C and E in “Alternate Pin Functions” on page 61.
3. Removed TWID from Port D and updated pin numbers in“Alternate Pin Functions” on page 61.
4. Added TOSC and removed AWEXE to/from Port E in “Alternate Pin Functions” on page 61.
5. Added notes to table for Port D and E in “Alternate Pin Functions” on page 61.
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39.4 8386B – 12/2011
39.5 8386A – 07/2011
6. Updated pin numbers for Port D and F in “Alternate Pin Functions” on page 61.
7. Removed AWEXE from the peripheral module address map in Table 33-1 on page 64.
8. Updated the “Electrical Characteristics” on page 73 by separating the characteristics for each device.
9.
Updated DAC clock and timing characteristics for all memory:
ATxmega64A3U: Table 36-13 on page 81.
ATxmega128A3U: Table 36-45 on page 103.
ATxmega192A3U: Table 36-77 on page 125.
ATxmega256A3U: Table 36-109 on page 147.
10.
Added ESR parameter to External 16MHz crystal oscillator and XOSC characteristics:
ATxmega64A3U: Table 36-29 on page 88.
ATxmega128A3U: Table 36-61 on page 110
ATxmega192A3U: Table 36-93 on page 132
ATxmega256A3U: Table 36-125 on page 154
11. Updated the “Typical Characteristics” on page 161 by separating the characteristics for each device.
12. Added “Electrical Characteristics” and “Typical Characteristics” for both ATxmega64A3U and ATxmega128A3U.
1. Updated the Figure 2-1 on page 5. JTAG written in the white color.
2. Updated “Overview” on page 13.
3. Updated Figure 30-1 on page 57.
4. Updated “Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses
via the external RAM interface.” on page 70.
5. Updated “Electrical Characteristics” on page 73.
6. Updated “Typical Characteristics” on page 161.
7. Several changes in “Typical Characteristics”
1. Initial revision.
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Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5. Capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6. AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.3 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.4 ALU - Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.5 Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.7 Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.8 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.3 Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.4 Fuses and Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.5 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.6 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.7 I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.8 Data Memory and Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.9 Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.10 Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.11 JTAG Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.12 I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.13 Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8. DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10. System Clock and Clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.3 Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
12. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12.3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12.4 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
13. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
14. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . . . . . . . . . . . . . . . 30
14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14.3 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
15. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
15.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
15.3 Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
15.4 Input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
15.5 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
16. TC0/1 – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
16.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17. TC2 - Timer/Counter Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
17.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
18. AWeX – Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
18.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
19. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
19.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
20. RTC – 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
20.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
21. USB – Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
21.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
22. TWI – Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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22.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
23.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
24. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
24.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
25. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
25.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
26. AES and DES Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
26.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
26.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
27. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
27.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
28. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
28.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
28.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
29. DAC – 12-bit Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
29.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
29.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
30. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
30.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
30.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
31. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
31.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
31.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
32. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
32.1 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
32.2 Alternate Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
33. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
34. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
35. Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
35.1 64A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
35.2 64M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
36. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
36.1 ATxmega64A3U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
36.2 ATxmega128A3U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
36.3 ATxmega192A3U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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36.4 ATxmega256A3U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
37. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
37.1 ATxmega64A3U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
37.2 ATxmega128A3U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
37.3 ATxmega192A3U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
37.4 ATxmega256A3U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
38. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
38.1 ATxmega64A3U, ATxmega128A3U, ATxmega192A3U, ATxmega256A3U. . . . . . . . . . . . . . . . . . 329
39. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
39.1 8386E – 07/2014. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
39.2 8386D – 03/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
39.3 8386C – 02/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
39.4 8386B – 12/2011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
39.5 8386A – 07/2011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
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Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com
© 2014 Atmel Corporation. / Rev.: Atmel-8386E-AVR-ATxmega64A3U-128A3U-192A3U-256A3U-Datasheet_09/2014.
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