LM21212-2 www.ti.com SNVS715A - MARCH 2011 - REVISED MARCH 2013 12A High Efficiency Synchronous Buck Regulator with Adjustable Switching Frequency Check for Samples: LM21212-2 FEATURES DESCRIPTION * The LM21212-2 is a monolithic synchronous buck regulator that is capable of delivering up to 12A of continuous output current while producing an output voltage down to 0.6V with outstanding efficiency. The device is optimized to work over an input voltage range of 2.95V to 5.5V, making it suited for a wide variety of low voltage systems. The voltage mode control loop provides high noise immunity, narrow duty cycle capability and can be compensated to be stable with any type of output capacitance, providing maximum flexibility and ease of use. 1 2 * * * * * * * * * * Integrated 7.0 m High Side and 4.3 m Low Side FET Switches 300 kHz to 1.55 MHz Resistor-Adjustable Frequency Adjustable Output Voltage from 0.6V to VIN (100% Duty Cycle Capable), 1% Reference Input Voltage Range 2.95V to 5.5V Startup Into Pre-Biased Loads Output Voltage Tracking Capability Wide Bandwidth Voltage Loop Error Amplifier Adjustable Soft-Start With External Capacitor Precision Enable Pin With Hysteresis Integrated OVP, OCP, OTP, UVLO and PowerGood Thermally Enhanced HTSSOP-20 Exposed Pad Package The LM21212-2 features internal over voltage protection (OVP) and over-current protection (OCP) for increased system reliability. A precision enable pin and integrated UVLO allow turn-on of the device to be tightly controlled and sequenced. Startup inrush currents are limited by both an internally fixed and externally adjustable soft-start circuit. Fault detection and supply sequencing are possible with the integrated power good circuit. APPLICATIONS * * * The LM21212-2 is designed to work well in multi-rail power supply architectures. The output voltage of the device can be configured to track an external voltage rail using the SS/TRK pin. The switching frequency can be programmed between 300 kHz and 1.55 MHz with an external resistor. Broadband, Networking and Wireless Communications High-Performance FPGAs, ASICs and Microprocessors Simple to Design, High Efficiency Point of Load Regulation from a 5V or 3.3V Bus If the output is pre-biased at startup, it will not sink current, allowing the output to smoothly rise past the pre-biased voltage. The regulator is offered in a 20pin HTSSOP package with an exposed pad that can be soldered to the PCB, eliminating the need for bulky heatsinks. SIMPLIFIED APPLICATION CIRCUIT HTSSOP-20 5,6,7 VIN CIN LOUT PVIN SW 11-16 VOUT COUT RF 4 CC3 AVIN RFB1 CF 3 LM21212-2 FB EN optional optional CSS COMP 19 18 2 SS/ TRK CC1 RC1 RFB2 CC2 17 1 FADJ RADJ RC2 PGOOD PGND AGND 8,9,10 20 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2013, Texas Instruments Incorporated LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com CONNECTION DIAGRAM Top View 20 AGND FADJ 1 SS/TRK 2 19 FB 18 COMP EN 3 AVIN 4 17 PGOOD PVIN 5 16 SW PVIN 6 EP 15 SW PVIN 7 14 SW PGND 8 13 SW PGND 9 12 SW PGND 10 11 SW Figure 1. Top View HTSSOP-20 Package PIN DESCRIPTIONS 2 Pins Name Description 1 FADJ Frequency Adjust pin. The switching frequency can be set to a predetermined rate by connecting a resistor between FADJ and AGND. 2 SS/TRK 3 EN Active high enable input for the device. If not used, the EN pin can be left open, which will go high due to an internal current source. 4 AVIN Analog input voltage supply that generates the internal bias. It is recommended to connect PVIN to AVIN through a low pass RC filter to minimize the influence of input rail ripple and noise on the analog control circuitry. 5,6,7 PVIN Input voltage to the power switches inside the device. These pins should be connected together at the device. A low ESR input capacitance should be located as close as possible to these pins. 8,9,10 PGND Power ground pins for the internal power switches. 11-16 SW 17 PGOOD 18 COMP 19 FB 20 AGND EP Exposed Pad Soft-start control pin. An internal 2 A current source charges an external capacitor connected between this pin and AGND to set the output voltage ramp rate during startup. This pin can also be used to configure the tracking feature. Switch node pins. These pins should be tied together locally and connected to the filter inductor. Open-drain power good indicator. Compensation pin is connected to the output of the voltage loop error amplifier. Feedback pin is connected to the inverting input of the voltage loop error amplifier. Quiet analog ground for the internal reference and bias circuitry. Exposed metal pad on the underside of the package with an electrical and thermal connection to PGND. It is recommended to connect this pad to the PC board ground plane in order to improve thermal dissipation. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 LM21212-2 www.ti.com SNVS715A - MARCH 2011 - REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) PVIN (3), AVIN to GND -0.3V to +6V SW (4), EN, FB, COMP, PGOOD, SS/TRK, FADJ to GND -0.3V to PVIN + 0.3V -65C to 150C Storage Temperature Soldering Specification for TSSOP Pb-Free Infrared or Convection (30 sec) ESD Rating, Human Body Model (1) (2) (3) (4) (5) 260C (5) 2kV Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The PVIN pin can tolerate transient voltages up to 6.5 V for a period of up to 6ns. These transients can occur during the normal operation of the device. The SW pin can tolerate transient voltages up to 9.0 V for a period of up to 6ns, and -1.0V for a duration of 4ns. These transients can occur during the normal operation of the device. The human body model is a 100 pF capacitor discharged through a 1.5 k resistor to each pin. OPERATING RATINGS PVIN, AVIN to GND +2.95V to +5.5V -40C to +125C Junction Temperature JA (1) (1) 24C/W Thermal measurements were performed on a 2x2 inch, 4 layer, 2 oz. copper outer layer, 1 oz.copper inner layer board with twelve 8 mil. vias underneath the EP of the device and an additional sixteen 8 mil. vias under the unexposed package. ELECTRICAL CHARACTERISTICS Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5V. Limits in standard type are for TJ = 25C only, limits in bold face type apply over the junction temperature (TJ) range of -40C to +125C. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Symbol Parameter Conditions Min Feedback pin voltage VIN = 2.95V to 5.5V -1% Typ Max 0.6 1% Units SYSTEM VFB V VOUT/IOUT Load Regulation 0.02 %VOUT/ A VOUT/VIN 0.1 %VOUT/ V Line Regulation RDSON HS High Side Switch On Resistance ISW = 12A RDSON LS Low Side Switch On Resistance ISW = 12A ICLR HS Rising Switch Current Limit ICLF LS Falling Switch Current Limit VZX Zero Cross Voltage 15 9.0 m 4.3 6.0 m 17 19 A 12 -8 IQ Operating Quiescent Current ISD Shutdown Quiescent Current VEN = 0V VUVLO AVIN Under Voltage Lockout AVIN Rising VUVLOHYS AVIN Under Voltage Lockout Hysteresis VTRACKOS SS/TRACK PIN accuracy (VSS - VFB) ISS 7.0 0 < VTRACK < 0.55V Soft-Start Pin Source Current CSS = 0 A 3 12 mV 1.5 3.0 mA 50 70 A 2.45 2.70 2.95 V 140 200 280 mV -10 6 20 mV 1.3 1.9 2.5 A tINTSS Internal Soft-Start Ramp to Vref 350 500 675 s tRESETSS Device Reset to Soft-Start Ramp 50 110 200 s FADJ Frequency Range 300 1550 kHz OSCILLATOR fRNG Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 3 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5V. Limits in standard type are for TJ = 25C only, limits in bold face type apply over the junction temperature (TJ) range of -40C to +125C. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Symbol fSW Parameter Conditions Min Typ Max Units Switching Frequency RADJ = 22.6k 1400 1550 1700 kHz RADJ = 95.3k 465 500 535 tHSBLANK HS OCP Blanking Time Rising edge of SW to ICLR comparison 55 ns tLSBLANK LS OCP Blanking Time Falling edge of SW to ICLF comparison 400 ns tZXBLANK Zero Cross Blanking Time Falling edge of SW to VZX comparison 120 ns Minimum HS on-time 140 ns PWM Ramp p-p Voltage 0.8 V 95 dBV/V 11 MHz tMINON Vramp ERROR AMPLIFIER VOL Error Amplifier Open Loop Voltage Gain GBW Error Amplifier Gain-Bandwidth Product IFB Feedback Pin Bias Current ICOMP = -65A to 1mA 1 nA ICOMPSRC COMP Output Source Current VFB = 0.6V 1 mA ICOMPSINK COMP Output Sink Current 65 A POWERGOOD VOVP VOVPHYS VUVP VUVPHYS Over Voltage Protection Rising Threshold VFB Rising Over Voltage Protection Hysteresis VFB Falling Under Voltage Protection Rising Threshold VFB Rising Under Voltage Protection Hysteresis VFB Falling 105 112.5 120 2 82 90 %VFB %VFB 97 %VFB 2.5 %VFB tPGDGL PGOOD Deglitch Low (OVP/UVP Condition Duration to PGOOD Falling) 15 s tPGDGH PGOOD Deglitch High (minimum low pulse) 12 s RPGOOD PGOOD Pull-down Resistance IPGOODLEAK PGOOD Leakage Current 10 VPGOOD = 5V 20 40 1 nA LOGIC VIHSYNC SYNC Pin Logic High VILSYNC SYNC Pin Logic Low VIHENR EN Pin Rising Threshold VENHYS EN Pin Hysteresis IEN EN Pin Pullup Current 2.0 VEN Rising VEN = 0V V 0.8 V 1.20 1.35 1.45 V 50 110 180 mV 2 A 165 C 10 C THERMAL SHUTDOWN TTHERMSD Thermal Shutdown TTHERMSDHYS Thermal Shutdown Hysteresis 4 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 LM21212-2 www.ti.com SNVS715A - MARCH 2011 - REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56H (1.8m RDCR), CSS = 33nF, fSW = 500 kHz (RADJ= 95.3k), TA = 25C for efficiency curves, loop gain plots and waveforms, and TJ = 25C for all others. Efficiency 96 Efficiency 100 FSW = 500kHz FSW = 1MHz FSW = 1.5MHz 94 98 96 EFFICIENCY (%) 92 EFFICIENCY (%) VOUT = 3.3 VOUT = 1.2 90 88 86 94 92 90 88 86 84 84 82 82 80 80 0 2 4 6 8 10 OUTPUT CURRENT(A) 12 0 Figure 2. Load Regulation 0.04 0.03 u OUTPUT VOLTAGE (%) 98 EFFICIENCY (%) 12 Figure 3. Efficiency (VOUT = 2.5 V, fSW= 300 kHz , Inductor P/N SER2010102MLD) 100 96 94 92 VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V 90 0 2 4 6 8 10 OUTPUT CURRENT(A) 0.02 0.01 0.00 -0.01 -0.02 VIN = 3.3V VIN = 5.0V -0.03 12 -0.04 0 Figure 4. 0.10 2 4 6 8 10 OUTPUT CURRENT (A) 12 Figure 5. Line Regulation Non-Switching IQTOTAL vs. VIN 1.5 0.08 0.06 1.4 0.04 IPVIN+ IAVIN(mA) u OUTPUT VOLTAGE (%) 2 4 6 8 10 OUTPUT CURRENT(A) 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 3.0 1.2 1.1 IOUT = 0A IOUT = 12A 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 1.3 5.5 1.0 3.0 Figure 6. 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 Figure 7. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 5 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56H (1.8m RDCR), CSS = 33nF, fSW = 500 kHz (RADJ= 95.3k), TA = 25C for efficiency curves, loop gain plots and waveforms, and TJ = 25C for all others. Non-Switching IAVIN and IPVIN vs. Temperature IAVIN IPVIN 0.602 0.172 1.14 0.164 1.11 0.156 1.08 0.148 1.05 0.140 1.02 0.132 0.99 0.124 0.96 0.116 0.93 0.108 0.601 VFB(V) 0.600 0.599 0.598 0.100 0.90 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) Figure 8. Figure 9. Enable Threshold and Hysteresis vs. Temperature V IHENR V ENHYS 2.80 V UVLO V UVLOHYS 300 2.78 144 2.76 270 1.35 136 2.74 255 1.34 128 2.72 240 1.33 120 2.70 225 1.32 112 2.68 210 1.31 104 2.66 195 1.30 96 2.64 180 1.29 88 2.62 165 1.28 80 2.60 150 VUVLO(V) 152 1.36 VENHYS(V) VIHENR(V) 1.37 UVLO Threshold and Hysteresis vs. Temperature 160 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) 285 VUVLOHYS(mV) IAVIN(mA) 1.17 VFB vs. Temperature 0.180 IPVIN(mA) 1.20 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) Figure 10. Figure 11. Enable Low Current vs. Temperature OVP/UVP Threshold vs. Temperature 58 0.68 56 0.66 54 VOVP,VUVP(V) SHUTDOWN CURRENT ISD(A) 60 52 50 48 46 44 42 0.64 0.62 0.60 0.58 0.57 0.54 40 0.52 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE(C) 0.50 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) Figure 12. 6 VUVP VOVP Figure 13. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 LM21212-2 www.ti.com SNVS715A - MARCH 2011 - REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56H (1.8m RDCR), CSS = 33nF, fSW = 500 kHz (RADJ= 95.3k), TA = 25C for efficiency curves, loop gain plots and waveforms, and TJ = 25C for all others. Minimum On-Time vs. Temperature FET Resistance vs. Temperature 160 10 9 152 148 LOW SIDE HIGH SIDE 8 144 RDSON(m ) MINIMUM ON-TIME (nS) 156 140 136 132 128 7 6 5 4 124 3 120 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE(C) 2 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) Figure 14. Figure 15. Peak Current Limit vs. Temperature 17.5 CURRENT LIMIT ICLR(A) 17.4 17.3 17.2 17.1 17.0 16.9 16.8 16.7 16.6 16.5 -40 -20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (C) Figure 16. Load Transient Response (fSW = 650 kHz) Output Voltage Ripple VOUT (50 mV/Div) VOUT (10 mV/Div) IOUT (5A/Div) 2 s/DIV Figure 18. 100 s/DIV Figure 17. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 7 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56H (1.8m RDCR), CSS = 33nF, fSW = 500 kHz (RADJ= 95.3k), TA = 25C for efficiency curves, loop gain plots and waveforms, and TJ = 25C for all others. Startup with Prebiased Output Startup with SS/TRK Open Circuit VOUT (500 mV/Div) VOUT (500 mV/Div) VPGOOD (5V/Div) VPGOOD (5V/Div) VENABLE (5V/Div) VENABLE (5V/Div) IOUT (10A/Div) 200 s/DIV 2 ms/DIV Figure 19. Figure 20. Startup with applied Track Signal Output Over-Current Condition VOUT (500 mV/Div) VPGOOD (5V/Div) VTRACK (500 mV/Div) VOUT (1V/Div) VPGOOD (5V/Div) IOUT (10A/Div) IL (10A/Div) 200 ms/DIV 10 s/DIV Figure 22. Figure 21. 8 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 LM21212-2 www.ti.com SNVS715A - MARCH 2011 - REVISED MARCH 2013 BLOCK DIAGRAM Ilimit high FADJ VREF AVIN PVIN Over temp + - PVIN UVLO 2.7V + - SD OR Driver Precision enable AVIN 1.35V + - EN Control Logic PWM comparator AVIN OSC RAMP + - Zero-cross + - PWM SW INT SS PVIN + SS/TRK 0.6V EA Driver FB OVP COMP 0.68V 0.54V + - Ilimit low OR Powerbad + - PGND UVP AGND PGOOD OR Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 9 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com OPERATION DESCRIPTION GENERAL The LM21212-2 switching regulator features all of the functions necessary to implement an efficient low voltage buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 12A of continuous output current. The regulator utilizes voltage mode control with trailing edge modulation to optimize stability and transient response over the entire output voltage range. The device can operate at high switching frequency allowing use of a small inductor while still achieving high efficiency. The precision internal voltage reference allows the output to be set as low as 0.6V. Fault protection features include: current limiting, thermal shutdown, over voltage protection, and shutdown capability. The device is available in the HTSSOP-20 package featuring an exposed pad to aid thermal dissipation. The LM21212-2 can be used in numerous applications to efficiently step-down from a 5V or 3.3V bus. PRECISION ENABLE The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.35V (typical). The EN pin has 110 mV of hysteresis and will disable the output when the enable voltage falls below 1.24V (typical). If the EN pin is not used, it can be left open, and will be pulled high by an internal 2 A current source. Since the enable pin has a precise turn-on threshold it can be used along with an external resistor divider network from VIN to configure the device to turn-on at a precise input voltage. UVLO The LM21212-2 has a built-in under-voltage lockout protection circuit that keeps the device from switching until the input voltage reaches 2.7V (typical). The UVLO threshold has 200 mV of hysteresis that keeps the device from responding to power-on glitches during start up. If desired the turn-on point of the supply can be changed by using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 27 in the design guide. CURRENT LIMIT The LM21212-2 has current limit protection to avoid dangerous current levels on the power FETs and inductor. A current limit condition is met when the current through the high side FET exceeds the rising current limit level (ICLR). The control circuitry will respond to this event by turning off the high side FET and turning on the low side FET. This forces a negative voltage on the inductor, thereby causing the inductor current to decrease. The high side FET will not conduct again until the lower current limit level (ICLF) is sensed on the low side FET. At this point, the device will resume normal switching. A current limit condition will cause the internal soft-start voltage to ramp downward. After the internal soft-start ramps below the Feedback (FB) pin voltage, (nominally 0.6 V), FB will begin to ramp downward, as well. This voltage foldback will limit the power consumption in the device, thereby protecting the device from continuously supplying power to the load under a condition that does not fall within the device SOA. After the current limit condition is cleared, the internal soft-start voltage will ramp up again. Figure 23 shows current limit behavior with VSS, VFB, VOUT and VSW. SHORT-CIRCUIT PROTECTION In the unfortunate event that the output is shorted with a low impedance to ground, the LM21212-2 will limit the current into the short by resetting the device. A short-circuit condition is sensed by a current-limit condition coinciding with a voltage on the FB pin that is lower than 100 mV. When this condition occurs, the device will begin its reset sequence, turning off both power FETs and discharging the soft-start capacitor after tRESETSS (nominally 110 s). The device will then attempt to restart. If the short-circuit condition still exists, it will reset again, and repeat until the short-circuit is cleared. The reset prevents excess current flowing through the FETs in a highly inefficient manner, potentially causing thermal damage to the device or the bus supply. 10 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 LM21212-2 www.ti.com SNVS715A - MARCH 2011 - REVISED MARCH 2013 Iclr IL Iclf VSS VFB 100 mV VOUT VSW CURRENT LIMIT SHORT-CIRCUIT SHORT-CIRCUIT REMOVED Figure 23. Current Limit Conditions THERMAL PROTECTION Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 165C, the LM21212-2 tri-states the power FETs and resets soft start. After the junction cools to approximately 155C, the device starts up using the normal start up routine. This feature is provided to prevent catastrophic failures from accidental device overheating. Note that thermal limit will not stop the die from operating above the specified operating maximum temperature,125C. The die should be kept under 125C to ensure correct operation. POWERGOOD FLAG The PGOOD pin provides the user with a way to monitor the status of the LM21212-2. In order to use the PGOOD pin, the application must provide a pull-up resistor to a desired DC voltage (i.e. Vin). PGOOD will respond to a fault condition by pulling the PGOOD pin low with the open-drain output. PGOOD will pull low on the following conditions - 1) VFB moves above or below the VOVP or VUVP, respectively 2) The enable pin is brought below the enable threshold 3) The device enters a pre-biased output condition (VFB>VSS). Figure 24 shows the conditions that will cause PGOOD to fall. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 11 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com tRESETSS Vss 0.6V Vovp VOVPHYS VFB Vuvp VUVPHYS VEN VPGOOD VSW OVP UVP DISABLE tPGDGL PRE-BIASED STARTUP tPGDGH Figure 24. PGOOD Conditions LIGHT LOAD OPERATION The LM21212-2 offers increased efficiency when operating at light loads. Whenever the load current is reduced to a point where the peak to peak inductor ripple current is greater than two times the load current, the device will enter the diode emulation mode preventing significant negative inductor current. The output current at which this occurs is the critical conduction boundary and can be calculated by the following equation: IBOUNDARY = (VIN VOUT) x D 2 x L x fSW (1) Several diagrams are shown in Figure 25 illustrating continuous conduction mode (CCM), discontinuous conduction mode (DCM), and the boundary condition. It can be seen that in diode emulation mode, whenever the inductor current reaches zero the SW node will become high impedance. Ringing will occur on this pin as a result of the LC tank circuit formed by the inductor and the parasitic capacitance at the node. If this ringing is of concern an additional RC snubber circuit can be added from the switch node to ground. At very light loads, usually below 500mA, several pulses may be skipped in between switching cycles, effectively reducing the switching frequency and further improving light-load efficiency. 12 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 Switchnode Voltage www.ti.com Continuous Conduction Mode (CCM) VIN Time (s) Inductor Current Continuous Conduction Mode (CCM) IAVERAGE Inductor Current Time (s) DCM - CCM Boundary IAVERAGE Switchnode Voltage Time (s) Discontinuous Conduction Mode (DCM) VIN Inductor Current Time (s) Discontinuous Conduction Mode (DCM) IPeak Time (s) Figure 25. Modes of Operation for LM21212-2 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 13 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com DESIGN GUIDE OUTPUT VOLTAGE The first step in designing the LM21212-2 application is setting the output voltage. This is done by using a voltage divider between VOUT and AGND, with the middle node connected to VFB. When operating under steadystate conditions, the LM21212-2 will force VOUT such that VFB is driven to 0.6 V. VOUT LM21212-2 RFB1 0.6V FB RFB2 Figure 26. Setting VOUT A good starting point for the lower feedback resistor, RFB2, is 10k. RFB1 can then be calculated the following equation: VOUT = RFB1 + RFB2 0.6V RFB2 (2) PRECISION ENABLE The enable (EN) pin of the LM21212-2 allows the output to be toggled on and off. This pin is a precision analog input. When the voltage exceeds 1.35V, the controller will try to regulate the output voltage as long as the input voltage has exceeded the UVLO voltage of 2.70V. There is an internal current source connected to EN so if enable is not used, the device will turn on automatically. If EN is not toggled directly the device can be preprogrammed to turn on at a certain input voltage higher than the UVLO voltage. This can be done with an external resistor divider from AVIN to EN and EN to AGND as shown below in Figure 27. Input Power Supply RA AVIN LM21212-2 EN VOUT RB Figure 27. Enable Startup Through Vin The resistor values of RA and RB can be relatively sized to allow EN to reach the enable threshold voltage depending on the input supply voltage. With the enable current source accounted for, the equation solving for RA is shown below: RB VPVIN - 1.35V RA = 1.35V - IENRB (3) In the above equation, RA is the resistor from VIN to enable, RB is the resistor from enable to ground, IEN is the internal enable pull-up current (2A) and 1.35V is the fixed precision enable threshold voltage. Typical values for RB range from 10k to 100k. 14 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 LM21212-2 www.ti.com SNVS715A - MARCH 2011 - REVISED MARCH 2013 SOFT START When EN has exceeded 1.35V, and both PVIN and AVIN have exceeded the UVLO threshold, the LM21212-2 will begin charging the output linearly to the voltage level dictated by the feedback resistor network. The LM21212-2 employs a user adjustable soft start circuit to lengthen the charging time of the output set by a capacitor from the soft start pin to ground. After enable exceeds 1.35V, an internal 2 A current source begins to charge the soft start capacitor. This allows the user to limit inrush currents due to a high output capacitance and not cause an over current condition. Adding a soft-start capacitor can also reduce the stress on the input rail. Larger capacitor values will result in longer startup times. Use the equation below to approximate the size of the soft-start capacitor: tSS x ISS = CSS 0.6V (4) where ISSis nominally 2 A and tSS is the desired startup time. If VIN is higher than the UVLO level and enable is toggled high the soft start sequence will begin. There is a small delay between enable transitioning high and the beginning of the soft start sequence. This delay allows the LM21212-2 to initialize its internal circuitry. Once the output has charged to 90% of the nominal output voltage the power good flag will transition high. This behavior is illustrated in Figure 28. Voltage 90% VOUT (VUVP) VOUT Enable Delay (tRESETSS) 0V VEN VPGOOD Soft Start Time (tss) Time Figure 28. Soft Start Timing As shown above, the size of the capacitor is influenced by the nominal feedback voltage level 0.6V, the soft-start charging current ISS (2 A), and the desired soft start time. If no soft-start capacitor is used then the LM21212-2 defaults to a minimum startup time of 500 s. The LM21212-2 will not startup faster than 500 s. When enable is cycled or the device enters UVLO, the charge developed on the soft-start capacitor is discharged to reset the startup process. This also happens when the device enters short circuit mode from an over-current event. RESISTOR-ADJUSTABLE FREQUENCY The frequency adjust (FADJ) pin allows the LM21212-2 to be programmed to a predetermined switching frequency between 300 kHz to 1.55 MHz by connecting a resistor between FADJ and AGND. To determine the resistor (RADJ) value for a desired frequency, the following equation can be used: 54680 RADJ = - 13.15 fSW (5) where RADJ is resistance in k, and fSW is frequency in kHz. The desired frequency must fall within the operational frequency range, 300 kHz to 1550 kHz, and a corresponding resistor must be used for normal operation. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 15 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com INDUCTOR SELECTION The inductor (L) used in the application will influence the ripple current and the efficiency of the system. The first selection criteria is to define a ripple current, IL. In a buck converter, it is typically selected to run between 20% to 30% of the maximum output current. Figure 29 shows the ripple current in a standard buck converter operating in continuous conduction mode. Larger ripple current will result in a smaller inductance value, which will lead to lower inductor series resistance, and improved efficiency. However, larger ripple current will also cause the device to operate in discontinuous conduction mode at a higher average output current. VSW VIN Time IL IL AVG = IOUT 'IL Time Figure 29. Switch and Inductor Current Waveforms Once the ripple current has been determined, the appropriate inductor size can be calculated using the following equation: L= (VIN VOUT) D uIL fSW (6) OUTPUT CAPACITOR SELECTION The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM21212-2 that provide various advantages. The best performance is typically obtained using ceramic, SP or OSCON type chemistries. Typical trade-offs are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes, while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading conditions. When selecting the value for the output capacitor, the two performance characteristics to consider are the output voltage ripple and transient response. The output voltage ripple can be approximated by using the following formula: 'VOUT 'IL x RESR + 1 8 x fSW x COUT (7) where VOUT (V) is the amount of peak to peak voltage ripple at the power supply output, RESR () is the series resistance of the output capacitor, fSW (Hz) is the switching frequency, and COUT (F) is the output capacitance used in the design. The amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also affect the output voltage droop during a load transient. The peak droop on the output voltage during a load transient is dependent on many factors; however, an approximation of the transient droop ignoring loop bandwidth can be obtained using the following equation: VDROOP = 'IOUTSTEP x RESR + 16 L x 'IOUTSTEP2 COUT x (VIN - VOUT) Submit Documentation Feedback (8) Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 LM21212-2 www.ti.com SNVS715A - MARCH 2011 - REVISED MARCH 2013 where, COUT (F) is the minimum required output capacitance, L (H) is the value of the inductor, VDROOP (V) is the output voltage drop ignoring loop bandwidth considerations, IOUTSTEP (A) is the load step change, RESR () is the output capacitor ESR, VIN (V) is the input voltage, and VOUT (V) is the set regulator output voltage. Both the tolerance and voltage coefficient of the capacitor should be examined when designing for a specific output ripple or transient droop target. INPUT CAPACITOR SELECTION Quality input capacitors are necessary to limit the ripple voltage at the PVIN pin while supplying most of the switch current during the on-time. Additionally, they help minimize input voltage droop in an output current transient condition. In general, it is recommended to use a ceramic capacitor for the input as it provides both a low impedance and small footprint. Use of a high grade dielectric for the ceramic capacitor, such as X5R or X7R, will provide improved performance over temperature and also minimize the DC voltage derating that occurs with Y5V capacitors. The input capacitors should be placed as close as possible to the PVIN and PGND pins. Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating is given by the relationship: IIN-RMS = IOUT D(1 - D) (9) As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device. When operating at low input voltages (3.3V or lower), additional capacitance may be necessary to protect from triggering an under-voltage condition on an output current transient. This will depend on the impedance between the input voltage supply and the LM21212-2, as well as the magnitude and slew rate of the output transient. The AVIN pin requires a 1 F ceramic capacitor to AGND and a 1 resistor to PVIN. This RC network will filter inherent noise on PVIN from the sensitive analog circuitry connected to AVIN. CONTROL LOOP COMPENSATION The LM21212-2 incorporates a high bandwidth amplifier between the FB and COMP pins to allow the user to design a compensation network that matches the application. This section will walk through the various steps in obtaining the open loop transfer function. There are three main blocks of a voltage mode buck switcher that the power supply designer must consider when designing the control system; the power train, modulator, and the compensated error amplifier. A closed loop diagram is shown in Figure 30. PWM Modulator Power Train VIN RDCR DRIVER LOUT VOUT SW RESR RO COUT PWM + Error Amplifier and Compensation COMP + EA - CC1 RC1 0.6V FB RFB1 RC2 C C3 RFB2 CC2 Figure 30. Loop Diagram Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 17 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com The power train consists of the output inductor (L) with DCR (DC resistance RDCR), output capacitor (C0) with ESR (effective series resistance RESR), and load resistance (Ro). The error amplifier (EA) constantly forces FB to 0.6V. The passive compensation components around the error amplifier help maintain system stability. The modulator creates the duty cycle by comparing the error amplifier signal with an internally generated ramp set at the switching frequency. There are three transfer functions that must be taken into consideration when obtaining the total open loop transfer function; COMP to SW (Modulator) , SW to VOUT (Power Train), and VOUT to COMP (Error Amplifier). The COMP to SW transfer function is simply the gain of the PWM modulator. GPWM = Vin AVramp (10) where VRAMP is the oscillator peak-to-peak ramp voltage (nominally 0.8 V). The SW to COMP transfer function includes the output inductor, output capacitor, and output load resistance. The inductor and capacitor create two complex poles at a frequency described by: fLC = RO + RDCR 1 2S LOUTCOUT(RO + RESR) (11) In addition to two complex poles, a left half plane zero is created by the output capacitor ESR located at a frequency described by: fESR = 1 2SCOUTRES (12) A Bode plot showing the power train response can be seen below. 60 0 -40 40 GAIN (dB) -120 0 -160 -20 -200 PHASE () -80 20 -240 -40 -280 -60 -80 100 GAIN PHASE 1k 10k 100k 1M FREQUENCY (HZ) -320 -360 10M Figure 31. Power Train Bode Plot The complex poles created by the output inductor and capacitor cause a 180 phase shift at the resonant frequency as seen in Figure 31. The phase is boosted back up to -90 because of the output capacitor ESR zero. The 180 phase shift must be compensated out and phase boosted through the error amplifier to stabilize the closed loop response. The compensation network shown around the error amplifier in Figure 30 creates two poles, two zeros and a pole at the origin. Placing these poles and zeros at the correct frequencies will stabilize the closed loop response. The Compensated Error Amplifier transfer function is: s s +1 +1 2SfZ1 2SfZ2 GEA = Km s 18 s s +1 +1 2SfP1 2SfP2 (13) Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 LM21212-2 www.ti.com SNVS715A - MARCH 2011 - REVISED MARCH 2013 The pole located at the origin gives high open loop gain at DC, translating into improved load regulation accuracy. This pole occurs at a very low frequency due to the limited gain of the error amplifier; however, it can be approximated at DC for the purposes of compensation. The other two poles and two zeros can be located accordingly to stabilize the voltage mode loop depending on the power stage complex poles and Q. Figure 32 is an illustration of what the Error Amplifier Compensation transfer function will look like. 90 GAIN PHASE 80 45 60 0 40 -45 20 -90 0 -135 -20 100 PHASE () GAIN (dB) 100 -180 1k 10k 100k 1M FREQUENCY (Hz) 10M Figure 32. Type 3 Compensation Network Bode Plot As seen in Figure 32, the two zeros (fLC/2, fLC) in the comensation network give a phase boost. This will cancel out the effects of the phase loss from the output filter. The compensation network also adds two poles to the system. One pole should be located at the zero caused by the output capacitor ESR (fESR) and the other pole should be at half the switching frequency (fSW/2) to roll off the high frequency response. The dependancy of the pole and zero locations on the compensation components is described below. fLC 1 fZ1 = 2 = 2SR C C1 C1 1 fZ2 = fLC = 2S(R + R )C C1 FB1 C3 fP1 = fESR = fP2 = fsw 2 1 2SRC2CC3 CC1 + CC2 = 2SR C C C1 C1 C2 (14) An example of the step-by-step procedure to generate compensation component values using the typical application setup (see Figure 37) is given. The parameters needed for the compensation values are given in the table below. Parameter Value VIN 5.0V VOUT 1.2V IOUT 12A fCROSSOVER 100 kHz L 0.56 H RDCR 1.8 m CO 150 F RESR 1.0 m VRAMP 0.8V fSW 500 kHz Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 19 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com where VRAMP is the oscillator peak-to-peak ramp voltage (nominally 0.8V), and fCROSSOVER is the frequency at which the open-loop gain is a magnitude of 1. It is recommended that the fcrossover not exceed one-fifth of the switching frequency. The output capacitance, CO, depends on capacitor chemistry and bias voltage. For MultiLayer Ceramic Capacitors (MLCC), the total capacitance will degrade as the DC bias voltage is increased. Measuring the actual capacitance value for the output capacitors at the output voltage is recommended to accurately calculate the compensation network. The example given here is the total output capacitance using the three MLCC output capacitors biased at 1.2V, as seen in the typical application schematic, Figure 37. Note that it is more conservative, from a stability standpoint, to err on the side of a smaller output capacitance value in the compensation calculations rather than a larger, as this will result in a lower bandwidth but increased phase margin. First, a the value of RFB1 should be chosen. A typical value is 10k. From this, the value of RC1 can be calculated to set the mid-band gain so that the desired crossover frequency is achieved: RC1 = fCROSSOVER 'VRAMP fLC VIN RFB1 100 kHz 0.8 V 10 k: 17.4 kHz 5.0 V = 9.2 k: = (15) Next, the value of CC1 can be calculated by placing a zero at half of the LC double pole frequency (fLC): CC1 = 1 SfLCRC1 = 1.99 nF (16) Now the value of CC2 can be calculated to place a pole at half of the switching frequency (fSW): CC2 = CC1 SfSWRC1 CC1 -1 = 71 pF (17) RC2 can then be calculated to set the second zero at the LC double pole frequency: RFB1 fLC RC2 = fESR - fLC = 166: (18) Last, CC3 can be calculated to place a pole at the same frequency as the zero created by the output capacitor ESR: 1 CC3 = 2SfESRRC2 = 898 pF (19) An illustration of the total loop response can be seen in Figure 33. 20 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 LM21212-2 www.ti.com SNVS715A - MARCH 2011 - REVISED MARCH 2013 GAIN PHASE 150 160 140 120 GAIN (dB) 100 100 80 60 50 40 20 0 PHASE MARGIN () 200 0 -20 -50 -40 10 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 33. Loop Response It is important to verify the stability by either observing the load transient response or by using a network analyzer. A phase margin between 45 and 70 is usually desired for voltage mode systems. Excessive phase margin can cause slow system response to load transients and low phase margin may cause an oscillatory load transient response. If the load step response peak deviation is larger than desired, increasing fCROSSOVER and recalculating the compensation components may help but usually at the expense of phase margin. THERMAL CONSIDERATIONS The thermal characteristics of the LM21212-2 are specified using the parameter JA, which relates the junction temperature to the ambient temperature. Although the value of JA is dependant on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship: TJ = PD TJA + TA (20) and PD = PIN (1 - Efficiency) - IOUT2 RDCR (21) Where: TJ is the junction temperature in C, PIN is the input power in Watts (PIN = VIN x IIN), JA is the junction to ambient thermal resistance for the LM21212-2, TA is the ambient temperature in C, and IOUT is the output load current in A. It is important to always keep the operating junction temperature (TJ) below 125C for reliable operation. If the junction temperature exceeds 165C the device will cycle in and out of thermal shutdown. If thermal shutdown occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device. Figure 34, shown below, provides a better approximation of the JA for a given PCB copper area. The PCB used in this test consisted of 4 layers: 1oz. copper was used for the internal layers while the external layers were plated to 2oz. copper weight. To provide an optimal thermal connection, a 3 x 4 array of 8 mil. vias under the thermal pad were used, and an additional sixteen 8 mil. vias under the rest of the device were used to connect the 4 layers. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 21 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com THERMAL RESISTANCE ( JA) 30 28 26 24 22 20 18 16 14 12 10 2 3 4 5 6 7 8 2 BOARD AREA (in ) 9 10 Figure 34. Thermal Resistance vs PCB Area (4 Layer Board) Figure 35 shows a plot of the maximum ambient temperature vs. output current for the typical application circuit shown in Figure 37, assuming a JA value of 24 C/W. MAX. AMBIENT TEMPERATURE (C) 125 115 105 95 85 75 0 2 4 6 IOUT(A) 8 10 12 Figure 35. Maximum Ambient Temperature vs. Output Current (0 LFM) PCB LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched at high slew rates. The first loop starts from the input capacitor, to the regulator PVIN pin, to the regulator SW pin, to the inductor then out to the output capacitor and load. The second loop starts from the output capacitor ground, to the regulator GND pins, to the inductor and then out to the load (see Figure 36). To minimize both loop areas, the input capacitor should be placed as close as possible to the VIN pin. Grounding for both the input and output capacitor should be close. Ideally, a ground plane should be placed on the top layer that connects the PGND pins, the exposed pad (EP) of the device, and the ground connections of the input and output capacitors in a small area near pins 10 and 11 of the device. The inductor should be placed as close as possible to the SW pin and output capacitor. 2. Minimize the copper area of the switch node. The six SW pins should be routed on a single top plane to the pad of the inductor. The inductor should be placed as close as possible to the switch pins of the device with 22 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 LM21212-2 www.ti.com 3. 4. 5. 6. SNVS715A - MARCH 2011 - REVISED MARCH 2013 a wide trace to minimize conductive losses. The inductor can be placed on the bottom side of the PCB relative to the LM21212-2, but care must be taken to not allow any coupling of the magnetic field of the inductor into the sensitive feedback or compensation traces. Have a solid ground plane between PGND, the EP and the input and output cap. ground connections. The ground connections for the AGND, compensation, feedback, and soft-start components should be physically isolated (located near pins 1 and 20) from the power ground plane but a separate ground connection is not necessary. If not properly handled, poor grounding can result in degraded load regulation or erratic switching behavior. Carefully route the connection from the VOUT signal to the compensation network. This node is high impedance and can be susceptible to noise coupling. The trace should be routed away from the SW pin and inductor to avoid contaminating the feedback signal with switch noise. Additionally,feedback resistors RFB1 and RFB2 should be located near the device to minimize the trace length to FB between these resistors. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and can improve efficiency. Voltage accuracy at the load is important so make sure feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the best output accuracy. Provide adequate device heatsinking. For most 12A designs a four layer board is recommended. Use as many vias as possible to connect the EP to the power plane heatsink. The vias located underneath the EP will wick solder into them if they are not filled. Complete solder coverage of the EP to the board is required to achieve the JA values described in the previous section. Either an adequate amount of solder must be applied to the EP pad to fill the vias, or the vias must be filled during manufacturing. See the THERMAL CONSIDERATIONS section to ensure enough copper heatsinking area is used to keep the junction temperature below 125C. LM21212-2 L VOUT SW PVIN VIN CIN COUT PGND LOOP1 LOOP2 Figure 36. Schematic of LM21212-2 Highlighting Layout Sensitive Nodes Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 23 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com HTSSOP-20 5,6,7 VIN 3 RF 4 CIN1 CIN2 CIN3 PVIN LO SW CC3 RFB1 RC2 AVIN LM21212-2 CSS VOUT EN CF 2 11-16 SS/ TRK FB COMP CO1 CO2 CO3 19 18 CC1 RC1 RFB2 CC2 VIN 1 17 FADJ RADJ PGOOD PGND AGND 8,9,10 RPGOOD 20 Figure 37. Typical Application Schematic 1 Table 1. Bill of Materials (VIN = 3.3V - 5.5V, VOUT = 1.2V, IOUT = 12A, fSW = 500kHz) ID DESCRIPTION VENDOR PART NUMBER QUANTITY CF CAP, CERM, 1 uF, 10V, +/-10%, X7R, 0603 MuRata GRM188R71A105KA61D 1 CIN1, CIN2, CIN3, CO1, CO2, CO3 CAP, CERM, 100 uF, 6.3V, +/-20%, X5R, 1206 MuRata GRM31CR60J107ME39L 6 CC1 CAP, CERM, 1800 pF, 50V, +/-5%, C0G/NP0, 0603 TDK C1608C0G1H182J 1 CC2 CAP, CERM, 68 pF, 50V, +/-5%, C0G/NP0, 0603 TDK C1608C0G1H680J 1 CC3 CAP, CERM, 820 pF, 50V, +/-5%, C0G/NP0, 0603 TDK C1608C0G1H821J 1 CSS CAP, CERM, 0.033 uF, 16V, +/-10%, X7R, 0603 MuRata GRM188R71C333KA01D 1 LO Inductor, Shielded Drum Core, Powdered Iron, 560nH, 27.5A, 0.0018 ohm, SMD Vishay-Dale IHLP4040DZERR56M01 1 RF RES, 1.0 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW06031R00JNEA 1 RC1 RES, 9.31 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW06039K31FKEA 1 RC2 RES, 165 ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW0603165RFKEA 1 RFB1, RFB2, RPGOOD RES, 10 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060310K0FKEA 3 RADJ RES, 95.3 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060395K3FKEA 1 24 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 LM21212-2 www.ti.com SNVS715A - MARCH 2011 - REVISED MARCH 2013 HTSSOP-20 LO 5,6,7 VIN PVIN CIN1 RF REN1 3 4 CF 11-16 SW CC3 EN RFB1 RC2 AVIN LM21212-2 REN2 2 SS/ TRK CO1 CO2 19 FB CSS VOUT COMP 18 CC1 RC1 RFB2 CC2 VIN 1 FADJ RADJ PGOOD 17 RPGOOD PGND AGND 8,9,10 20 Figure 38. Typical Application Schematic 2 Table 2. Bill of Materials (VIN = 4.0V - 5.5V, VOUT = 0.9V, IOUT = 8A, fSW = 1MHz) ID DESCRIPTION VENDOR PART NUMBER QUANTITY CF CAP, CERM, 1 uF, 10V, +/-10%, X7R, 0603 MuRata GRM188R71A105KA61D 1 CIN1, CO1, CO2 CAP, CERM, 100 uF, 6.3V, +/-20%, X5R, 1206 MuRata GRM31CR60J107ME39L 3 CC1 CAP, CERM, 1800 pF, 50V, +/-5%, C0G/NP0, 0603 MuRata GRM1885C1H182JA01D 1 CC2 CAP, CERM, 68 pF, 50V, +/-5%, C0G/NP0, 0603 TDK C1608C0G1H680J 1 CC3 CAP, CERM, 470 pF, 50V, +/-5%, C0G/NP0, 0603 TDK C1608C0G1H471J 1 CSS CAP, CERM, 0.033 uF, 16V, +/-10%, X7R, 0603 MuRata GRM188R71C333KA01D 1 LO Inductor, Shielded Drum Core, Superflux, 240nH, 20A, 0.001 ohm, SMD Wurth Elektronik 744314024 1 RF RES, 1.0 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW06031R00JNEA 1 RC1 RES, 4.87 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW06034K87FKEA 1 RC2 RES, 210 ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW0603210RFKEA 1 REN1, RFB1, RPGOOD RES, 10k ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060310K0FKEA 3 REN2 RES, 19.6 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060319K6FKEA 1 RFB2 RES, 20.0 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060320K0FKEA 1 RADJ RES, 41.2 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060341K2FKEA 1 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 25 LM21212-2 SNVS715A - MARCH 2011 - REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Original (March 2013) to Revision A * 26 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 25 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LM21212-2 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LM21212MH-2/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM21212 MH-2 LM21212MHE-2/NOPB ACTIVE HTSSOP PWP 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM21212 MH-2 LM21212MHX-2/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM21212 MH-2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 29-Dec-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM21212MHE-2/NOPB HTSSOP PWP 20 250 178.0 16.4 LM21212MHX-2/NOPB HTSSOP PWP 20 2500 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 7.1 1.6 8.0 16.0 Q1 6.95 7.1 1.6 8.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Dec-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM21212MHE-2/NOPB HTSSOP PWP LM21212MHX-2/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0 20 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA PWP0020AA MYB20XX (REV E) 4214875/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. C. Reference JEDEC Registration MO-153, Variation ACT. www.ti.com 02/2013 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. 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