Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 LMV641 10-MHz, 12-V, Low-Power Amplifier 1 Features 3 Description * * * * * * * * * * * The LMV641 is a low-power, wide-bandwidth operational amplifier with an extended power supply voltage range of 2.7 V to 12 V. 1 Specified for 2.7-V, and 5-V Performance Low Power Supply Current: 138 A High Unity Gain Bandwidth: 10 MHz Max Input Offset Voltage: 500 V CMRR: 120 dB PSRR: 105 dB Input Referred Voltage Noise: 14 nV/Hz 1/f Corner Frequency: 4 Hz Output Swing With 2-k Load 40 mV from Rail Total Harmonic Distortion: 0.002% at 1 kHz, 2 k Temperature Range -40C to 125C 2 Applications * * * Portable Equipment Battery-Powered Systems Sensors and Instrumentation The device features 10 MHz of gain bandwidth product with unity gain stability on a typical supply current of 138 A. Other key specifications are a PSRR of 105 dB, CMRR of 120 dB, VOS of 500 V, input referred voltage noise of 14 nV/Hz, and a THD of 0.002%. This amplifier has a rail-to-rail output stage and a common mode input voltage, which includes the negative supply. The LMV641 device operates over a temperature range of -40C to +125C and is offered in the boardspace-saving 5-Pin SC70, SOT-23, and 8-Pin SOIC packages. Device Information(1) PART NUMBER PACKAGE LMV641 BODY SIZE (NOM) SOIC (8) 4.90 mm x 3.91 mm SOT-23 (5) 2.90 mm x 1.60 mm SC70 (5) 2.00 mm x 1.25 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 20 UNITS TESTED = 12,000 18 + 180 V = +5V V = -5V 150 PHASE GAIN (dB) 12 10 8 6 4 2 RL = 10 k: 120 120 TA = 25C CL = 20 pF 90 60 GAIN 0 100 200 300 400 OFFSET VOLTAGE (PV) 90 60 30 30 0 0 -30 -30 0 -400 -300 -200 -100 150 - V = -6V VCM = 0V 14 180 + V = +6V - 16 PERCENTAGE (%) Open Loop Gain and Phase vs Frequency -60 100 PHASE () Offset Voltage Distribution 1k 10k 100k 1M 10M -60 100M FREQUENCY (Hz) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 8 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. DC Electrical Characteristics: 2.7 V ......................... DC Electrical Characteristics: 10 V ........................... Typical Characteristics .............................................. Detailed Description ............................................ 14 7.1 Overview ................................................................. 14 7.2 Functional Block Diagram ....................................... 14 7.3 Feature Description................................................. 14 7.4 Device Functional Modes........................................ 15 8 Application and Implementation ........................ 17 8.1 Application Information............................................ 17 8.2 Typical Applications ................................................ 17 9 Power Supply Recommendations...................... 23 10 Layout................................................................... 23 10.1 Layout Guidelines ................................................. 23 10.2 Layout Example .................................................... 23 11 Device and Documentation Support ................. 24 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support .................................................... Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 24 24 24 24 24 24 24 12 Mechanical, Packaging, and Orderable Information ........................................................... 25 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (February 2013) to Revision D Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 * Moved Package thermal resistance (RJA) rows from Recommended Operating Conditions to Thermal Information........... 4 Changes from Revision B (February 2013) to Revision C * 2 Page Changed layout of National Semiconductor Data Sheet to TI Format ................................................................................... 1 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 5 Pin Configuration and Functions DBV and DCK Packages 5-Pin SOT-23 and SC70 Top View D Package 8-Pin SOIC Top View N/C VIN- 1 2 VIN+ 3 V- 4 8 - + 7 6 5 N/C V+ VOUT N/C Pin Functions PIN NAME SOT-23 SC70 SOIC VIN+ 3 3 3 VIN- 4 4 VOUT 1 1 V+ 5 V- 2 (1) TYPE (1) DESCRIPTION I Noninverting Input 2 I Inverting Input 6 O Output 5 7 P Positive supply input 2 4 P Supply negative input I = input; O = output; P = power Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 3 LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) Differential input VID + MIN MAX UNIT 0.3 0.3 V 13.2 V (V- -0.3) V+ +0.3 V 150 C 150 C - Supply voltage (VS = V - V ) Input and output pin voltage Junction temperature (3) Storage temperature, Tstg (1) (2) (3) -65 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office / Distributors for availability and specifications. The maximum power dissipation is a function of TJ(MAX, RJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ RJA. All numbers apply for packages soldered directly onto a PC board. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), (1) 2000 Machine model (MM) 200 UNIT V Human Body Model, applicable std. MIL-STD-883, Method 3015.7. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MAX UNIT (1) MIN -40 125 C Supply voltage (VS = V+ - V-) 2.7 12 V Temperature (1) NOM The maximum power dissipation is a function of TJ(MAX, RJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ RJA. All numbers apply for packages soldered directly onto a PC board. 6.4 Thermal Information LMV641 THERMAL METRIC (1) DBV (SOT-23) DCK (SC70) D (SOIC) 5 PINS 5 PINS 8 PINS UNIT RJA (2) Junction-to-ambient thermal resistance 325 456 166 C/W RJC(top) Junction-to-case (top) thermal resistance 178.1 121.8 93.6 C/W RJB Junction-to-board thermal resistance 60.8 68.9 90.9 C/W JT Junction-to-top characterization parameter 57.7 5.3 38.4 C/W JB Junction-to-board characterization parameter 60.2 68.1 90.4 C/W RJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a C/W (1) (2) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. The maximum power dissipation is a function of TJ(MAX, RJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ RJA. All numbers apply for packages soldered directly onto a PC board. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 6.5 DC Electrical Characteristics: 2.7 V Unless otherwise specified, all limits are specified for TA = 25C, V+ = 2.7 V, V- = 0 V, VO = VCM = V+/2, and RL > 1 M. PARAMETER VOS Input offset voltage TC VOS Input offset average drift IB Input bias current IOS Input offset current CMRR PSRR CMVR AVOL Common-mode rejection ratio Power supply rejection ratio Input common-mode voltage range Large signal voltage gain (1) TA = 25C TYP MAX 30 500 (2) Temperature extremes 0.1 TA = 25C (3) 75 Temperature extremes TA = 25C 0 V VCM 1.7 V (3) 89 Temperature extremes 84 (3) 2.7 V V+ 10 V, VCM = TA = 25C 0.5 Temperature extremes 94.5 (3) 2.7 V V+ 12 V, VCM = TA = 25C 0.5 Temperature extremes 94 (3) CMRR 80 dB TA = 25C CMRR 68 dB Temperature extremes nA TA = 25C 0.4 V VO 2.3 V, RL = 10 k to V+/2 Temperature extremes TA = 25C (3) (3) RL = 2 k to V+/2, VIN = 100 mV TA = 25C (3) 0 1.8 86 V 88 dB 98 82 42 58 68 22 35 40 38 48 mV from rail 58 18 RL = 10 k to V /2, VIN = 100 mV dB 100 Temperature extremes + dB 105 Temperature extremes (3) = TA = 25C Temperature extremes nA 114 1.8 78 0.3 V VO 2.4 V, RL = 10 k to V+/2 5 0 82 Output swing low 95 92 0.4 V VO 2.3 V, RL = 2 k to V+/2 RL = 10 k to V /2, VIN 100 mV V/C 92.5 0.3 V VO 2.4 V, RL = 2 k to V+/2 + V 110 0.9 Output swing high UNIT (1) 750 RL = 2 k to V+/2, VIN = 100 mV VO MIN TEST CONDITIONS 30 35 Sourcing 22 Sinking 25 IOUT Sourcing and sinking output VIN_DIFF = 100 mV to VO current = V+/2 (4) IS Supply current SR Slew rate GBW Gain bandwidth product 10 MHz en Input-referred voltage noise f = 1 kHz 14 nV/Hz in Input-referred current noise f = 1 kHz 0.15 pA/Hz THD Total harmonic distortion f = 1 kHz, AV = 2, RL = 2 k (1) (2) (3) (4) TA = 25C (3) 138 Temperature extremes AV = 1, VO = 1 VPP mA 170 A 220 Rising (10% to 90%) 2.3 Falling (90% to 10%) 1.6 V/s 0.014% Limits are 100% production tested at 25C. Limits over the operating temperature range are specified through correlations using Statistical Quality Control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. Positive current corresponds to current flowing into the device. The part is not short-circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output current curves are provided in Typical Characteristics and should be consulted before designing for heavy loads. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 5 LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 www.ti.com 6.6 DC Electrical Characteristics: 10 V Unless otherwise specified, all limits are specified for TA = 25C, V+ = 10 V, V- = 0 V,VO = VCM = V+/2, and RL > 1 M. PARAMETER VOS Input offset voltage TC VOS Input offset average drift TA = 25C Input bias current IOS Input offset current CMRR Common-mode rejection ratio CMVR AVOL Power supply rejection ratio Input common-mode voltage range Large signal voltage gain VO (3) IOUT Sourcing and sinking output current IS Supply current SR Slew rate (1) (2) (3) (4) 6 5 500 (1) 750 (3) 70 Temperature extremes 0.7 94 0 V VCM 9 V Temperature extremes 90 (3) 94.5 Temperature extremes 92.5 2.7 V V+ 12 V, VCM = 0.5 V (3) 94 Temperature extremes 92 TA = 25C TA = 25C 5 105 dB 100 0 9.1 CMRR 76 dB Temperature extremes 0 9.1 (3) 90 Temperature extremes 85 (3) 97 Temperature extremes 92 TA = 25C TA = 25C (3) 37 (3) 65 55 65 Temperature extremes 90 mV from rail 110 TA = 25C (3) RL = 10 k to V+/2, VIN = 100 Temperature mV extremes 32 42 52 Sourcing 26 Sinking mA 112 (3) 158 Temperature extremes AV = 1, VO = 2 V to 8 VPP 95 125 TA = 25C RL = 10 k to V+/2, VIN = 100 Temperature mV extremes TA = 25C dB 104 68 (3) VIN_DIFF = 100 mV to VO = V+/2 (4) V 99 Temperature extremes TA = 25C nA dB (3) 0.3 V VO 9.7 V, RL = 10 k to V+/2 0.4 V VO 9.6 V, RL = 10 k to V+/2 nA 120 TA = 25C TA = 25C V 90 CMRR 80 dB 0.3 V VO 9.7 V, RL = 2 k to V+/2 0.4 V VO 9.6 V, RL = 2 k to V+/2 UNIT V/C 105 (3) TA = 25C RL = 2 k to V+/2, VIN = 100 mV Output Swing Low MAX (2) 0.1 RL = 2 k to V+/2, VIN = 100 mV Output Swing High TYP Temperature extremes 2.7 V V+ 10 V, VCM = 0.5 V PSRR (1) (3) TA = 25C IB MIN TEST CONDITIONS 190 240 Rising (10% to 90%) 2.6 Falling (90% to 10%) 1.6 A V/s Limits are 100% production tested at 25C. Limits over the operating temperature range are specified through correlations using Statistical Quality Control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. Positive current corresponds to current flowing into the device. The part is not short-circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output current curves are provided in Typical Characteristics and should be consulted before designing for heavy loads. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 DC Electrical Characteristics: 10 V (continued) Unless otherwise specified, all limits are specified for TA = 25C, V+ = 10 V, V- = 0 V,VO = VCM = V+/2, and RL > 1 M. PARAMETER GBW Gain bandwidth product en Input-referred voltage noise in THD TEST CONDITIONS MIN (1) TYP (2) MAX UNIT (1) 10 MHz f = 1 kHz 14 nV/Hz Input-referred current noise f = 1 kHz 0.15 pA/Hz Total harmonic distortion f = 1 kHz, AV = 2, RL = 2 k 0.002% Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 7 LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 www.ti.com 6.7 Typical Characteristics Unless otherwise specified, TA = 25C, V+ = 10 V, V- = 0 V, VCM = VS/2. 220 40 125C 20 180 OFFSET VOLTAGE (PV) SUPPLY CURRENT (PA) 200 160 25C 140 120 -40C 100 80 -40C 0 25C -20 -40 125C -60 -80 60 40 2 3 4 5 6 7 8 9 -100 10 11 12 2 3 4 5 6 8 9 10 11 12 SUPPLY VOLTAGE (V) Figure 1. Supply Current vs Supply Voltage Figure 2. Offset Voltage vs Supply Voltage 50 0 -40C -20 -30 -40 25C -50 -60 -70 125C -80 + V = +2.7V -90 - V = 0V 30 -40C 20 10 0 25C -10 -20 -30 -40 - V = 0V -100 -50 0 + V = +5V 40 OFFSET VOLTAGE (PV) OFFSET VOLTAGE (PV) -10 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 125C 0 0.5 1 1.5 Figure 3. Offset Voltage vs VCM 50 OFFSET VOLTAGE (PV) OFFSET VOLTAGE (PV) -40C 20 10 25C -10 -20 -30 125C 1 2 3 4 5 4 6 7 + - V = 0V -40C 30 20 10 0 25C -10 -20 -30 -40 -50 0 3.5 V = +12V 40 - V = 0V -40 3 Figure 4. Offset Voltage vs VCM + 0 2.5 50 V = +10V 40 30 2 VCM (V) VCM (V) 8 125C -50 9 0 1 2 3 4 5 6 7 8 9 10 11 VCM (V) VCM (V) Figure 6. Offset Voltage vs VCM Figure 5. Offset Voltage vs VCM 8 7 SUPPLY VOLTAGE (V) Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 Typical Characteristics (continued) Unless otherwise specified, TA = 25C, V+ = 10 V, V- = 0 V, VCM = VS/2. 20 UNITS TESTED = 12,000 18 UNITS TESTED = 12,000 V = -1.35V PERCENTAGE (%) TA = 25C 12 10 8 6 VCM = 0V 14 10 8 6 4 2 2 0 TA = 25C 12 4 0 -400 -300 -200 -100 - V = -5V 16 VCM = 0V 14 + V = +5V 18 - 16 PERCENTAGE (%) 20 + V = +1.35V 0 -400 -300 -200 -100 100 200 300 400 OFFSET VOLTAGE (PV) 0 100 200 300 400 OFFSET VOLTAGE (PV) Figure 7. Offset Voltage Distribution Figure 8. Offset Voltage Distribution 130 160 +PSRR + V = 5V 140 V = +5V 110 V = 5V - V = -5V RL = 1 k: 120 80 100 PSRR (dB) CMRR (dB) + - 80 60 -PSRR 70 V+ = +5V - V = -5V -PSRR 50 + V = +1.35V - V = -1.35V 30 40 +PSRR + 10 20 V = +1.35V - V = -1.35V 0 10 100 1k 10k 100k 1M -10 10 10M 1k 100 Figure 9. CMRR vs Frequency 100 + - 95 V = 0V 125C 90 10M + V = +10V - V = 0V 90 85 125C 85 80 IBIAS (nA) IBIAS (nA) 1M 100k Figure 10. PSRR vs Frequency 100 V = +2.7V 95 10k FREQUENCY (Hz) FREQUENCY (Hz) 25C 75 70 65 -40C 80 70 65 60 60 55 55 50 0 0.2 0.4 0.6 0.8 1 25C 75 -40C 50 1.2 1.4 1.6 1.8 0 1 2 3 4 5 6 7 8 9 VCM (V) VCM (V) Figure 11. Input Bias Current vs VCM Figure 12. Input Bias Current vs VCM Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 9 LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 www.ti.com Typical Characteristics (continued) Unless otherwise specified, TA = 25C, V+ = 10 V, V- = 0 V, VCM = VS/2. 180 180 180 180 150 150 150 150 120 120 CL = 100 pF CL = 50 pF 30 30 0 0 + V = +1.35V - -30 V = -1.35V RL = 2 k: -60 100 10k 1k 100k CL = 100 pF GAIN CL = 50 pF 30 0 + V = +5V - -30 V = -5V RL = 2 k: -60 100 10k 1k -60 100M 60 30 0 -30 10M 1M 90 90 60 CL = 100 pF CL = 50 pF 120 CL = 20 pF FREQUENCY (Hz) CL = 100 pF 100k 10M 1M -60 100M FREQUENCY (Hz) Figure 13. Open-Loop Gain and Phase With Capacitive Load Figure 14. Open-Loop Gain and Phase With Capacitive Load 180 180 180 180 150 150 150 150 120 120 90 90 PHASE 120 + V = +5V PHASE - V = -5V 60 60 GAIN RL = 10 k: 30 0 30 0 + V = +6V - GAIN (dB) 90 PHASE () RL = 2 k: GAIN (dB) -30 CL = 50 pF -30 V = -6V CL = 20 pF -60 100 10k 1k 60 60 GAIN 30 30 0 + 10M 1M -30 RL = 2 k: CL = 20 pF -60 100 10k 1k -30 RL = 2 k: 100k 90 0 RL = 10 k: 120 PHASE () GAIN 60 GAIN (dB) 90 90 60 PHASE () GAIN (dB) CL = 20 pF PHASE PHASE () PHASE 120 -60 100M FREQUENCY (Hz) V = +1.35V -30 - V = -1.35V 100k 10M 1M -60 100M FREQUENCY (Hz) Figure 15. Open-Loop Gain and Phase With Resistive Load Figure 16. Open-Loop Gain and Phase With Supply Voltage 1000 1000 + V = +5V NOISE VOLTAGE 10 1 10 0.1 1 0.10 1 10 100 1k 10k 0.01 10 100k 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 17. Input Referred Noise Voltage vs Frequency 10 AV = +1 100 ZOUT (:) VOLTAGE NOISE (nV/ Hz) - V = -5V 100 Figure 18. Close Loop Output Impedance vs Frequency Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 Typical Characteristics (continued) Unless otherwise specified, TA = 25C, V+ = 10 V, V- = 0 V, VCM = VS/2. 0.1 0.1 + V = +5V - V = -5V VIN = 1 VPP 0.01 AV = +2 THD+N (%) THD+N (%) RL = 2 k: 0.01 RL = 10 k: RL = 2 k: + 0.001 V = +1.35V RL = 10 k: - V = -1.35V VIN = 1 VPP AV = +2 0.001 10 100 10k 1k 0.0001 10 100k 100 FREQUENCY (Hz) 1k 10k 100k FREQUENCY (Hz) 0.1 0.1 THD+N (%) Figure 20. THD+N vs Frequency 1 THD+N (%) Figure 19. THD+N vs Frequency 1 RL = 100 k: RL = 2 k: 0.01 V+ = +1.35V RL = 2 k: 0.01 V+ = +5V - - V = -1.35V V = -5V VIN = 1 kHz SINE WAVE VIN = 1 kHz SINE WAVE AV = +2 0.001 0.001 0.01 0.1 1 RL = 10 k: AV = +2 0.001 0.001 0.01 10 0.1 1 10 VOUT (V) VOUT (V) Figure 21. THD+N vs VOUT Figure 22. THD+N vs VOUT 35 120 + + VOUT = V /2 VOUT = V /2 30 100 25C 80 20 ISINK (mA) ISOURCE (mA) 25 -40C 15 40 125C 10 25C 20 5 0 -40C 60 125C 2 3 4 5 6 7 8 9 0 10 11 12 SUPPLY VOLTAGE (V) 2 3 4 5 6 7 8 9 10 SUPPLY VOLTAGE (V) Figure 23. Sourcing Current vs Supply Voltage Figure 24. Sinking Current vs Supply Voltage Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 11 LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 www.ti.com Typical Characteristics (continued) Unless otherwise specified, TA = 25C, V+ = 10 V, V- = 0 V, VCM = VS/2. 25 45 + V = +1.35V - V = -1.35V 35 -40C 30 -40C 15 10 ISINK (mA) ISOURCE (mA) 40 V = -1.35V 20 + V = +1.35V 25C - 125C 25 25C 20 125C 15 10 5 5 0 0 0 0.5 1 1.5 2 2.5 1.5 2 2.5 VOUT FROM RAIL (V) Figure 25. Sourcing Current vs VOUT 35 1 0.5 0 VOUT FROM RAIL (V) Figure 26. Sinking Current vs VOUT 1.5 + V = +5V - 30 V = -5V 1 25C 0.5 -40C 20 VOUT (mV) ISOURCE (mA) 25 15 125C + V = +5V - V = -5V 0 CL = 15 pF, AV = +1 VIN = 2 VPP, 20 kHz -0.5 10 -1 5 0 0 1 2 3 4 5 6 7 8 9 -1.5 10 0 20 VOUT FROM RAIL (V) + 80 100 Figure 28. Large-Signal Transient 30 CL = 125 pF, AV = +1 25 V = +5V 20 V = -5V 60 TIME (Ps) Figure 27. Sourcing Current vs VOUT 30 40 + CL = 15 pF, AV = +1 V = +5V 25 - VIN = 20 mVPP, 20 kHz VIN = 20 mVPP, 20 kHz V = -5V 20 15 15 VOUT (mV) VOUT (mV) 10 5 0 -5 -10 0 -10 -20 -15 -25 12 5 -5 -15 -30 10 0 20 40 -20 60 70 80 0 20 40 60 80 100 TIME (Ps) TIME (Ps) Figure 29. Small-Signal Transient Response Figure 30. Small-Signal Transient Response Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 Typical Characteristics (continued) Unless otherwise specified, TA = 25C, V+ = 10 V, V- = 0 V, VCM = VS/2. 100 100 RL = 2 k: RL = 2 k: 90 125C VOUT FROM RAIL (mV) VOUT FROM RAIL (mV) 90 80 70 25C 60 50 -40C 40 80 125C 70 25C 60 -40C 50 40 30 30 2 3 4 5 6 7 8 9 10 11 12 2 3 4 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 31. Output Swing High vs Supply Voltage Figure 32. Output Swing Low vs Supply voltage 50 50 RL = 10 k: RL = 10 k: 45 125C VOUT FROM RAIL (mV) VOUT FROM RAIL (mV) 45 25C 40 35 30 -40C 25 20 40 125C 35 25C 30 -40C 25 20 15 15 2 3 4 5 6 7 8 9 10 11 12 2 3 4 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 33. Output Swing High vs Supply Voltage Figure 34. Output Swing Low and Supply Voltage 3 RISING SLEW RATE (V/Ps) 2.5 2 1.5 FALLING 1 0.5 RL = 1 M: CL = 20 pF 0 2 3 4 5 6 7 8 9 10 SUPPLY VOLTAGE (V) Figure 35. Slew Rate vs Supply Voltage Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 13 LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 www.ti.com 7 Detailed Description 7.1 Overview The LMV641 is a wide-bandwidth, low-power operational amplifier with an extended power supply voltage range of 2.7 V to 12 V. The device is unity-gain stable with a 10 MHz of gain bandwidth product. Operating on a typical supply current of 138 A, it provides a PSRR of 105 dB, CMRR of 120 dB, VOS of 500 V, input referred voltage noise of 14 nV/Hz, and a THD of 0.002%. This amplifier has a rail-to-rail output stage and a common mode input voltage which includes the negative supply. 7.2 Functional Block Diagram V IN + OUT IN + + V Copyright (c) 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Low-Voltage and Low-Power Operation The LMV641 has performance guaranteed at supply voltages of 2.7 V and 10 V. It is ensured to be operational at all supply voltages between 2.7 V and 12 V. The LMV641 draws a low supply current of 138 A. The LMV641 provides the low-voltage and low-power amplification, which is essential for portable applications. 7.3.2 Wide Bandwidth Despite drawing the very low supply current of 138 A, the LMV641 manages to provide a wide unity gain bandwidth of 10 MHz. This is easily one of the best bandwidth to power ratios ever achieved, and allows this op amp to provide wideband amplification while using the minimum amount of power. This makes the LMV641 ideal for low power signal processing applications such as portable media players and other accessories. 7.3.3 Low Input Referred Noise The LMV641 provides a flatband input referred voltage noise density of 14 nV/Hz, which is significantly better than the noise performance expected from a low-power op amp. This op amp also feature exceptionally low 1/f noise, with a very low 1/f noise corner frequency of 4 Hz. Because of this the LMV641 is ideal for low-power applications which require decent noise performance, such as PDAs and portable sensors. 7.3.4 Ground Sensing and Rail-to-Rail Output The LMV641 has a rail-to-rail output stage, which provides the maximum possible output dynamic range. This is especially important for applications requiring a large output swing. The input common mode range of this part includes the negative supply rail which allows direct sensing at ground in a single supply operation. 7.3.5 Small Size The small footprint of the packages for the LMV641 saves space on printed-circuit boards, and enables the design of smaller and more compact electronic products. Long traces between the signal source and the op amp make the signal path susceptible to noise. By using a physically smaller package, these op amps can be placed closer to the signal source, reducing noise pickup and enhancing signal integrity. 14 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 7.4 Device Functional Modes 7.4.1 Stability of Op Amp Circuits GAIN If the phase margin of the LMV641 is plotted with respect to the capacitive load (CL) at its output, and if CL is increased beyond 100 pF then the phase margin reduces significantly. This is because the op amp is designed to provide the maximum bandwidth possible for a low supply current. Stabilizing the LMV641 for higher capacitive loads would have required either a drastic increase in supply current, or a large internal compensation capacitance, which would have reduced the bandwidth. Hence, if this device is to be used for driving higher capacitive loads, it will have to be externally compensated. STABLE ROC 20 dB/decade UNSTABLE ROC = 40 dB/decade 0 FREQUENCY (Hz) Figure 36. Gain vs Frequency for an Op Amp An op amp, ideally, has a dominant pole close to DC which causes its gain to decay at the rate of 20 dB/decade with respect to frequency. If this rate of decay, also known as the rate of closure (ROC), remains the same until the op amp's unity gain bandwidth, then the op amp is stable. If, however, a large capacitance is added to the output of the op amp, it combines with the output impedance of the op amp to create another pole in its frequency response before its unity gain frequency (Figure 36). This increases the ROC to 40 dB/decade and causes instability. In such a case, a number of techniques can be used to restore stability to the circuit. The idea behind all these schemes is to modify the frequency response such that it can be restored to an ROC of 20 dB/decade, which ensures stability. 7.4.1.1 In The Loop Compensation Figure 37 illustrates a compensation technique, known as in the loop compensation, that employs an RC feedback circuit within the feedback loop to stabilize a non-inverting amplifier configuration. A small series resistance, RS, is used to isolate the amplifier output from the load capacitance, CL, and a small capacitance, CF, is inserted across the feedback resistor to bypass CL at higher frequencies. VIN + ROUT RS - CL RL CF RF RIN Figure 37. In the Loop Compensation Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 15 LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 www.ti.com Device Functional Modes (continued) The values for RS and CF are decided by ensuring that the zero attributed to CF lies at the same frequency as the pole attributed to CL. This ensures that the effect of the second pole on the transfer function is compensated for by the presence of the zero, and that the ROC is maintained at 20 dB/ decade. For the circuit shown in Figure 37 the values of RS and CF are given by Equation 1. Values of RS and CF required for maintaining stability for different values of CL, as well as the phase margins obtained, are shown in Table 1. RF and RIN are 10 k, RL is 2 k, while ROUT is 680. RS = ROUTRIN RF RF + 2RIN CLROUT CF = 2 (c) RF (c) (1) Table 1. Loop Compensation Stability CL (nF) RS () CF (pF) PHASE MARGIN () 0.5 680 10 17.4 1 680 20 12.4 1.5 680 30 10.1 The LMV641 is capable of driving heavy capacitive loads of up to 1 nF without oscillating, however it is recommended to use compensation should the load exceed 1 nF. Using this methodology will reduce any excessive ringing and help maintain the phase margin for stability. The values of the compensation network tabulated above illustrate the phase margin degradation as a function of the capacitive load. Although this methodology provides circuit stability for any load capacitance, it does so at the price of bandwidth. The closed loop bandwidth of the circuit is now limited by RF and CF. 7.4.1.2 Compensation by External Resistor In some applications it is essential to drive a capacitive load without sacrificing bandwidth. In such a case, in the loop compensation is not viable. A simpler scheme for compensation is shown in Figure 38. A resistor, RISO, is placed in series between the load capacitance and the output. This introduces a zero in the circuit transfer function, which counteracts the effect of the pole formed by the load capacitance, and ensures stability. The value of RISO to be used should be decided depending on the size of CL and the level of performance desired. Values ranging from 5 to 50 are usually sufficient to ensure stability. A larger value of RISO will result in a system with less ringing and overshoot, but will also limit the output swing and the short circuit current of the circuit. RSO VOUT VIN CL Figure 38. Compensation by Isolation Resistor 16 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMV641 is a low-power, low noise, wide-bandwidth operational amplifier with an extended power supply voltage range of 2.7 V to 12 V. With 10 MHz of gain bandwidth, 14 nV/Hz input referred noise, and supply current of 138 A, the LMV641 is well suited for portable applications that require precision while amplifying at high gains. 8.2 Typical Applications 8.2.1 High-Gain, Low-Power Inverting Amplifiers CF CC1 R1 1 k: R2 100 k: + VIN - RB1 V CC2 + + + - VOUT RB2 AV = - R2 R1 = -100 Copyright (c) 2016, Texas Instruments Incorporated Figure 39. High-Gain Inverting Amplifier 8.2.1.1 Design Requirements The wide unity-gain bandwidth allows these parts to provide large gain over a wide frequency range, while driving loads as low as 2 k with less than 0.003% distortion. 8.2.1.2 Detailed Design Procedure Figure 39 is an inverting amplifier, with a 100-k feedback resistor, R2, and a 1-k input resistor, R1, and provides a gain of -100. With the LMV641, these circuits can provide gain of -100 with a -3-dB bandwidth of 120 kHz, for a quiescent current as low as 116 A. Coupling capacitors CC1 and CC2 can be added to isolate the circuit from DC voltages, while RB1 and RB2 provide DC biasing. A feedback capacitor CF can also be added to improve compensation. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 17 LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 www.ti.com Typical Applications (continued) Signal Amplitudee 8.2.1.3 Application Curve Vout (1V/div) Vin (10mV/div) 0 50 100 150 200 Time (us) C001 Figure 40. High Gain Inverting Amplifier Results 8.2.2 Anisotropic Magnetoresistive Sensor BRIDGE TEMPCO COMPENSATION NETWORK RA RB STANDOFF DISTANCE x 580: 1% + V 24.5 k: 1% x - B + V + V RTH - U1 LMV641 + LMV641 + x x FROM mAs TO 20A G = 23.2 BW-3 dB = 431 kHz 568 k: 1% I(AC or DC) HONEYWELL HMC1051Z or EQUIVALENT CONDUCTOR TO BE CURRENT MEASURED VOUT TO ADC or METER CIRCUITRY 24.5 k: 1% x U2 0.1 PF + V 9V ALKALINE BATTERY x 20 k: 5 k: 20 k: OFFSET TRIM Copyright (c) 2016, Texas Instruments Incorporated Figure 41. A Battery-Operated System for Contact-Less Current Sensing Using an Anisotropic Magnetoresistive Sensor 8.2.2.1 Design Requirements The low operating current of the LMV641 makes it a good choice for battery-operated applications. Figure 41 shows two LMV641s in a portable application with a magnetic field sensor. The LMV641s condition the output from an anisotropic magnetoresistive (AMR) sensor. The sensor is arranged in the form of a Wheatstone bridge. This type of sensor can be used to accurately measure the current (either DC or AC) flowing in a wire by measuring the magnetic flux density, B, emanating from the wire. 18 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 Typical Applications (continued) 8.2.2.2 Detailed Design Procedure In this circuit, the use of a 9-V alkaline battery exploits the LMV641's high voltage and low supply current for a low-power, portable-current-sensing application. The sensor converts an incident magnetic field (through the magnetic flux linkage) in the sensitive direction, to a balanced voltage output. The LMV641 can be used for moderate to high current sensing applications (from a few milliamps and up to 20 A) using a nearby external conductor providing the sensed magnetic field to the bridge. The circuit shows a Honeywell HMC1051Z used as a current sensor. Note that the circuit must be calibrated based on the final displacement of the sensed conductor relative to the measurement bridge. Typically, once the sensor has been oriented properly, with respect to the conductor to be measured, the conductor can be placed about one centimeter away from the bridge and have reasonable capability of measuring from tens of milliamperes to beyond 20 amperes. In Figure 41, U1 is configured as a single differential input amplifier. Its input impedance is relatively low, however, and requires that the source impedance of the sensor be considered in the gain calculations. Also, the asymmetrical loading on the bridge will produce a small offset voltage that can be cancelled out with the offset trim circuit shown in Figure 41. Figure 42 shows a typical magnetoresistive Wheatstone bridge and the Thevenin equivalent of its resistive elements. As we shall see, the Thevenin equivalent model of the sensor is useful in calculating the gain needed in the differential amplifier. VEXC R + 'R R - 'R SIG - SIG + R + 'R R - 'R (a) R/2 SIG + + R/2 SIG - + - WITH 'R << R, THEN RTH | R/2 THUS, VEXC VSIG VTH = 2 (b) Figure 42. Anisotropic Magnetoresistive Wheatstone Bridge Sensor, (a), and Thevenin Equivalent Circuit, (b) Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 19 LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 www.ti.com Typical Applications (continued) Using Thevenin's Theorem, the bridge can be reduced to two voltage sources with series resistances. R is normally very small in comparison to R, thus the Thevenin equivalent resistance, commonly called the source resistance, can be taken to be R. When a bias voltage is applied between VEXC and ground, in the absence of a magnetic field, all of the resistances are considered equal. The voltage at Sig+ and Sig- is half VEXC, or 4.5 V, and Sig+ - Sig- = 0. Bridges are designed such that, when immersed in a magnetic field, opposite resistances in the bridge change by R with an amount proportional to the strength of the magnetic field. This causes the bridge's output differential voltage, to change from its half VEXC value. Thus Sig+ - Sig- = Vsig 0. With four active elements, the output voltage is: VSIG = VEXC x 'R R (2) Because R is proportional to the field strength, BS, the amount of output voltage from the sensor is a function of sensor sensitivity, S. This expression can rewritten as , where VSIG = VEXC * S * BS where * * S = material constant (nominally 1 mV/V/gauss) BS = magnetic flux in gauss (3) A simplified schematic of a single op amp, differential amplifier is shown in Figure 43. The Thevenin equivalent circuit of the sensor can be used to calculate the gain of this amplifier. R4 R2 - SIG - VO = [(SIG + ) (SIG -)] + SIG + R4 R2 R1 R3 R1 = R2 = R3 = R4 Figure 43. Differential Input Amplifier The Honeywell HMC1051Z AMR sensor has nominal 1-k elements and a sensitivity of 1 mV/V/gauss and is being used with 9 V of excitation with a full scale magnetic field range of 6 gauss. At full-scale, the resistors will have R 12 and 108 mV will be seen from Sig- to Sig+ (see Figure 44). 9V 1012: 988: SIG + = 4.554V 988: 1012: VSIG = 108 mV SIG - = 4.446V Figure 44. Sensor Output with No Load 20 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 Typical Applications (continued) Referring to the simplified diagram in Figure 43, and assuming that required full scale at the output of the amplifier is 2.5 V, a gain of 23.2 is needed for U1. It is clear from the Thevenin equivalent circuit in Figure 45 that a sensor Thevenin equivalent source resistance, RTHEV, of 500 will be in series with both the inverting and noninverting inputs of the LMV641. Therefore, the required gain is: R4 = 23.2 AVCL = RTHEV + R2 (4) Choosing R1 = R2 = 24.5 k, then R4 will be approximately 580 k. The actual values chosen will depend on the full-scale needs of the succeeding circuitry as well as bandwidth requirements. The values shown here provide a -3-dB bandwidth of approximately 431 kHz, and are found as follows. BW-3 dB = GAIN-BANDWIDTH PRODUCT AVCL = 10 MHz = 431 kHz 23.2 580 k: SENSOR 500: 24.5 k: 4.446V - 4.554V + LMV641 500: VO = 2.50V 24.5 k: 580 k: Figure 45. Thevenin Equivalent Showing Required Gain By choosing input resistor values for R1 and R2 that are four to ten times the bridge element resistance, the bridge is minimally loaded and the offset errors induced by the op amp stages are minimized. These resistors should have 1% tolerance, or better, for the best noise rejection and offset minimization. Referring once again to Figure 41, U2 is an additional gain stage with a thermistor element, RTH, in the feedback loop. It performs a temperature compensation function for the bridge so that it will have greater accuracy over a wide range of operational temperatures. With mangetoresistive sensors, temperature drift of the bridge sensitivity is negative and linear, and in the case of the sensor used here, is nominally -3000 PP/M. Thus the gain of U2 needs to increase proportionally with increasing temperature, suggesting a thermistor with a positive temperature coefficient. Selection of the temperature compensation resistor, RTH, depends on the additional gain required, on the thermistor chosen, and is dependent on the thermistor's %/C shift in resistance. For best op amp compatibility, the thermistor resistance should be greater than 1000 . RTH should also be much less than RA, the feedback resistor. Because the temperature coefficient of the AMR bridge is largely linear, RTH also needs to behave in a linear fashion with temperature, thus RA is placed in parallel with RTH, which acts to linearize the thermistor. 8.2.2.2.1 Gain Error and Bandwidth Consideration if Using an Analog to Digital Converter The bandwidth available from Figure 41 is dependent on the system closed loop gain required and the maximum gain-error allowed if driving an analog to digital converter (ADC). If the output from the sensor is intended to drive an ADC, the bandwidth will be considerably reduced from the closed-loop corner frequency. This is because the gain error of the pre-amplifier stage needs to be taken into account when calculating total error budget. Good practice dictates that the gain error of the amplifier be less than or equal to half LSB (preferably less in order to allow for other system errors that will eat up a portion of the available error budget) of the ADC. However, at the -3 dB corner frequency the gain error for any amplifier is 29.3%. In reality, the gain starts rolling off long before the -3 dB corner is reached. For example, if the amplifier is driving an 8-bit ADC, the minimum gain error allowed for half LSB would be approximately 0.2%. To achieve this gain error with the op amp, the maximum frequency of interest can be no higher than Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 21 LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 www.ti.com Typical Applications (continued) 1 1 - 2 n+1 (c) 1 (c) 2 - 1 x f-3 dB where * * n is the bit resolution of the ADC f-3 dB is the closed loop corner frequency. (5) Given that the LMV641 has a GBW of 10 MHz, and is operating with a closed loop gain of 26.3, its closed loop bandwidth is 380 kHZ, therefore 1 1 (c) 1 - 2 n+1 (c) MAX FREQ = 2 - 1 = 0.062 x f-3 dB = 0.062 x 380 kHz = 23.56 kHz (6) which is the highest frequency that can be measured with required accuracy. 8.2.3 Voiceband Filter The majority of the energy of recognizable speech is within a band of frequencies between 200 Hz and 4 kHz. Therefore, it is beneficial to design circuits which transmit telephone signals that pass only certain frequencies and eliminate unwanted signals (noise) that could interfere with conversations and introduce error into control signals. The pass band of these circuits is defined as the ranges of frequencies that are passed. A telephone system voice frequency (VF) channel has a pass band of 0 Hz to 4 kHz. Specifically for human voices most of the energy content is found from 300 Hz to 3 kHz and any signal within this range is considered an in-band signal. Alternatively, any signal outside this range but within the VF channel is considered an out-of-band signal. To properly recover a voice signal in applications such as cellular phones, cordless phones, and voice pagers, a low power bandpass filter that is matched to the human voice spectrum can be implemented using an LMV641 op amp. Figure 46 shows a multi-feedback, multi-pole filter (2nd order response) with a gain of -1. The lower 3 dB cutoff frequency which is set by the DC blocking capacitor C1 and resistor R1 is 60 Hz and the upper cutoff frequency is 3.5 kHz. The total current consumption is a mere 138 A. The LV641 is operating with a gain of -1, but the circuit is easily modified to add gain. The op amp is powered from a single supply, hence the need for offset (common-mode) adjustment of its output, which is set to 1/2 VS via its non-inverting input. This filter is also useful in applications for battery operated talking toys and games. R3 5.23 k: C3 2.2 nF VOICE IN C1 0.5 PF R1 5.23 k: VS R2 12.1 k: LMV641 C2 15 nF VOUT + VS/2 Figure 46. Low Power Voice In-Band Receive Filter for Battery-Powered Portable Use 22 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 9 Power Supply Recommendations For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For single supply, place a capacitor between V+ and V- supply leads. For dual supplies, place one capacitor between V+ and ground, and one capacitor between V- and ground. 10 Layout 10.1 Layout Guidelines To properly bypass the power supply, several locations on a printed circuit board need to be considered. A 6.8 F or greater tantalum capacitor should be placed at the point where the power supply for the amplifier is introduced onto the board. Another 0.1-F ceramic capacitor should be placed as close as possible to the power supply pin of the amplifier. If the amplifier is operated in a single power supply, only the V+ pin needs to be bypassed with a 0.1-F capacitor. If the amplifier is operated in a dual power supply, both V+ and V- pins need to be bypassed. It is good practice to use a ground plane on a printed-circuit board to provide all components with a low-inductive ground connection. 10.2 Layout Example Rf Cf V+ Cbyp GND OUTPUT GND INPUT Rin Figure 47. LMV641 Layout Example Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 23 LMV641 SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support For development support see the following: * LMV641 PSPICE Model * TINA-TI SPICE-Based Analog Simulation Program * DIP Adapter Evaluation Module * TI Universal Operational Amplifier Evaluation Module * TI Filterpro Software 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: * Absolute Maximum Ratings for Soldering (SNOA549) * AN-29 IC Op Amp Beats FETs on Input Current (SNOA624) * AN-31 Op Amp Circuit Collection (SNLA140) * AN-71 Micropower Circuits Using the LM4250 Programmable Op Amp (SNOA652) * AN-127 LM143 Monolithic High Voltage Operational Amplifier Applications (SNVA516) 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 24 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3D - SEPTEMBER 2007 - REVISED AUGUST 2016 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMV641 25 PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMV641MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV64 1MA LMV641MAE/NOPB ACTIVE SOIC D 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV64 1MA LMV641MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV64 1MA LMV641MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM AB9A LMV641MFE/NOPB ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM AB9A LMV641MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM AB9A LMV641MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A99 LMV641MGE/NOPB ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A99 LMV641MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A99 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2016 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jan-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMV641MAE/NOPB Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMV641MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMV641MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV641MFE/NOPB SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV641MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV641MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV641MGE/NOPB SC70 DCK 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV641MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jan-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV641MAE/NOPB SOIC D LMV641MAX/NOPB SOIC D 8 250 210.0 185.0 35.0 8 2500 367.0 367.0 35.0 LMV641MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV641MFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0 LMV641MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV641MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LMV641MGE/NOPB SC70 DCK 5 250 210.0 185.0 35.0 LMV641MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, "Designers") understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers' applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI's provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, "TI Resources") are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer's company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI's provision of TI Resources does not expand or otherwise alter TI's applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2018, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: LMV641MA/NOPB LMV641MAE/NOPB LMV641MAX/NOPB LMV641MG/NOPB LMV641MGE/NOPB LMV641MGX/NOPB LMV641MF/NOPB LMV641MFX/NOPB LMV641MFE/NOPB