Crystal Oscillator Circuit Design 2 Application Note
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In parallel resonance mode the crystal can be made to oscillate anywhere on the fs - fa slope of the reactance plot, shown
in Figure 2, by varying the load of the crystal. All of MX-COM’s crystal oscillator circuits recommend using parallel
resonant mode crystals.
Figure 3. shows the recommended Crystal oscillator circuit diagram. In this type of setup the crystal is expected to
oscillate in parallel resonant mode. The inverter which is internal to the chip acts as class AB amplifier and provides
approximately 180° phase shift from input to the output and the π network formed by the crystal, R1, C1 and C2 provides
additional 180° phase shift. So the total phase shift around the loop is 360°. This satisfies one of the conditions required to
sustain oscillation. The other condition, for proper startup and sustaining oscillation is the closed loop gain should be ≥1.
The resistor Rf around the inverter provides negative feedback and sets the bias point of the inverter near mid-supply
operating the inverter in the high gain linear region. The value of this resistor is high, usually in the range of a 500KΩ ~
2MΩ. Some of MXCOM’s ICs have this resistor internal, refer to the external component specifications in the data sheet of
a particular chip.
Internal to IC
Inverter
Rf
R1
C1
C2 Crystal
Figure 3. Crystal oscillator circuit.
The capacitors C1 and C2 form the load capacitance for the crystal. The optimum load capacitance (CL) for a given crystal
is specified by the crystal manufacturer. The equation to calculate the values of C1 and C2 is
CCC
CC C
LS
=
+
+
12
12
*
Where CS is the stray capacitance on the printed circuit board, typically a value of 5pf can be used for calculation
purposes. Now C1 and C2 can be selected to satisfy the above equation. Usually C1 and C2 are selected such that they
are approximately equal. Large values of C1 and/or C2 increases frequency stability but decreases loop gain and may
cause start-up problems.
R1 is the drive limiting resistor, the primary function of this resistor is to limit the output of the inverter so that the crystal is
not over driven. R1 and C1 form a voltage dividing circuit, the values of these components are chosen in such a way that
the output of the inverter goes close to rail-to-rail and the input to the crystal is 60% of rail-to-rail, usual practice is to make
resistance of R1 and reactance of C1 equal at the operating frequency, i.e. R1 ≈ XC1. This makes the input to the crystal
half that of the inverter output. Always make sure that the power dissipated by the crystal is with-in the crystal
manufacturer’s specifications. Over-driving the crystal may damage the crystal. Please refer to the crystal manufacturer’s
recommendations.
Ideally the inverter provides 180° phase shift, but the inherent delay of the inverter provides additional phase shift
proportional to the delay. In order to ensure the total phase shift of
n
360° around the loop, the π network should provide
180° less the phase shift due to the inverter delay. R1 can be varied to accomplish this. With fixed C1 and C2, the closed
loop gain and phase can be altered by varying R1. In some applications R1 can be ignored if the above two conditions are
met.