DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 1
© Copyright 2006–2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. All other trademarks are the property of their respective owners.
Virtex-4Q FPGA Electrical Characteristics
Defense-grade Virtex®-4Q FPGAs are available in -10
speed grade and are qualified for industrial (Tj= –40C to
+100C), and military (Tj= –55C to +125C) operational
temperatures. Some devices are also available using a -11
speed specification for industrial temperature only.
Defense-grade Virtex-4Q FPGA DC and AC characteristics
are specified for military and industrial grades only. Except
the operating temperature range or unless otherwise noted,
all the DC and AC electrical parameters are the same for a
particular speed grade (that is, the timing characteristics of
a -10 speed grade military device are the same as for a -10
speed grade industrial device).
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
This Defense-grade Virtex-4Q FPGA data sheet is part of
an overall set of documentation on the Virtex-4 family of
FPGAs available on the Xilinx website:
•DS112, Virtex-4 Family Overview
•UG070, Virtex-4 User Guide
•UG071, Virtex-4 FPGA Configuration Guide
•UG073, XtremeDSP for Virtex-4 FPGAs User Guide
•UG075, Virtex-4 Packaging and Pinout Specifications
•UG072, Virtex-4 FPGA PCB Designer’s Guide
All specifications are subject to change without notice.
Virtex-4Q FPGA DC Characteristics
Virtex-4Q FPGA Data Sheet:
DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 Product Specification
Table 1: Absolute Maximum Ratings(1)
Symbol Description Values Units
VCCINT Internal supply voltage relative to GND –0.5 to 1.32 V
VCCAUX Auxiliary supply voltage relative to GND –0.5 to 3.0 V
VCCO Output drivers supply voltage relative to GND –0.5 to 3.75 V
VBATT Key memory battery backup supply –0.5 to 4.05 V
VREF Input reference voltage –0.3 to 3.75 V
VIN
I/O input voltage relative to GND (all user and dedicated I/Os) –0.75 to 4.05 V
I/O input voltage relative to GND(3) (restricted to maximum of 100 user I/Os)(4) –0.85 to 4.3 V
2.5V or below I/O input voltage relative to GND (user and dedicated I/Os) –0.75 to VCCO +0.5 V
VTS
Voltage applied to 3-state 3.3V output(3) (all user and dedicated I/Os) –0.75 to 4.05 V
Voltage applied to 3-state 3.3V output(3) (restricted to maximum of 100 user I/Os)(4) –0.85 to 4.3 V
2.5V or below I/O input voltage relative to GND (user and dedicated I/Os) –0.75 to VCCO +0.5 V
VTRX Terminal receive supply voltage relative to GND –0.5 to 3.0 V
VTTX Terminal transmit supply voltage relative to GND –0.5 to 1.65 V
TSTG Storage temperature (ambient) –65 to 150 C
TSOL Maximum soldering temperature(2) +220 C
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 2
TjMaximum junction temperature(2) +125 C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. For soldering guidelines and thermal considerations, see the Virtex-4 Packaging and Pinout Specifications.
3. For 3.3V I/O operation, refer to the Virtex-4 User Guide, Chapter 6, 3.3V I/O Design Guidelines.
4. For more flexibility in specific designs, a maximum of 100 user I/O s can be stressed beyond the normal spec for no more than 20% of a data
period. There are no bank restrictions.
Tabl e 2 : Recommended Operating Conditions
Symbol Description Min Max Units
VCCINT Internal supply voltage relative to GND 1.14 1.26 V
VCCAUX Auxiliary supply voltage relative to GND 2.375 2.625 V
VCCO(1)(3)(4)(5) Supply voltage relative to GND 1.14 3.45 V
VIN
3.3V supply voltage relative to GND GND – 0.20 3.45 V
2.5V and below supply voltage relative to GND GND – 0.20 VCCO +0.2 V
VBATT(2) Battery voltage relative to GND 1.0 3.6 V
Notes:
1. Configuration data is retained even if VCCO drops to 0V.
2. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX.
3. For 3.3V I/O operation, refer to the Virtex-4 User Guide.
4. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
5. The configuration output supply voltage VCC_CONFIG is also known as VCCO_0.
Tabl e 3 : DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Typ Max Units
VDRINT Data retention VCCINT voltage
(below which configuration data might be lost) 0.9 – – V
VDRI Data retention VCCAUX voltage
(below which configuration data might be lost) 2.0 – – V
IREF VREF current per pin – – 10 µA
ILInput or output leakage current per pin (sample-tested) – – 10 µA
CIN Input capacitance (sample-tested) – – 10 pF
IRPU(1)
Pad pull-up (when selected) @ VIN =0V, V
CCO =3.3V 5 – 200 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =3.0V 5 – 125 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =2.5V 5 – 120 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =1.8V 5 – 60 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =1.5V 5 – 40 µA
IRPD(1) Pad pull-down (when selected) @ VIN =V
CCO 5–100µA
IBATT(1) Battery supply current – 75 –v nA
n Temperature diode ideality factor – 1.02 – n
r Series resistance – 2 –
Notes:
1. Typical values are specified at nominal voltage, 25°C.
Tabl e 1 : Absolute Maximum Ratings(1) (Cont’d)
Symbol Description Values Units
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 3
Tabl e 4 : Quiescent Supply Current
Symbol Description Device Typ(1)
Max Units
I-Grade M-Grade
ICCINTQ Quiescent VCCINT supply current
XQ4VLX25 – 139 Note 4 mA
XQ4VLX40 121 218 Note 4 mA
XQ4VLX60 167 301 Note 4 mA
XQ4VLX80 220 – Note 4 mA
XQ4VLX100 292 – Note 4 mA
XQ4VLX160 384 – Note 4 mA
XQ4VSX55 271 488 Note 4 mA
XQ4VFX60 203 365 Note 4 mA
XQ4VFX100 311 – Note 4 mA
ICCOQ Quiescent VCCO supply current
XQ4VLX25 – 2.50 Note 4 mA
XQ4VLX40 1.25 2.50 Note 4 mA
XQ4VLX60 1.5 3.00 Note 4 mA
XQ4VLX80 1.5 – Note 4 mA
XQ4VLX100 1.75 – Note 4 mA
XQ4VLX160 2.5 – Note 4 mA
XQ4VSX55 1.5 3.00 Note 4 mA
XQ4VFX60 1.5 3.00 Note 4 mA
XQ4VFX100 1.75 – Note 4 mA
ICCAUXQ Quiescent VCCAUX supply current
XQ4VLX25 – 54 Note 4 mA
XQ4VLX40 43 65 Note 4 mA
XQ4VLX60 74 111 Note 4 mA
XQ4VLX80 83 – Note 4 mA
XQ4VLX100 95 – Note 4 mA
XQ4VLX160 133 – Note 4 mA
XQ4VSX55 91 137 Note 4 mA
XQ4VFX60 80 120 Note 4 mA
XQ4VFX100 98 – Note 4 mA
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
3. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the Power Estimator or XPOWER
tool.
4. Use the XPower Estimator (XPE) tool to calculate maximum static power for specific process, voltage, and temperature conditions.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 4
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual
current consumed depends on the power-on ramp rate of the power supply.
The power supplies can be turned on in any sequence, though the specifications shown in Ta b l e 5 are for the recommended
power-on sequence of VCCINT
, VCCAUX, VCCO. Xilinx does not specify the current for other power-on sequences.
Ta bl e 5 shows the maximum current required by Virtex-4Q devices for proper power-on and configuration.
Once initialized and configured, use the XPOWER tool to estimate current drain on these supplies.
Tabl e 5 : Maximum Power-On Current for Virtex-4Q Devices
Device ICCINT ICCAUX ICCO Units
Typ (1) Max(2) Typ (1) Max(2) Typ (1) Max(2)
XQ4VLX25 220 2862 85 555 75 390 mA
XQ4VLX40 315 3150 110 705 75 390 mA
XQ4VLX60 300 3960 225 825 150 390 mA
XQ4VLX80 400 2550 280 350 150 275 mA
XQ4VLX100(3) 585 6912 335 1050 200 450 mA
XQ4VLX160(3) 855 8325 500 1238 250 600 mA
XQ4VSX55 520 5355 225 930 150 450 mA
XQ4VFX60 410 4680 220 1050 150 435 mA
XQ4VFX100 511 3300 278 500 200 300 mA
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Maximum values are specified under worst-case process, voltage, and military temperature conditions.
3. XQ4VLX100 and XQ4VLX160 are offered in I grade only. Values represent worst-case process, voltage and industrial temperature
operating conditions.
Tabl e 6 : Power Supply Ramp Time
Symbol Description Ramp Time Units
VCCINT Internal supply voltage relative to GND 0.20 to 50.0 ms
VCCO Output drivers supply voltage relative to GND 0.20 to 50.0 ms
VCCAUX Auxiliary supply voltage relative to GND 0.20 to 50.0 ms
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 5
SelectIO™ DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and
VOH voltage levels shown. Other standards are sample tested.
Tabl e 7 : Select I/O DC Input and Output Levels
IOSTANDARD
Attribute
VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
LVTTL –0.2 0.8 2.0 3.45 0.4 2.4 Note 3 Note 3
LVCMOS33 –0.2 0.8 2.0 3.45 0.4 VCCO –0.4 Note 3 Note 3
Note 6
LVCMOS25 –0.3 0.7 1.7 VCCO +0.3 0.4 V
CCO –0.4 Note 3 Note 3
LVCMOS18 –0.3 35% VCCO 65% VCCO VCCO +0.3 0.4 V
CCO –0.45 Note 4 Note 4
LVCMOS15 –0.3 35% VCCO 65% VCCO VCCO +0.3 0.4 V
CCO –0.45 Note 4 Note 4
Note 6
PCI33_3(5) –0.2 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO 1.5 –0.5
PCI66_3(5) –0.2 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO 1.5 –0.5
PCI-X(5) –0.2 35% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO 1.5 –0.5
GTLP –0.3 VREF –0.1 V
REF + 0.1 – 0.6 N/A 36 N/A
GTL –0.3 VREF –0.05 V
REF + 0.05 – 0.4 N/A 32 N/A
HSTL I(2) –0.3 VREF –0.1 V
REF +0.1 V
CCO +0.3 0.4 V
CCO –0.4 8 –8
HSTL II(2) –0.3 VREF –0.1 V
REF +0.1 V
CCO +0.3 0.4 V
CCO –0.4 16 –16
HSTL III(2) –0.3 VREF –0.1 V
REF +0.1 V
CCO +0.3 0.4 V
CCO – 0.4 24 –8
HSTL IV(2) –0.3 VREF –0.1 V
REF +0.1 V
CCO +0.3 0.4 V
CCO – 0.4 48 –8
DIFF HSTL II(2) –0.3 50% VCCO –0.1 50% V
CCO +0.1 V
CCO +0.3 0.4 V
CCO –0.4 – –
SSTL2 I –0.3 VREF –0.15 V
REF +0.15 V
CCO +0.3 V
TT –0.61 V
TT + 0.61 8.1 –8.1
SSTL2 II –0.3 VREF –0.15 V
REF +0.15 V
CCO +0.3 V
TT –0.81 V
TT + 0.81 16.2 –16.2
DIFF SSTL2 II –0.3 50% VCCO – 0.15 50% VCCO +0.15 V
CCO +0.3 0.5 V
CCO –0.5 – –
SSTL18 I –0.3 VREF – 0.125 VREF +0.125 V
CCO +0.3 V
TT –0.47 V
TT + 0.47 6.7 –6.7
SSTL18 II –0.3 VREF – 0.125 VREF +0.125 V
CCO +0.3 V
TT –0.60 V
TT + 0.60 13.4 –13.4
DIFF SSTL18 II –0.3 50% VCCO – 0.125 50% VCCO +0.125 V
CCO +0.3 0.4 V
CCO –0.4 – –
Notes:
1. Tested according to relevant specifications.
2. Applies to both 1.5V and 1.8V HSTL.
3. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
4. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
5. For more information on PCI33_3, PCI66_3, and PCI-X refer to the Virtex-4 FPGA User Guide, SelectIO Resources, Chapter 6.
6. LVCMOS15 4 mA, LVCMOS33 6 mA, LVCMOS33 8 mA have reduced drive strength (IOH) by 20%.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 6
LDT DC Specifications (LDT_25)
LVDS DC Specifications (LVDS_25)
Tabl e 8 : LDT DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply Voltage 2.38 2.5 2.63 V
VOD Differential Output Voltage(1)(2) RT = 100 across Q and Q signals 495 600 750 mV
VOD Change in VOD Magnitude –15 15 mV
VOCM Output Common Mode Voltage RT = 100 across Q and Q signals 495 600 715 mV
VOCM Change in VOCM Magnitude –15 15 mV
VID Input Differential Voltage 200 600 1000 mV
VID Change in VID Magnitude –15 15 mV
VICM Input Common Mode Voltage 440 600 780 mV
VICM Change in VICM Magnitude –15 15 mV
Notes:
1. Recommended input maximum voltage not to exceed VCCO +0.2V.
2. Recommended input minimum voltage not to go below –0.5V.
Tabl e 9 : LVDS DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply Voltage 2.38 2.5 2.63 V
VOH Output High Voltage for Q and Q RT = 100 across Q and Q signals 1.602 V
VOL Output Low Voltage for Q and Q RT = 100 across Q and Q signals 0.898 V
VODIFF Differential Output Voltage(1)(2) (Q – Q),
Q = High (Q –Q), Q = High RT = 100 across Q and Q signals 247 350 550 mV
VOCM Output Common-Mode Voltage RT = 100 across Q and Q signals 1.100 1.250 1.375 V
VIDIFF Differential Input Voltage (Q – Q),
Q = High (Q –Q), Q = High 100 350 600 mV
VICM Input Common-Mode Voltage 0.3 1.2 2.2 V
Notes:
1. Recommended input maximum voltage not to exceed VCCO +0.2V.
2. Recommended input minimum voltage not to go below –0.5V.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 7
Extended LVDS DC Specifications (LVDSEXT_25)
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100 differential load only, for example, a 100 resistor between the two receiver
pins. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower
common-mode ranges. Ta bl e 1 1 summarizes the DC output specifications of LVPECL. For more information on using
LVPECL, see the Virtex-4 FPGA User Guide, Chapter 6, SelectIO Resources.
Tabl e 1 0 : Extended LVDS DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply Voltage 2.38 2.5 2.63 V
VOH Output High Voltage for Q and Q RT = 100 across Q and Q signals – – 1.785 V
VOL Output Low Voltage for Q and Q RT = 100 across Q and Q signals 0.715 – – V
VODIFF Differential Output Voltage (Q – Q),
Q = High (Q –Q), Q = High RT = 100 across Q and Q signals 380 – 820 mV
VOCM Output Common-Mode Voltage RT = 100 across Q and Q signals 1.000 1.250 1.375 V
VIDIFF Differential Input Voltage(1)(2) (Q – Q),
Q = High (Q –Q), Q = High Common-mode input voltage = 1.25V 100 – 1000 mV
VICM Input Common-Mode Voltage Differential input voltage = ±350 mV 0.3 1.2 2.2 V
Notes:
1. Recommended input maximum voltage not to exceed VCCO +0.2V.
2. Recommended input minimum voltage not to go below –0.5V.
Tabl e 1 1 : LVPECL DC Specifications
Symbol DC Parameter Min Typ Max Units
VOH Output High Voltage VCC – 1.025 1.545 VCC –0.88 V
VOL Output Low Voltage VCC – 1.81 0.795 VCC –1.62 V
VICM Input Common-Mode Voltage 0.6 2.2 V
VIDIFF Differential Input Voltage(1)(2) 0.100 1.5 V
Notes:
1. Recommended input maximum voltage not to exceed VCCO +0.2V.
2. Recommended input minimum voltage not to go below –0.5V.
X-Ref Target - Figure 1
Figure 1: Single-Ended Output Voltage Swing
X-Ref Target - Figure 2
Figure 2: Peak-to-Peak Differential Output Voltage
0
+V TXP
TXN DVOUT
DS595_01_111406
0
+V
–V
TXP–TXN
DV
PPOUT
DS595_02_111406
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 8
Interface Performance Characteristics
Switching Characteristics
Switching characteristics are specified on a per-speed grade basis and can be designated as Advance, Preliminary, or
Production. Each designation is defined as follows:
Advance Product Specification
These specifications are based on simulations only and are typically available soon after device design specifications are
frozen. Although speed grades with this designation are considered relatively stable and conservative, some
under-reporting might still occur.
Preliminary Product Specification
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades
with this designation are intended to give a better indication of the expected performance of production silicon. The
probability of under-reporting delays is greatly reduced as compared to Advance data.
Production Product Specification
These specifications are released once enough production silicon of a particular device family member has been
characterized to provide full correlation between specifications and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest
speed grades transition to Production before faster speed grades.
Speed Specification Designations by Device
Since individual family members are produced at different times, the migration from one category to another depends
completely on the status of the fabrication process for each device.
All specifications are always representative of worst-case supply voltage and junction temperature conditions.
Ta bl e 1 3 correlates the current status of each Virtex-4Q device on a per speed grade basis.
Tabl e 1 2 : Interface Performances
Description Speed Grade
-11 -10
Networking Applications
SFI-4.1 (SDR LVDS Interface)(1)(7) 710 MHz 644 MHz
SPI-4.2 (DDR LVDS Interface)(2) 1 Gb/s 800 Mb/s
Memory Interfaces
DDR(3) 426 Mb/s 426 Mb/s
DDR2(4) 510 Mb/s 510 Mb/s
QDR II SRAM(5) 514 Mb/s 514 Mb/s
RLDRAM II(6) 524 Mb/s 524 Mb/s
Notes:
1. Performance defined using design implementation described in application note XAPP704, Virtex-4 High-Speed SDR LVDS Transceiver.
2. Performance defined using design implementation described in application note XAPP700, Dynamic Phase Alignment for Networking
Applications or XAPP705, Virtex-4 High-Speed DDR LVDS Transceiver.
3. Performance defined using design implementation described in application note XAPP709, DDR SDRAM Controller Using Virtex-4 Devices.
4. Performance defined using design implementation described in application note XAPP702, DDR2 Controller Using Virtex-4 Devices.
5. Performance defined using design implementation described in application note XAPP703, QDR II SRAM Interface for Virtex-4 Devices.
6. Performance defined using design implementation described in application note XAPP710, Synthesizable CIO DDR RLDRAM II Controller
for Virtex-4 FPGAs.
7. Maximum frequency of 500 MHz for operation beyond industrial temperature range.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 9
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed
below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotate to the simulation net list. Unless
otherwise noted, values apply to all Virtex-4 FPGAs.
Production Silicon and ISE Software Status
Ta bl e 1 4 lists the production released Virtex-4Q family member, speed grade, and the minimum corresponding supported
speed specification version and ISE® software revisions. The ISE software and speed specifications listed are the minimum
releases required for production. All subsequent releases of software and speed specifications are valid.
Tabl e 1 3 : Virtex-4Q Device Speed Grade Designations
Device Speed Grade Designations
Advance Preliminary Production
XQ4VLX25 -10(M)
XQ4VLX40 -10(M), -10(I)
XQ4VLX60 -10(M)
XQ4VLX80 -11(I)
XQ4VLX100 -11(I), -10(I)
XQ4VLX160 -10(I)
XQ4VSX55 -10(M)
XQ4VFX60 -10(M), -10(I)
XQ4VFX100 -11(I)
Tabl e 1 4 : Virtex-5 Device Production Software and Speed Specification Release
Device Speed Grade Designations
-11(I) -10(I) -10(M)
XQ4VLX25 N/A N/A ISE 9.2 v1.67
XQ4VLX40 N/A ISE 9.2 v1.67 ISE 9.2 v1.67
XQ4VLX60 N/A N/A ISE 9.2 v1.67
XQ4VLX80 ISE 14.1 v1.71 N/A N/A
XQ4VLX100 ISE 14.1 v1.71 ISE 9.2 v1.67 N/A
XQ4VLX160 N/A ISE 9.2 v1.67 N/A
XQ4VSX55 N/A N/A ISE 9.2 v1.67
XQ4VFX60 N/A ISE 9.2 v1.67 ISE 9.2 v1.67
XQ4VFX100 ISE 14.1 v1.71 N/A N/A
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 10
PowerPC Switching Characteristics
Consult UG018, PowerPC® 405 Processor Block Reference Guide for further information.
Tabl e 1 5 : PowerPC 405 Processor Clocks Absolute AC Characteristics
Description
Speed Grade
Units-11 -10
Min Max Min Max
Characteristics when APU Not Used
CPMC405CLOCK frequency(1)(4) 04000350MHz
CPMDCRCLK(3) 04000350MHz
CPMFCMCLK(3) ––––MHz
JTAGC405TCK frequency(2) 02000175MHz
PLBCLK(3) 04000350MHz
BRAMDSOCMCLK(3) 04000350MHz
BRAMISOCMCLK(3) 04000350MHz
Characteristics when APU Used
CPMC405CLOCK frequency(1)(4) 02750233MHz
CPMDCRCLK(3) 02750233MHz
CPMFCMCLK(3) 02750233MHz
JTAGC405TCK frequency(2) 0137.50116.5MHz
PLBCLK(3) 02750233MHz
BRAMDSOCMCLK(3) 02750233MHz
BRAMISOCMCLK(3) 02750233MHz
Notes:
1. Worst-case DCM output clock jitter is included in these specifications.
2. The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is system dependent,
and will be much less.
3. The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. Integer clock ratios are required for the
CPMC405CLOCK and BRAMDSOCMCLK, CPMC405CLOCK and BRAMISOCMCLK, CPMC405CLOCK and CPMDCRCLK,
CPMC405CLOCK and CPMFCMCLK, and CPMC405CLOCK and PLBCLK. The integer ratios can be different for each interface. However,
the achievable maximum is system dependent.
4. Maximum operating frequency of CPMC405CLOCK is specified with the input pin TIEC405DISOPERANDFWD connected to a logic 1.
Tabl e 1 6 : Processor Block Switching Characteristics
Description Symbol Speed Grade Units
-11 -10
Setup and Hold Relative to Clock (CPMC405CLOCK)
Clock and Power Management control inputs TPPCDCK_CORECKI
TPPCCKD_CORECKI 0.65/0.20 0.74/0.23 ns Min
Reset control inputs TPPCDCK_RSTCHIP
TPPCCKD_RSTCHIP 0.65/0.20 0.74/0.23 ns Min
Debug control inputs TPPCDCK_EXBUSHAK
TPPCCKD_EXBUSHAK 0.65/0.20 0.74/0.23 ns Min
Trace control inputs TPPCDCK_TRCDIS
TPPCCKD_TRCDIS 0.65/0.20 0.74/0.23 ns Min
External Interrupt Controller control inputs TPPCDCK_CINPIRQ
TPPCCKD_CINPIRQ 1.15/0.20 1.40/0.23 ns Min
Clock to Out
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 11
Clock and Power Management control outputs TPPCCKO_CORESLP 1.51 1.74 ns Max
Reset control outputs TPPCCKO_RSTCHIP 1.59 1.83 ns Max
Debug control outputs TPPCCKO_DBGLDAPU 1.48 1.70 ns Max
Trace control outputs TPPCCKO_TRCCYCLE 1.68 1.83 ns Max
Clock
CPMC405CLOCK minimum pulse width, High TCPWH 1.25 1.43 ns Min
CPMC405CLOCK minimum pulse width, Low TCPWL 1.25 1.43 ns Min
Tabl e 1 7 : Processor Block PLB Switching Characteristics
Description Symbol Speed Grade Units
-11 -10
Setup and Hold Relative to Clock (PLBCLK)
Processor Local Bus (ICU/DCU) control inputs TPPCDCK_ICUBUSY
TPPCCKD_ICUBUSY 0.66/0.20 0.76/0.23 ns Min
Processor Local Bus (ICU/DCU) data inputs TPPCDCK_ICURDDB
TPPCCKD_ICURDDB 1.00/0.20 1.15/0.23 ns Min
Clock to Out
Processor Local Bus (ICU/DCU) control outputs TPPCCKO_DCUABORT 1.78 2.05 ns Max
Processor Local Bus (ICU/DCU) address bus outputs TPPCCKO_ICUABUS 1.85 2.13 ns Max
Processor Local Bus (ICU/DCU) data bus outputs TPPCCKO_DCUWRDBUS 2.24 2.57 ns Max
Tabl e 1 8 : Processor Block JTAG Switching Characteristics
Description Symbol Speed Grade Units
-11 -10
Setup and Hold Relative to Clock (JTAGC405TCK)
JTAG control inputs TPPCDCK_JTGTDI
TPPCCKD_JTGTDI 1.29/0.20 1.48/0.23 ns Min
JTAG reset input TPPCDCK_JTGTRSTN
TPPCCKD_JTGTRSTN 0.65/0.20 0.74/0.23 ns Min
Clock to Out
JTAG control outputs TPPCCKO_JTGTDO 1.79 2.14 ns Max
Tabl e 1 9 : PowerPC 405 Data-Side On-Chip Memory Switching Characteristics
Description Symbol Speed Grade Units
-11 -10
Setup and Hold Relative to Clock (BRAMDSOCMCLK)
Data-Side On-Chip Memory data bus inputs TPPCDCK_DSOCMRDDB
TPPCCKD_DSOCMRDDB 0.65/0.20 0.74/0.23 ns Min
Clock to Out
Data-Side On-Chip Memory control outputs TPPCCKO_BRAMBWR 2.30 2.65 ns Max
Data-Side On-Chip Memory address bus outputs TPPCCKO_BRAMABUS 2.30 2.65 ns Max
Data-Side On-Chip Memory data bus outputs TPPCCKO_IBRAMWRDBUS01 1.79 2.06 ns Max
Tabl e 1 6 : Processor Block Switching Characteristics (Cont’d)
Description Symbol Speed Grade Units
-11 -10
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 12
Tabl e 2 0 : PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics
Description Symbol Speed Grade Units
-11 -10
Setup and Hold Relative to Clock (BRAMISOCMCLK)
Instruction-Side On-Chip Memory data bus inputs TPPCDCK_ISOCMRDDB
TPPCCKD_ISOCMRDDB 0.82/0.20 0.94/0.23 ns Min
Clock to Out
Instruction-Side On-Chip Memory control outputs TPPCCKO_IBRAMEN 3.37 3.88 ns Max
Instruction-Side On-Chip Memory address bus outputs TPPCCKO_IBRAMRDABUS 1.85 2.13 ns Max
Instruction-Side On-Chip Memory data bus outputs TPPCCKO_IBRAMWRDBUS 1.86 2.14 ns Max
Tabl e 2 1 : Processor Block DCR Bus Switching Characteristics
Description Symbol Speed Grade Units
-11 -10
Setup and Hold Relative to Clock (CPMDCRCLOCK)
Device Control Register Bus control inputs TPPCDCK_EXDCRACK
TPPCCKD_EXDCRACK 0.13/0.17 0.15/0.19 ns Min
Device Control Register Bus data inputs TPPCDCK_EXDCRDBUSI
TPPCCKD_EXDCRDBUSI 0.57/0.16 1.02/0.27 ns Min
Clock to Out
Device Control Register Bus control outputs TPPCCKO_EXDCRRD 1.35 1.54 ns Max
Device Control Register Bus address bus outputs TPPCCKO_EXDCRABUS 1.45 1.66 ns Max
Device Control Register Bus data bus outputs TPPCCKO_EXDCRDBUSO 1.45 1.67 ns Max
Tabl e 2 2 : Processor Block APU Interface Switching Characteristics
Description Symbol Speed Grade Units
-11 -10
Setup and Hold Relative to Clock (CPMDFCMCLOCK)
APU bus control inputs TPPCDCK_DCDCREN
TPPCCKD_DCDCREN 0.36/0.20 0.42/0.23 ns Min
APU bus data inputs TPPCDCK_RESULT
TPPCCKD_RESULT 0.67/0.20 0.78/0.23 ns Min
Clock to Out
APU bus control outputs TPPCCKO_APUFCMDEC 1.75 2.00 ns Max
APU bus data outputs TPPCCKO_RADATA 1.75 2.00 ns Max
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 13
IOB Pad Input/Output/3-State Switching Characteristics
Table 23, page 13 summarizes the values of standard-specific data input delay adjustments, output delays terminating at
pads (based on standard and 3-state delays.
TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending
on the capability of the SelectIO™ input buffer.
TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
depending on the capability of the SelectIO output buffer.
TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO capability of the output buffer.
Table 25, page 18 summarizes the value of TIOTPHZ. TIOTPHZ is described as the delay from the T pin to the IOB pad through
the output buffer of an IOB pad, when 3-state is enabled (for example, a high-impedance state).
Tabl e 2 3 : IOB Switching Characteristics(1)(2)
IOSTANDARD Attribute(1)
Speed Grade
Units-11 -10
TIOPI TIOOP TIOTP TIOPI TIOOP TIOTP
LVDS_25 1.15 1.71 1.71 1.28 1.85 1.85 ns
RSDS_25 1.15 1.71 1.71 1.28 1.85 1.85 ns
LVDSEXT_25 1.16 1.75 1.75 1.30 1.91 1.91 ns
LDT_25 1.15 1.68 1.68 1.28 1.82 1.82 ns
BLVDS_25 1.15 2.15 2.15 1.28 2.34 2.34 ns
ULVDS_25 1.15 1.68 1.68 1.28 1.83 1.83 ns
PCI33_3 (PCI®, 33 MHz, 3.3V) 0.87 2.76 2.76 0.97 3.02 3.02 ns
PCI66_3 (PCI, 66 MHz, 3.3V) 0.87 2.46 2.46 0.97 2.72 2.72 ns
PCI-X (PCI-X) 0.87 2.21 2.21 0.97 2.25 2.25 ns
GTL 1.47 1.87 1.87 1.63 2.03 2.03 ns
GTLP 1.51 1.87 1.87 1.68 2.03 2.03 ns
HSTL_I 1.47 2.16 2.16 1.64 2.35 2.35 ns
HSTL_II 1.47 1.96 1.96 1.64 2.13 2.13 ns
HSTL_III 1.47 2.04 2.04 1.64 2.22 2.22 ns
HSTL_IV 1.47 1.87 1.87 1.64 2.03 2.03 ns
HSTL_I _18 1.44 2.03 2.03 1.60 2.21 2.21 ns
HSTL_II _18 1.44 1.98 1.98 1.60 2.16 2.16 ns
HSTL_III _18 1.44 1.93 1.93 1.60 2.09 2.09 ns
HSTL_IV_18 1.44 1.89 1.89 1.60 2.06 2.06 ns
SSTL2_I 1.51 2.23 2.23 1.68 2.43 2.43 ns
SSTL2_II 1.51 1.98 1.98 1.68 2.16 2.16 ns
LVTTL, Slow, 2 mA 0.87 6.37 6.37 0.97 7.03 7.03 ns
LVTTL, Slow, 4 mA 0.87 4.57 4.57 0.97 5.04 5.04 ns
LVTTL, Slow, 6 mA 0.87 4.46 4.46 0.97 4.91 4.91 ns
LVTTL, Slow, 8 mA 0.87 4.46 4.46 0.97 4.91 4.91 ns
LVTTL, Slow, 12 mA 0.87 3.61 3.61 0.97 3.96 3.96 ns
LVTTL, Slow, 16 mA 0.87 3.61 3.61 0.97 3.46 3.46 ns
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 14
LVTTL, Slow, 24 mA 0.87 2.85 2.85 0.97 3.12 3.12 ns
LVTTL, Fast, 2 mA 0.87 4.41 4.41 0.97 4.86 4.86 ns
LVTTL, Fast, 4 mA 0.87 3.16 3.16 0.97 3.46 3.46 ns
LVTTL, Fast, 6 mA 0.87 2.74 2.74 0.97 3.00 3.00 ns
LVTTL, Fast, 8 mA 0.87 2.55 2.55 0.97 2.79 2.79 ns
LVTTL, Fast, 12 mA 0.87 2.26 2.26 0.97 2.47 2.47 ns
LVTTL, Fast, 16 mA 0.87 2.26 2.26 0.97 2.47 2.47 ns
LVTTL, Fast, 24 mA 0.87 2.02 2.02 0.97 2.20 2.20 ns
LVCMOS33, Slow, 2 mA 0.87 7.88 7.88 0.97 8.73 8.73 ns
LVCMOS33, Slow, 4 mA 0.87 5.52 5.52 0.97 6.09 6.09 ns
LVCMOS33, Slow, 6 mA 0.87 4.54 4.54 0.97 5.00 5.00 ns
LVCMOS33, Slow, 8 mA 0.87 3.59 3.59 0.97 3.95 3.95 ns
LVCMOS33, Slow, 12 mA 0.87 3.11 3.11 0.97 3.42 3.42 ns
LVCMOS33, Slow, 16 mA 0.87 2.28 2.28 0.97 2.49 2.49 ns
LVCMOS33, Slow, 24 mA 0.87 2.28 2.28 0.97 2.49 2.49 ns
LVCMOS33, Fast, 2 mA 0.87 6.73 6.73 0.97 7.44 7.44 ns
LVCMOS33, Fast, 4 mA 0.87 3.93 3.93 0.97 4.33 4.33 ns
LVCMOS33, Fast, 6 mA 0.87 3.23 3.23 0.97 3.55 3.55 ns
LVCMOS33, Fast, 8 mA 0.87 2.25 2.25 0.97 2.46 2.46 ns
LVCMOS33, Fast, 12 mA 0.87 2.08 2.08 0.97 2.27 2.27 ns
LVCMOS33, Fast, 16 mA 0.87 1.91 1.91 0.97 2.08 2.08 ns
LVCMOS33, Fast, 24 mA 0.87 1.91 1.91 0.97 2.08 2.08 ns
LVCMOS25, Slow, 2 mA 0.80 5.34 5.34 0.88 5.89 5.89 ns
LVCMOS25, Slow, 4 mA 0.80 4.56 4.56 0.88 5.02 5.02 ns
LVCMOS25, Slow, 6 mA 0.80 3.92 3.92 0.88 4.31 4.31 ns
LVCMOS25, Slow, 8 mA 0.80 3.92 3.92 0.88 4.31 4.31 ns
LVCMOS25, Slow, 12 mA 0.80 3.19 3.19 0.88 3.50 3.50 ns
LVCMOS25, Slow, 16 mA 0.80 3.02 3.02 0.88 3.31 3.31 ns
LVCMOS25, Slow, 24 mA 0.80 2.54 2.54 0.88 2.77 2.77 ns
LVCMOS25, Fast, 2 mA 0.80 3.54 3.54 0.88 3.89 3.89 ns
LVCMOS25, Fast, 4 mA 0.80 2.92 2.92 0.88 3.19 3.19 ns
LVCMOS25, Fast, 6 mA 0.80 2.57 2.57 0.88 2.81 2.81 ns
LVCMOS25, Fast, 8 mA 0.80 2.31 2.31 0.88 2.52 2.52 ns
LVCMOS25, Fast, 12 mA 0.80 2.23 2.23 0.88 2.43 2.43 ns
LVCMOS25, Fast, 16 mA 0.80 2.03 2.03 0.88 2.21 2.21 ns
LVCMOS25, Fast, 24 mA 0.80 1.96 1.96 0.88 2.13 2.13 ns
LVCMOS18, Slow, 2 mA 1.12 5.34 5.34 1.25 5.89 5.89 ns
LVCMOS18, Slow, 4 mA 1.12 3.95 3.95 1.25 4.35 4.35 ns
Tabl e 2 3 : IOB Switching Characteristics(1)(2) (Cont’d)
IOSTANDARD Attribute(1)
Speed Grade
Units-11 -10
TIOPI TIOOP TIOTP TIOPI TIOOP TIOTP
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 15
LVCMOS18, Slow, 6 mA 1.12 3.64 3.64 1.25 4.00 4.00 ns
LVCMOS18, Slow, 8 mA 1.12 3.42 3.42 1.25 3.76 3.76 ns
LVCMOS18, Slow, 12 mA 1.12 3.41 3.41 1.25 3.74 3.74 ns
LVCMOS18, Slow, 16 mA 1.12 3.24 3.24 1.25 3.55 3.55 ns
LVCMOS18, Fast, 2 mA 1.12 3.54 3.54 1.25 3.89 3.89 ns
LVCMOS18, Fast, 4 mA 1.12 2.75 2.75 1.25 3.02 3.02 ns
LVCMOS18, Fast, 6 mA 1.12 2.49 2.49 1.25 2.72 2.72 ns
LVCMOS18, Fast, 8 mA 1.12 2.31 2.31 1.25 2.52 2.52 ns
LVCMOS18, Fast, 12 mA 1.12 2.17 2.17 1.25 2.36 2.36 ns
LVCMOS18, Fast, 16 mA 1.12 2.09 2.09 1.25 2.27 2.27 ns
LVCMOS15, Slow, 2 mA 1.20 5.99 5.99 1.34 6.61 6.61 ns
LVCMOS15, Slow, 4 mA 1.20 4.70 4.70 1.34 4.88 4.88 ns
LVCMOS15, Slow, 6 mA 1.20 3.87 3.87 1.34 4.26 4.26 ns
LVCMOS15, Slow, 8 mA 1.20 3.87 3.87 1.34 4.26 4.26 ns
LVCMOS15, Slow, 12 mA 1.20 3.43 3.43 1.34 3.77 3.77 ns
LVCMOS15, Slow, 16 mA 1.20 3.21 3.21 1.34 3.53 3.53 ns
LVCMOS15, Fast, 2 mA 1.20 3.79 3.79 1.34 4.17 4.17 ns
LVCMOS15, Fast, 4 mA 1.20 3.03 3.03 1.34 3.32 3.32 ns
LVCMOS15, Fast, 6 mA 1.20 2.69 2.69 1.34 2.94 2.94 ns
LVCMOS15, Fast, 8 mA 1.20 2.48 2.48 1.34 2.71 2.71 ns
LVCMOS15, Fast, 12 mA 1.20 2.29 2.29 1.34 2.50 2.50 ns
LVCMOS15, Fast, 16 mA 1.20 2.23 2.23 1.34 2.43 2.43 ns
LVDCI_33 0.87 2.86 2.86 0.97 3.13 3.13 ns
LVDCI_25 0.80 2.76 2.76 0.88 3.02 3.02 ns
LVDCI_18 1.12 2.69 2.69 1.25 2.95 2.95 ns
LVDCI_15 1.20 2.68 2.68 1.34 2.93 2.93 ns
LVDCI_DV2_25 0.80 2.08 2.08 0.88 2.27 2.27 ns
LVDCI_DV2_18 1.12 2.09 2.09 1.25 2.28 2.28 ns
LVDCI_DV2_15 1.20 2.36 2.36 1.34 2.58 2.58 ns
GTL_DCI 1.36 1.87 1.87 1.51 2.03 2.03 ns
GTLP_DCI 1.11 1.87 1.87 1.23 2.03 2.03 ns
HSTL_I_DCI 1.47 2.16 2.16 1.64 2.35 2.35 ns
HSTL_II_DCI 1.47 1.96 1.96 1.64 2.13 2.13 ns
HSTL_III_DCI 1.47 2.04 2.04 1.64 2.22 2.22 ns
HSTL_IV_DCI 1.47 1.87 1.87 1.64 2.03 2.03 ns
HSTL_I_DCI_18 1.44 2.03 2.03 1.60 2.21 2.21 ns
HSTL_II_DCI_18 1.44 1.98 1.98 1.60 2.16 2.16 ns
HSTL_III_DCI_18 1.44 1.93 1.93 1.60 2.09 2.09 ns
Tabl e 2 3 : IOB Switching Characteristics(1)(2) (Cont’d)
IOSTANDARD Attribute(1)
Speed Grade
Units-11 -10
TIOPI TIOOP TIOTP TIOPI TIOOP TIOTP
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 16
HSTL_IV_DCI_18 1.44 1.89 1.89 1.60 2.06 2.06 ns
SSTL2_I_DCI 1.51 2.25 2.25 1.68 2.46 2.46 ns
SSTL2_II_DCI 1.51 2.24 2.24 1.68 2.45 2.45 ns
LVPECL_25 1.59 1.61 1.61 1.77 1.74 1.74 ns
SSTL18_I 1.51 2.33 2.33 1.68 2.54 2.54 ns
SSTL18_II 1.51 2.06 2.06 1.68 2.24 2.24 ns
SSTL18_I_DCI 1.51 2.12 2.12 1.68 2.32 2.32 ns
SSTL18_II_DCI 1.51 2.00 2.00 1.68 2.18 2.18 ns
Notes:
1. The I/O standard is selected in the Xilinx ISE® software using the IOSTANDARD attribute.
2. All I/O timing specifications are measured with VCCO at –5% from nominal.
Tabl e 2 4 : TIOOP and TIOTP Offset for 125°C Operation
IOSTANDARD Attribute
Speed Grade
Units-10
I-Grade M-Grade Delta
LVD S 1.85 2.23 0.38 ns
RSDS 1.85 2.23 0.38 ns
LVDSEXT 1.91 2.25 0.34 ns
LDT 1.82 2.23 0.41 ns
PCI33_3 3.02 3.26 0.24 ns
PCI66_3 2.72 3.26 0.54 ns
PCIX 2.25 2.49 0.24 ns
GTL 2.03 2.27 0.24 ns
GTLP 2.03 2.25 0.22 ns
HSTL_I 2.35 2.54 0.19 ns
HSTL_II 2.13 2.47 0.34 ns
HSTL_III 2.22 2.55 0.33 ns
HSTL_IV 2.03 2.43 0.40 ns
HSTL_I_18 2.21 2.43 0.22 ns
HSTL_II_18 2.16 2.39 0.23 ns
HSTL_III_18 2.09 2.40 0.31 ns
HSTL_IV_18 2.06 2.38 0.32 ns
SSTL2_I 2.43 2.46 0.03 ns
SSTL2_II 2.16 2.27 0.11 ns
LVTTL_S2 7.03 9.95 2.92 ns
LVTTL_S4 5.04 7.84 2.80 ns
LVTTL_S6 4.91 6.67 1.76 ns
LVTTL_S8 4.91 6.40 1.49 ns
Tabl e 2 3 : IOB Switching Characteristics(1)(2) (Cont’d)
IOSTANDARD Attribute(1)
Speed Grade
Units-11 -10
TIOPI TIOOP TIOTP TIOPI TIOOP TIOTP
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 17
LVTTL_S12 3.96 4.87 0.91 ns
LVTTL_S16 3.46 4.42 0.96 ns
LVTTL_S24 3.12 3.24 0.12 ns
LVTTL_F2 4.86 8.44 3.58 ns
LVTTL_F4 3.46 6.41 2.95 ns
LVTTL_F6 3.00 4.76 1.76 ns
LVTTL_F8 2.79 3.97 1.18 ns
LVTTL_F12 2.47 2.92 0.45 ns
LVTTL_F16 2.47 2.93 0.46 ns
LVTTL_F24 2.20 2.87 0.67 ns
LVCMOS33_S2 8.73 11.43 2.70 ns
LVCMOS33_S4 6.09 8.56 2.47 ns
LVCMOS33_S6 5.00 7.27 2.27 ns
LVCMOS33_S8 3.95 6.35 2.40 ns
LVCMOS33_S12 3.42 4.74 1.32 ns
LVCMOS33_S16 2.49 4.56 2.07 ns
LVCMOS33_S24 2.49 3.06 0.57 ns
LVCMOS33_F2 7.44 10.18 2.74 ns
LVCMOS33_F4 4.33 6.18 1.85 ns
LVCMOS33_F6 3.55 5.53 1.98 ns
LVCMOS33_F8 2.46 4.47 2.01 ns
LVCMOS33_F12 2.27 3.22 0.95 ns
LVCMOS33_F16 2.08 2.74 0.66 ns
LVCMOS33_F24 2.08 2.61 0.53 ns
LVCMOS25_S2 5.89 8.57 2.68 ns
LVCMOS25_S4 5.02 6.44 1.42 ns
LVCMOS25_S6 4.31 6.00 1.69 ns
LVCMOS25_S8 4.31 5.24 0.93 ns
LVCMOS25_S12 3.50 4.30 0.80 ns
LVCMOS25_S16 3.31 3.95 0.64 ns
LVCMOS25_S24 2.77 2.64 -0.13 ns
LVCMOS25_F2 3.89 7.97 4.08 ns
LVCMOS25_F4 3.19 4.99 1.80 ns
LVCMOS25_F6 2.81 3.92 1.11 ns
LVCMOS25_F8 2.52 3.29 0.77 ns
LVCMOS25_F12 2.43 2.43 0.00 ns
LVCMOS25_F16 2.21 2.39 0.18 ns
LVCMOS25_F24 2.13 2.39 0.26 ns
Tabl e 2 4 : TIOOP and TIOTP Offset for 125°C Operation (Cont’d)
IOSTANDARD Attribute
Speed Grade
Units-10
I-Grade M-Grade Delta
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 18
Ethernet MAC Switching Characteristics
Consult UG074,Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User Guide for further information.
LVCMOS18_S2 5.89 8.68 2.79 ns
LVCMOS18_S4 4.35 7.31 2.96 ns
LVCMOS18_S6 4.00 5.66 1.66 ns
LVCMOS18_S8 3.76 5.11 1.35 ns
LVCMOS18_S12 3.74 4.59 0.85 ns
LVCMOS18_S16 3.55 3.89 0.34 ns
LVCMOS18_F2 3.89 8.34 4.45 ns
LVCMOS18_F4 3.02 5.99 2.97 ns
LVCMOS18_F6 2.72 4.35 1.63 ns
LVCMOS18_F8 2.52 3.66 1.14 ns
LVCMOS18_F12 2.36 2.80 0.44 ns
LVCMOS18_F16 2.27 2.70 0.43 ns
LVCMOS15_S2 6.61 9.21 2.60 ns
LVCMOS15_S4 4.88 7.75 2.87 ns
LVCMOS15_S6 4.26 6.14 1.88 ns
LVCMOS15_S8 4.26 6.18 1.92 ns
LVCMOS15_S12 3.77 4.77 1.00 ns
LVCMOS15_S16 3.53 4.07 0.54 ns
LVCMOS15_F2 4.17 8.32 4.15 ns
LVCMOS15_F4 3.32 6.53 3.21 ns
LVCMOS15_F6 2.94 4.69 1.75 ns
LVCMOS15_F8 2.71 3.90 1.19 ns
LVCMOS15_F12 2.50 2.92 0.42 ns
LVCMOS15_F16 2.43 2.84 0.41 ns
SSTL18_I 2.54 2.44 -0.10 ns
SSTL18_II 2.24 2.42 0.18 ns
Tabl e 2 5 : IOB 3-State On Output Switching Characteristics (TIOTPHZ)
Symbol Description Speed Grade Units
-11 -10
TIOTPHZ T input to Pad high-impedance 1.01 1.12 ns
Tabl e 2 6 : Maximum Ethernet MAC Performance
Description Speed Grade Units
-11 -10
Ethernet MAC Maximum Performance 10/100/1000 Mb/s
Tabl e 2 4 : TIOOP and TIOTP Offset for 125°C Operation (Cont’d)
IOSTANDARD Attribute
Speed Grade
Units-10
I-Grade M-Grade Delta
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 19
Input/Output Logic Switching Characteristics
Tabl e 2 7 : ILOGIC Switching Characteristics
Symbol Description Speed Grade Units
-11 -10
Setup/Hold
TICE1CK /T
ICKCE1 CE1 pin setup/hold with respect to CLK 0.66/–0.23 0.79/–0.23 ns
TICECK /T
ICKCE DLYCE pin setup/hold with respect to CLKDIV 0.19/0.13 0.23/0.16 ns
TIRSTCK /T
ICKRST DLYRST pin setup/hold with respect to CLKDIV –0.02/0.45 –0.02/0.54 ns
TIINCCK /T
ICKINC DLYINC pin setup/hold with respect to CLKDIV 0.01/0.43 0.01/0.51 ns
TISRCK /T
ICKSR SR/REV pin setup/hold with respect to CLK 1.33/–0.56 1.59/–0.56 ns
TIDOCK /T
IOCKD D pin setup/hold with respect to CLK without Delay 0.28/–0.10 0.34/–0.10 ns
TIDOCKD /T
IOCKDD
D pin setup/hold with respect to CLK
(IOBDELAY_TYPE = DEFAULT) 7.63/–5.99 8.84/–5.99 ns
D pin setup/hold with respect to CLK
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 0.87/–0.63 1.09/–0.63 ns
Combinatorial
TIDI D pin to O pin propagation delay, no Delay 0.20 0.24 ns
TIDID
D pin to O pin propagation delay
(IOBDELAY_TYPE = DEFAULT) 6.91 7.96 ns
D pin to O pin propagation delay
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 0.79 0.99 ns
Sequential Delays
TIDLO D pin to Q1 pin using flip-flop as a latch without Delay 0.59 0.71 ns
TIDLOD
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = DEFAULT) 7.94 9.21 ns
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 1.18 1.45 ns
TICKQ CLK to Q outputs 0.60 0.72 ns
TICE1Q CE1 pin to Q1 using flip-flop as a latch, propagation delay 1.06 1.27 ns
TRQ SR/REV pin to OQ/TQ out 2.03 2.44 ns
TGSRQ Global Set/Reset to Q outputs 1.73 2.03 ns
Set/Reset
TRPW Minimum Pulse Width, SR/REV inputs 0.59 0.70 ns, Min
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 20
Tabl e 2 8 : OLOGIC Switching Characteristics
Symbol Description Speed Grade Units
-11 -10
Setup/Hold
TODCK /TOCKD D1/D2 pins setup/hold with respect to CLK 0.62/–0.22 0.75/–0.22 ns
TOOCECK /TOCKOCE OCE pin setup/hold with respect to CLK 0.64/–0.33 0.77/–0.33 ns
TOSRCK /T
OCKSR SR/REV pin setup/hold with respect to CLK 1.18/–0.55 1.42/–0.55 ns
TOTCK /T
OCKT T1/T2 pins setup/hold with respect to CLK 0.62/–0.22 0.75/–0.22 ns
TOTCECK /T
OCKTCE TCE pin setup/hold with respect to CLK 0.64/–0.33 0.77/–0.33 ns
Combinatorial
TODQ D1 to OQ out 0.65 0.76 ns
TOTQ T1 to TQ out 0.65 0.76 ns
Sequential Delays
TIOSRON REV pin to TQ out 1.37 1.64 ns
TOCKQ CLK to OQ/TQ out 0.49 0.59 ns
TRQ SR/REV pin to OQ/TQ out 1.37 1.64 ns
TGSRQ Global Set/Reset to Q outputs 1.73 2.03 ns
Set/Reset
TRPW Minimum Pulse Width, SR/REV inputs 0.59 0.70 ns Min
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 21
Input Serializer/Deserializer Switching Characteristics
Tabl e 2 9 : ISERDES Switching Characteristics
Symbol Description Speed Grade Units
-11 -10
Setup/Hold for Control Lines
TISCCK_BITSLIP /TISCKC_BITSLIP BITSLIP pin setup/hold with respect to CLKDIV 0.34/–0.16 0.40/–0.13 ns
TISCCK_CE /TISCKC_CE(2) CE pin setup/hold with respect to CLK (for CE1) 0.57/–0.30 0.69/–0.25 ns
TISCCK_CE2 /TISCKC_CE2(2) CE pin setup/hold with respect to CLKDIV (for CE2) 0.14/–0.03 0.16/–0.02 ns
TISCCK_DLYCE /TISCKC_DLYCE DLYCE pin setup/hold with respect to CLKDIV 0.19/0.13 0.23/0.16 ns
TISCCK_DLYINC /TISCKC_DLYINC DLYINC pin setup/hold with respect to CLKDIV 0.01/0.43 0.01/0.51 ns
TISCCK_DLYRST /TISCKC_DLYRST DLYRST pin setup/hold with respect to CLKDIV –0.02/0.45 –0.02/0.54 ns
TISCCK_REV REV pin setup with respect to CLK 1.23 1.23 ns
TISCCK_SR SR pin setup with respect to CLKDIV 0.77 0.92 ns
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D
D pin setup/hold with respect to CLK
(IOBDELAY = IBUF or NONE) 0.28/–0.11 0.34/–0.11 ns
D pin setup/hold with respect to CLK
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
7.63/–6.51 8.84/–6.51 ns
D pin setup/hold with respect to CLK(1)
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
0.87/–0.68 1.08/–0.68 ns
TISDCK_DDR /TISCKD_DDR
D pin setup/hold with respect to CLK at DDR mode
(IOBDELAY = IBUF or NONE) 0.28/–0.11 0.34/–0.11 ns
D pin setup/hold with respect to CLK at DDR mode
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
7.63/–6.51 8.84/–6.51 ns
D pin setup/hold with respect to CLK at DDR mode(1)
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
0.87/–0.68 1.08/–0.68 ns
Sequential Delays
TISCKO_Q CLKDIV to out at Q pin 0.71 0.85 ns
Propagation Delays
TISDO_DO_IOBDELAY_IFD D input to DO output pin (IOBDELAY = IFD) 0.20 0.24 ns
TISDO_DO_IOBDELAY_NONE D input to DO output pin (IOBDELAY = NONE) 0.20 0.24 ns
TISDO_DO_IOBDELAY_BOTH
D input to DO output pin (IOBDELAY = BOTH,
IOBDELAY_TYPE = DEFAULT) 6.91 7.96 ns
D input to DO output pin(1) (IOBDELAY = BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 0.79 0.99 ns
TISDO_DO_IOBDELAY_IBUF
D input to DO output pin (IOBDELAY = IBUF,
IOBDELAY_TYPE = DEFAULT) 6.91 7.96 ns
D input to DO output pin(1) (IOBDELAY = IBUF,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 0.79 0.99 ns
Notes:
1. Recorded at 0 tap value.
2. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE /TISCKC_CE in TRCE report.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 22
Input Delay Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Tabl e 3 0 : Input Delay Switching Characteristics
Symbol Description Speed Grade Units
-11 -10
TIDELAYRESOLUTION IDELAY Chain Delay Resolution 75 75 ps
TIDELAYTOTAL_ERR Cumulative delay at a given tap(3) [(tap 1) x 75 34]
0.07[(tap 1) x 75 34] ps
TIDELAYCTRLCO_RDY Reset to Ready for IDELAYCTRL (Maximum) 3.00 3.00 µs
FIDELAYCTRL_REF REFCLK frequency 200 200 MHz
IDELAYCTRL_REF_PRECISION(2) REFCLK precision ±10 ±10 MHz
TIDELAYCTRL_RPW Minimum Reset pulse width 50.0 50.0 ns
TIDELAYPAT_JIT
Pattern dependent period jitter in delay chain for clock
pattern 00Note 1
Pattern dependent period jitter in delay chain for random
data pattern (PRBS 23) 10 ± 2 10 ± 2 Note 1
Notes:
1. Units in ps peak-to-peak per tap.
2. See the “REFCLK - Reference Clock” section (specific to IDELAYCTRL) in the Virtex-4 FPGA User Guide, Chapter 7, SelectIO Logic
Resources.
3. This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps.
Tabl e 3 1 : OSERDES Switching Characteristics
Symbol Description Speed Grade Units
-11 -10
Setup/Hold
TOSDCK_D /TOSCKD_D D input setup/hold with respect to CLKDIV 0.42/–0.04 0.50/–0.03 ns
TOSDCK_T /T
OSCKD_T(1) T input setup/hold with respect to CLK 0.52/–0.16 0.62/–0.16 ns
TOSDCK_T2 /T
OSCKD_T2(1) T input setup/hold with respect to CLKDIV 0.42/–0.04 0.50/–0.03 ns
TOSCCK_OCE /TOSCKC_OCE OCE input setup/hold with respect to CLK 0.53/0.02 0.64/0.03 ns
TOSCCK_S SR (Reset) input setup with respect to CLKDIV 0.80 0.96 ns
TOSCCK_TCE /TOSCKC_TCE TCE input setup/hold with respect to CLK 0.53/0.02 0.64/0.03 ns
Sequential Delays
TOSCKO_OQ Clock to out from CLK to OQ 0.49 0.59 ns
TOSCKO_TQ Clock to out from CLK to TQ 0.49 0.59 ns
Combinatorial
TOSDO_TTQ T input to TQ Out 0.65 0.76 ns
TOSCO_OQ Asynchronous Reset to OQ 1.37 1.64 ns
TOSCO_TQ Asynchronous Reset to TQ 1.37 1.64 ns
Notes:
1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T /TOSCKD_T in TRCE report.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 23
CLB Switching Characteristics
Tabl e 3 2 : CLB Switching Characteristics
Symbol Description Speed Grade Units
-11 -10
Combinatorial Delays
TILO 4-input function: F/G inputs to X/Y outputs 0.17 0.20 ns, max
TIF5 5-input function: F/G inputs to F5 output 0.40 0.46 ns, max
TIF5X 5-input function: F/G inputs to X output 0.49 0.57 ns, max
TIF6Y FXINA or FXINB inputs to YMUX output 0.34 0.39 ns, max
TINAFX FXINA input to FX output via MUXFX 0.23 0.27 ns, max
TINBFX FXINB input to FX output via MUXFX 0.23 0.26 ns, max
TBXX BX input to XMUX output 0.65 0.76 ns, max
TBYY BY input to YMUX output 0.48 0.56 ns, max
TBXCY BX input to COUT output – Getting into carry chain(2) 0.66 0.78 ns, max
TBYCY BY input to COUT output – Getting into carry chain(2) 0.54 0.63 ns, max
TBYP CIN input to COUT output – Carry chain delay(2) 0.08 0.09 ns, max
TOPCYF F input to COUT output – Getting out from carry chain(2) 0.50 0.58 ns, max
TOPCYG G input to COUT output – Getting out from carry chain(2) 0.48 0.57 ns, max
Sequential Delays
TCKO FF Clock CLK to XQ/YQ outputs 0.31 0.36 ns, max
TCKLO Latch Clock CLK to XQ/YQ outputs 0.41 0.48 ns, max
Setup-and-Hold Times of CLB Flip-Flops Before/After Clock CLK
TDICK /TCKDI BX/BY inputs 0.40/–0.09 0.47/–0.09 ns, min
TCECK /TCKCE CE input 0.64/–0.16 0.75/–0.16 ns, min
TFXCK /TCKFX FXINA/FXINB inputs 0.46/–0.14 0.54/–0.14 ns, min
TSRCK /TCKSR SR/BY inputs (synchronous) 1.15/–0.73 1.35/–0.73 ns, min
TCINCK /TCKCIN CIN Data Inputs (DI) – Getting out from carry chain(2) 0.57/–0.23 0.67/–0.23 ns, min
Set/Reset
TRPW Minimum Pulse Width, SR/BY inputs 0.59 0.70 ns, min
TRQ Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) 1.15 1.35 ns, max
FTOG Toggle Frequency (MHz) (for export control) 1205(3) 1028 MHz
Notes:
1. A zero “0” hold time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case,” but if a “0” is
listed, there is no positive hold time.
2. These items are of interest for carry chain applications.
3. XQ4VFX -11 devices are 1181 MHz.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 24
CLB Distributed RAM Switching Characteristics (SLICEM Only)
)
CLB Shift Register Switching Characteristics (SLICEM Only)
)
Tabl e 3 3 : CLB Distributed RAM Switching Characteristics
Symbol Description Speed Grade Units
-11 -10
Sequential Delays
TSHCKO Clock CLK to X outputs (WE active) 1.77 2.08 ns, max
TSHCKOF5 Clock CLK to F5 output (WE active) 1.69 1.98 ns, max
Setup-and-Hold Times Before/After Clock CLK
TDS /TDH BX/BY data inputs (DI) 1.46/–0.88 1.80/–0.88 ns, min
TAS /TAH F/G address inputs 0.97/–0.34 1.13/–0.29 ns, min
TWS /TWH WE input (SR) 1.21/–0.47 1.42/–0.47 ns, min
Clock CLK
TWPH Minimum Pulse Width, High 0.59 0.69 ns, min
TWPL Minimum Pulse Width, Low 0.60 0.70 ns, min
TWC Minimum clock period to meet address write cycle time 0.84 0.98 ns, min
Notes:
1. A zero “0” hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is
listed, there is no positive hold time.
2. TSHCKO also represents the CLK to XMUX output. Refer to TRCE report for the CLK to XMUX path.
Tabl e 3 4 : CLB Shift Register Switching Characteristics
Symbol Description
Speed Grade Units
-11 -10
XQ4VFX XQ4VLX/SX All
Sequential Delays
TREG Clock CLK to X/Y outputs 2.19 2.19 2.57 ns, max
TREGXB Clock CLK to XB output via MC15 LUT output 1.90 1.84 2.04 ns, max
TREGYB Clock CLK to YB output via MC15 LUT output 1.92 1.85 2.17 ns, max
TCKSH Clock CLK to Shiftout 1.76 1.70 1.99 ns, max
TREGF5 Clock CLK to F5 output 2.11 2.11 2.47 ns, max
Setup-and-Hold Times Before/After Clock CLK
TWS /TWH WE input (SR) 0.96/–0.70 0.96/–0.70 1.12/–0.62 ns, min
TDS /TDH BX/BY data inputs (DI) 1.45/–1.11 1.45/–1.11 1.75/–1.11 ns, min
Clock CLK
TWPH Minimum Pulse Width, High 0.59 0.59 0.69 ns, min
TWPL Minimum Pulse Width, Low 0.60 0.60 0.70 ns, min
Notes:
1. A zero “0” hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is
listed, there is no positive hold time.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 25
Block RAM and FIFO Switching Characteristics
Tabl e 3 5 : Block RAM Switching Characteristics
Symbol Description Speed Grade Units
-11 -10
Sequential Delays
TRCKO_DORA Clock CLK to DOUT output (without output register)(2) 1.83 2.10 ns, max
TRCKO_DOA Clock CLK to DOUT output (with output register)(3) 0.80 0.92 ns, min
Setup-and-Hold Times Before Clock CLK
TRCCK_ADDR /TRCKC_ADDR ADDR inputs 0.37/0.28 0.43/0.33 ns, min
TRDCK_DI /TRCKD_DI DIN inputs(4) 0.20/0.28 0.23/0.33 ns, min
TRCCK_EN /TRCKC_EN EN input(5) 0.45/0.28 0.52/0.33 ns, min
TRCCK_REGCE /TRCKC_REGCE CE input of output register 0.27/0.28 0.32/0.33 ns, min
TRCCK_SSR /TRCKC_SSR RST input 0.27/0.28 0.32/0.33 ns, min
TRCCK_WE /TRCKC_WE WEN input 0.65/0.28 0.75/0.33 ns, min
Maximum Frequency
FMAX Write first and no change mode 450.45 400.00 MHz
FMAX Read first mode 450.45 400.00 MHz
Notes:
1. A zero “0” hold time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case,” but if a “0” is
listed, there is no positive hold time.
2. TRCKO_DORA includes TRCKO_DOWA, TRCKO_DOPAR, and TRCKO_DOPAW as well as the B port equivalent timing parameters.
3. TRCKO_DOA includes TRCKO_DOPA as well as the B port equivalent timing parameters.
4. TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B.
5. Xilinx Block RAMs do not have asynchronous inputs on an enabled port address. During the time that a port is enabled, its addresses must
be stable during the specified set-up time. Do not create an asynchronous input on an enabled port address.
Tabl e 3 6 : FIFO Switching Characteristics
Symbol Description Speed Grade Units
-11 -10
Sequential Delays
TFCKO_DO Clock CLK to DO output(2) 0.80 0.92 ns, max
TFCKO_FLAGS Clock CLK to FIFO flags outputs(3) 1.04 1.19 ns, max
TFCKO_POINTERS Clock CLK to FIFO pointer outputs(4) 1.29 1.48 ns, max
Setup-and-Hold Times Before Clock CLK
TFDCK_DI /TFCKD_DI DI input(5) 0.20/0.28 0.23/0.33 ns, min
TFCCK_EN /TFCKC_EN Enable inputs(6) 0.73/0.28 0.84/0.33 ns, min
Reset Delays
TFCO_FLAGS Reset RST to FLAGS(7) 1.46 1.68 ns, max
Maximum Frequency
FMAX FIFO in all modes 450.45 400.00 MHz
Notes:
1. A zero “0” hold time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case,” but if a “0” is
listed, there is no positive hold time.
2. TFCKO_DO includes parity output (TFCKO_DOP).
3. TFCKO_FLAGS includes the following parameters: TFCKO_AEMPTY
, TFCKO_AFULL, TFCKO_EMPTY
, TFCKO_FULL, TFCKO_RDERR, TFCKO_WRERR.
4. TFCKO_POINTERS includes both TFCKO_RDCOUNT and TFCKO_WRCOUNT.
5. TFDCK_DI includes parity inputs (TFDCK_DIP).
6. TFCCK_EN includes both WRITE and READ enable.
7. TFCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT and WRCOUNT.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 26
XtremeDSP Switching Characteristics
Configuration Switching Characteristics
Tabl e 3 7 : XtremeDSP™ Switching Characteristics
Symbol Description Speed Grade Units
-11 -10
Setup and Hold of CE Pins
TDSPCCK_CE /TDSPCKC_CE Setup/hold of all CE inputs of the DSP48 slice 0.43/0.10 0.49/0.12 ns
TDSPCCK_RST /TDSPCKC_RST Setup/hold of all RST inputs of the DSP48 slice 0.36/0.10 0.40/0.12 ns
Setup-and-Hold Times of Data
TDSPDCK_{AA, BB, CC} /
TDSPCKD_{AA, BB, CC} Setup/hold of {A, B, C} input to {A, B, C} register 0.28/0.26 0.32/0.29 ns
TDSPDCK_{AM, BM} /
TDSPCKD_{AM, BM} Setup/hold of {A, B} input to M register 2.03/0.00 2.28/0.00 ns
Sequential Delays
TDSPCKO_PP Clock to out from P register to P output 0.71 0.79 ns
TDSPCKO_PM Clock to out from M register to P output 2.65 2.98 ns
Combinatorial
TDSPDO_{AP, BP}L From {A, B} input to P output
(LEGACY_MODE = MULT18X18) 3.92 4.41 ns
Maximum Frequency
FMAX
From {A, B} register to P register
(LEGACY_MODE = MULT18X18) 285.71 253.94 MHz
Fully Pipelined 450.05 400.00 MHz
Tabl e 3 8 : Configuration Switching Characteristics
Symbol Description
Speed Grade
Units-11 -10
I-Grade I-Grade M-Grade
Power-up Timing Characteristics
TPL Program latency 0.5 0.5 0.5 µs/frame,
max
TPOR Power-on-reset TPL +10 ms, max
TICCK CCLK (output) delay 500 500 500 ns, min
TPROGRAM Program Pulse Width 300 300 400 ns, min
Master/Slave Serial Mode Programming Switching
TDCC /TCCD DIN setup/hold, slave mode 0.5/1.0 0.5/1.0 1.0/1.0 ns, min
TDSCK /TSCKD DIN setup/hold, master mode 0.5/1.0 0.5/1.0 1.0/1.0 ns, min
TCCO DOUT 7.5 7.5 8.0 ns, max
TCCH High time 2.0 2.0 2.0 ns, min
TCCL Low time 2.0 2.0 2.0 ns, min
FCC_SERIAL Maximum frequency, master mode
with respect to nominal CCLK. 100 100 80 MHz, max
FMCCTOL Frequency tolerance, master mode
with respect to nominal CCLK. ±50 ±50 ±50 %
FMAX_SLAVE Slave mode external CCLK 100 100 80 MHz
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 27
Master/Slave SelectMAP Parameters
Figure 3 is a generic timing diagram for data loading using SelectMAP. For other data loading diagrams, refer to the
Virtex-4 FPGA User Guide.
SelectMAP Mode Programming Switching
TSMDCC /TSMCCD SelectMAP setup/hold 2.0/0.0 2.0/0.0 3.0/0.0 ns, min
TSMCSCC /TSMCCCS CS_B setup/hold 1.0/0.5 1.0/0.5 2.0/0.5 ns, min
TSMCCW /TSMWCC RDWR_B setup/hold 6.0/1.0 6.0/1.0 8.0/1.0 ns, min
TSMCKBY BUSY propagation delay 8.0 8.0 8.0 ns, max
FCC_SELECTMAP Maximum frequency, master mode
with respect to nominal CCLK. 100 100 80 MHz, max
FMCCTOL Frequency tolerance, master mode
with respect to nominal CCLK. ±50 ±50 ±50 %
Boundary-Scan Port Timing Specifications
TTAPTCK TMS and TDI setup time before
TCK 1.0 1.0 1.5 ns, min
TTCKTAP TMS and TDI hold time after TCK 2.0 2.0 2.0 ns, min
TTCKTDO TCK falling edge to TDO output
valid 6.0 6.0 8.0 ns, max
FTCK Maximum configuration TCK clock
frequency 66 66 66 MHz, max
FTCKB Maximum Boundary-Scan TCK
clock frequency 50 50 50 MHz, max
Dynamic Reconfiguration Port (DRP) for DCM
CLKIN_FREQ_DLL_HF_MS_MAX Maximum frequency for DCLK 450 400 400 MHz, max
D_DCMADV_DADDR_DCLK_SETUP/
D_DCMADV_DADDR_DCLK_HOLD DADDR setup/hold 0.63/0.00 0.72/0.00 0.72/0.00 ns, max
D_DCMADV_DI_DCLK_SETUP/
D_DCMADV_DI_DCLK_HOLD DI setup/hold 0.63/0.00 0.72/0.00 0.72/0.00 ns, max
D_DCMADV_DEN_DCLK_SETUP/
D_DCMADV_DEN_DCLK_HOLD DEN setup/hold time 0.58/0.00 0.58/0.00 0.58/0.00 ns, max
D_DCMADV_DWE_DCLK_SETUP/
D_DCMADV_DWE_DCLK_HOLD DWE setup/hold time 0.58/0.00 0.58/0.00 0.58/0.00 ns, max
D_DCMADV_DCLK_DO CLK to out of DO(1) 000ns, max
D_DCMADV_DCLK_DRDY CLK to out of DRDY 0.80 0.92 0.92 ns, max
Notes:
1. DO holds until next DRP operation.
Tabl e 3 8 : Configuration Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units-11 -10
I-Grade I-Grade M-Grade
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 28
Clock Buffers and Networks
DCM and PMCD Switching Characteristics
DCM in Maximum Range (MR) Mode is not supported for M-grade devices.
X-Ref Target - Figure 3
Figure 3: SelectMAP Mode Data Loading Sequence (Generic)
Tabl e 3 9 : Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol Description Speed Grade Units
-11 -10
TBCCCK_CE /TBCCKC_CE(1) CE pins setup/hold 0.31/0.00 0.35/0.00 ns
TBCCCK_S /TBCCKC_S(1) S pins setup/hold 0.31/0.00 0.35/0.00 ns
TBCCKO_O BUFGCTRL delay 0.77 0.90 ns
Maximum Frequency
FMAX Global clock tree 450 400 MHz
Notes:
1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup-and-hold
times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching
between clocks.
Tabl e 4 0 : Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
Symbol Description Speed Grade Units
-11 -10
Outputs Clocks (Low Frequency Mode)
CLKOUT_FREQ_1X_LF_MS_MIN CLK0, CLK90, CLK180, CLK270 32 32 MHz
CLKOUT_FREQ_1X_LF_MS_MAX 150 150 MHz
CLKOUT_FREQ_2X_LF_MS_MIN CLK2X, CLK2X180 64 64 MHz
CLKOUT_FREQ_2X_LF_MS_MAX 300 300 MHz
CLKOUT_FREQ_DV_LF_MS_MIN CLKDV 22MHz
CLKOUT_FREQ_DV_LF_MS_MAX 100 100 MHz
DS595_03_041408
CCLK
No Write Write No Write Write
DATA[0:7]
CS_B
RDWR_B
BUSY
T
SMCSCC
T
SMDCC
T
SMCCD
T
SMCCCS
T
SMWCC
T
SMCKBY
T
SMCCW
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 29
CLKOUT_FREQ_FX_LF_MS_MIN CLKFX, CLKFX180 32 32 MHz
CLKOUT_FREQ_FX_LF_MS_MAX 210 210 MHz
Input Clocks (Low Frequency Mode)
CLKIN_FREQ_DLL_LF_MS_MIN CLKIN (using DLL outputs)(1)(3)(4)(5) 32 32 MHz
CLKIN_FREQ_DLL_LF_MS_MAX 150 150 MHz
CLKIN_FREQ_FX_LF_MS_MIN CLKIN (using DFS outputs only)(2)(3)(4) 11MHz
CLKIN_FREQ_FX_LF_MS_MAX 210 210 MHz
PSCLK_FREQ_LF_MS_MIN PSCLK 11KHz
PSCLK_FREQ_LF_MS_MAX 450 400 MHz
Outputs Clocks (High Frequency Mode)
CLKOUT_FREQ_1X_HF_MS_MIN CLK0, CLK90, CLK180, CLK270 150 150 MHz
CLKOUT_FREQ_1X_HF_MS_MAX 450 400 MHz
CLKOUT_FREQ_2X_HF_MS_MIN CLK2X, CLK2X180 300 300 MHz
CLKOUT_FREQ_2X_HF_MS_MAX 450 400 MHz
CLKOUT_FREQ_DV_HF_MS_MIN CLKDV 9.4 9.4 MHz
CLKOUT_FREQ_DV_HF_MS_MAX 300 267 MHz
CLKOUT_FREQ_FX_HF_MS_MIN CLKFX, CLKFX180 210 210 MHz
CLKOUT_FREQ_FX_HF_MS_MAX 315 300 MHz
Input Clocks (High Frequency Mode)
CLKIN_FREQ_DLL_HF_MS_MIN CLKIN (using DLL outputs)(1)(3)(4) 150 150 MHz
CLKIN_FREQ_DLL_HF_MS_MAX 450 400 MHz
CLKIN_FREQ_FX_HF_MS_MIN CLKIN (using DFS outputs only)(2)(3)(4) 50 50 MHz
CLKIN_FREQ_FX_HF_MS_MAX 315 300 MHz
PSCLK_FREQ_HF_MS_MIN PSCLK 11KHz
PSCLK_FREQ_HF_MS_MAX 450 400 MHz
Notes:
1. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled.
4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
5. The DCM must be reset if the clock input clock stops for more than 100 ms.
Tabl e 4 0 : Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode (Cont’d)
Symbol Description Speed Grade Units
-11 -10
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 30
Tabl e 4 1 : Operating Frequency Ranges for DCM in Maximum Range (MR) Mode (Industrial Grade Only)(5)
Symbol Description Speed Grade Units
-11 -10
Outputs Clocks (Low Frequency Mode)
CLKOUT_FREQ_1X_LF_MR_MIN CLK0, CLK90, CLK180, CLK270 19 19 MHz
CLKOUT_FREQ_1X_LF_MR_MAX 36 32 MHz
CLKOUT_FREQ_2X_LF_MR_MIN CLK2X, CLK2X180 38 38 MHz
CLKOUT_FREQ_2X_LF_MR_MAX 72 64 MHz
CLKOUT_FREQ_DV_LF_MR_MIN CLKDV 1.2 1.2 MHz
CLKOUT_FREQ_DV_LF_MR_MAX 24 21.3 MHz
CLKOUT_FREQ_FX_LF_MR_MIN CLKFX, CLKFX180 19 19 MHz
CLKOUT_FREQ_FX_LF_MR_MAX 36 32 MHz
Input Clocks (Low Frequency Mode)
CLKIN_FREQ_DLL_LF_MR_MIN CLKIN (using DLL outputs)(1)(3)(4) 19 19 MHz
CLKIN_FREQ_DLL_LF_MR_MAX 36 32 MHz
CLKIN_FREQ_FX_LF_MR_MIN CLKIN (using DFS outputs only)(2)(3)(4) 11MHz
CLKIN_FREQ_FX_LF_MR_MAX 32 28 MHz
PSCLK_FREQ_LF_MR_MIN PSCLK 11KHz
PSCLK_FREQ_LF_MR_MAX 236.30 210.00 MHz
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled.
4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
5. DCM in Maximum Range (MR) Mode is not supported for M-grade devices.
Tabl e 4 2 : Input Clock Duty Cycle Input Tolerance
Symbol Description Frequency Range Value Units
CLKIN_PSCLK_PULSE_RANGE_1 PSCLK only < 1 MHz 25 – 75 %
CLKIN_PSCLK_PULSE_RANGE_1_50 PSCLK and CLKIN 1 – 50 MHz 25 – 75 %
CLKIN_PSCLK_PULSE_RANGE_50_100 50 – 100 MHz 30 – 70 %
CLKIN_PSCLK_PULSE_RANGE_100_200 100 – 200 MHz 40 – 60 %
CLKIN_PSCLK_PULSE_RANGE_200_400 200 – 400 MHz 45 – 55 %
Tabl e 4 3 : Input Clock Tolerances
Symbol Description Speed Grade Units
-11 -10
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
CLKIN_CYC_JITT_DLL_LF CLKIN (using DLL outputs)(1) ±300 ±300 ps
CLKIN_CYC_JITT_FX_LF CLKIN (using DFS outputs)(2) ±300 ±300 ps
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN_CYC_JITT_DLL_HF CLKIN (using DLL outputs)(1) ±150 ±150 ps
CLKIN_CYC_JITT_FX_HF CLKIN (using DFS outputs)(2) ±150 ±150 ps
Input Clock Period Jitter (Low Frequency Mode)
CLKIN_PER_JITT_DLL_LF CLKIN (using DLL outputs)(1) ±1.0 ±1.0 ns
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 31
Output Clock Jitter
CLKIN_PER_JITT_FX_LF CLKIN (using DFS outputs)(2) ±1.0 ±1.0 ns
Input Clock Period Jitter (High Frequency Mode)
CLKIN_PER_JITT_DLL_HF CLKIN (using DLL outputs)(1) ±1.0 ±1.0 ns
CLKIN_PER_JITT_FX_HF CLKIN (using DFS outputs)(2) ±1.0 ±1.0 ns
Feedback Clock Path Delay Variation
CLKFB_DELAY_VAR_EXT CLKFB off-chip feedback ±1.0 ±1.0 ns
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. If both DLL and DFS outputs are used, follow the more restrictive specifications.
Tabl e 4 4 : Output Clock Jitter
Symbol Description Speed Grade Units
-11 -10
Clock Synthesis Period Jitter
CLK0 CLKOUT_PER_JITT_0 ±100 ±100 ps
CLK90 CLKOUT_PER_JITT_90 ±150 ±150 ps
CLK180 CLKOUT_PER_JITT_180 ±150 ±150 ps
CLK270 CLKOUT_PER_JITT_270 ±150 ±150 ps
CLK2X, CLK2X180 CLKOUT_PER_JITT_2X ±200 ±200 ps
CLKDV (integer division) CLKOUT_PER_JITT_DV1 ±150 ±150 ps
CLKDV (non-integer division) CLKOUT_PER_JITT_DV2 ±300 ±300 ps
CLKFX, CLKFX180 CLKOUT_PER_JITT_FX Note 1 Note 1 ps
Notes:
1. Values for this parameter are available at www.xilinx.com.
Tabl e 4 3 : Input Clock Tolerances (Cont’d)
Symbol Description Speed Grade Units
-11 -10
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 32
Output Clock Phase Alignment
Tabl e 4 5 : Output Clock Phase Alignment
Description Symbol
Speed Grade
Units-11 -10
I-Grade I-Grade M-Grade
Phase Offset Between CLKIN and CLKFB
CLKIN /CLKFB CLKIN_CLKFB_PHASE ±120 ±120 ±120 ps
Phase Offset Between Any DCM Outputs
All CLK outputs CLKOUT_PHASE ±140 ±140 ±200 ps
Duty Cycle Precision
DLL outputs(1) CLKOUT_DUTY_CYCLE_DLL(3)(4) ±150 ±150 ±150 ps
DFS outputs(2) CLKOUT_DUTY_CYCLE_FX(4) ±200 ±200 ±250 ps
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION=TRUE.
4. The measured value includes the duty cycle distortion of the global clock tree.
Tabl e 4 6 : Miscellaneous Timing Parameters
Symbol Description Speed Grade Units
-11 -10
Time Required to Achieve LOCK
T_LOCK_DLL_240 DLL output – Frequency range > 240 MHz(1) 20 20 µs
T_LOCK_DLL_120_240 DLL output – Frequency range 120 – 240 MHz(1) 63 63 µs
T_LOCK_DLL_60_120 DLL output – Frequency range 60 – 120 MHz(1) 225 225 µs
T_LOCK_DLL_50_60 DLL output – Frequency range 50 – 60 MHz(1) 325 325 µs
T_LOCK_DLL_40_50 DLL output – Frequency range 40 – 50 MHz(1) 500 500 µs
T_LOCK_DLL_30_40 DLL output – Frequency range 30 – 40 MHz(1) 900 900 µs
T_LOCK_DLL_24_30 DLL output – Frequency range 24 – 30 MHz(1) 1250 1250 µs
T_LOCK_DLL_30 DLL output – Frequency range < 30 MHz(1) 1250 1250 µs
T_LOCK_FX_MIN DFS outputs(2) 10 10 ms
T_LOCK_FX_MAX 10 10 ms
T_LOCK_DLL_FINE_SHIFT Multiplication factor for DLL lock time with Fine Shift 2 2 –
Fine Phase Shifting
FINE_SHIFT_RANGE_MS Absolute shifting range in maximum speed mode 7 7 ns
FINE_SHIFT_RANGE_MR(7) Absolute shifting range in maximum range mode 10 10 ns
Delay Lines
DCM_TAP_MS_MIN Tap delay resolution (Min) in maximum speed mode 5 5 ps
DCM_TAP_MS_MAX Tap delay resolution (Max) in maximum speed mode 40 40 ps
DCM_TAP_MR_MIN(7) Tap delay resolution (Min) in maximum range mode 10 10 ps
DCM_TAP_MR_MAX(7) Tap delay resolution (Max) in maximum range mode 60 60 ps
DCM_RESET(3) Minimum duration that RST must be held asserted 200 200 ms
Maximum duration that RST can be held asserted(4) 10 10 sec
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 33
DCM_INPUT_CLOCK_STOP Maximum duration that CLKIN and CLKFB can be
stopped(5)(6) 100 100 ms
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. CLKIN must be present and stable during the DCM_RESET.
4. This only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in answer record 21127 for
support of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement.
5. For production step 1 LX and SX devices, use the design solutions described in answer record 21127 for support of longer durations of
stopped clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small
macro to support longer durations of stopped clocks.
6. For all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset.
7. DCM in Maximum Range (MR) Mode is not supported for M-grade devices.
Tabl e 4 7 : Frequency Synthesis
Attribute Min Max
CLKFX_MULTIPLY 2 32
CLKFX_DIVIDE 1 32
Tabl e 4 8 : DCM Switching Characteristics
Symbol Description Speed Grade Units
-11 -10
TDMCCK_PSEN /TDMCKC_PSEN PSEN setup/hold 0.93/0.00 1.07/0.00 ns
TDMCCK_PSINCDEC /TDMCKC_PSINCDEC PSINCDEC setup/hold 0.93/0.00 1.07/0.00 ns
TDMCKO_PSDONE Clock to out of PSDONE 0.60 0.69 ns
Tabl e 4 9 : PMCD Switching Characteristic
Symbol Description Speed Grade Units
-11 -10
TPMCCCK_REL /TPMCCKC_REL REL setup/hold for all outputs 0.60/0.00 0.60/0.00 ns
TPMCCO_CLK{A1,B,C,D} RST assertion to clock output deassertion 4.00 4.50 ns
TPMCCKO_CLK{A1,B,C,D} Max clock propagation delay of PMCD for all outputs 4.60 5.20 ns
PMCD_CLK_SKEW Max phase between all outputs assuming all inputs ±150 ±150 ps
CLKIN_FREQ_PMCD_CLKA_MAX Max input/output frequency 450 400 MHz
CLKIN_PSCLK_PULSE_RANGE Max duty-cycle input tolerance (same as DCM) Note 1 Note 1 –
PMCD_REL_HIGH_PULSE_MIN Min pulse width for REL 1.11 1.25 ns
PMCD_RST_HIGH_PULSE_MIN Min pulse width for RST 1.11 1.25 ns
Notes:
1. Refer to Table 42, page 30 parameter: CLKIN_PSCLK_PULSE_RANGE.
Tabl e 4 6 : Miscellaneous Timing Parameters (Cont’d)
Symbol Description Speed Grade Units
-11 -10
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 34
System-Synchronous Switching Characteristics
Virtex-4Q Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Ta bl e 5 0 . Values are expressed in nanoseconds unless otherwise noted.
Tabl e 5 0 : Global Clock Input-to-Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, With DCM
Symbol Description Device
Speed Grade
Units-11 -10
I-Grade I-Grade M-Grade
LVCMOS25 Global Clock Input-to-Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM.
TICKOFDCM Global Clock and OFF with DCM
XQ4VLX25 – – 3.36 ns
XQ4VLX40 – 3.32 3.42 ns
XQ4VLX60 – 3.45 3.53 ns
XQ4VLX80 3.27 – – ns
XQ4VLX100 3.33 3.79 – ns
XQ4VLX160 – 3.82 – ns
XQ4VSX55 – 3.62 4.14 ns
XQ4VFX60 – 3.77 3.96 ns
XQ4VFX100 3.58 – – ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
3. Clock to out has +320 ps offset for operation outside of the industrial temperature range.
Tabl e 5 1 : Global Clock Input-to-Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, Without DCM
Symbol Description Device
Speed Grade
Units-11 -10
I-Grade I-Grade M-Grade
LVCMOS25 Global Clock Input-to-Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM.
TICKOF Global Clock and OFF without DCM XQ4VLX25 – – 8.34 ns
XQ4VLX40 – 8.50 8.73 ns
XQ4VLX60 – 8.70 8.94 ns
XQ4VLX80 7.85 – – ns
XQ4VLX100 8.15 9.18 – ns
XQ4VLX160 – 9.46 – ns
XQ4VSX55 – 9.00 9.54 ns
XQ4VFX60 – 8.85 9.11 ns
XQ4VFX100 8.40 – – ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Clock to out has +250 ps offset for operation outside of the industrial temperature range.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 35
Virtex-4Q Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Ta bl e 5 2 . Values are expressed in nanoseconds unless otherwise noted.
Tabl e 5 2 : Global Clock Setup and Hold for LVCMOS25 Standard, With DCM
Symbol Description Device
Speed Grade
Units-11 -10
I-Grade I-Grade M-Grade
Input Setup-and-Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSDCM /TPHDCM No Delay Global Clock and IFF
with DCM(2)
XQ4VLX25 – – 1.65/–0.43 ns
XQ4VLX40 – 1.50/–0.46 1.69/–0.46 ns
XQ4VLX60 – 1.55/–0.36 1.71/–0.36 ns
XQ4VLX80 1.42/–0.21 – – ns
XQ4VLX100 1.48/–0.14 1.56/–0.08 – ns
XQ4VLX160 – 1.89/–0.05 – ns
XQ4VSX55 – 1.55/–0.13 1.73/–0.13 ns
XQ4VFX60 – 1.44/0.09 1.53/0.12 ns
XQ4VFX100 1.42/0.20 – – ns
Notes:
1. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative
to the Global Clock input signal with the slowest route and heaviest load.
2. These measurements include:
CLK0 DCM jitter
IFF = input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
4. Hold time has +200 ps offset for operation outside of the industrial temperature range.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 36
Tabl e 5 3 : Global Clock Setup and Hold for LVCMOS25 Standard, With DCM in Source-Synchronous Mode
Symbol Description Device
Speed Grade
Units-11 -10
I-Grade I-Grade M-Grade
Example Data Input Setup-and-hold Times Relative to a Forwarded Clock Input Pin, Using DCM and Global Clock
Buffer.(1)(3)
TPSDCM_0 /TPHDCM_0 No Delay Global Clock and IFF
with DCM in
Source-Synchronous Mode(2)
XQ4VLX25 – – –0.07/1.09 ns
XQ4VLX40 – –0.37/1.19 –0.03/1.19 ns
XQ4VLX60 – –0.32/1.29 –0.11/1.29 ns
XQ4VLX80 –0.38/1.34 – – ns
XQ4VLX100 –0.31/1.41 –0.31/1.57 – ns
XQ4VLX160 – –0.31/1.89 – ns
XQ4VSX55 – –0.32/1.52 –0.09/1.52 ns
XQ4VFX60 – –0.43/1.74 –0.25/1.77 ns
XQ4VFX100 –0.38/1.75 – – ns
Notes:
1. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CLK0 DCM jitter.
Package skew is not included in these measurements.
2. IFF = input flip-flop.
3. For situations where clock and data inputs conform to different standards, adjust the setup-and-hold values accordingly using the values
shown in IOB Switching Characteristics(1)(2), page 13.
4. Setup time has +150 ps offset for operation outside of the industrial temperature range.
Tabl e 5 4 : Global Clock Setup and Hold for LVCMOS25 Standard, Without DCM
Symbol Description Device
Speed Grade
Units-11 -10
I-Grade I-Grade M-Grade
Input Setup-and-Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSFD /T
PHFD Full Delay Global Clock and
IFF without DCM(2) XQ4VLX25 – – 2.72/0.50 ns
XQ4VLX40 – 3.06/0.44 3.11/0.44 ns
XQ4VLX60 – 3.50/0.34 3.53/0.37 ns
XQ4VLX80 2.96/0.26 – – ns
XQ4VLX100 5.83/–0.09 6.76/–0.01 – ns
XQ4VLX160 – 3.76/0.88 – ns
XQ4VSX55 – 2.97/0.98 3.02/0.98 ns
XQ4VFX60 – 3.54/0.59 3.58/0.62 ns
XQ4VFX100 2.21/1.31 – – ns
Notes:
1. Setup time is measured relative to the global clock input signal with the fastest route and the lightest load. Hold time is measured relative to
the global clock input signal with the slowest route and heaviest load.
2. IFF = input flip-flop or latch.
3. A zero “0” hold time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed best-case, but if a “0” is
listed, there is no positive hold time.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 37
ChipSync Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-4Q
source-synchronous transmitter and receiver data-valid windows.
Tabl e 5 5 : Duty Cycle Distortion and Clock-Tree Skew
Symbol Description Device Speed Grade Units
-11 -10
TDCD_CLK Global Clock Tree Duty Cycle
Distortion(1) All 150 150 ps
TCKSKEW Global Clock Tree Skew(2)
XQ4VLX25 – 110 ps
XQ4VLX40 – 180 ps
XQ4VLX60 – 180 ps
XQ4VLX80 230 – ps
XQ4VLX100 310 350 ps
XQ4VLX160 – 350 ps
XQ4VSX55 – 190 ps
XQ4VFX60 – 190 ps
XQ4VFX100 230 – ps
TDCD_BUFIO
I/O clock tree duty cycle distortion All 100 100 ps
I/O clock tree skew across one clock
region All 50 50 ps
TBUFIOSKEW I/O clock tree skew across multiple clock
regions All 50 50 ps
TDCD_BUFR Regional clock tree duty cycle distortion All 250 250 ps
TBUFIO_MAX_FREQ(3) I/O clock tree MAX frequency All 710 645 MHz
TBUFR_MAX_FREQ Regional clock tree MAX frequency All 250 250 MHz
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to the application.
3. Maximum frequency for operation outside of the industrial temperature range is 500 MHz.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 38
Tabl e 5 6 : Package Skew
Symbol Description Device Package Value Units
TPKGSKEW Package Skew(1)
XQ4VLX25 SF363 90 ps
FF668 110 ps
XQ4VLX40 FF668 110 ps
XQ4VLX60
EF668 130 ps
FF668 130 ps
FF1148 140 ps
XQ4VLX80 FF1148 155 ps
XQ4VLX100 FF1148 140 ps
XQ4VLX160 FF1148 145 ps
XQ4VSX55 FF1148 145 ps
XQ4VFX60 EF672 110 ps
XQ4VFX100 FF1152 150 ps
Notes:
1. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from pad to ball
(7.1 ps/mm).
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
Tabl e 5 7 : Sample Window
Symbol Description Device Speed Grade Units
-11 -10
TSAMP Sampling Error at Receiver Pins(1) All 500 550 ps
TSAMP_BUFIO Sampling Error at Receiver Pins using BUFIO(2) All 400 450 ps
Notes:
1. This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Tabl e 5 8 : ChipSync™ Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol Description Speed Grade Units
-11 -10
Data Input Setup-and-Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
TPSCS /T
PHCS Setup/hold of I/O clock across multiple clock regions –0.45/1.08 –0.44/1.17 ns
Pin-to-Pin Clock-to-Out Using BUFIO
TICKOFCS Clock-to-Out of I/O clock across multiple clock regions 4.54 5.02 ns
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 39
Production Stepping
The Virtex-4Q FPGA stepping identification system denotes the capability improvement of production released devices. By
definition, devices from one stepping are functional supersets of previous devices. Bitstreams compiled for a device with an
earlier stepping are guaranteed to operate correctly in subsequent device steppings.
New device steppings can be shipped in place of earlier device steppings. Existing production designs are guaranteed on
new device steppings. To take advantage of the capabilities of a newer device stepping, customers are able to order a new
stepping version and compile a new bitstream.
Production devices are marked with a stepping version, with the exception of some step 1 devices. Designs should be
compiled with a CONFIG STEPPING parameter set to a specific stepping version.
This parameter is set in the UCF file:
CONFIG STEPPING = “#”;
Where
# = the stepping version
Ta bl e 5 9 shows the JTAG ID code by step.
Current Virtex-4Q Production Devices
Ta bl e 6 0 summarizes the current production LX and SX device stepping.
Tabl e 5 9 : JTAG ID Code by Step
Device ID Code Stepping
XQ4VLX25 A 2
XQ4VLX40 5 2
XQ4VLX60 4 or 5 2
XQ4VLX80 5 2
XQ4VLX100 4 or 5 2
XQ4VLX160 4 or 5 2
XQ4VSX55 4 2
XQ4VFX60 8 1
XQ4VFX100 6 1
Tabl e 6 0 : Current LX and SX Production Devices
LX/SX Device Stepping Step 2
Example Ordering Code XQ4VLX60-10FF668M
Device steppings shipped when ordered per
Example Ordering Code
Step 2 only (see Ta bl e 59 )
Capability Improvements
•T
CONFIG requirement is removed
• DCM_RESET requirement is removed
• DCM_INPUT_CLOCK_STOP requirement is removed by a
macro (automatically inserted by ISE software)
CONFIG STEPPING parameter (must be set in UCF file) “2”
Minimum Software Required ISE 7.1i SP4
Minimum Speed Specification Required 1.58
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 40
Ta bl e 6 1 summarizes the current production FX device stepping.
Revision History
The following table shows the revision history for this document.
Tabl e 6 1 : Current FX Production Devices
FX Device Stepping Step 1
Example Ordering Code XQ4VFX60-10EF672M
Device steppings shipped when ordered per
Example Ordering Code
Step 1 only (see Ta bl e 59 )
Capability Improvements See FX Errata for details
CONFIG STEPPING parameter (must be set in UCF file) “1”
Minimum Software Required ISE 8.1i SP2
Minimum Speed Specification Required 1.58
Date Version Revisions
11/29/06 1.0 Initial Xilinx release.
10/11/07 1.1 • SPEED SPECIFICATION version for this data sheet release: v1.67.
• Updated template.
• Added support for industrial temperature range devices: XQ4VLX100-10FF1148I, and
XQ4VLX160-10FF1148I.
• Added section Master/Slave SelectMAP Parameters, page 27.
• Other updates and fixes.
12/20/07 1.2 • Updated document template.
• Updated URLs.
• Added support for XQ4VFX60-10EF672M and XQ4FVFX60-10EF672I.
• Other minor fixes.
02/11/08 1.3 Added support for XQ4VLX40-10FF668I.
05/05/08 1.4 • Added support for XQ4VLX40-10FF668M.
• Added I-Grade and M-Grade columns and updated values to Table 4, page 3, Table 38, page 26,
and Table 50, page 34 through Table 54, page 36.
• Updated values in Table 5, page 4.
• Updated device production status in Table 13, page 9.
• Added section PowerPC Switching Characteristics, page 10.
• Added Table 24, page 16.
• Added section Ethernet MAC Switching Characteristics, page 18.
• Added note to Table 41, page 30 regarding support for MR mode.
• Updated values in Table43, page30.
• Added parameters DCM_RESET(3) and DCM_INPUT_CLOCK_STOP to Table46, page32.
• Added Table 61, page 40.
• Updated trademark notations.
• Removed Notice of Disclaimer.
10/16/09 1.5 • Added EF668 package to XQ4VLX60 in Table 56, page 38.
• Added Notice of Disclaimer, page 41.
04/27/10 1.6 Changed the document classification from Preliminary Product Specification to Product Specification.
Replaced “QPro Virtex-4 FPGA” with “Virtex-4Q FPGA” throughout. Removed XQ4VLX25 I-grade from
Ta b l e 4 , Ta b l e 5 0 , Ta b l e 5 1 , Ta b l e 5 2 , Ta bl e 5 3 , and Ta b l e 5 4 . (This device was planned but never
opened for order entry.)
12/21/11 2.0 Revised the first page summary to incorporate adding the XQ4VLX80 and XQ4VFX100 in -11 speed
specification for industrial temperature ranges only throughout this data sheet. Also added the
XQ4VLX100 -11 speed specification industrial temperature range throughout this data sheet.
Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics
DS595 (v2.0) December 21, 2011 www.xilinx.com
Product Specification 41
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