1
SuperLite™
SY55857L
Micrel, Inc.
M9999-082306
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
Input accepts virtually all logic standards:
Single-ended: SSTL, TTL, CMOS
Differential: LVDS, HSTL, CML
Guaranteed AC parameters over temperature:
•f
MAX > 2.5Gbps (2.5GHz toggle)
•t
r/t
f < 200ps
Within-device skew < 50ps
Propagation delay < 400ps
Low power: 46mW/channel (typ)
3.0V to 3.6V power supply
100K LVPECL outputs
Flow-through pinout and fully differential design
Two channels in a 10-pin (3mm ××
××
×3mm) MSOP
package
The SY55857L is a fully differential, high-speed dual
translator optimized to accept any logic standard from
single-ended TTL/CMOS to differential LVDS, HSTL, or
CML and translate it to LVPECL. Translation is
guaranteed for speeds up to 2.5Gbps (2.5GHz toggle
frequency). The SY55857L does not internally terminate
its inputs, as different interfacing standards have different
termination requirements.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
FEATURES
3.3V, 2.5Gbps
ANY INPUT-to-LVPECL
DUAL TRANSLATOR
SuperLite™
SY55857L
APPLICATIONS
High-speed logic
Data communications systems
Wireless communications systems
Telecom systems
FUNCTIONAL BLOCK DIAGRAM
Rev.: E Amendment: /0
Issue Date: August 2006
SuperLite is a trademark of Micrel, Inc.
D0
/D0
Q0
/Q0
D1
/D1
Q1
/Q1
CH0
CH1
LVPECL OUT
LVPECL OUT
Any IN
Any IN
SuperLite™
2
SuperLite™
SY55857L
Micrel, Inc.
M9999-082306
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTIONS
Pin Number Pin Name Description
D0, /D0 1, 2 Channel 0 Differential Inputs (clock or data). See Figure 2 for input structure.
See Input Interface section for typical interface recommendations.
D1, /D1 3, 4 Channel 1 Differential Inputs (clock or data). See Figure 2 for input structure.
See Input Interface section for typical interface recommendations.
Q0, /Q0 9, 8 Channel 0 Differential 100k-compatible LVPECL Outputs. Terminate to
VCC 2V. See LVPECL Output Termination section. Outputs are low
impedance, emitter-followers. For AC-coupled applications, a pull-down
resistor is required on Q and /Q to ensure a DC current path to GND.
Q1, /Q1 7, 6 Channel 1 Differential 100k-compatible LVPECL Outputs. Terminate to
VCC 2V. See LVPECL Output Termination section. Outputs are low
impedance, emitter-followers. For AC-coupled applications, a pull-down
resistor is required on Q and /Q to ensure a DC current path to GND.
GND 5 Device Ground. Typically connected to Logic ground.
VCC 10 Supply Voltage. Typically connect to +3.3V ±10% supply. Bypass with
0.01µF0.1µF low ESR capacitors.
1D0
/D0
D1
/D1
GND
10 VCC
Q0
/Q0
Q1
/Q1
9
8
7
6
2
3
4
5
10-Pin MSOP (K10-1)
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY55857LKI K10-1 Industrial 857L Sn-Pb
SY55857LKITR(2) K10-1 Industrial 857L Sn-Pb
SY55857LKG(3) K10-1 Industrial 857L with NiPdAu
Pb-Free bar line indicator Pb-Free
SY55857LKGTR(2, 3) K10-1 Industrial 857L with NiPdAu
Pb-Free bar line indicator Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
3
SuperLite™
SY55857L
Micrel, Inc.
M9999-082306
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings(1)
Power Supply Voltage (VCC )...................... 0.5V to +6.0V
Input Voltage (VIN) ...............................0.5V to VCC +0.5V
Output Current (IOUT)
Continuous .............................................................50mA
Surge....................................................................100mA
Lead Temperature (soldering, 20 sec.) ................... +260°C
Storage Temperature Range (TS )...........65°C to +150°C
Operating Ratings(2)
Power Supply Voltage (VCC)....................... +3.0V to +3.6V
Ambient Temperature Range (TA) .............40°C to +85°C
Package Thermal Resistance(3)
MSOP (θJA)
Still-Air ...........................................................113°C/W
500lpfm............................................................96°C/W
MSOP (θJC)
Junction-to-Case .............................................42°C/W
TA = 40°C to +85°C; unless noted.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply Voltage 3.0 3.3 3.6 V
ICC Power Supply Current Inputs/outputs open 28 45 mA
DC ELECTRICAL CHARACTERISTICS(4)
VCC = +3.0V to +3.6V; GND = 0V; TA = 40°C to +85°C; unless noted.
Symbol Parameter Condition Min Typ Max Units
VID Input Voltage Swing See Figure 1a, VIN < 2.4V. 100 mV
VIN <V
CC+0.3V 200 mV
VIH Input HIGH Voltage VCC+0.3 V
VIL Input LOW Voltage 0.3 V
INPUT ELECTRICAL CHARACTERISTICS(4)
VCC = +3.0V to +3.6V; GND = 0V; TA = 40°C to +85°C; RL = 50 to VCC 2V, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VOL Output LOW Voltage VCC1.945 VCC1.820 VCC1.695 V
Q, /Q
VOH Output HIGH Voltage VCC1.145 VCC1.020 VCC0.895 V
Q, /Q
VOUT Output Voltage Swing See Figure 1a. 550 800 mV
Q, /Q
VDIFF_OUT Differential Output Voltage Swing See Figure 1b. 1100 1600 mVpp
Q, /Q
Notes:
1. Permanent device damage may occur if the ratings in Absolute Maximum Ratings section are exceeded. This is a stress rating only and functional
operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential (GND) on the PCB. ψJB uses
4-layer θJA in still air unless otherwise stated.
4. The specifications shown are valid after thermal equilibrium has been established.
5. 100K circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
(100K) LVPECL OUTPUT CHARACTERISTICS(5)
4
SuperLite™
SY55857L
Micrel, Inc.
M9999-082306
hbwhelp@micrel.com or (408) 955-1690
VCC = 3.3V ±10%; TA= 40°C to +85°C; RL = 50 to VCC 2V, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Operating Frequency VIN < 2.4V NRZ Data 2.5 Gbps
Note 6 VIN < 2.4V Clock 2.5 GHz
VIN < VCC +0.3V NRZ Data 1.25 Gbps
VIN < VCC +0.3V Clock 1.25 GHz
tPD Propagation Delay D-to-Q 400 ps
tSKEW Within-Device-Skew (Differential) Note 7 50 ps
Part-to-Part Skew (Differential) Note 8 200 ps
tJITTER Random Jitter (RJ) Note 9 1ps
RMS
Deterministic Jitter (DJ) Note 10 10 psPP
Total Jitter (TJ) Note 11 110ps
PP
tr, tfOutput Rise/Fall Time 20% to 80% At full output swing 200 ps
Notes:
6. Clock frequency is defined as the maximum toggle frequency, and guaranteed for functionality only. Measured with a 750mV signal, 50% duty cycle
and VOUT swing 400mV. High -frequency AC-parameters are guaranteed by design and characterization.
7. Within-device skew is measured between two different outputs under identical transitions.
8. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
9. Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps.
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2231 PRBS pattern.
11. Total jitter definition: with an ideal differential clock input of frequency fMAX, no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS
SINGLE-ENDED AND DIFFERENTIAL SWINGS
VID,
VOUT 800mV (Typ.)
Figure 1a. Single-Ended Voltage Swing
VDIFF_IN,
VDIFF_OUT 1600mV (Typ.)
Figure 1b. Differential Voltage Swing
5
SuperLite™
SY55857L
Micrel, Inc.
M9999-082306
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL DESCRIPTION
Establishing Static Logic Inputs
Do not leave unused inputs floating. Tie either the true or
complement inputs to ground, but not both. A logic zero is
achieved by connecting the complement input to ground
with the true input floating. For a TTL input, tie a 2.5k
resistor between the complement input and ground. See
Input Interface section.
Input Levels
LVDS, CML and HSTL differential signals may be
connected directly to the D inputs. Depending on the actual
worst case voltage seen, performance of SY55857L varies
as per the following table:
Input Voltage Minimum Maximum
Range Voltage Swing Translation Speed
0 to 2.4V 100mV 2.5Gbps
0 to VCC +0.3 200mV 1.25Gbps
Table 1. Input Voltage Swings
For LVDS applications, only point-to-point interfaces are
supported. Due to the current required by the input structure
shown in Figure 2, mutli-drop and multi-point architectures
are not supported.
R2
1.5k
R2
1.5k
R1
1.05k
R1
1.05k
GND
DIN
/DIN
VCC
Figure 2. Simplified Input Structure
6
SuperLite™
SY55857L
Micrel, Inc.
M9999-082306
hbwhelp@micrel.com or (408) 955-1690
INPUT INTERFACE
D
/D SY55857L
TTL
LVTTL
2.5k
1%
V
CC(DRIVER)
V
CC(857)
V
CC(DRIVER)
Figure 3. 3.3V TTL
CML D
/D
VCC(DRIVER) VCC(857) VCC(DRIVER)
102
1% SY55857L
Figure 4. CML-DC Coupled
D
/D SY55857L
2.5V
LVTTL
2.5k
1%
2.3V to 2.7V V
CC
Figure 5. 2.5V TTL
PECL D
/D
51
1%
51
1%
V
CC(DRIVER)
V
CC(857)
V
CC(DRIVER)
SY55857L
V
CC
2V
Figure 6. PECL-DC Coupled
HSTL D
/D SY55857L
V
CC
5050
Figure 7. HSTL
CML D
/D
3.92k
1%
3.92k
1%
102
1%
V
CC(DRIVER)
V
CC
SY55857L
Figure 8. CML-AC Coupled
Short Lines
CML D
/D
130
1%
130
1%
VCC(DRIVER) VCC
SY55857L
82
1%
82
1%
VCC
Figure 9. CML-AC Coupled
Long Lines
LVDS D
/D
VCC
102
1% SY55857L
Figure 10. LVDS
D
/D
100
1%
100
1%
V
CC
SY55857L
105
1%
105
1%
SSTL_2
V
DDQ
Figure 11. SSTL_2
D
/D
90.9
1%
90.9
1%
VCC
SY55857L
110
1%
110
1%
SSTL_3
VDDQ
Figure 12. SSTL_3
7
SuperLite
SY55857L
Micrel, Inc.
M9999-082306
hbwhelp@micrel.com or (408) 955-1690
LVPECL OUTPUT TERMINATION
LVPECL output have very low output impedance (open
emitter), and small signal swing which results in low EMI.
LVPECL is ideal for driving 50 and 100-controlled
impedance transmission lines. There are several
techniques in terminating the LVPECL output, as shown
in Figures 13 through 15.
R2
82
R2
82
*Note. For +2.5V systems,
R1 = 250Ω, R2 = 62.5
Z
O
= 50
Z
O
= 50
+3.3V* +3.3V*
V
T
= V
CC
2V
R1
130R1
130
+3.3V*
SY58021U
Figure 13. Parallel Termination-Thevenin Equivalent
Notes:
1. For +2.5V systems: R1 = 250, R2 = 62.5.
2. For +3.3V systems: R1 = 130, R2 = 82.
Z = 50
Z = 50
5050
50
+3.3V +3.3V
sourcedestination
Rb*C1 (optional)
0.01µF
* For +2.5V, Rb = 19
* For +3.3V, Rb = 46to 50
Notes:
1. Power saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. Rb resistor sets the DC bias voltage, equal to VT.
SY58021U
VDD
Figure 14. Three-Resistor Y-Termination
Notes:
1. Power-saving alternatives to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. Rb resistor sets the DC bias voltage, equal to VT.
For +2.5V systems: Rb = 19.
For +3.3V systems: Rb = 46 to 50.
4. C1 is an optional bypass capacitor intended to compensate for any tr/tf
mismatches.
R2
82
R2
82
*Note:
For +2.5V systems,
R1 = 250Ω, R2 = 62.5
Z
O
= 50
Z
O
= 50
+3.3V* +3.3V*
V
T
= V
CC
2V
R1
130R1
130
+3.3V*
SY58021U
Figure 15. Terminating Unused I/O
Notes:
1. Unused output (/Q) must be terminated to balance the output.
2. For +2.5V systems: R1 = 250, R2 = 62.5, R3 = 1.25k, R4 =
1.2k.
For +3.3V systems: R1 = 130, R2 = 82, R3 = 1k, R4 = 1.6k.
3. Unused output pairs (Q and /Q) may be left floating.
8
SuperLite
SY55857L
Micrel, Inc.
M9999-082306
hbwhelp@micrel.com or (408) 955-1690
10-PIN MSOP (K10-1)
Rev. 00
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchasers
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchasers own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.