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FEATURES
DL PACKAGE
(TOP VIEW)
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1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
DESCRIPTION/ORDERING INFORMATION
SN74LVTH162373-EP3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCBS811A – JULY 2006 – REVISED JULY 2006
•Controlled Baseline •Flow-Through Architecture Optimizes PCBLayout– One Assembly/Test Site, One FabricationSite •Latch-Up Performance Exceeds 500 mA PerJESD 17•Extended Temperature Performance of –55 °Cto 125 °C•ESD Protection Exceeds JESD 22•Enhanced Diminishing Manufacturing – 2000-V Human-Body Model (A114-A)Sources (DMS) Support
– 200-V Machine Model (A115-A)•Enhanced Product-Change Notification
xxxxxxxxxxxx
•Qualification Pedigree
(1)
•Member of the Texas Instruments Widebus™Family
•Output Ports Have Equivalent 22- ΩSeriesResistors, So No External Resistors AreRequired
•Supports Mixed-Mode Signal Operation (5-VInput and Output Voltages With 3.3-V V
CC
)•Supports Unregulated Battery OperationDown to 2.7 V•Typical V
OLP
(Output Ground Bounce) <0.8 Vat V
CC
= 3.3 V, T
A
= 25 °C•I
off
and Power-Up 3-State Support HotInsertion
•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•Distributed V
CC
and GND Pins MinimizeHigh-Speed Switching Noise
(1) Component qualification in accordance with JEDEC andindustry standards to ensure reliable operation over anextended temperature range. This includes, but is not limitedto, Highly Accelerated Stress Test (HAST) or biased 85/85,temperature cycle, autoclave or unbiased HAST,electromigration, bond intermetallic life, and mold compoundlife. Such qualification testing should not be viewed asjustifying use of this component beyond specifiedperformance and environmental limits. xxxx
The SN74LVTH162373 is a 16-bit transparent D-type latch with 3-state outputs designed for low-voltage (3.3-V)V
CC
operation, but with the capability to provide a TTL interface to a 5-V system environment. This device isparticularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
–55 °C to 125 °C SSOP – DL Tape and reel CLVTH162373MDLREP LVTH162373EP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
1OE
1LE
1D1
ToSevenOtherChannels
1Q1
2OE
2LE
2D1
2Q1
ToSevenOtherChannels
1
48
47
24
25
36
C1
1D
132
C1
1D
SN74LVTH162373-EP
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCBS811A – JULY 2006 – REVISED JULY 2006
A buffered output-enable ( OE) input can be used to place the eight outputs in either a normal logic state (high orlow logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive thebus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lineswithout interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered whilethe outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- Ωseries resistors toreduce overshoot and undershoot.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldownresistors with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitrydisables the outputs, preventing damaging current backflow through the device when it is powered down. Thepower-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,which prevents driver conflict.
This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Qoutputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the Dinputs.
FUNCTION TABLE(EACH 8-BIT SECTION)
INPUTS
OUTPUT
QOE LE D
L H H HL H L LL L X Q
0
H X X Z
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN74LVTH162373-EP3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCBS811A – JULY 2006 – REVISED JULY 2006
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 4.6 VV
I
Input voltage range
(2)
–0.5 7 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
–0.5 7 VV
O
Voltage range applied to any output in the high state
(2)
–0.5 V
CC
+ 0.5 VI
O
Current into any output in the low state 30 mAI
O
Current into any output in the high state
(3)
30 mAI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAθ
JA
Package thermal impedance
(4)
63 °C/WT
stg
Storage temperature range
(5)
–65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3) This current flows only when the output is in the high state and V
O
> V
CC
.(4) The package thermal impedance is calculated in accordance with JESD 51-7.(5) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction ofoverall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
MIN MAX UNIT
V
CC
Supply voltage 2.7 3.6 VV
IH
High-level input voltage 2 VV
IL
Low-level input voltage 0.8 VV
I
Input voltage 5.5 VI
OH
High-level output current –12 mAI
OL
Low-level output current 12 mA∆t/ ∆v Input transition rise or fall rate Outputs enabled 10 ns/V∆t/ ∆V
CC
Power-up ramp rate 200 µs/VT
A
Operating free-air temperature –55 125 °C
(1) All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3Submit Documentation Feedback
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Electrical Characteristics
Timing Requirements
SN74LVTH162373-EP
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCBS811A – JULY 2006 – REVISED JULY 2006
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IK
V
CC
= 2.7 V, I
I
= –18 mA –1.2 VV
OH
V
CC
= 3 V, I
OH
= –12 mA 2 VV
OL
V
CC
= 3 V, I
OL
= 12 mA 0.8 VV
CC
= 0 or 3.6 V, V
I
= 5.5 V 10Control inputs V
CC
= 3.6 V, V
I
= V
CC
or GND ±1I
I
µAV
I
= V
CC
1Data inputs V
CC
= 3.6 V
V
I
= 0 –5V
I
= 0.8 V 75I
I(hold)
Data inputs V
CC
= 3 V µAV
I
= 2 V –75I
OZH
V
CC
= 3.6 V, V
O
= 3 V 5 µAI
OZL
V
CC
= 3.6 V, V
O
= 0.5 V –5 µAI
OZPU
V
CC
= 0 to 1.5 V, V
O
= 0.5 V to 3 V, OE = don't care ±100
(1)
µAI
OZPD
V
CC
= 1.5 V to 0, V
O
= 0.5 V to 3 V, OE = don't care ±100
(1)
µAOutputs high 0.19V
CC
= 3.6 V,I
CC
I
O
= 0, Outputs low 5 mAV
I
= V
CC
or GND
Outputs disabled 0.19V
CC
= 3 V to 3.6 V, One input at V
CC
– 0.6 V,∆I
CC
(2)
0.2 mAOther inputs at V
CC
or GNDC
i
V
I
= 3 V or 0 3 pFC
o
V
O
= 3 V or 0 9 pF
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.(2) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC
or GND.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
V
CC
= 3.3 V
V
CC
= 2.7 V±0.3 V
UNITMIN MAX MIN MAX
t
w
Pulse duration, LE high 3 3 nst
su
Setup time, data before LE ↓1.3 0.6 nst
h
Hold time, data after LE ↓1 1.1 ns
4
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Switching Characteristics
SN74LVTH162373-EP3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCBS811A – JULY 2006 – REVISED JULY 2006
over recommended operating free-air temperature range, C
L
= 50 pF (unless otherwise noted) (see Figure 1 )
V
CC
= 3.3 V
V
CC
= 2.7 VFROM TO
±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX
t
PLH
1.8 5 5.7D Q nst
PHL
1.8 4.4 4.8t
PLH
2.1 5.4 6.2LE Q nst
PHL
2.1 4.9 4.7t
PZH
1.7 5.6 7OE Q nst
PZL
1.7 5.3 5.9t
PHZ
2.3 6.3 6.6OE Q nst
PLZ
1 7.4 6.4
5Submit Documentation Feedback
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PARAMETER MEASUREMENT INFORMATION
th
tsu
FromOutput
UnderTest
C =50pF
(seeNote A)
L
LOADCIRCUIT
S1
6V
GND
500 W
500 W
DataInput
TimingInput
2.7V
0V
2.7V
0V
2.7V
0V
tw
Input
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
VOLTAGEWAVEFORMS
PULSEDURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
2.7V
0V
Input Output
Control
Output
Waveform1
S1at6V
(seeNoteB)
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3V
0V
V +0.3V
OL
V 0.3V
OH -
»0V
2.7V
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
Output
Output
t /t
PLH PHL
t /t
PLZ PZL
t /t
PHZ PZH
Open
6V
GND
TEST S1
Open
1.5V 1.5V
1.5V 1.5V
1.5V 1.5V
1.5V 1.5V
1.5V
1.5V 1.5V
1.5V 1.5V
1.5V
1.5V
SN74LVTH162373-EP
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCBS811A – JULY 2006 – REVISED JULY 2006
A. C
L
includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the outputcontrol. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by theoutput control.C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω,t
r
≤2.5 ns, t
f
≤2.5 ns.D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CLVTH162373MDLREP ACTIVE SSOP DL 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06654-01XE ACTIVE SSOP DL 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVTH162373-EP :
•Catalog: SN74LVTH162373
•Military: SN54LVTH162373
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CLVTH162373MDLREP SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Aug-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CLVTH162373MDLREP SSOP DL 48 1000 346.0 346.0 49.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Aug-2008
Pack Materials-Page 2
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