2:4, LVDS Output Fanout Buffer, 2.5V IDT8SLVD1204I Datasheet Description Features The IDT8SLVD1204I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8SLVD1204I is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVD1204I ideal for those clock distribution applications demanding well-defined performance and repeatability. * * * Four low skew, low additive jitter LVDS output pairs * * * * * Maximum input clock frequency: 2GHz * * * Full 2.5V supply voltage Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise. Two selectable differential clock input pairs Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL LVCMOS/LVTTL interface levels for the control input select pin Output skew: 20ps (maximum) Propagation delay: 300ps (maximum) Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz - 20MHz: 95fs (maximum) Lead-free (RoHS 6), 16-Lead VFQFPN packaging -40C to 85C ambient operating temperature 12 11 10 Q2 13 GND GND Q1 0 VDD nQ1 7 nPCLK0 Q3 15 6 PCLK0 nQ3 16 1 5 VDD 2 3 4 PCLK1 nQ0 8 VREF nPCLK1 Q0 Pullup/Pulldown 9 nQ2 14 SEL nPCLK0 Pulldown GND PCLK0 Q0 nQ1 VDD nQ0 Pin Assignment Q1 Block Diagram IDT8SLVD1204I 16 lead VFQFPN PCLK1 nPCLK1 Pulldown Q2 1 Pullup/Pulldown nQ2 3.0mm x 3.0mm x 0.9mm package body 1.7mm x 1.7mm ePad NL Package Top View Q3 GND GND nQ3 VDD SEL Pullup/Pulldown GND VREF IDT8SLVD1204I November 29, 2018 Reference Voltage Generator 1 (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 GND Power 2 SEL Input Pullup/ Pulldown Reference select control pin. See Table 3 for function. LVCMOS/LVTTL interface levels. 3 PCLK1 Input Pulldown Non-inverting differential clock/data input. 4 nPCLK1 Input Pullup/ Pulldown Inverting differential clock/data input. VDD/2 default when left floating. 5 VDD Power 6 PCLK0 Input Pulldown Non-inverting differential clock/data input. 7 nPCLK0 Input Pullup/ Pulldown Inverting differential clock/data input. VDD/2 default when left floating. 8 VREF Output Bias voltage reference for the PCLK, nPCLK inputs. 9, 10 Q0, nQ0 Output Differential output pair 0. LVDS interface levels. 11, 12 Q1, nQ1 Output Differential output pair 1. LVDS interface levels. 13, 14 Q2, nQ2 Output Differential output pair 2. LVDS interface levels. 15, 16 Q3, nQ3 Output Differential output pair 3. LVDS interface levels. Power supply ground. Power supply pin. NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 2 pF RPULLDOWN Input Pulldown Resistor 51 k RPULLUP Input Pullup Resistor 51 k Function Table Table 3. SEL Input Selection Function Table Input SEL Operation 0 PCLK0, nPCLK0 is the selected differential clock input. 1 PCLK1, nPCLK1 is the selected differential clock input. Open (default) Input buffers are disabled and outputs are static. NOTE: SEL is an asynchronous control. IDT8SLVD1204I November 29, 2018 2 (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET Absolute Maximum Ratings Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA VREF current Sink/Source, IREF 2mA Maximum Junction Temperature, TJ,MAX 150C Storage Temperature, TSTG -65C to 150C ESD - Human Body Model, NOTE 1 2000V ESD - Charged Device Model, NOTE 1 1500V NOTE 1: According to JEDEC/JESD JS-001-2012/22-C101E. Recommended Operating Conditions Symbol Parameter TA Ambient air temperature TJ Junction temperature Minimum Typical Maximum Units 85 C 125 C -40 NOTE 1: It is the user's responsibility to ensure that device junction temperature remains below the maximum allowed. NOTE 2: All conditions in the table must be met to guarantee device functionality. NOTE 3: The device is verified to the maximum operating junction temperature through simulation. Electrical Characteristics Table 4A. Power Supply Characteristics, VDD = 2.5V 5%, TA = -40C to 85C Symbol Parameter VDD Power Supply Voltage IDD Power Supply Current IDT8SLVD1204I November 29, 2018 Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V SEL = 0 or 1; fREF = 100MHz; Q0 to Q3 terminated 100 between nQx, Qx 84 100 mA SEL = 0 or 1; fREF = 800MHz; Q0 to Q3 terminated 100 between nQx, Qx 84 100 mA SEL = 0 or 1; fREF = 2GHz; Q0 to Q3 terminated 100 between nQx, Qx 84 100 mA 3 (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C Symbol Parameter Test Conditions Minimum VdI3 Open-Pin Voltage (Default State) SEL VIH Input High Voltage SEL 0.7 * VDD VDD + 0.3 V VIL Input Low Voltage SEL -0.3 0.2 * VDD V IIH Input High Current SEL VDD = VIN = 2.625V 150 A IIL Input Low Current SEL VDD = 2.625V, VIN = 0V Open Typical Maximum VDD / 2 Units V -150 A Table 4C. Differential Input DC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VREF Reference Voltage for Input Bias VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units 150 A PCLK0, nPCLK1 PCLK1, nPCLK1 VDD = VIN = 2.625V PCLK0, PCLK1 VDD = 2.625V, VIN = 0V -10 A nPCLK0, nPCLK1 VDD = 2.625V, VIN = 0V -150 A IREF = 1mA VDD - 1.50 fREF < 1.5 GHz fREF > 1.5 GHz VDD - 1.35 VDD - 1.15 V 0.1 1.5 V 0.2 1.5 V 1.0 VDD - 0.6 V Maximum Units 450 mV 50 mV 1.45 V 50 mV NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined at the crosspoint. Table 4D. LVDS DC Characteristics, VDD = 2.5V 5%, TA = -40C to 85 Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change IDT8SLVD1204I November 29, 2018 Test Conditions Minimum 250 1.15 4 Typical (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET AC Electrical Characteristics Table 5. AC Electrical Characteristics, VDD = 2.5V 5%, TA = -40C to 85C Symbol Parameter Test Conditions fREF Input Frequency PCLK[0:1], nPCLK[0:1] V/t Input Edge Rate PCLK[0:1], nPCLK[0:1] tPD Propagation Delay; NOTE 1 tsk(o) Minimum Typical Maximum Units 2 GHz 1.5 PCLK[0:1], nPCLK[0:1] to any Qx, nQx for VPP = 0.1V or 0.3V 300 ps Output Skew; NOTE 2, 3 20 ps tsk(i) Input Skew; NOTE 3 20 ps tsk(p) Pulse Skew 15 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 230 ps tJIT Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 120 V/ns 210 fREF = 100MHz fREF = 122.88MHz Square Wave, VPP = 1V, Integration Range: 1kHz - 40MHz 138 205 fs fREF = 122.88MHz Square Wave, VPP = 1V, Integration Range: 10kHz - 20MHz 92 135 fs fREF = 122.88MHz Square Wave, VPP = 1V, Integration Range: 12kHz - 20MHz 92 135 fs fREF = 156.25MHz Square Wave, VPP = 1V, Integration Range: 1kHz - 40MHz 89 130 fs fREF = 156.25MHz Square Wave, VPP = 1V, Integration Range: 10kHz - 20MHz 65 95 fs fREF = 156.25MHz Square Wave, VPP = 1V, Integration Range: 12kHz - 20MHz 65 95 fs fREF = 156.25MHz Square Wave, VPP = 0.5V, Integration Range: 1kHz - 40MHz 87 130 fs fREF = 156.25MHz Square Wave, VPP = 0.5V, Integration Range: 10kHz - 20MHz 64 95 fs fREF = 156.25MHz Square Wave, VPP = 0.5V, Integration Range: 12kHz - 20MHz 64 95 fs 250 ps t R / tF Output Rise/ Fall Time 20% to 80% outputs loaded with 100 MUXISOLATION Mux Isolation; NOTE 5 fREF = 100MHz 40 72 dB NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint. NOTE 5: Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section. IDT8SLVD1204I November 29, 2018 5 (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise (dBc/Hz) Additive Phase Jitter @ 156.25MHz, VPP = 1V, Integration Range (12kHz to 20MHz) = 65fs (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. The noise floor of the equipment can be higher or lower than the noise floor of the device. Additive phase noise is dependent on both the noise floor of the input source and measurement equipment. IDT8SLVD1204I November 29, 2018 Measured using a Wenzel 156.25MHz Oscillator as the input source. 6 (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET Parameter Measurement Information VDD VDD nPCLK[0:1] PCLK[0:1] GND LVDS Output Load Test Circuit Differential Input Level nPCLK[0:1] nQx PCLK[0:1] Qx nQy nQy Qy t PLH Qy t PHL tsk(p) = |t PHL - t PLH| Pulse Skew nQx Output Skew Par t 1 nQ[0:3] 80% 80% Qx nQy VOD Par t 2 Q[0:3] 20% 20% tR tF Qy tsk(pp) Part-to-Part Skew IDT8SLVD1204I November 29, 2018 Output Rise/Fall Time 7 (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET Parameter Measurement Information, continued nPCLK0 Spectrum of Output Signal Q PCLK0 MUX selects active input clock signal A0 Amplitude (dB) nPCLK1 PCLK1 nQ[0:3] MUX_ISOLATION = A0 - A1 MUX selects other input A1 Q[0:3] tPD2 tPD1 (fundamental) tsk(i) Frequency tsk(i) = |tPD1 - tPD2| Input Skew MUX Isolation nPCLK[0:1] PCLK[0:1] nQ[0:3] Q[0:3] tPD Propagation Delay Offset Voltage Setup Differential Output Voltage Setup IDT8SLVD1204I November 29, 2018 8 (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: PCLK/nPCLK Inputs LVDS Outputs For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V1 = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1 in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 2.5V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels IDT8SLVD1204I November 29, 2018 9 (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET 2.5V LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, LVDS, and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2C show interface examples for the PCLK/ nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V PCLK nPCLK LVPECL Input LVPECL Figure 2B. PCLK/nPCLK Input Driven by a 2.5V LVPECL Driver with AC Couple Figure 2A. PCLK/nPCLK Input Driven by a 2.5V LVPECL Driver PCLK nPCLK Figure 2C. PCLK/nPCLK Input Driven by a 2.5V LVDS Driver IDT8SLVD1204I November 29, 2018 10 (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The LVDS Driver standard termination schematic as shown in Figure 3A can be used with either type of output structure. Figure 3B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver's amplitude and common-mode input range should be verified for compatibility with the output. ZO ZT ZT LVDS Receiver Figure 3A. Standard Termination LVDS Driver ZO ZT C ZT 2 LVDS ZT Receiver 2 Figure 3B. Optional Termination LVDS Termination IDT8SLVD1204I November 29, 2018 11 (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET VFQFPN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale) IDT8SLVD1204I November 29, 2018 12 (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET Power Considerations This section provides information on power dissipation and junction temperature for the IDT8SLVD1204I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the IDT8SLVD1204I is the sum of the core power plus the output power dissipation due to the load. The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. * 2. Total Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 100mA = 262.5mW Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 74.7C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.263W * 74.7C/W = 104.6C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 16-Lead VFQFPN, Forced Convection JA at 0 Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT8SLVD1204I November 29, 2018 0 1 2.5 74.7C/W 65.3C/W 58.5C/W 13 (c)2018 Integrated Device Technology, Inc. IDT8SLVD1204I DATASHEET Reliability Information Table 7. JA vs. Air Flow Table for a 16-Lead VFQFPN JA at 0 Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 74.7C/W 65.3C/W 58.5C/W Transistor Count The transistor count for the IDT8SLVD1204I is: 417 Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/document/psc/16-vfqfpn-package-outline-drawing-30-x-30-x-09-mm-05-mm-170-x-170-mm-epad-nlnlg16p2 Ordering Information Table 8. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8SLVD1204NLGI 1204I "Lead-Free" 16-Lead VFQFPN Tube -40C to 85C 8SLVD1204NLGI8 1204I "Lead-Free" 16-Lead VFQFPN Tape & Reel, pin 1 orientation: EIA-481-C -40C to 85C 8SLVD1204NLGI/W 1204I "Lead-Free" 16-Lead VFQFPN Tape & Reel, pin 1 orientation: EIA-481-D -40C to 85C Table 9. Pin 1 Orientation in Tape and Reel Packaging Part Number Suffix Pin 1 Orientation Illustration Correct Pin 1 ORIENTATION 8 CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 1 (EIA-481-C) USER DIRECTION OF FEED Correct Pin 1 ORIENTATION /W CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 2 (EIA-481-D) USER DIRECTION OF FEED IDT8SLVD1204I November 29, 2018 14 (c)2018 Integrated Device Technology, Inc. Revision History Revision Date Description of Change * Updated the description of Absolute Maximum Ratings November 29, 2018 * Added Recommended Operating Conditions * Updated the description of Package Outline Drawings January 21, 2018 July 8, 2014 February 26, 2014 * Updated the package outline drawings; however, no technical changes. * Replaced the package term VFQFN with VFQFPN. Corrected part number Ordering Info: Changed Tray to Tube. Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as "IDT") reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc All rights reserved. IDT8SLVD1204I November 29, 2018 15 (c)2018 Integrated Device Technology, Inc. 16-VFQFPN Package Outline Drawing 3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad NL/NLG16P2, PSC-4169-02, Rev 05, Page 1 16-VFQFPN Package Outline Drawing 3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad NL/NLG16P2, PSC-4169-02, Rev 05, Page 2 Package Revision History Description Date Created Rev No. Oct 25, 2017 Rev 04 Remove Bookmak at Pdf Format & Update Thickness Tolerance Jan 18, 2018 Rev 05 Change QFN to VFQFPN