K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 1 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
Document Title
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
History
1. Initial draft
1. Changed DC parameters
Icc ; from 570mA to 490mA at -30,
from 520mA to 440mA at -27,
from 470mA to 400mA at -25,
from 440mA to 360mA at -22,
from 400mA to 330mA at -20,
from 370mA to 310mA at -18,
ISB ; from 200mA to 180mA at -30,
from 190mA to 170mA at -27,
from 180mA to 160mA at -25,
from 170mA to 155mA at -22,
from 160mA to 150mA at -20,
from 150mA to 140mA at -18,
ISB1 ; from 100mA to 80mA
2. Input set-up(tAS,tSS,tDS,tWS,tADVS,tCSS) from 0.6ns to 0.7ns at -30
1. Delete Pass-Through
1. Changed Input set-up(tAS,tSS,tDS,tWS,tADVS,tCSS)
- from 0.8ns to 1.0ns at -25
- from 075ns to 0.8ns at -27
- from 0.7ns to 0.8ns at -30
1. Add x32 org and industrial range temperature
Draft Date
May. 15. 2001
June. 12. 2001
June. 25. 2001
July. 31. 2001
Aug. 11. 2001
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. No
0.0
0.1
0.2
0.3
0.4
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 2 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
4Mb SB/SPB Synchronous SRAM Ordering Information
Org. Part Number Mode VDD Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz) PKG Temp
256Kx18 K7B401825B-QC(I)65/75/80 SB 3.3 6.5/7.5/8.0 ns
Q
(100TQFP)
C
(Commercial
Temperature
Range)
I:
(Industrial
Temperature
Range)
K7A401800B-QC(I)16/14 SPB(2E1D) 3.3 167/138 MHz
K7A401809B-QC(I)30/27/25/22/20 SPB(2E1D) 3.3 300/275/250/225/200 MHz
128Kx32
K7B403225B-QC(I)65/75/80 SB 3.3 6.5/7.5/8.0 ns
K7A403200B-QC(I)16/14 SPB(2E1D) 3.3 167/138 MHz
K7A403209B-QC(I)30/27/25/22/20 SPB(2E1D) 3.3 300/275/250/225/200 MHz
K7A403201B-QC(I)16/14 SPB(2E2D) 3.3 167/138/ MHz
128Kx36
K7B403625B-QC(I)65/75/80 SB 3.3 6.5/7.5/8.0 ns
K7A403600B-QC(I)16/14 SPB(2E1D) 3.3 167/138 MHz
K7A403609B-QC(I)30/27/25/22/20 SPB(2E1D) 3.3 300/275/250/225/200 MHz
K7A403601B-QC(I)16/14 SPB(2E2D) 3.3 167/138 MHz
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 3 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
The K7A403609B, K7A403209B and K7A401809B are
4,718,592-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pen-
tium and Power PC based System.
It is organized as 128K(256K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system′s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A403609B, K7A403209B and K7A401809B are fab-
ricated using SAMSUNG′s high performance CMOS tech-
nology and is available in a 100pin TQFP package. Multiple
power and ground pins are utilized to minimize ground
bounce.
GENERAL DESCRIPTIONFEATURES
LOGIC BLOCK DIAGRAM
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Cont-
nention ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A .
• Operating in commeical and industrial temperature range.
CLK
LBO
ADV
ADSC
ADSP
CS1
CS2
CS2
GW
BW
WEx
OE
ZZ
DQa0 ~ DQd7
BURST CONTROL
LOGIC BURST 128Kx36/32 , 256Kx18
ADDRESS
CONTROL OUTPUT
DATA-IN
ADDRESS
COUNTER
MEMORY
ARRAY
REGISTER
REGISTER
BUFFER
LOGIC
CONTROL
REGISTER
CONTROL
REGISTER
A
′
0~A
′
1
A0~A1
or A2~A17
A0~A16
REGISTER
DQPa ~ DQPd
or A 0~A17
A2~A16
(x=a,b,c,d or a,b)
or DQa0 ~ DQb7
DQPa ~ DQPb
36/32 or 18
FAST ACCESS TIMES
PARAMETER Symbol -30 -27 -25 -22 -20 Unit
Cycle Time tCYC 3.3 3.6 4.0 4.4 5.0 ns
Clock Access Time tCD 2.2 2.2 2.4 2.6 2.8 ns
Output Enable Access Time tOE 2.2 2.2 2.4 2.6 2.8 ns
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 4 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
PIN CONFIGURATION(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
DQPc/NC
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
VDD
N.C.
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd/NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
N.C.
VDD
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa/NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
WEd
WEc
WEb
WEa
CS2
VDD
VSS
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
81 A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A16
A15
A14
A13
A12
A11
A10
N.C.
N.C.
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31
LBO
PIN NAME
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A16
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37
44,45,46,47,48,49
50,81,82,99,100
83
84
85
89
98
97
92
93,94,95,96
86
88
87
64
31
VDD
VSS
N.C.
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
/NC
VDDQ
VSSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,41,65,91
17,40,67,90
14,16,38,39,42,43,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
K7A403609B(128Kx36)
/K7A403209B(128Kx32)
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 5 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
PIN CONFIGURATION(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
N.C.
N.C.
WEb
WEa
CS2
VDD
VSS
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
81 A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A17
A16
A15
A14
A13
A12
A11
N.C.
N.C.
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31
LBO
PIN NAME
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A17
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
(x=a,b)
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37,
44,45,46,47,48,49,
50,80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31
VDD
VSS
N.C.
DQa0~a7
DQb0~b7
DQPa, Pb
VDDQ
VSSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,43,51,52,53,
56,57,66,75,78,79,95,96
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
100 Pin TQFP
(20mm x 14mm)
K7A401809B(256Kx18)
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 6 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
FUNCTION DESCRIPTION
The K7A4036/3209B and K7A401809B are synchronous SRAM designed to support the burst address accessing sequence of the
P6 and Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The
start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regardless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE (Interleaved Burst)
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
LBO PIN HIGH Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
BQ TABLE (Linear Burst)
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
LBO PIN LOW Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION ZZ OE I/O STATUS
Sleep Mode HXHigh-Z
Read L L DQ
LHHigh-Z
Write LXDin, High-Z
Deselected LXHigh-Z
Notes
1. X means "Don′t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 7 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
SYNCHRONOUS TRUTH TABLE
Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
CS1CS2CS 2ADSP ADSC ADV WRITE CLK ADDRESS ACCESSED OPERATION
HXXXLX X ↑N/A Not Selected
LLXLX X X ↑N/A Not Selected
LXHLX X X ↑N/A Not Selected
LLX X LX X ↑N/A Not Selected
LXHXLX X ↑N/A Not Selected
LHLLX X X ↑External Address Begin Burst Read Cycle
LHLHLXL↑External Address Begin Burst Write Cycle
LHLHLXH↑External Address Begin Burst Read Cycle
XXXHHLH↑Next Address Continue Burst Read Cycle
HXXXHLH↑Next Address Continue Burst Read Cycle
XXXHHLL↑Next Address Continue Burst Write Cycle
HXXXHLL↑Next Address Continue Burst Write Cycle
XXXH H H H ↑Current Address Suspend Burst Read Cycle
HXXXH H H ↑Current Address Suspend Burst Read Cycle
XXXH H H L↑Current Address Suspend Burst Write Cycle
HXXXH H L↑Current Address Suspend Burst Write Cycle
WRITE TRUTH TABLE( x36/32)
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
GW BW WEaWEbWEcWEdOPERATION
HHXXXX READ
HLH H H H READ
HL L H H H WRITE BYTE a
HLHLH H WRITE BYTE b
HLHHL L WRITE BYTE c and d
HLLLLL WRITE ALL BYTEs
LXXXXX WRITE ALL BYTEs
TRUTH TABLES
WRITE TRUTH TABLE(x18)
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
GW BW WEaWEbOPERATION
H H X X READ
HLH H READ
HL L HWRITE BYTE a
HLHLWRITE BYTE b
HL L L WRITE ALL BYTEs
LXXX WRITE ALL BYTEs
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 8 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
CAPACITANCE*(TA=25°C, f=1MHz)
*Note : Sampled not 100% tested.
PARAMETER SYMBOL TEST CONDITION MIN MAX UNIT
Input Capacitance CIN VIN=0V -5pF
Output Capacitance COUT VOUT =0V -7pF
OPERATING CONDITIONS at 3.3V I/O (0°C≤ TA≤70°C)
PARAMETER SYMBOL MIN Typ. MAX UNIT
Supply Voltage VDD 3.135 3.3 3.6 V
VDDQ 3.135 3.3 3.6 V
Ground VSS 00 0V
OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)
PARAMETER SYMBOL MIN Typ. MAX UNIT
Supply Voltage VDD 3.135 3.3 3.6 V
VDDQ 2.375 2.5 2.9 V
Ground VSS 000V
ABSOLUTE MAXIMUM RATINGS*
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER SYMBOL RATING UNIT
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
VDD -0.3 to 4.6 V
VDDQ VDD V
Voltage on Input Pin Relative to VSS VIN -0.3 to VDD+0.3 V
Voltage on I/O Pin Relative to VSS VIO -0.3 to VDDQ+0.3 V
Power Dissipation PD2.2 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TOPR 0 to 70 °C
Industrial TOPR -40 to 85 °C
Storage Temperature Range Under Bias TBIAS -10 to 85 °C
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 9 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
* VIL(Min)=-2.0(Pulse Width ≤ tCYC/2)
** VIH(Max)=4.6(Pulse Width ≤ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT
Input Leakage Current(except ZZ) IIL VDD = Max ; VIN=VSS to VDD -2 +2 µA
Output Leakage Current IOL Output Disabled, VOUT=VSS to VDDQ -2 +2 µA
Operating Current ICC Device Selected, IOUT=0mA, ZZ≤VIL,
All Inputs=VIL or VIH , Cycle Time ≥cyc Min
-30 -490
mA
-27 -440
-25 -400
-22 -360
-20 -330
Standby Current
ISB Device deselected, IOUT=0mA,ZZ≤VIL,
f=Max, All Inputs≤0.2V or ≥ VDD-0.2V
-30 -180
mA
-27 -170
-25 -160
-22 -155
-20 -150
ISB1 Device deselected, IOUT=0mA, ZZ≤0.2V,
f = 0, All Inputs=fixed (VDD-0.2V or 0.2V) -80 mA
ISB2 Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,
f=Max, All Inputs≤VIL or ≥VIH -50 mA
Output Low Voltage(3.3V I/O) VOL IOL = 8.0mA -0.4 V
Output High Voltage(3.3V I/O) VOH IOH = -4.0mA 2.4 -V
Output Low Voltage(2.5V I/O) VOL IOL = 1.0mA -0.4 V
Output High Voltage(2.5V I/O) VOH IOH = -1.0mA 2.0 -V
Input Low Voltage(3.3V I/O) VIL -0.5* 0.8 V
Input High Voltage(3.3V I/O) VIH 2.0 VDD+0.5** V
Input Low Voltage(2.5V I/O) VIL -0.3* 0.7 V
Input High Voltage(2.5V I/O) VIH 1.7 VDD+0.5** V
TEST CONDITIONS
PARAMETER VALUE
Input Pulse Level(for 3.3V I/O) 0 to 3V
Input Pulse Level(for 2.5V I/O) 0 to 2.5V
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O) 1ns
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O) 1ns
Input and Output Timing Reference Levels for 3.3V I/O 1.5V
Input and Output Timing Reference Levels for 2.5V I/O VDDQ/2
Output Load See Fig. 1
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or V DD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, T A=0 to 70
°
C)
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 10 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP
is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times
whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
PARAMETER Symbol -30 -27 -25 -22 -20 Unit
Min Max Min Max Min Max Min Max Min Max
Cycle Time tCYC 3.3 -3.6 -4.0 -4.4 -5.0 -ns
Clock Access Time tCD -2.2 -2.2 -2.4 -2.6 -2.8 ns
Output Enable to Data Valid tOE -2.2 -2.2 -2.4 -2.6 -2.8 ns
Clock High to Output Low-Z tLZC 0-0-0-0-0-ns
Output Hold from Clock High tOH 0.8 -0.8 -0.8 -1.0 -1.0 -ns
Output Enable Low to Output Low-Z tLZOE 0-0-0-0-0-ns
Output Enable High to Output High-Z tHZOE -2.2 -2.2 -2.4 -2.6 -2.8 ns
Clock High to Output High-Z tHZC 0.8 2.2 0.8 2.2 0.8 2.4 1.0 2.6 1.0 2.8 ns
Clock High Pulse Width tCH 1.5 -1.5 -1.7 -2.0 -2.0 -ns
Clock Low Pulse Width tCL 1.5 -1.5 -1.7 -2.0 -2.0 -ns
Address Setup to Clock High tAS 0.8 -0.8 -1.0 -1.2 -1.2 -ns
Address Status Setup to Clock High tSS 0.8 -0.8 -1.0 -1.2 -1.2 -ns
Data Setup to Clock High tDS 0.8 -0.8 -1.0 -1.2 -1.2 -ns
Write Setup to Clock High (GW, BW, WEX) tWS 0.8 -0.8 -1.0 -1.2 -1.2 -ns
Address Advance Setup to Clock High tADVS 0.8 -0.8 -1.0 -1.2 -1.2 -ns
Chip Select Setup to Clock High tCSS 0.8 -0.8 -1.0 -1.2 -1.2 -ns
Address Hold from Clock High tAH 0.3 -0.3 -0.3 -0.4 -0.4 -ns
Address Status Hold from Clock High tSH 0.3 -0.3 -0.3 -0.4 -0.4 -ns
Data Hold from Clock High tDH 0.3 -0.3 -0.3 -0.4 -0.4 -ns
Write Hold from Clock High (GW, BW, WEX) tWH 0.3 -0.3 -0.3 -0.4 -0.4 -ns
Address Advance Hold from Clock High tADVH 0.3 -0.3 -0.3 -0.4 -0.4 -ns
Chip Select Hold from Clock High tCSH 0.3 -0.3 -0.3 -0.4 -0.4 -ns
ZZ High to Power Down tPDS 2-2-2-2-2-cycle
ZZ Low to Power Up tPUS 2-2-2-2-2-cycle
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
5pF*
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Z0=50Ω
* Capacitive Load consists of all components of
30pF*
the test environment.
RL=50Ω
353Ω / 1538Ω
+3.3V for 3.3V I/O
319Ω / 1667Ω
VL=1.5V for 3.3V I/O
VDDQ /2 for 2.5V I/O
/+2.5V for 2.5V I/O
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 11 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
CLOCK
ADSP
ADSC
ADDRESS
WRITE
CS
ADV
OE
Data Out
TIMING WAVEFORM OF READ CYCLE
NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tCH tCL
tSS tSH
tSS tSH
tAS tAH
A1A2A3
BURST CONTINUED WITH
NEW BASE ADDRESS
tWStWH
tCSS tCSH
tADVS tADVH
tOEtHZOE
tLZOE
tCD
tOH
(ADV INSERTS WAIT STATE)
tHZC
Q3-4Q3-3Q3-2Q3-1Q2-4Q2-3Q2-2Q2-1Q1-1
Don′t Care
Undefined
tCYC
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 12 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
TIMING WAVEFORM OF WRTE CYCLE
CLOCK
ADSP
ADSC
ADDRESS
WRITE
CS
ADV
Data In
tCH tCL
tSS tSH
tAS tAH
A1A2A3
(ADSC EXTENDED BURST)
D2-1D1-1
tCSS tCSH
(ADV SUSPENDS BURST)
D2-2D2-3D2-4D3-1D3-2D3-3D2-2D3-4
Q0-3Q0-4
OE
Data Out
tSS tSH
tWStWH
tADVS tADVH
tDStDH
tHZOE
Don′t Care
Undefined
tCYC
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 13 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED , ADSC=HIGH)
CLOCK
ADSP
ADDRESS
WRITE
CS
ADV
OE
Data Out
tCH tCL
tDStDH
Q3-2
Data In
tOH
A1A2A3
D2-1
Q3-1Q3-3
tSS tSH
tAS tAH
tWStWH
tADVS tADVH
tLZOE
tHZOE
tCD
tHZC
Q3-4
tLZC
Q1-1
Don′t Care
Undefined
tCYC
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 14 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED , ADSP=HIGH)
CLOCK
ADSC
ADDRESS
WRITE
CS
ADV
OE
Data In
tCH tCL
tHZOE
D6-1
Data Out
tWStWH
tLZOEtOH
tOE
D5-1D7-1
tWStWH
tLZOE
tDHtDS
A1A2A3A4A5A6A7A8A9
Q3-1Q1-1Q2-1Q4-1Q8-1
tCSS tCSH
tSS tSH
Q9-1
Don′t Care
Undefined
tCYC
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 15 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
TIMING WAVEFORM OF POWER DOWN CYCLE
CLOCK
ADSP
ADDRESS
WRITE
CS
ADV
Data In
tCH tCL
D2-2
OE
tHZOE
D2-1
A1
tSS tSH
Data OuttPUS
ADSC
ZZ
tAS tAH
tCSS tCSH
Sleep State
Normal Operation ModeZZ Recovery Cycle
A2
tWStWH
tLZOE
Q1-1
tOE
tHZC
tPDS
ZZ Setup CycleDon′t Care
Undefined
tCYC
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 16 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
APPLICATION INFORMATION
The Samsung 128Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
DEPTH EXPANSION
This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic.
Data
Address
CLK
ADS
64-Bits
CS2
CS2
CLK
ADSC
WEx
OE
CS1
Address Data
ADV ADSP
128Kx36
SPB
SRAM
(Bank 0)
CS2
CS2
CLK
ADSC
WEx
OE
CS1
Address Data
ADV ADSP
128Kx36
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A[0:17] A[17] A[0:16] A[17] A[0:16]
I/O[0:71]
Microprocessor
Clock
ADSP
ADDRESS
Data Out
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
Q1-1 Q1-2 Q1-4Q1-3
OE
Data Out
tSS tSH
A1 A2
WRITE
CS1
An+1
ADV
(Bank 0)
(Bank 1) Q2-2 Q2-4Q2-3
tAS tAH
tWS tWH
tADVS tADVH
tOE
tLZOE tHZC
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tCSS tCSH
tCD
tLZC
[0:n]
Q2-1
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
Don′t Care Undefined
*Notes : n = 14 32K depth
15 64K depth
16 128K depth
17 256K depth
(ADSP CONTROLLED , ADSC=HIGH)
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 17 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
APPLICATION INFORMATION
The Samsung 256Kx18 Synchronous Pipelinde Burst SRAM has two additional chip selects for simple depth expansion.
DEPTH EXPANSION
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
Data
Address
CLK
ADS
Microprocessor
CS2
CS2
CLK
ADSC
WEx
OE
CS1
Address Data
ADV ADSP
256Kx18
SPB
SRAM
(Bank 0)
CS2
CS2
CLK
ADSC
WEx
OE
CS1
Address Data
ADV ADSP
256Kx18
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A[0:18] A[18] A[0:17] A[18] A[0:17]
I/O[0:71]
Clock
ADSP
ADDRESS
Data Out
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
Q1-1 Q1-2 Q1-4Q1-3
OE
Data Out
tSS tSH
A1 A2
WRITE
CS1
An+1
ADV
(Bank 0)
(Bank 1) Q2-2 Q2-4Q2-3
tAS tAH
tWS tWH
tADVS tADVH
tOE
tLZOE tHZC
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tCSS tCSH
tCD
tLZC
[0:n]
Q2-1
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
Don′t Care Undefined
*Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
(ADSP CONTROLLED , ADSC=HIGH)
K7A401809B 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 18 - Rev 0.4
Aug 2001
K7A403209B Preliminary
K7A403609B
0.10 MAX
0~8°22.00 ±0.30
20.00 ±0.20
16.00 ±0.30
14.00 ±0.20
1.40 ±0.10 1.60 MAX
0.05 MIN
(0.58)
0.50 ±0.10
#1
(0.83) 0.50 ±0.10
100-TQFP-1420A
0.65 0.30 ±0.10
0.10 MAX
+ 0.10
- 0.05
0.127
PACKAGE DIMENSIONS
Units ; millimeters/Inches
