Date Version Changes
• Updated TCCS specifications in the following tables:
— True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated RSDS_E_1R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
— Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
• Updated tx Jitter specifications in the following tables:
— True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated RSDS_E_1R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
• Updated SW specifications in LVDS Receiver Timing Specifications for Intel MAX 10 Single Supply Devices table.
• Added a note to tx Jitter for all LVDS tables. Note: TX jitter is the jitter induced from core noise and I/O switching noise.
•Updated the description for tLOCK for all LVDS tables: Time required for the PLL to lock, after CONF_DONE signal goes high,
indicating the completion of device configuration.
• Updated Memory Output Clock Jitter Specifications section.
— Updated maximum external memory interfaces frequency from 300 MHz to 303 MHz.
— Updated PLL output routing from global clock network to PHY clock network.
• Added I/O Timing for Intel MAX 10 Devices table.
• Added VHYS in the Glossary table.
January 2015 2015.01.23 • Removed a note to VCCA in Power Supplies Recommended Operating Conditions for Intel MAX 10 Dual Supply Devices
table. This note is not valid: All VCCA pins must be connected together for EQFP package.
• Corrected the maximum value for tOUTJITTER_CCJ_ IO (FOUT ≥ 100 MHz) from 60 ps to 650 ps in PLL Specifications for Intel
MAX 10 Devices table.
December 2014 2014.12.15 • Restructured Programming/Erasure Specifications for Intel MAX 10 Devices table to add temperature specifications that
affect the data retention duration.
• Added statements in the I/O Pin Leakage Current section: Input channel leakage of ADC I/O pins due to hot socket is up
to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is enabled or disabled. This is applicable
to all Intel MAX 10 devices with ADC IP core, which are 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50 devices. The
ADC I/O pins are in Bank 1A.
• Added a statement in the I/O Standards Specifications section: You must perform timing closure analysis to determine the
maximum achievable frequency for general purpose I/O standards.
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Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
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