2
Linear Technology Chronicle •
January 1998
14-Bit 400ksps ADC Achieves 80dB SINAD at
Nyquist, Consumes Only 75mW
den by an external source to improve tem-
perature or time stability. The LTC1416’s
three-state parallel interface easily connects
to DSP and microprocessor parallel ports. It
also has a separate convert start input pin
and a data ready signal (BUSY) pin to facili-
tate these connections.
The LTC1416 14-bit ADC is available
in a 28-pin SSOP package. Contact your
local Linear Technology sales office for a
data sheet and evaluation samples or visit
our web site at www.linear-tech.com for
more information.
The 400ksps LTC1416 14-bit analog-
to-digital converter (ADC) delivers 80dB
SINAD and –90dB total harmonic distortion
(THD) at the Nyquist input frequency of
200kHz while drawing only 75mW from
±5V supplies. The LTC1416’s full-scale
input range is ±2.5V. Maximum DC specifi-
cations include ±1LSB DNL and ±1.25LSB
INL over temperature (see Figure 1). It
offers a simple and cost-effective solution
for upgrading performance of 12-bit data
conversion systems wherever low power
operation is essential.
At 100kHz, the LTC1416 delivers
80.5dB of SINAD, –93dB THD and –95dB
spurious-free dynamic range. The
LTC1416’s differential input sample-and-
hold can acquire single-ended or differential
input signals up to its 15MHz bandwidth.
The 60dB common mode rejection allows
users to eliminate ground loops and common
mode noise by measuring signals differen-
tially from the source. Figure 2 shows a
typical application for the LTC1416 as a low
power, 400ksps sampling ADC. It is avail-
able in a 28-pin SSOP package.
The LTC1416 is capable of going into
two power shutdown modes—nap and sleep,
to save power during inactive periods. In nap
frequency error typically less than ±0.2%.
The LTC1067-50 has a ratio of 50:1 and
consumes just 1mA—less than half the cur-
rent of the LTC1067.
Using a double-sampled architecture,
which places aliasing and imaging compo-
nents at twice the clock frequency, the
LTC1067’s dynamic range on a single 3.3V
supply is over 80dB and noise is less than
Figure 2. Frequency Response of Filter in
Figure 1 Has a Center Frequency Error of
Less Than
±
0.2%
FREQUENCY (kHz)
4.0
GAIN (dB)
6.0
1067 • TA02
4.5 5.0 5.5
0
–10
–20
–30
–40
Universal Dual Filter in
SSOP Offers Rail-to-Rail
Operation with 3V Supply
rail-to-rail 2nd order filter sections, together
with three to five resistors, allows various
filter functions to be quickly designed—such
as bandpass, lowpass, notch and allpass filter
responses. Like all switched-capacitor
filters, the LTC1067’s corner or center
frequency is adjustable with the clock
frequency. The LTC1067’s internal clock-
to-center frequency ratio is 100:1 with center
Figure 1. The LTC1416 ADC
Guarantees ±1.25LDB INL (Max)
over Temperature but It’s Typically
Only ±0.5LSB
Linear Technology Corporation intro-
duces an SSOP-16 version of its LTC1067
rail-to-rail, low noise, universal dual filter
building block. The smaller SSOP package
occupies an area less than half that of an
SO-16, the package in which the LTC1067
was originally introduced and 86% less area
than a 16-pin DIP package. It operates from
a single 3V to ±5V supply with rail-to-rail
input and output operation and draws only
2.5mA. The smaller SSOP package com-
bined with its high performance at low
supply voltages makes the LTC1067 an
excellent choice for small, portable filters for
data acquisition and telecommunications.
The LTC1067 is the evolutionary
descendant of the MF10 and the LTC1060
4th order filter but with greatly improved
specifications. Each of the LTC1067’s two
Continued on page 4
Figure 1. The LTC1067 Configured as a
Single 3.3V Supply Rail-to-Rail 4th Order
5kHz Bandpass Filter
0.1µF
1067 TA01
LTC1067
V
+
NC
V
+
SA
LPA
BPA
HPA/NA
INV A
CLK
AGND
V
–
SB
LPB
BPB
HPB/NB
INV B
3.3V
R32, 200k
R22, 10k
R31, 200k
R21, 10k
R11
200k
IN
R12, 200k
OUT
1µF
f
CLK
= 500kHz
TOTAL OUTPUT NOISE: 90µV
RMS
S/N RATIO: 80dB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUTPUT CODE
0
INTEGRAL NONLINEARITY (LSB)
16384
1416 TA02
4096 8192 12288
1.0
0.5
0
–0.5
–1.0 2048 6144 10240 14336
mode only the digital logic and reference is
powered up so it can wake up and convert
immediately. In sleep mode all bias currents
are shut down and only leakage current
remains. Wake-up time from sleep mode is
slower since the reference circuit must
power up and settle for full 14-bit accuracy.
In sleep mode it consumes just 10µW and in
nap mode only 4mW.
The internal 2.5V precision reference
can be used for external circuitry or overrid-
Figure 2. The LTC1416 14-Bit ADC
Includes an Internal Reference and
High Dynamic Range Sample-and-
Hold. It Operates from ±5V Supplies
and Draws Only 75mW
While Converting
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+A
IN
–A
IN
V
REF
REFCOMP
AGND
D13(MSB)
D12
D11
D10
D9
D8
D7
D6
DGND
AV
DD
DV
DD
V
SS
BUSY
CS
CONVST
RD
SHDN
D0
D1
D2
D3
D4
D5
LTC1416
10µF
1µF
DIFFERENTIAL
ANALOG INPUT
(–2.5V TO 2.5V)
10µF
10µF
–5V
5V
PARALLEL
OUTPUT
(BITS 6 TO 13) PARALLEL
OUTPUT
(BITS 0 TO 5)
µP
CONTROL
LINES
1416 TA01
V
REF
OUTPUT
2.50V