MC14007UB Dual Complementary Pair Plus Inverter The MC14007UB multi-purpose device consists of three N-channel and three P-channel enhancement mode devices packaged to provide access to each device. These versatile parts are useful in inverter circuits, pulse-shapers, linear amplifiers, high input impedance amplifiers, threshold detectors, transmission gating, and functional gating. http://onsemi.com MARKING DIAGRAMS * Diode Protection on All Inputs * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-power TTL Loads or One Low-power * * 14 PDIP-14 P SUFFIX CASE 646 Schottky TTL Load Over the Rated Temperature Range Pin-for-Pin Replacement for CD4007A or CD4007UB This device has 2 outputs without ESD Protection. Anti-static precautions must be taken. MC14007UBCP AWLYYWW 1 14 SOIC-14 D SUFFIX CASE 751A 14007U AWLYWW 1 14 MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol VDD Vin, Vout Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Value Unit -0.5 to +18.0 V -0.5 to VDD + 0.5 V 14 007U ALYW 1 14 Input or Output Current (DC or Transient) per Pin 10 PD Power Dissipation, per Package (Note 3.) 500 mW TA Ambient Temperature Range -55 to +125 C Tstg Storage Temperature Range -65 to +150 C TL Lead Temperature (8-Second Soldering) 260 C Iin, Iout TSSOP-14 DT SUFFIX CASE 948G mA SOEIAJ-14 F SUFFIX CASE 965 MC14007U ALYW 1 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/C From 65C To 125C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping MC14007UBCP PDIP-14 2000/Box MC14007UBD SOIC-14 55/Rail MC14007UBDR2 SOIC-14 2500/Tape & Reel MC14007UBDT TSSOP-14 96/Rail MC14007UBF SOEIAJ-14 See Note 1. MC14007UBFEL SOEIAJ-14 See Note 1. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. Semiconductor Components Industries, LLC, 2000 August, 2000 - Rev. 4 1 Publication Order Number: MC14007UB/D MC14007UB PIN ASSIGNMENT D-PB 1 14 VDD S-PB 2 13 D-PA GATEB 3 12 OUTC S-NB 4 11 S-PC D-NB 5 10 GATEC GATEA 6 9 S-NC VSS 7 8 D-NA D = DRAIN S = SOURCE SCHEMATIC 14 13 2 1 11 6 12 7 8 3 4 5 10 9 VDD = PIN 14 VSS = PIN 7 A A 12 B 9 B 1 C 2 3 INPUT 4 5 VDD 14 C 11 INPUT OUTPUT CONDITION 1 0 13 INPUT 6 A = C, B = OPEN A = B, C = OPEN Substrates of P-channel devices internally connected to VDD; substrates of N-channel devices internally connected to VSS. 8 7 10 VSS Figure 1. Typical Application: 2-Input Analog Multiplexer http://onsemi.com 2 MC14007UB IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III IIIII IIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III I III IIII III III III III IIIII IIIIIIIII IIIII IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III IIII IIII III III III III IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol - 55C 25C 125C VDD Vdc Min Max Min Typ (4.) Max Min Max Unit Output Voltage Vin = VDD or 0 "0" Level VOL 5.0 10 15 -- -- -- 0.05 0.05 0.05 -- -- -- 0 0 0 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 Vdc Vin = 0 or VDD "1" Level VOH 5.0 10 15 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 5.0 10 15 -- -- -- 4.95 9.95 14.95 -- -- -- Vdc "0" Level VIL 5.0 10 15 -- -- -- 1.0 2.0 2.5 -- -- -- 2.25 4.50 6.75 1.0 2.0 2.5 -- -- -- 1.0 2.0 2.5 5.0 10 15 4.0 8.0 12.5 -- -- -- 4.0 8.0 12.5 2.75 5.50 8.25 -- -- -- 4.0 8.0 12.5 -- -- -- 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 - 5.0 - 1.0 - 2.5 - 10 -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 -- -- -- -- IOL 5.0 10 15 0.64 1.6 4.2 -- -- -- 0.51 1.3 3.4 1.0 2.5 10 -- -- -- 0.36 0.9 2.4 -- -- -- mAdc Input Current Iin 15 -- 0.1 -- 0.00001 0.1 -- 1.0 Adc Input Capacitance (Vin = 0) Cin -- -- -- -- 5.0 7.5 -- -- pF Quiescent Current (Per Package) IDD 5.0 10 15 -- -- -- 0.25 0.5 1.0 -- -- -- 0.0005 0.0010 0.0015 0.25 0.5 1.0 -- -- -- 7.5 15 30 Adc IT 5.0 10 15 Input Voltage (VO = 4.5 Vdc) (VO = 9.0 Vdc) (VO = 13.5 Vdc) (VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) "1" Level VIH Vdc IOH Source (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Gate) (CL = 50 pF) Sink Vdc mAdc IT = (0.7 A/kHz) f + IDD/6 IT = (1.4 A/kHz) f + IDD/6 IT = (2.2 A/kHz) f + IDD/6 4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at 25C. 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.003. http://onsemi.com 3 Adc MC14007UB IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25C) Characteristic Symbol Output Rise Time tTLH = (1.2 ns/pF) CL + 30 ns tTLH = (0.5 ns/pF) CL + 20 ns tTLH = (0.4 ns/pF) CL + 15 ns tTLH Output Fall Time tTHL = (1.2 ns/pF) CL + 15 ns tTHL = (0.5 ns/pF) CL + 15 ns tTHL = (0.4 ns/pF) CL + 10 ns tTHL Turn-Off Delay Time tPLH = (1.5 ns/pF) CL + 35 ns tPLH = (0.2 ns/pF) CL + 20 ns tPLH = (0.15 ns/pF) CL + 17.5 ns tPLH Turn-On Delay Time tPHL = (1.0 ns/pF) CL + 10 ns tPHL = (0.3 ns/pF) CL + 15 ns tPHL = (0.2 ns/pF) CL + 15 ns tPHL VDD Vdc Min Typ (8.) Max 5.0 10 15 -- -- -- 90 45 35 180 90 70 5.0 10 15 -- -- -- 75 40 30 150 80 60 5.0 10 15 -- -- -- 60 30 25 125 75 55 5.0 10 15 -- -- -- 60 30 25 125 75 55 Unit ns ns ns ns 7. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter. 8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD = -VGS VDD = VGS 14 IOH 7 14 VDS = VOH - VDD IOL VSS 7 All unused inputs connected to ground. c a TA = -55C b TA = +25C c TA = +125C -8.0 b a c -12 b b -10 Vdc -16 IOL , DRAIN CURRENT (mAdc) IOH , DRAIN CURRENT (mAdc) 20 VGS = -5.0 Vdc c -15 Vdc a a -20 -10 -8.0 -6.0 -4.0 VDS, DRAIN VOLTAGE (Vdc) VSS All unused inputs connected to ground. 0 -4.0 VDS = VOL -2.0 a VGS = 15 Vdc b c 16 a 12 10 Vdc b c a TA = -55C b TA = +25C c TA = +125C 8.0 a 4.0 c 0 -0 0 Figure 2. Typical Output Source Characteristics 2.0 b 5.0 Vdc 4.0 6.0 VDS, DRAIN VOLTAGE (Vdc) 8.0 Figure 3. Typical Output Sink Characteristics These typical curves are not guarantees, but are design aids. Caution: The maximum current rating is 10 mA per pin. http://onsemi.com 4 10 MC14007UB VDD 500F PULSE GENERATOR 20 ns 0.01 F CERAMIC ID 7 VDD 90% 50% 10% Vin 14 Vin tPHL VSS CL Vout 20 ns 90% 50% 10% Vout VSS tPLH VOH VOL tTHL tTLH Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms APPLICATIONS VDD 14 The MC14007UB dual pair plus inverter, which has access to all its elements offers a number of unique circuit applications. Figures 1, 5, and 6 are a few examples of the device flexibility. OUT = A+B*C 13 11 +VDD 2 DISABLE3 B 1 2 12 10 1 8 OUTPUT 11 9 12OUTPUT INPUT10 7 5 C 3 4 9 8 A DISABLE6 6 7 Substrates of P-channel devices internally connected to VDD; Substrates of N-channel devices internally connected to VSS. INPUT DISABLE OUTPUT 1 0 X 0 0 1 0 1 OPEN Figure 6. AOI Functions Using Tree Logic X = Don't Care Figure 5. 3-State Buffer http://onsemi.com 5 MC14007UB PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE M 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F DIM A B C D F G H J K L M N L N C -T- SEATING PLANE J K H D 14 PL G M 0.13 (0.005) INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --10 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --10 0.38 1.01 M D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- 1 P 7 PL 0.25 (0.010) 7 G B M M F R X 45 C -T- SEATING PLANE 0.25 (0.010) M K D 14 PL M T B S A S http://onsemi.com 6 J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 MC14007UB PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U T U M V S S S N 2X 14 L/2 0.25 (0.010) 8 M B -U- L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A -V- CCC EE CCC EE K1 J J1 SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE H G D DETAIL E F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 965-01 ISSUE O 14 LE 8 Q1 E HE L 7 1 M DETAIL P Z D VIEW P A e c A1 b 0.13 (0.005) M 0.10 (0.004) http://onsemi.com 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --1.20 --0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 --1.42 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 --0.056 MC14007UB ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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