MAX5316GTG+ - Hytronics

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

General Description

The MAX5316 is a high-accuracy, 16-bit, serial SPI input,

buffered voltage output digital-to-analog converter (DAC)

in a 4mm x 5mm, 24-lead TQFN package. The device

features Q1 LSB INL (max) accuracy and a Q0.25 LSB

DNL (typ) accuracy over the temperature range of -40NC

to +105NC.

The DAC voltage output is buffered with a fast set-

tling time of 3Fs and a low offset and gain drift of

Q0.6ppm/NC of FSR (typ). The force-sense output (OUT)

maintains accuracy while driving loads with long lead

lengths. A separate AVSS supply pin is provided to per-

mit the output amplifier to go to 0V (GND) to maintain full

linearity performance near ground.

At power-up, the device resets its outputs to zero or

midscale.

The wide 2.7V to 5.5V supply voltage range and inte-

grated low-drift, low-noise reference buffer make for ease

of use. The MAX5316 features a 50MHz 3-wire SPI inter-

face. For an I2C interface, use the MAX5317.

The MAX5316 is available in a 24-lead TQFN-EP pack-

age and operates over the -40NC to +105NC temperature

range.

Applications

Test and Measurement

Automatic Test Equipment

Gain and Offset Adjustment

Data-Acquisition Systems

Process Control and Servo Loops

Programmable Voltage and Current Sources

Automatic Calibration

Communication Systems

Medical Equipment

Benefits and Features

S Ideal for ATE and High-Precision Instruments

INL Accuracy Guaranteed with ±1 LSB (Max)

Over Temperature

S Fast Settling Time (3µs) with 10kI || 100pF Load

S Safe Power-Up-Reset to Zero or Midscale DAC

Output (Pin-Selectable)

 Predetermined Output Device State in Power-Up

and Reset in System Design

S Negative Supply (AVSS) Option Allows Full INL

and DNL Performance to 0V

S SPI Interface Compatible with 1.7V to 5.5V

Logic

S High Integration Reduces Development Time and

PCB Area

 Buffered Voltage Output Directly Drives

2kI Load Rail-to-Rail

 Integrated Reference Buffer

 No External Amplifiers Required

S Small 4mm x 5mm, 24-Pin TQFN Package

19-6166; Rev 0; 1/12

Ordering Information appears at end of data sheet.

For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX5316.related.

QSPI is a trademark of Motorola, Inc.

MICROWIRE is a registered trademark of Texas Instrument

Incorporated.

EVALUATION KIT AVAILABLE

Functional Diagram

16-BIT

DAC

OUTPUT

BUFFER

REF

CONTROL

LOGIC

SHUTDOWN

POWER-ON

RESET

SPI

INTERFACE

BUFFER

VDDIO

DGND BYPASS AGND_S AGND_F AVSS

AVDD2 AVDD1

1622 19 12

REFO

RFB

OUT

7.8kI

7.8kI7.8kI

7.8kI

LDAC

READY

SCLK

DIN

DOUT

AGND

21 20 17 18 1011

MAX5316

SPI

BUSY

RST

M/Z

TC/SB

INPUT/

DAC

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-

4642, or visit Maxim’s website at www.maxim-ic.com.

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

AGND to DGND ...................................................-0.3V to +0.3V

AGND_F, AGND_S to AGND ...............................-0.3V to +0.3V

AGND_F, AGND_S to DGND ...............................-0.3V to +0.3V

AVDD_ to AGND .....................................................-0.3V to +6V

AVDD_ to REF .........................................................-0.3V to +6V

AVSS to AGND ........................................................-2V to +0.3V

VDDIO to DGND .......................................................-0.3V to +6V

BYPASS to DGND .......................................-0.3V to the lower of

(VAVDD_ or VDDIO + 0.3V) and +6V

OUT, REFO, RFB to AGND .........................-0.3V to the lower of

(VAVDD_ + 0.3V) and +6V

REF to AGND ..............................................-0.3V to the lower of

VAVDD and +6V

SCLK, DIN, CS, BUSY, LDAC, READY,

M/Z, TC/SB, RST, PD, DOUT to DGND .......-0.3V to the lower of

(VDDIO + 0.3V) and +6V

Continuous Power Dissipation (TA = +70NC)

TQFN (derate 28.6mW/NC above +70NC) ...............2285.7mW

Operating Temperature Range ........................ -40NC to +105NC

Maximum Junction Temperature .....................................+150NC

Storage Temperature Range ............................ -65NC to +150NC

Lead Temperature (soldering, 10s) ................................+300NC

Soldering Temperature (reflow) ......................................+260NC

TQFN

Junction-to-Case Thermal Resistance (qJA) ..............1.8°C/W

Junction-to-Ambient Thermal Resistance (qJA) ..........35°C/W

ABSOLUTE MAXIMUM RATINGS

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-

tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL CHARACTERISTICS (Note 1)

ELECTRICAL CHARACTERISTICS

(VAVDD_ = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB = PD = LDAC

= M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise

noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE

Resolution N 16 Bits

Integral Nonlinearity (Note 3) INL

DIN = 0x0000 to 0xFFFF (binary

mode), DIN = 0x8000 to 0x7FFF (two’s

complement mode) -1 Q0.25 +1 LSB

DIN = 0x0640 to 0xFFFF (binary

mode), DIN = 0x8280 to 0x7FFF (two’s

complement mode), VAVSS = 0V

Differential Nonlinearity (Note 3) DNL -1 Q0.25 +1 LSB

Zero Code Error OE DIN = 0, TA = +25NC-19 Q1+19 LSB

DIN = 0, TA = -40NC to +105NCQ6

Zero Code Error Drift DIN = 0 -2.5 Q0.4 +2.5 ppm/NC

Gain Error GE TA = +25NC-4 Q0.25 +4 LSB

TA = -40NC to +105NCQ3

Gain Error Temperature

Coefficient TCGE -2.75 Q0.6 +2.75 ppm/NC

of FSR

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD_ = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB = PD = LDAC

= M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise

noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Voltage Range 0 VAVDD

- 0.1 V

Reset Voltage Output VOUT-RESET

RST = pulse low M/Z = DGND 75 FV

M/Z = VDDIO 2.048 V

RST = pulse low,

VAVSS = 0V

M/Z = DGND 10 mV

M/Z = VDDIO 2.048 V

RST = DGND M/Z = DGND -40 mV

M/Z = VDDIO 2.037 V

RST = DGND,

VAVSS = 0V

M/Z = DGND 10 mV

M/Z = VDDIO 2.037 V

DC Output Impedance

(Normal Mode) ROUT Closed-loop connection (RFB connected

to OUT) 4mI

Output Resistance

(Power-Down Mode) PD = VDDIO 2kI

Output Current IOUT

Source/sink within 100mV of the supply

rails Q4

Source/sink within 800mV of the supply

rails Q25

Load Capacitance to GND CL200 pF

Load Resistance to GND RLFor specified performance 2 kI

Short-Circuit Current ISC

OUT shorted to AGND or AVDD Q60

mAREFO shorted to AGND or AVDD Q65

BYPASS shorted to AGND or AVDD Q48

Short-Circuit Duration TSC Short to AGND or AVDD Indefinite s

DC Power-Supply Rejection DC PSRR VOUT at full scale, VAVDD = 4.5V to 5.5V -1 Q0.05 +1 LSB/V

VAVSS = -1.5V to -0.5V -1 Q0.003 +1

STATIC PERFORMANCE—VOLTAGE REFERENCE INPUT SECTION

Reference High Input Range VREF 2.4 VAVDD

- 0.1 V

Reference Input Capacitance CREF 10 pF

Reference Input Resistance RREF 10 MI

Reference Input Current IBQ0.05 FA

STATIC PERFORMANCE—VOLTAGE REFERENCE OUTPUT SECTION

Reference High Output Range 2.4 VAVDD

- 0.1 V

Reference High Output Load

Regulation 500 ppm/

Reference Output Capacitor RESR < 5I0.1 0.15 nF

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD_ = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB = PD = LDAC

= M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise

noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE—VBYPASS OUT SECTION

Output Voltage VBYPASS 2.3 2.4 2.5 V

Load Capacitance to GND CLRequired for stability, RESR = 0.1I (typ) 1 10 FF

POWER-SUPPLY REQUIREMENTS

Positive Analog Power-Supply

Range VAVDD 4.5 5.5 V

Digital Interface Power-Supply

Range VDDIO 1.7 VAVDD V

Negative Analog Power-Supply

Range VAVSS -1.5 -1.25 0 V

Positive Analog Power-Supply

Current IAVDD No load, external reference, output at

zero scale 5.5 7.5 mA

Negative Analog Power-Supply

Current IAVSS No load, external reference, output at

zero scale -1.75 -1.0 mA

Interface Power-Supply Current IVDDIO Digital inputs at VDDIO or DGND 1 10 FA

Positive Analog Power-Supply

Power-Down Current PD = VDDIO, power-down mode 20 50 FA

Negative Analog Power-Supply

Power-Down Current PD = VDDIO, power-down mode -10 -3 FA

DYNAMIC PERFORMANCE

Voltage Output Slew Rate SR From 10% to 90% full scale, positive and

negative transitions 4.9 V/Fs

Voltage Output Settling Time tS

From falling edge of LDAC to within

0.003% FS, RL = 10kI, DIN = 1000h

(6.25% FS) to F000h (93.75% FS)

3Fs

Busy Time tBUSY (Note 4) 1.9 Fs

DAC Glitch Impulse Major code transition (1FFFh to 8000h),

RL = 10kI, CL = 50pF 4 nVs

Digital Feed Through CSB = VDDIO, fSCLK = 1kHz, all digital

inputs from 0V to VDDIO 1 nVs

Output Voltage-Noise Spectral

Density

At f = 1kHz to 10kHz, without reference

noise, code = 8000h 26 nV/√Hz

Output Voltage Noise At f = 0.1Hz to 10Hz, without reference

noise, code = 8000h 1.55 FVP-P

Wake-Up Time From power-down mode 75 Fs

Power-Up Time From power-off 1 ms

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

ELECTRICAL CHARACTERISTICS

(VAVDD_ = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC

= M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise

noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE

Resolution N 16 Bits

Integral Nonlinearity (Note 3) INL

DIN = 0x0000 to 0xFFFF (binary mode),

DIN = 0x8000 to 0x7FFF (two’s complement

mode) -1.0 Q0.20 +1.0 LSB

DIN = 0x0640 to 0xFFFF (binary mode),

DIN = 0x8280 to 0x7FFF (two’s complement

mode), VAVSS = 0V

Differential Nonlinearity (Note 3) DNL -1.0 Q0.10 +1.0 LSB

Zero Code Error OE DIN = 0, TA = +25NC-20 +1.5 +20 LSB

DIN = 0, TA = -40NC to +105NCQ4

Zero Code Error Drift (Note 2) DIN = 0 -3 Q0.35 +3 ppm/NC

Gain Error GE TA = +25NC-4 Q0.65 +4 LSB

TA = -40NC to +105NCQ3

Gain Error Temperature

Coefficient (Note 2) TCGE -3 +3 ppm/NC

of FSR

Output Voltage Range 0 VAVDD

- 0.1 V

Reset Voltage Output

VOUT-

RESET

RST = pulse low M/Z = DGND 75 FV

M/Z = VDDIO 1.25 V

RST = pulse low,

VAVSS = 0V

M/Z = DGND 10 mV

M/Z = VDDIO 1.25 V

RST = DGND M/Z = DGND -40 mV

M/Z = VDDIO 1.25 V

RST = DGND,

VAVSS = 0V

M/Z = DGND 10 mV

M/Z = VDDIO 1.24 V

DC Output Impedance ROUT Closed-loop connection, RFB connected

to OUT 4mI

Output Current IOUT

Source/sink within 100mV of the supply rails Q4mA

Source/sink within 800mV of the supply rails Q25

Load Capacitance to GND CL200 pF

Load Resistance to GND RLFor specified performance 2 kI

Short-Circuit Current ISC

OUT shorted to AGND or AVDD Q60

mAREFO shorted to AGND or AVDD Q65

BYPASS shorted to AGND or AVDD Q48

Short-Circuit Duration TSC Short to AGND or AVDD Indefinite s

DC Power-Supply Rejection DCPSRR VOUT at full scale, VAVDD = 2.7V to 3.3V -1 Q0.1 +1 LSB/V

VAVSS = -1.5V to -0.5V -1 Q0.01 +1

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD_ = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC

= M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise

noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE—VOLTAGE REFERENCE INPUT SECTION

Reference High Input Range VREF 2.4 VAVDD

- 0.1 V

Reference Input Capacitance CREF 10 pF

Reference Input Resistance RREF 10 MI

Reference Input Current IB Q0.05 FA

STATIC PERFORMANCE—VOLTAGE REFERENCE OUTPUT SECTION

Reference High Output Range 2.4 VAVDD

- 0.1 V

Reference High Output Load

Regulation 500 ppm/mA

Reference Output Capacitor RESR < 5I0.1 0.15 nF

STATIC PERFORMANCE—VBYPASS OUT SECTION

Output Voltage VBYPASS 2.3 2.4 2.5 V

Load Capacitance to GND CLRequired for stability, RESR = 0.1I (typ) 1 10 FF

POWER-SUPPLY REQUIREMENTS

Positive Analog Power-Supply

Range VAVDD 2.7 3.3 V

Interface Power-Supply Range VDDIO 1.7 VAVDD V

Negative Analog Power-Supply

Range VAVSS -1.5 -1.25 0 V

Positive Analog Power-Supply

Current IAVDD No load, external reference, output at zero

scale 4 6.5 mA

Negative Analog Power-Supply

Current IAVSS No load, external reference, output at zero

scale -1.5 -0.8 mA

Interface Power-Supply Current IVDDIO Digital inputs at VDDIO or DGND 1 10 FA

Positive Analog Power-Supply

Power-Down Current PD = VDDIO, power-down mode 20 50 FA

Negative Analog Power-Supply

Power-Down Current PD = VDDIO, power-down mode -10 -3 FA

DYNAMIC PERFORMANCE

Voltage Output Slew Rate SR From 10% to 90% full scale, positive and

negative transitions 4.9 V/Fs

Voltage Output Settling Time tS

From falling edge of LDAC to within 0.003%

FS, RL = 10kI, DIN = 1000h (6.25% FS) to

F000h (93.75% FS)

3Fs

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD_ = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC

= M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise

noted. Typical values are at TA = +25°C.) (Note 2)

Note 2: All devices are 100% tested at TA = +25°C and TA = +105°C. Limits at TA = -40°C are guaranteed by design.

Note 3: Linearity is tested from VREFO to AGND.

Note 4: The total analog throughput time from DIN to VOUT is the sum of tS and tBUSY (4.9µs, typ).

DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS

(VAVDD_ = 5V, VDDIO = 2.7V to 5.5V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z, CREFO = 100pF, CL = 100pF,

CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Busy Time tBUSY (Note 4) 1.9 Fs

DAC Glitch Impulse Major code transition (7FFFh to 8000h), RL

= 10kI, CL = 50pF 2.5 nVs

Digital Feedthrough CSB = VDDIO, fSCLK = 1kHz, all digital

inputs from 0V to VDDIO 1 nVs

Output Voltage-Noise Spectral

Density

At f = 1kHZ to 10kHz, without reference

noise, code = 8000h 26 nV/√Hz

Output Voltage Noise At f = 0.1Hz to 10Hz, without reference

noise, code = 8000h 1.55 FVP-P

Wake-Up Time From power-down mode 75 Fs

Power-Up Time From power-off 1 ms

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS (SCLK, DIN, CS, LDAC)

Input High Voltage VIH 0.7 x

VDDIO V

Input Low Voltage VIL 0.3 x

VDDIO V

Input Hysteresis VIHYST 200 300 mV

Input Leakage Current IIN Input = 0V of VDDIO Q0.1 Q1FA

Input Capacitance CIN 10 pF

DIGITAL OUTPUT CHARACTERISTICS (DOUT, READY, BUSY)

Output Low Voltage VOL ISOURCE = 5.0mA 0.25 V

Output High Voltage VOH ISINK = 5.0mA, except for BUSY VDDIO

- 0.25

Output Three-State Leakage IOZ DOUT only Q0.1 Q1FA

Output Three-State Capacitance COZ DOUT only 15 pF

Output Short-Circuit Current IOSS VDDIO = 5.5V Q150 mA

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)

(VAVDD_ = 5V, VDDIO = 2.7V to 5.5V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z, CREFO = 100pF, CL = 100pF,

CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TIMING CHARACTERISTICS

Serial Clock Frequency fSCLK

Stand-alone, write mode 50

MHz

Stand-alone read mode and daisy-

chained read and write modes (Note 5) 12.5

SCLK Period tCP

Stand-alone, write mode 20

Stand-alone read mode and daisy-

chained read and write modes 80

SCLK Pulse Width High tCH 40% duty cycle 8 ns

SCLK Pulse Width Low tCL 40% duty cycle 8 ns

CS Fall to SCLK Fall Setup Time tCSSO First SCLK

falling edge

Stand-alone, write

mode 8

Stand-alone read

mode and daisy-

chained read and

write modes

CS Fall to SCLK Fall Hold Time tCSH0 Inactive falling edge preceding first falling

edge 0 ns

SCLK Fall to CS Rise Hold Time tCSH1 24th falling edge 2 ns

DIN to SCLK Fall Setup Time tDS 5 ns

DIN to SCLK Fall Hold Time tDH 4.5 ns

SCLK Rise to DOUT Settle Time tDOT CL = 20pF (Note 6) 32 ns

SCLK Rise to DOUT Hold Time tDOH CL = 0pF (Note 6) 2 ns

SCLK Fall to DOUT Disable Time tDOZ 24th active edge deassertion 2 30 ns

CS Fall to DOUT Enable tDOE Asynchronous assertion 2 30 ns

CS Rise to DOUT Disable tCSDOZ

Stand-alone, aborted sequence 35 ns

Daisy-chained, aborted sequence 20

SCLK Fall to READY Fall tCRF 24th falling-edge assertion, CL = 20pF 30 ns

SCLK Fall to READY Hold tCRH 24th falling-edge assertion, CL = 0pF 2 ns

SCLK Fall to BUSY Fall tCBF BUSY assertion 5 ns

CS Rise to READY Rise tCSR CL = 20pF 35 ns

CS Rise to SCLK Fall tCSA 24th falling edge, aborted sequence 20 ns

CS Pulse Width High tCSPW Stand alone 20 ns

SCLK Fall to CS Fall tCSF 24th falling edge 100 ns

LDAC Pulse Width tLDPW 20 ns

LDAC Fall to SCLK Fall Hold tLDH Last active falling edge 20 ns

RST Pulse Width tRSTPW 20 ns

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)

(VAVDD_ = 5V, VDDIO = 1.8V to 2.7V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z, CREFO = 100pF, CL = 100pF,

CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS (SCLK, DIN, CS, LDAC)

Input High Voltage VIH 0.8 x

VDDIO V

Input Low Voltage VIL 0.2 x

VDDIO V

Input Hysteresis VIHYST 200 300 mV

Input Leakage Current IIN Input = 0V or VDDIO Q0.1 Q1FA

Input Capacitance CIN 10 pF

DIGITAL OUTPUT CHARACTERISTICS (DOUT, READY, BUSY)

Output Low Voltage VOL ISOURCE = 1.0mA 0.2 V

Output High Voltage VOH ISINK = 1.0mA, except for BUSY VDDIO

- 0.2 V

Output Three-State Leakage IOZ DOUT only Q0.1 Q1FA

Output Three-State Capacitance COZ DOUT only 15 pF

Output Short-Circuit Current IOSS VDDIO = 2.7V Q150 mA

TIMING CHARACTERISTICS

Serial Clock Frequency fSCLK

Stand-alone, write mode 50

MHz

Stand-alone read mode and daisy

chained read and write modes (Note 5) 8

SCLK Period tCP

Stand-alone, write mode 20

Stand-alone read mode and daisy-

chained read and write modes 125

SCLK Pulse Width High tCH 40% duty cycle 12 ns

SCLK Pulse Width Low tCL 40% duty cycle 12 ns

CS Fall to SCLK Fall Setup Time tCSSO First SCLK

falling edge

Stand-alone, read mode 12

Stand-alone read mode

and daisy-chained read

and write modes

CS Fall to SCLK Fall Hold Time tCSH0 Inactive falling edge preceding first

falling edge 0 ns

SCLK Fall to CS Rise Hold Time tCSH1 24th falling edge 4 ns

DIN to SCLK Fall Setup Time tDS 8 ns

DIN to SCLK Fall Hold Time tDH 8 ns

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)

(VAVDD_ = 5V, VDDIO = 1.8V to 2.7V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z, CREFO = 100pF, CL = 100pF,

CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

Note 5: Daisy-chain speed is relaxed to accommodate (tCRF + tCSS0).

Note 6: DOUT speed limits overall SPI speed. 50MHz is only specified without DOUT functionality.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCLK Rise to DOUT Settle Time tDOT CL = 20pF (Note 6) 60 ns

SCLK Rise to DOUT Hold Time tDOH CL = 0pF (Note 6) 2 ns

SCLK Fall to DOUT Disable Time tDOZ 24th active edge deassertion 2 40 ns

CS Fall to DOUT Enable tDOE Asynchronous assertion 2 50 ns

CS Rise to DOUT Disable tCSDOZ

Stand-alone, aborted sequence 70 ns

Daisy-chained, aborted sequence 130

SCLK Fall to READY Fall tCRF 24th falling edge assertion, CL = 20pF 60 ns

SCLK Fall to READY Hold tCRH 24th falling edge assertion, CL = 0pF 2 ns

SCLK Fall to BUSY Fall tCBF BUSY assertion 5 ns

CS Rise to READY Rise tCSR CL = 20pF 60 ns

CS Rise to SCLK Fall tCSA 24th falling edge, aborted sequence 20 ns

CS Pulse Width High tCSPW Stand alone 20 ns

SCLK Fall to CS Fall tCSF 24th falling edge 100 ns

LDAC Pulse Width tLDPW 20 ns

LDAC Fall to SCLK Fall Hold tLDH Last active falling edge 20 ns

RST Pulse Width tRSTPW 20 ns

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Figure 1. Serial Interface Timing Diagram, Stand-Alone Operation

Typical Operating Characteristics

(VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,

RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)

tCSSO

345678 21 22 23 24 25

DIN

SCLK

tCSH0

R2 R1 R0 D17 D16 D15 D14 D1 D0 X––

0R3 R2 R1 R0 D17 D16 D15 D2 D1 D0 0 ZDOUT

tCSH1

tCSA

tDS

tDH

tCP

tCL

tCH

tDOH

tDOT

tDOE

tCSPW

tDOZ

tCRH

tCSF

tCRF tCSR

READY

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE

MAX5316 toc01

CODE

DNL (LSB)

49152 655363276816384

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

VREF = 2.5V

VAVDD = 3V

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE

MAX5316 toc02

CODE

INL (LSB)

49152 655363276816384

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

VREF = 2.5V

VAVDD = 3V

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Typical Operating Characteristics (continued)

(VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,

RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE

MAX5316 toc03

CODE

DNL (LSB)

49152 655363276816384

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

VREF = 4.096V

VAVDD = 5V

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE

MAX5316 toc04

CODE

INL (LSB)

49152 655363276816384

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

VREF = 4.096V

VAVDD = 5V

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE

MAX5316 toc05

CODE

DNL (LSB)

49152 655363276816384

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

VREF = 5V

VAVDD = 5.25V

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE

MAX5316 toc06

CODE

INL (LSB)

49152 655363276816384

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

VREF = 5V

VAVDD = 5.25V

TEMPERATURE (°C)

8050 65-10 5 20 35-25 110

DIFFERENTIAL NONLINEARITY

vs. TEMPERATURE

MAX5316 toc07

DNL (LSB)

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

-40

VREF = 2.5V

MIN DNL

MAX DNL

TEMPERATURE (°C)

8050 65-10 5 20 35-25 110

INTEGRAL NONLINEARITY

vs. TEMPERATURE

MAX5316 toc08

INL (LSB)

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

-40

VREF = 2.5V

MIN INL

MAX INL

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Typical Operating Characteristics (continued)

(VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,

RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)

5.14.73.9 4.33.53.12.7 5.5

VAVDD (V)

INTEGRAL NONLINEARITY

vs. SUPPLY VOLTAGE

MAX5316 toc12

INL (LSB)

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

VREF = 2.5V

MIN INL

MAX INL

4.84.43.6 4.03.22.82.4 5.2

REFERENCE VOLTAGE (V)

DIFFERENTIAL NONLINEARITY

vs. REFERENCE VOLTAGE

MAX5316 toc13

DNL (LSB)

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

VAVDD = 5.25V

MIN DNL

MAX DNL

4.84.43.6 4.03.22.82.4 5.2

REFERENCE VOLTAGE (V)

INTEGRAL NONLINEARITY

vs. REFERENCE VOLTAGE

MAX5316 toc14

INL (LSB)

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

VAVDD = 5.25V

MIN INL

MAX INL

TEMPERATURE (°C)

8050 65-10 5 20 35-25 110

DIFFERENTIAL NONLINEARITY

vs. TEMPERATURE

MAX5316 toc09

DNL (LSB)

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

-40

VREF = 4.096V

MIN DNL

MAX DNL

TEMPERATURE (°C)

8050 65-10 5 20 35-25 110

INTEGRAL NONLINEARITY

vs. TEMPERATURE

MAX5316 toc10

INL (LSB)

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

-40

MIN INL

MAX INL

VREF = 4.096V

5.14.73.9 4.33.53.12.7 5.5

VAVDD (V)

DIFFERENTIAL NONLINEARITY

vs. SUPPLY VOLTAGE

MAX5316 toc11

DNL (LSB)

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

VREF = 2.5V

MIN DNL

MAX DNL

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Typical Operating Characteristics (continued)

(VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,

RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)

ZERO-SCALE OUTPUT ERROR

vs. SUPPLY VOLTAGE

MAX5316 toc15

OUTPUT ERROR (LSB)

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

VREF = 2.5V

CODE = 0x0000

5.14.73.9 4.33.53.12.7 5.5

VAVDD (V)

FULL-SCALE OUTPUT ERROR

vs. SUPPLY VOLTAGE

MAX5316 toc16

OUTPUT ERROR (LSB)

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

VREF = 2.5V

CODE = 0xFFFF

5.14.73.9 4.33.53.12.7 5.5

VAVDD (V)

ZERO-SCALE OUTPUT ERROR

vs. OUTPUT CURRENT

MAX5316 toc17

OUTPUT CURRENT (mA)

OUTPUT ERROR (LSB)

272418 216 9 12 153

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

CODE = 0x0000

VAVSS = -1.25V

VREF = 4.096V

SINKING

SOURCING

FULL-SCALE OUTPUT ERROR

vs. OUTPUT CURRENT

MAX5316 toc18

OUTPUT CURRENT (mA)

OUTPUT ERROR (LSB)

272418 216 9 12 153

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

CODE = 0xFFFF

VREF = 4.096V

SINKING

SOURCING

OUTPUT DRIVE CAPABILITY

MAX5316 toc19

OUTPUT CURRENT (mA)

OUTPUT ERROR (LSB)

764 52 31

-8

-6

-4

-2

-10

CODE = 0x0640

VAVSS = 0V

VREF = 4.096V

SINKING CURRENT

TA = +25°C

OUTPUT DRIVE CAPABILITY

MAX5316 toc20

OUTPUT CURRENT (mA)

OUTPUT ERROR (LSB)

764 52 31

-8

-6

-4

-2

-10

CODE = 0xFFFF

VAVDD = 4.2V

VREF = 4.096V

SOURCING CURRENT

TA = +25°C

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Typical Operating Characteristics (continued)

(VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,

RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)

454030 3510 15 20 255

OUTPUT DRIVE CAPABILITY

MAX5316 toc21

OUTPUT CURRENT (mA)

OUTPUT ERROR (LSB)

-8

-6

-4

-2

-10

CODE = 0x0000

VAVSS = -1.25V

VREF = 4.096V

SINKING CURRENT

TA = +25°C

454030 3510 15 20 255

OUTPUT DRIVE CAPABILITY

MAX5316 toc22

OUTPUT CURRENT (mA)

OUTPUT ERROR (LSB)

-8

-6

-4

-2

-10

CODE = 0xFFFF

VAVDD = 5V

VREF = 4.096V

SOURCING CURRENT

TA = +25°C

454030 3510 15 20 255

OUTPUT DRIVE CAPABILITY

MAX5316 toc23

OUTPUT CURRENT (mA)

OUTPUT ERROR (LSB)

-8

-6

-4

-2

-10

CODE = 0x0000

VAVSS = -1.25V

VREF = 2.5V

SINKING CURRENT

TA = +25°C

5550454030 3510 15 20 255

OUTPUT DRIVE CAPABILITY

MAX5316 toc24

OUTPUT CURRENT (mA)

OUTPUT ERROR (LSB)

-8

-6

-4

-2

-10

CODE = 0xFFFF

VAVDD = 5V

VREF = 2.5V

SOURCING CURRENT

TA = +25°C

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX5316 toc25

VAVDD (V)

IAVDD (mA)

5.255.004.75

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

6.0

5.0

4.50 5.50

TA = +25°C TA = -40°C

TA = +105°C

VREF = 4.096V

POWER-DOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX5316 toc26

VAVDD (V)

IAVDD (µA)

5.255.004.75

4.50 5.50

TA = +25°C

TA = -40°C

TA = +105°C

VPD = VDDIO

VREF = 4.096V

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Typical Operating Characteristics (continued)

(VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,

RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)

100

200

300

400

500

GROUND CURRENT vs. CODE

MAX5316 toc27

CODE

CURRENT (µA)

49152 655363276816384

600

CURRENT OUT OF

AGND_F AND AGND_S

VREF = 4.096V

0.1Hz TO 10Hz OUTPUT NOISE

MAX5316 toc29

VOUT

1µV/div

1s/div

10k1k10010 100k

OUTPUT NOISE DENSITY

MAX5316 toc28

FREQUENCY (Hz)

VOLTAGE NOISE (nV/√Hz)

100

CODE = 0x8000

MAJOR CARRY GLITCH

(1 LSB NEGATIVE STEP)

MAX5316 toc30

VLDAC

5V/div

VOUT

10mV/div

400ns/div

MAJOR CARRY GLITCH

(1 LSB POSITIVE STEP)

MAX5316 toc31

400ns/div

VLDAC

5V/div

VOUT

10mV/div

SETTLING TIME

(CODE = 0x1000 TO 0xF000)

MAX5316 toc32

1µs/div

VLDAC

5V/div

VOUT

2V/div

VOUT

200µV/div

SETTLING TIME

(CODE = 0xF000 TO 0x1000)

MAX5316 toc33

1µs/div

VLDAC

5V/div

VOUT

2V/div

VOUT

200µV/div

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Typical Operating Characteristics (continued)

(VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,

RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)

DIGITAL CLOCK FEEDTHROUGH

MAX5316 toc34

VSCLK

5V/div

VOUT

1mV/div

2µs/div

EXITING POWER-DOWN RESPONSE

MAX5316 toc36

VPD

1V/div

VOUT

2V/div

10µs/div

ENTERING POWER-DOWN RESPONSE

MAX5316 toc35

VPD

1V/div

VOUT

2V/div

10µs/div

SLOW POWER-UP RESPONSE

(RSTSEL = LOW)

MAX5316 toc37

VAVDD

5V/div

VAVSS

2V/div

VREFO

2V/div

VBYPASS

2V/div

VOUT

2V/div

4ms/div

SLOW POWER-UP RESPONSE

(RSTSEL = HIGH)

MAX5316 toc38

VAVDD

5V/div

VAVSS

2V/div

VREFO

2V/div

VBYPASS

2V/div

VOUT

2V/div

4ms/div

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Pin Description

Pin Configuration

TQFN

*EXPOSED PAD-CONNECT TO AGND.

TOP VIEW

MAX5316

1M/Z

4DOUT

5DIN

6SCLK

7CS

*EP

19 AVDD2

18 AGND_F

17 AGND_S

16 REF

15 REFO

RST

VDDIO

DGND

BYPASS

14 RFB

13 OUT

TC/SB

AVSS

AGND

AVDD1

24 23 22 21 20

BUSY

LDAC

READY

PIN NAME FUNCTION

1M/Z

Reset Select Input. M/Z selects the default state of the analog output (OUT) after power-on or hardware or

software reset. Connect M/Z to VDDIO to set the default output voltage to midscale or to DGND to set the

default output voltage to zero scale.

2BUSY

Digital Input/Open-Drain Output. Connect a 5.1kI pullup resistor from BUSY to VDDIO. BUSY goes low

immediately after writing to the DIN register. During this time, the user can continue writing new data to

the DIN register, but no further updates to the DAC register and DAC output can take place. If LDAC

is asserted low while BUSY is low, this event is stored. BUSY is bidirectional, and can be asserted low

externally to delay LDAC action. BUSY also goes low during power-on reset, when RST is low, or when

software reset is activated.

3LDAC

Active-Low Load DAC Logic Input. If LDAC is taken low while BUSY is inactive (high), the contents of the

input registers are transferred to the DAC register and the DAC output is updated. If LDAC is taken low

while BUSY is asserted low, the LDAC event is stored and the DAC register update is delayed until BUSY

deasserts. Any event on LDAC during power-on reset or when RST is low is ignored.

4 DOUT SPI Bus Serial Data Output. See the Serial Interface section for details.

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Pin Description (continued)

PIN NAME FUNCTION

5 DIN SPI Bus Serial Data Input. See the Serial Interface section for details.

6 SCLK SPI Bus Serial Clock Input. See the Serial Interface section for details.

7CS SPI Bus Active-Low Chip-Select Input. See the Serial Interface section for details.

8TC/SB DIN Format Select Input. Connect TC/SB to DGND to set the data input format to straight binary or to

VDDIO to set it to two’s complement.

9 PD

Active-High Power-Down Input. Connect PD to DGND for normal operation. Connect PD to VDDIO to

place the device in power-down. In power-down, OUT (analog voltage output) is connected to AGND

through a 2kω resistor, but the contents of the input registers and the DAC latch do not change. The SPI

interface remains active in power-down.

10 AVSS Negative Analog Power-Supply Input. Connect to AGND or a negative supply voltage. When connected to

the negative supply voltage, bypass AVSS with a 0.1µF capacitor to AGND.

11 AGND Analog Ground. Connect to the analog ground plane.

12, 19 AVDD1 Positive Analog Power-Supply Input. Bypass each AVDD_ locally with a 0.1µF and 10µF capacitor to

AGND (analog ground plane). Connect AVDD1 and AVDD2 together.

13 OUT

Buffered Analog Voltage Output. Connect OUT to RFB externally to close the output buffer feedback loop.

The buffered output is capable of directly driving a 10kω load. The state of M/Z sets the power-on reset

state of OUT (zero or midscale). In power-down, OUT is connected to AGND through a 2kω pulldown

resistor.

14 RFB Feedback Resistor Input. RFB is connected through the internal feedback resistor to the inverting input of

the analog output buffer. Externally connect RFB to OUT to close the output buffer feedback loop.

15 REFO Voltage Reference Buffered Output. Bypass with a 100pF capacitor to AGND.

16 REF High-Impedance 10Mω Voltage Reference Input

17 AGND_S DAC Analog Ground Sense

18 AGND_F DAC Analog Ground Force. Connect to the analog ground plane.

19 AVDD2 Positive Analog Power-Supply Input. AVDD2 supplies power to the internal digital linear regulator. Bypass

AVDD2 locally to AGND with 0.1µF and 10µF capacitors. Connect AVDD2 and AVDD1 together.

20 BYPASS Internal Bypass Connection. Connect BYPASS to DGND with 0.01µF and 1µF capacitors.

21 DGND Digital Ground

22 VDDIO Digital Interface Power-Supply Input. Connect to a 1.7V to 5.5V logic-level supply. Bypass VDDIO with a

0.1µF capacitor to DGND. The supply voltage at VDDIO sets the logic-level for the digital interface.

23 RST

Active-Low Reset Input. Drive RST low to DGND to put the device into a reset state. A reset state sets all

SPI input registers to their default power-on reset states as defined by the state of inputs M/Z and TC/SB.

Set RST high to VDDIO, the DAC output remains at the state defined by M/Z until LDAC is taken low.

24 READY

SPI Active-Low Ready Output. READY asserts low when the device successfully completes processing an

SPI data frame. READY asserts high at the next rising edge of CS. In daisy-chain applications, the READY

output typically drives the CS input of the next device in the chain or a GPIO of a microcontroller.

— EP Exposed Pad. EP is internally connected to AGND. Connect to the analog ground plane.

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Detailed Description

The MAX5316 is a high-accuracy, 16-bit, serial SPI input,

buffered voltage output digital-to-analog converter (DAC) in

a 4mm x 5mm, 24-lead TQFN package. The device features

Q1 LSB INL (max) accuracy and a Q1 LSB DNL (max) accu-

racy over the -40NC to +105NC temperature range.

The DAC voltage output is buffered with a fast set-

tling time of 3Fs and a low offset and gain drift of

Q0.6ppm/NC of FSR (typ). The force-sense output (OUT)

maintains accuracy while driving loads with long lead

lengths. A separate AVSS supply allows the output amplifier

to go to 0V (GND) while maintaining full linearity performance.

At power-up, the device resets its outputs to zero or mid-

scale, providing additional safety for applications which

drive valves or other transducers that need to be off on

power-up. This is selected by the state of the M/Z input

on power-up.

The wide supply voltage range of 2.7V to 5.5V and

integrated low-drift, low-noise reference buffer ampli-

fier makes for ease of use. Since the reference buffer

input has a high input resistance, an external buffer is

not required. The device accepts an external reference

between 2.4V and VAVDD - 0.1V for maximum flexibility.

The MAX5316 features a 50MHz, 3-wire SPI, QSPI,

MICROWIRE, and DSP-compatible serial interface. The

separate digital interface supply voltage input (VDDIO) is

compatible with a wide range of digital logic levels from 1.7V

to 5.5V, eliminating the need for separate voltage translators.

DAC Reference Buffer

The external reference input has a high input (REF) imped-

ance of 10MI || 10pF and accepts an input voltage from

+2.4V to VAVDD - 0.1V. Connect an external reference

supply between REF and AGND. Bypass the reference

buffer output REFO to AGND with a 100pF capacitor.

Connect the anode of an external Schottky diode to REF

and the cathode to AVDD1 to prevent internal ESD diode

conduction in the event that the reference voltage comes

up before AVDD at power up. Follow the recommenda-

tions described in the Power-Supply Sequencing section.

Visit www.maxim-ic.com/products/references for a list

of available external voltage-reference devices.

Output Amplifier (OUT)

The MAX5316 includes an internal buffer for the DAC

output. The internal buffer provides improved load

regulation for the DAC output. The output buffer slews at

5V/Fs and can drive up to 2kI in parallel with 200pF.

The buffer has a rail-to-rail output capable of swinging to

within 100mV of AVDD_ and AVSS.

The positive analog supply voltage (AVDD_) determines

the maximum output voltage of the device as AVDD_

powers the output buffer.

The output is diode clamped to ground, preventing nega-

tive voltage excursions beyond approximately -0.6V.

Negative Supply Voltage (AVSS)

The negative supply voltage (AVSS) determines the minmum

output voltage. If AVSS is connected to ground, the output

voltage can be set to as low as 100mV without degrading

linearity. For operation down to 0V, connect AVSS to a nega-

tive supply voltage between -0.1V and -1.25V. The MAX1735

is recommended for generating -1.25V from a -5V supply.

Force/Sense

The MAX5316 uses force/sense techniques to ensure

that the load is regulated to the desired output volt-

age despite line drops due to long lead lengths. Since

AGND_F and AGND_S have code dependent ground

currents, a ground impedance less than 13mω ensures

that the INL will not degrade by more than 0.1 LSB. Form

a star ground connection (Figure 2a) near the device

with AGND_F, AGND_S, and AGND tied together. Always

refer remote DAC loads to this system ground for best

performance. Figure 2b shows how to configure the

device and an external op amp for proper force/sense

operation. The amplifier provides as much drive as

needed to force the sensed voltage (measured between

RFB and AGND_S) to equal the desired voltage.

Figure 2a. Star Ground Connection

Figure 2b. Force/Sense Connection

OUT

RFB

AGND_F

AGND_S

AGND

MAX5316

OUT

RFB

AGND

AGND_F

AGND_S

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

16-Bit Ideal Transfer Function

The transfer function for the MAX5316 is given by:

OUT REF 16

CODE

(DIN code from 0x0000 to 0xFFFF)

= ×

For the simple binary case and:

OUT REF 16

REF

OUT REF 16

(CODE 0x8000)

(DIN code from 0x8000 to 0xFFFF)

CODE

VV 2

(DIN code from 0x0000 to 0xFFFF)

−

= ×

=×+

For the two’s complement case.

Straight Binary vs. Two’s Complement

Table 1 and Table 2 show the math necessary to convert

the DIN code into VOUT for the 16-bit DAC. 1 LSB is

equal to VREF/216.

Input Range

The range of DIN is summarized in Table 3 and Table 4.

Also shown are the range values for the MAX5316 with a

4.096V reference. Note that VREF is the reference voltage

applied to REF and 1 LSB is equal to VREF/216.

Table 3. DIN Range (Straight Binary Mode)

Table 4. DIN Range (Two’s Complement Mode)

Figure 3. DIN to VOUT Transfer Curve

DIN

VOUT

VREF

0x0000

0x8000

0x0000

0xFFFF STRAIGHT BINARY

0x7FFF TWO’S COMPLEMENT

ZERO-SCALE

MIDSCALE

FULL-SCALE

VREF/2

RANGE DIN CODE VOUT (V) MAX5316 VALUE (V)

Minimum 0x0000 0 0

Maximum 0xFFFF (VREF - 1 LSB) 4.095938

RANGE DIN CODE VOUT (V) MAX5316 VALUE (V)

Minimum 0x8000 0 0

Maximum 0x7FFF (VREF - 1 LSB) 4.095938

Table 1. Straight Binary Mode

DIN CODE EQUATION FOR VOUT RANGE

0x0000 to 0xFFFF 0V to (VREF - 1 LSB)

OUT REF 16

CODE

= ×

Table 2. Two’s Complement Mode

DIN CODE EQUATION FOR VOUT RANGE

0x8000 to 0xFFFF 0V to (VREF/2 -1 LSB)

0x0000 to 0x7FFF VREF/2 to (VREF - 1 LSB)

REF

OUT REF 16

CODE

VV 2

=×+

OUT REF 16

CODE 0x8000

−



= ×





MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Reset

The device is reset upon power-on, hardware reset using

RST, or software reset using register 0x4, bit 15, com-

mand RSTSW. After reset, the value of the input register,

the DAC latch and the output voltage are set to the values

defined by the M/Z input. If a hardware reset occurs dur-

ing a SPI programming frame, anything before and after

the reset for the frame will be ignored. A software reset

initiated through the SPI interface takes effect after the

end of the valid frame.

Output State Upon Reset

The output voltage can be set to either zero or mid-

scale upon power-up, or a hardware or software reset,

depending on the state of the M/Z input. After power-up,

if the device detects that this input is low, the output volt-

age is set to zero scale. If M/Z is high, the output voltage

is set to midscale.

Note that during reset, when RST is low or RSTSW is set

to 0, the output voltage is set slightly lower than the value

after coming out of reset. During reset, the output voltage

is set to the values shown for the VOUT-RESET specifica-

tion in the Electrical Characteristics.

Power-Down

The device can be powered down by either hardware

(pulling PD high) or software (setting the PD_SW bit in

either the 0x4 or 0xC registers). Note that the hardware

and software inputs are ORed. Asserting either is enough

to place the device in power-down mode.

In order to restore normal operation to the device, satisfy

both of these conditions:

1) Pull PD low.

2) Set the bits PD_SW’s (in both 0x4 and 0xC registers)

to 0.

In power-down, the output is internally connected to

AGND through a 2kI resistor. The SPI interface remains

active and the DAC register content remains unchanged.

Data Format Selection

(Straight Binary vs. Two’s Complement)

The MAX5316 interprets the data code input (DIN) as

either straight binary or two’s complement. To choose the

straight binary format, set the TC/SB input low. For two’s

complement, set the input high.

LDAC and BUSY Interaction

The BUSY line is open drain and is normally pulled up by

an external resistor. It is software-configurable to be bidi-

rectional and can be pulled down externally. Whenever

the DIN register is changed, the device transfers the

value to the DAC register. To indicate to the host proces-

sor that the device is busy transferring, the device pulls

the BUSY output low. Once transfer is complete, the

device releases BUSY and the host processor can load

the DAC by toggling the LDAC input. If LDAC is set low

while BUSY is low, the LDAC event is latched and imple-

mented when the transfer is complete and BUSY rises.

There are four ways in which the LDAC and BUSY out-

puts can be used. This is shown graphically in Figure 4.

1) The host sends a new command. The device sets

BUSY low. The host monitors BUSY to determine

when it goes high. The device then pulses LDAC low

to update the DAC.

2) The host sends a new command. The device sets

BUSY low. The host toggles LDAC low then high

before BUSY goes high. The device latches the LDAC

event but does not implement it until processing is

complete. Then, BUSY goes high and the device

updates the DAC.

3) LDAC is held low. The host sends a new command

and the device sets BUSY low. The device updates

the DAC when the processing is complete and BUSY

goes high.

4) BUSY is pulled down externally to delay DAC update.

The BUSY pin is bidirectional. To use BUSY as an

input, set the NO_BUSY bit to 1 using the 0x4 or

0xC command. When configured as an input, pulling

BUSY low at least 50ns before the device releases

the line delays DAC update. DAC update occurs only

after BUSY is released and goes high. If used as an

input, drive BUSY with an open-drain output with a

pullup to VDDIO.

If the DAC must be updated at a precise time with the

least amount of jitter, use option 1.

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Serial Interface

Overview

The SPI interface supports speeds up to 50MHz. When

CS is high, the remaining interface inputs are disabled to

reduce transient currents. The interface supports daisy

chaining to enable multiple device to be controlled on

the same SPI bus.

The device has a double-buffered interface consisting of

two register banks: the input register and the DAC reg-

ister. The input register for DIN is connected directly to

the 24-bit SPI input shift register. The DAC latch contains

the DAC code and is loaded as defined in the LDAC and

BUSY Interaction section.

A valid SPI frame is 24-bit wide with 4-bit command R3

to R0, 16-bit data D15 to D0, and 4 unused LSBs. A full

24-bit SPI command sequence is required for all SPI

command operations, regardless of the number of data

bits actually used for the command. Any commands

terminating with less than a full 24-bit sequence will be

aborted without impacting the operation of the part (sub-

ject to tCSA timing requirements). Data is not written into

the SPI input register or DAC and it continues to hold the

preceding valid data. If a command sequence with more

than 24 bits is provided, the command will be executed

on the 24th SCLK falling edge and the remainder of the

command will be ignored.

All SPI commands result in the device assuming con-

trol of the DOUT line from the first SCLK edge through

the 24th SCLK edge. After relinquishing the DOUT line,

the MAX5316 will return to a high-impedance state. An

optional bus hold circuit can be engaged to hold DOUT

at its last bit value while not interfering with other devices

on the bus.

DOUT is disabled at power-up and must be enabled

through the SPI interface. When enabled, DOUT echoes

the 4-bit command plus 16-bit data, which is being

programmed. During readback, DOUT echoes the 4-bit

command followed by the true readback data depending

upon the type of read command. Table 4 shows the bit

positions for DOUT and DIN within the 24-bit SPI frame.

The device is designed such that SCLK idles low, and

DIN and DOUT change on the rising clock edge and get

latched on the falling clock edge. The SPI host controller

should be set accordingly.

Figure 4. BUSY and LDAC Timing

DIN

SCLK

BUSY

LDAC

VOUT

OPTION 1

INPUT REGISTER LOADED

OPTION 2

OPTION 3

OPTION 4 (USED AS INPUT)

X1 2X21 22 23 X

tBUSY

tCBF

tLDH

50ns

tLDPW

BUSY PULLED LOW EXTERNALLY

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Daisy-Chain SPI Operation Using READY Output

The READY pulse appears 24 clock cycles after the neg-

ative edge of CS as shown in Figure 5 and can therefore

be used as the CS line for the next device in the daisy

chain. Since the device looks at the first 24 bits of the

transmission following the falling edge of CS, it is pos-

sible to daisy-chain the device with different command

word lengths. READY goes high after CS is driven high.

To perform a daisy-chain write operation, drive CS low

and output the data serially to DIN. The propagation of

the READY signal then controls how the data is read by

the device. As the data propagates through the daisy

chain, each individual command in the chain is executed

on the 24th falling clock edge following the falling edge

of the respective CS input. To update just one device

in a daisy chain, send the no-op command to the other

device in the chain. To update the first device in the

chain, raise the CS input after writing to that device.

Because daisy-chain operation requires paralleling the

DOUTs of all the MAX5316 in the chain, the NO_HOLDEN

bit in register 0x4 or 0xC should be set to 1 for all devices.

Doing so ensures that DOUT goes into high-impedance

after the SPI frame is complete (i.e. after the 24th clock

cycle) as shown in Figure 6.

Note that ‘X’ is don’t care.

Table 5. SPI Command and Data Mapping with Clock Falling Edges

Figure 5. Daisy-Chain SPI Connection Terminating with a Standard SPI Device

µC

SLAVE 1

SCLK

DIN

DOUT

MOSI

MISO

I/O

SCK

SLAVE 3

SCLK

DIN

POUT

SLAVE 2

SCLK

DIN

DOUT

CS READY CS READY

CS READY

CLOCK

EDGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

DIN R3 R2 R1 R0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

DOUT 0 R3 R2 R1 R0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Figure 6. Daisy-Chain SPI Connection Timing

Figure 7. Stand-Alone Operation

Stand-Alone Operation

The diagram in Figure 7 shows a stand-alone connec-

tion of the MAX5316 in a typical SPI application. If more

than one peripheral device shares the DOUT bus, the

NO_HOLDEN bit in register 0x4 or 0xC should be set to 1

for the MAX5316. Doing so ensures that DOUT goes into

high-impedance after the SPI frame is complete (i.e. after

the 24th clock cycle).

Command and Register Map

All command and data registers have read and write

functionality. The register selected depends on the com-

mand select bits R[3:0]. Each write to the device consists

of 4 command select bits (R[3:0]), 16 data bits (which are

detailed in Tables 7–11), and 4 don’t care LSBs. A sum-

mary of the commands is shown in Table 6.

DIN

DOUT1

SCLK

12324222120432123 2422215432123 2422215432

SLAVE 1 DATA SLAVE 2 DATA SLAVE 3 DATA

READY 1

READY 3

READY 2

DOUT2 HI-Z HI-Z

HI-Z

DOUT3

CSm

CS1

CS CS

SCLK

µC

DWRITE

DREAD

SCLK

DIN

DOUT

MAX5316

TO OTHER DEVICES/CHAINS

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Table 6. Register Map Summary

Table 7. No-Op Command (0x0)

Table 8a. Straight Binary DIN Write Register (TC/SB) = 0) (0x1)

HEX R3 R2 R1 R0 FUNCTION

0 0 0 0 0 No-op. Used mainly in daisy-chain communications.

1 0 0 0 1 DIN register write

2, 3,

5–8, A,

B, D–F

— — — — Reserved

4 0 1 0 0 Configuration register write

9 1 0 0 1 DIN register read

C 1 1 0 0 Configuration and status register read.

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NAME X X X X X X X X X X X X X X X X

DEFAULT X X X X X X X X X X X X X X X X

BIT NAME DESCRIPTION

15:0 Don’t care No action on SPI shift register and DAC input registers. Use for daisy-chain purposes when

R[3:0] = 0000.

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NAME B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

DEFAULT 0x0000 when MZ = DGND (zero scale)

0x8000 when MZ = VDDIO (midscale)

BIT NAME DESCRIPTION

15:0 B[15:0]

16-bit DAC input code in straight binary format. For clarity, a few examples are shown below.

0000 0000 0000 0000 0x0000 zero scale

0100 0000 0000 0000 0x4000 quarter scale

1000 0000 0000 0000 0x8000 midscale

1100 0000 0000 0000 0xC000 three-quarter scale

1111 1111 1111 1111 0xFFFF full scale - 1 LSB

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Table 8b. Two’s Complement DIN Write Register (TC/SB) = 1) (0x1)

Table 9. General Configuration Write Register (0x4)

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NAME B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

DEFAULT 0x8000 when MZ = DGND (zero scale)

0x0000 when MZ = VDDIO (midscale)

BIT NAME DESCRIPTION

15:0 B[15:0]

16-bit DAC input code in two’s complement format. For clarity, a few examples are shown below.

1000 0000 0000 0000 0x8000 zero scale

1100 0000 0000 0000 0xC000 quarter scale

1111 1111 1111 1111 0xFFFF midscale – 1 LSB

0000 0000 0000 0000 0x0000 midscale

0000 0000 0000 0001 0x0001 midscale + 1 LSB

0100 0000 0000 0000 0x4000 three-quarter scale

0111 1111 1111 1111 0x7FFF full scale – 1 LSB

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NAME PD_SW NO_HOLDEN RST_SW NO_BUSY DOUT_ON XXXXXXXXXXX

DEFAULT 0 0 1 0 0 X X X X X X X X X X X

BIT NAME DESCRIPTION

15 PD_SW

Software PD (Power-Down). Equivalent to the PD input.

0: Normal mode

1: Power-down mode. OUT is internally connected to AGND using a 2kI resistor.

14 NO_HOLDEN

SPI Bus Hold Enable.

0: Bus hold enabled for SPI DOUT output. DOUT stays at its last value after the SPI CS

input rises at the end of the SPI frame (i.e. after the 24th clock cycle).

1: Bus hold disabled for SPI DOUT output. DOUT goes high impedance after the SPI CS

input rises at the end of the SPI frame (i.e. after the 24th clock cycle).

13 RST_SW

Software Reset. Equivalent to the RST input.

0: Place device in reset

1: Normal operation

Set the active low RST_SW bit low to initiate a software reset (equivalent to pulling RST low)

12 NO_BUSY

BUSY Input Disable.

0: BUSY input is active.

1: BUSY input is disabled.

Note that this does not affect the BUSY bit in the General Configuration and Status

delay DAC updates.

11 DOUT_ON

SPI DOUT Output Disable. DOUT is disabled by default.

0: DOUT output disabled. When DOUT is disabled, the output is pulled low for the

duration of the SPI frame.

1: DOUT output enabled.

10:0 — Don’t care. These bits are reserved for the corresponding read command.

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Table 10. DIN Read Register (0x9)

Table 11. General Configuration and Status Read Register (0xC)

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NAME B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

DEFAULT 0000000000000000

BIT NAME DESCRIPTION

15:0 B[15:0] 16-bit DIN readback value stored in the bits B[15:0].

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NAME PD_SW NO_

HOLDEN RST_SW NO_BUSY DOUT_ON BUSY X X X X X X REV_ID[3:0]

DEFAULT 0 0 1 0 0 0 0 0 0 0 0 0 0001

BIT NAME DESCRIPTION

15 PD_SW

Software PD (Power-Down). Equivalent to the PD input.

0: Normal mode.

1: Power-down mode. OUT is internally connected to AGND using a 2kI resistor.

14 NO_HOLDEN

SPI Bus Hold Enable.

0: Bus hold enabled for SPI DOUT output. DOUT stays at its final value after the SPI CS input

rises at the end of the SPI frame.

1: Bus hold disabled for SPI DOUT output. DOUT goes high impedance after the SPI CS input

rises at the end of the SPI frame.

13 RST_SW

Software Reset. Equivalent to the RST input.

0: Place device in reset.

1: Normal operation.

Set the active low RST_SW bit low to initiate a software reset (equivalent to pulling RST low).

12 NO_BUSY

BUSY Input Disable.

0: BUSY input is active.

1: BUSY input is disabled.

Note that this does not affect the BUSY bit in the General Configuration and Status Register.

The BUSY pin is bidirectional. When enabled, it can be pulled down externally to delay DAC

updates.

11 DOUT_ON

SPI DOUT Output Disable. DOUT is disabled by default.

0: DOUT output disabled. When DOUT is disabled, the output is pulled low for the duration of

the SPI frame.

1: DOUT output enabled.

10 BUSY

Global BUSY status readback.

0: Device is busy transferring DIN code to the DAC register.

1: Device is not busy.

9:4 — Reserved. Will read back 0.

3:0 REV_ID[3:0] Device revision

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Applications Information

Power-On Reset (POR)

Upon power-on, the output is set to either zero-scale (if

M/Z is low) or midscale (if M/Z is high). The entire register

map is set to their default values as shown in Tables 7–11.

Power Supplies and

Bypassing Considerations

For best performance, use a separate supply for the

MAX5316. Bypass VDDIO, AVDD_, and AVSS with high-

quality ceramic capacitors to a low-impedance ground

as close as possible to the device. A typical high-quality

X7R 10FF capacitor can become self resonant at 2MHz.

Therefore, it is actually an inductor above 2MHz and is

useless for decoupling signals above 2MHz. It is therefore

recommended that several capacitors of different values

are connected in parallel (e.g. 0.1µF || 10µF). Figure 8

shows the magnitude of impedance of typical 1FF, 100nF,

and 10nF X7R capacitors. As the capacitance reduces,

the self-resonant frequency increases. In addition, the

parallel combination of all three is shown and exhibits a

significant improvement over a single capacitor. These

plots do not include any PCB trace inductance.

Minimize lead lengths to reduce lead inductance. Adding

just 2nH trace inductance to each of the typical capacitors

above produces the effects shown in Figure 9. This shows

significant reduction in the self-resonant frequencies of

the capacitors.

Internal Linear Regulator (BYPASS)

BYPASS is the output of an internal linear regulator and is

used to power digital circuitry. Connect BYPASS to DGND

with a ceramic capacitor in the range of 1FF to 10FF with

ESR in the range of 100mI to 20mI to ensure stability.

Power-Supply Sequencing

During power-up, ensure that AVDD_ comes up before

the reference does. If this is not possible, connect a

Schottky diode between the REF and AVDD_ such as

the MBR0530T1G. If REF does come up before AVDD_,

the diode conducts and clamps REF to AVDD_. Once

AVDD_ has come up, the diode no longer conducts.

REF should always be below AVDD_ as specified in the

Electrical Characteristics. AVDD_ and AVDD_ should be

connected together and powered from the same supply.

VDDIO and AVSS can be sequenced in any order. Always

perform a reset operation after all the supplies are brought

up to place the device in a known operating state.

Layout Considerations

Digital and AC transient signals on AGND inputs can

create noise at the outputs. Connect both AGND inputs

to form the star ground for the DAC system. Refer remote

DAC loads to this system ground for the best possible

performance (see the Force/Sense section).

Use proper grounding techniques, such as a multilayer

board with a low-inductance ground plane, or star con-

nect all ground return paths back to AGND. Do not use

wire-wrapped boards and sockets. Use ground plane

Figure 8. Typical X7R Capacitor Impedance Figure 9. Typical X7R Capacitor Impedance with Additional

2nH PCB Trace Inductance

100

100m

10m

100k 1M 10M 100M

IMPEDANCE (I)

FREQUENCY (Hz)

10nF

1µF

100nF

10nF

1µF

100nF

100

100m

10m

100k 1M 10M 100M

IMPEDANCE (I)

FREQUENCY (Hz)

10nF

1µF

100nF

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

shielding to improve noise immunity. Do not run analog

and digital signals parallel to one another (especially

clock signals) and avoid routing digital lines underneath

the device package. Connect the exposed pad to AGND

(analog ground plane).

For a recommended layout, consult the MAX5316/

MAX5318 Evaluation Kit datasheet.

Voltage Reference Selection and Layout

The voltage reference should be placed close to the DAC.

The same power-supply decoupling and grounding rules

as the DAC should be implemented. Many voltage refer-

ences require an output capacitor for stability or noise

reduction. Provided the trace between the reference

device and the DAC is kept short and well shielded, a sin-

gle capacitor may be used and placed close to the DAC.

However, for improved noise immunity, additional capaci-

tors may be used but be careful not to exceed the recom-

mended capacitance range for the voltage reference.

Refer to Applications Note AN4300: Calculating the Error

Budget in Precision Digital-to-Analog Converter (DAC)

Applications for detailed description of voltage refer-

ence parameters and trading off the error budget. The

MAX6126 is recommended for 16-bit applications.

Optimizing Data Throughput Rate

The LDAC and BUSY Interaction section details the timing

of data written to the device and how the DAC is updated.

Data throughput speed can be increased by overlapping

the data load time with the busy period and settling time

as shown below in Figure 10. Following the 24th SCLK

falling edge, the device holds BUSY low while transfer-

ring the value from the DIN register to the DAC register.

Providing that the LDAC falling edge arrives before the

24th SCLK falling edge, and assuming the SPI clock fre-

quency is high enough, the throughput period is therefore

limited by tBUSY and settling times only. A slight further

increase in throughput time can be gained by either tog-

gling LDAC during the busy period or by pulling it low

permanently. However, the exact point at which the DAC

update occurs is then determined internally as indicated

by the BUSY line rising edge. This is not an exact time.

BUSY Line Pullup Resistor Selection

The BUSY pin is an open-drain output. It therefore

requires a pullup resistor. A 5.1kI value is recommend-

ed as a compromise between power and speed. Stray

capacitance on this line can easily slow the rise time

to an unacceptable level. The BUSY pin can sink up to

5mA. Therefore a resistor as low as VDDIO/0.005 may be

used if faster rise times are required.

Figure 10. Optimum Throughput with Stable Update Period

24TH SCLK

tBUSY

DIN

OUT

BUSY

LDAC

24TH SCLK

LDAC FALLING EDGE BEFORE 24TH SCLK FALLING EDGE

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Producing Unipolar High-Voltage

and Bipolar Outputs

Figure 11 and Figure 12 show how external op amps can

be used to produce a unipolar high-voltage output and

a bipolar output

Definitions

Integral Nonlinearity (INL)

INL is the deviation of the measured transfer function from

a straight line drawn between two codes. This line is drawn

between the zero and full-scale codes of the transfer func-

tion, once offset and gain errors have been nullified.

Differential Nonlinearity (DNL)

DNL is the difference between an actual step height and

the ideal value of 1 LSB. If the magnitude of the DNL is

less than or equal to 1 LSB, the DAC guarantees no miss-

ing codes and is monotonic.

Offset Error

Offset error indicates how well the actual transfer func-

tion matches the ideal transfer function at a single point.

Typically, the point at which the offset error is specified

is at or near the zero-scale point of the transfer function.

Gain Error

Gain error is the difference between the ideal and the

actual full-scale output voltage on the transfer curve,

after removing the offset error. This error alters the slope

of the transfer function and corresponds to the same

percentage error in each step.

Settling Time

The settling time is the amount of time required from the

start of a LDAC high-to-low transition or BUSY low-to-high

transition (whichever occurs last), until the DAC output

settles to within 0.003% around the final value.

Digital Feedthrough

Digital feedthrough is the amount of noise that appears

on the DAC output when the DAC digital control lines

are toggled.

Digital-to-Analog Glitch Impulse

The glitch impulse occurs at the major carry transitions

along the segmented bit boundaries. It is specified as the

net area of the glitch impulse which appears at the output

when the digital input code changes by 1 LSB. The glitch

impulse is specified in nanovolts-seconds (nV-s).

Digital-to-Analog Power-Up Glitch Impulse

The digital-to-analog power-up glitch is the net area of

the glitch impulse which appears at the output when the

device exits power-down mode.

Figure 11. Unipolar High-Voltage Output Figure 12. Bipolar Output

OUT

0V TO KVREF

K = 1 + R2/R1

R2R1

MAX5316

MAX44251 OUT

REFO

-VREF

VREF

R1 = R2

MAX5316

MAX9632

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Ordering Information

Chip Information

PROCESS: BiCMOS

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maxim-ic.com/packages. Note that a

“+”, “#”, or “-” in the package code indicates RoHS status only.

Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

Typical Operating Circuit

2.4V TO (VAVDD -0.1V) MBR0530T1G

VDDIO

5.1kI

REF

0.1µF 0.01µF

µC

GPIO’s

SPI

INTERFACE

*CONNECT THE EXPOSED PAD TO AGND.

0.1µF1µF 10µF

2.7V TO 5V

1.8V TO 5V

AVDD2

AVDD1

15 REFO

13 OUT

14 RFB

BYPASS

LINEAR

REGULATOR

MAX5316

DGND

AGND

AGND_S

AGND_F

AVSS

BUFFER

OUTPUT

BUFFER

0 TO -1.25V

BUSY

M/Z

TS/SB

RSTSEL

LDAC

READY

SCLK

DIN

DOUT

0.1µF

10µF

100pF

INTERFACE

AND

CONTROL

INPUT

DAC

16-BIT

DAC

PART TEMP RANGE PIN-PACKAGE

MAX5316GTG+ -40NC to +105NC24 TQFN-EP*

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

24 TQFN-EP T2445+1 21-0201 90-0083

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.

Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical

Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 33

MAX5316

16-Bit, ±1 LSB Accuracy Voltage Output

DAC with SPI Interface

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 1/12 Initial release —