12/21/04
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AUTOMOTIVE MOSFET
PD - 95953
HEXFET® Power MOSFET
VDSS = 75V
RDS(on) = 22mΩ
ID = 42A
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low on-
resistance per silicon area. Additional features of
this design are a 175°C junction operating tempera-
ture, fast switching speed and improved repetitive
avalanche rating . These features combine to make
this design an extremely efficient and reliable device
for use in Automotive applications and a wide variety
of other applications.
S
D
G
Description
lAdvanced Process Technology
lUltra Low On-Resistance
l175°C Operating Temperature
lFast Switching
lRepetitive Avalanche Allowed up to Tjmax
Features
D-Pak
IRFR2607Z
I-Pak
IRFU2607Z
IRFR2607ZPbF
IRFU2607ZPbF
Absolute Maximum Ratings
Parameter Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)
IDM Pulsed Drain Current
c
PD @TC = 25°C Power Dissipation W
Linear Derating Factor W/°C
VGS Gate-to-Source Voltage V
EAS (Thermally limited) Single Pulse Avalanche Energy
d
mJ
EAS (Tested ) Single Pulse Avalanche Energy Tested Value
h
IAR Avalanche Current
c
A
EAR Repetitive Avalanche Energy
g
mJ
TJ Operating Junction and
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case
j
––– 1.38
RθJA Junction-to-Ambient (PCB mount)
ij
––– 40 °C/W
RθJA Junction-to-Ambient
j
––– 110
-55 to + 175
300 (1.6mm from case )
10 lbf
y
in (1.1N
y
m)
110
0.72
± 20
Max.
45
32
180
42
96
96
See Fig.12a, 12b, 15, 16
lLead-Free
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El
ectr
i
ca
l Ch
aracter
i
st
i
cs
@ T
J
=
2
5°
C (
un
l
ess
ot
h
erw
i
se
spec
ifi
e
d)
Parameter Min. Typ. Max. Units
V(BR)DSS Drain-to-Source Breakdown Voltage 75 ––– ––– V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.074 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 17.6 22 mΩ
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V
gfs Forward Transconductance 36 ––– ––– S
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA
Gate-to-Source Reverse Leakage ––– ––– -200
QgTotal Gate Charge ––– 34 51
Qgs Gate-to-Source Charge ––– 8.9 ––– nC
Qgd Gate-to-Drain ("Miller") Charge ––– 14 –––
td(on) Turn-On Delay Time ––– 14 –––
trRise Time ––– 59 –––
td(off) Turn-Off Delay Time ––– 39 ––– ns
tfFall Time ––– 28 –––
LDInternal Drain Inductance ––– 4.5 ––– Between lead,
nH 6mm (0.25in.)
LSInternal Source Inductance ––– 7.5 ––– from package
and center of die contact
Ciss Input Capacitance ––– 1440 –––
Coss Output Capacitance ––– 190 –––
Crss Reverse Transfer Capacitance ––– 110 ––– pF
Coss Output Capacitance ––– 720 –––
Coss Output Capacitance ––– 130 –––
Coss eff. Effective Output Capacitance ––– 230 –––
Source-Drain Ratin
g
s and Characteristics
Parameter Min. Typ. Max. Units
ISContinuous Source Current ––– ––– 45
(Body Diode) A
ISM Pulsed Source Current ––– ––– 180
(Body Diode)
c
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Recovery Time ––– 30 45 ns
Qrr Reverse Recovery Charge ––– 28 42 nC
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
VGS = 20V
VGS = -20V
VDS = 60V
VDS = 25V, ID = 30A
ID = 30A
Conditions
VGS = 10V
e
VGS = 0V
VDS = 25V
ƒ = 1.0MHz
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 60V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V
f
MOSFET symbol
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 30A, VGS = 0V
e
TJ = 25°C, IF = 30A, VDD = 38V
di/dt = 100A/µs
e
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 30A
e
VDS = VGS, ID = 50µA
VDS = 75V, VGS = 0V
VDS = 75V, VGS = 0V, TJ = 125°C
VGS = 10V
e
VDD = 38V
ID = 30A
RG = 15 Ω
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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance
Vs. Drain Current
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60µs PULSE WIDTH
Tj = 175°C
4.5V
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VGS, Gate-to-Source Voltage (V)
0.1
1.0
10.0
100.0
1000.0
ID, Drain-to-Source Current
(Α)
VDS = 20V
≤ 60µs PULSE WIDTH
TJ = 25°C
TJ = 175°C
0 10203040
ID, Drain-to-Source Current (A)
0
10
20
30
40
50
60
Gfs, Forward Transconductance (S)
TJ = 25°C
TJ = 175°C
VDS = 10V
380µs PULSE WIDTH
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60µs PULSE WIDTH
Tj = 25°C
4.5V
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
0
400
800
1200
1600
2000
2400
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 1020304050
QG Total Gate Charge (nC)
0
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
VDS= 60V
VDS= 30V
VDS= 12V
ID= 30A
FOR TEST CIRCUIT
SEE FIGURE 13
0.0 0.4 0.8 1.2 1.6 2.0 2.4
VSD, Source-to-Drain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
1 10 100 1000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
DC
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1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
Thermal Response ( Z
thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Normalized On-Resistance
Vs. Temperature
Ri (°C/W) τi (sec)
0.71826 0.000423
0.66173 0.004503
τJ
τJ
τ1
τ1
τ2
τ2
R1
R1R2
R2
τ
τC
Ci i/Ri
Ci= τi/Ri
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
10
20
30
40
50
ID , Drain Current (A)
LIMITED BY PACKAGE
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 30A
VGS = 10V
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QG
QGS QGD
VG
Charge
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage Vs. Temperature
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
25 50 75 100 125 150 175
Starting TJ, Junction Temperature (°C)
0
100
200
300
400
EAS, Single Pulse Avalanche Energy (mJ)
I D
TOP 3.5A
4.8A
BOTTOM 30A
1K
VCC
DUT
0
L
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VGS(th) Gate threshold Voltage (V)
ID = 1.0A
ID = 1.0mA
ID = 250µA
ID = 50µA
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Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 30A
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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
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D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline
12
IN THE ASSEMBLY LINE "A"
AS S E MBL E D ON WW 16, 1999
EXAMPLE:
WITH ASSEMBLY
THIS IS AN IRFR120
LOT CODE 1234
YEAR 9 = 1999
DAT E CODE
WEEK 16
PART NUMBER
LOGO
INT ERNATIONAL
RECTIFIER
ASSEMBLY
LOT CODE
916A
IRF U120
34
YEAR 9 = 1999
DAT E CODE
OR
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
Note: "P" in ass embly line position
indicates "L ead-F ree"
12 34
WEEK 16
A = ASSEMBLY SITE CODE
PART NUMBER
IRFU120
LINE A
LOGO
LOT CODE
ASSEMBLY
INT ERNATIONAL
RECTIFIER
IRFR/U2607ZPbF
10 www.irf.com
I-Pak (TO-251AA) Package Outline
I-Pak (TO-251AA) Part Marking Information
ASSEMBLY
EXAMPLE:
WIT H AS S E MB L Y
THIS IS AN IRFU120
YEAR 9 = 1999
DAT E CODE
LINE A
WEEK 19
IN THE ASSEMBLY LINE "A"
AS S E MBL E D ON WW 19, 1999
LOT CODE 5678
PART NUMBER
56
IR F U 120
INTE RNAT IONAL
LOGO
RECTIFIER
LOT CODE
919A
78
Note: "P" in as s embly line
pos ition indi cates "L ead-F ree"
OR
56 78
AS S E MB L Y
LOT CODE
RECTIFIER
LOGO
INTE RNATIONAL
IRF U 120
PART NUMBER
WEEK 19
DAT E CODE
YEAR 9 = 1999
A = ASSEMBLY SITE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
IRFR/U2607ZPbF
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Data and specifications subject to change without notice.
This product has been designed for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.21mH
RG = 25Ω, IAS = 30A, VGS =10V. Part not
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Notes:
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994
Rθ is measured at TJ approximately 90°C
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
TRR TRL
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
