ADSST-VC200 - Analog Devices

Preliminary

VideoCon H.3 2 4

The VideoCon H.324 reference design delivers videophone,

videoconferencing and multim edia capabilities to any Pentium

PC over analog telephone lines. The VideoCon H.324

performs a l l vid eo compression and de comp ression on i t s

included SHARC floating-point digi tal signal processor (DSP)

and all audio compression and decompression on its included

fixed-point D SP. The reference design only us es the Pentium

processor for system control functions.

Highlights

Compliance with H.324 for POTS

Videoconfere n cing

Programmable support fo r MPEG, AC3

and High-E nd Audio for Multimedia

applications

Supports H.223 Data Framing, H.245 End-

to-End Signali n g an d Indi cation/Control

Supports G.723.1 at 6.3/5.3 kbps

Includes 60-400 ms of Acoustic Echo

Cancellation

Supports WindowsTM95 API to enable User

Customization of the Videoconferencin g

Application GUI

The Vid eoCon H. 324 reference design

implements the G.723.1 audio compression/

decompre ssion algorithms on its on-board

ADSP-2181 fixed-point DSP, the H.263 video

compr es s ion/de compression algorithms on its

on-board ADS P -21061 SHARC floating-point

DSP, the V.34 m odem algorithm s on any

external V.34 modem, and the H.223/245 system

control al gorithms on the ho st Pentium

processor.

The reference design includes a board, software

modules and development tools. The board is

plugged into the PCI bus of the Pentium PC .

The VideoCon H.324 – not the processor in the

PC – performs the audio and video compression

and decompression, audio acoustic echo

cancellation, standards-compliant processing of

audio, video, and telephony algorithms and

programmable multim edia support for MPEG,

Dolby AC-3 and high-end audio. The Pentium

process or is used only for sy stem control

functions. The design supports the

WindowsTM95 AP I to enable user cu stomization

of the videoconferencing a pplication Graphica l

User Interface (GUI). The hardware

compon ents consist of Analog Device s’ DSPs

and media codecs for real-time application

implementation.

The VideoCon H.324 design complies with the

H.324 standa rd for POTS videoconferencing

over ana log telephone lines. Th e Vide oCon

H.324 architecture includes a high degree of

hardware and s oftware integratio n to reduce

system cost as well as a reprogrammable media

and communications architecture which can be

upgraded to new er design implementations in the

future.

The ref ere nce design includes a flexi ble set of

softw are modules consisting of standards-

compliant audio, video, telephony and system

control algorithms. The Vide oCon H.324 design

provides advantages that proprietary, ASIC-

based systems cannot match

Controller

Video

Capture

PCI Bridge

Video Codec

ADSP-

21061

1 MB

DRAM

Multimedia

Codec

AD1843

Audio

Codec/AEC

ADSP-2181

SRAM

32K x 48

Preliminary

The H.324 bits tream is tra nsferred to

t h e syst em controller wher e video

and audio data are dem ultiplexed and

tr an s f e rr ed t o th e r esp ectiv e

decoders. The video bits tre am is

decoded by t he ADSP-21061 and

passed in 4:2:0 format to the host

using DMA channel 6. YUV to

RGB format conversion is performed

either by the host or by the graphics

con troller. Data to and fr om the

reconstructed fra m e buffer is

transferred in and out of the internal

memory using DMA channel 9.

The ADSP-2181 implements the

audio c odec and acoustic echo

cancella tion. Speech signals are

digitiz ed by the AD1843 and

transferred to the ADSP-2181 e cho

cancellation module with a

capab ility to cancel 60 to 400 ms of

acoustic echo. The data is then

encoded, lip synchronized with video

and transferred to the system

con troller for mu ltiplexing with

video data. Demultiplexed audio is

transferred to the ADSP-2181 to be

decoded. Decoded data is lip

synchronized with video and played

back through the ADSP-1843.

Communication between the ADSP-

21061 and AD2181 is through the

IDMA port of the ADSP-2181.

ADSP-21061

Analog Devices’

VideoCon H.324

reference design is a

hardware/software

upgradable board fo r

videoconferencing

a n d mult imed i a

applications. It is

based on the ADSP-

21061 to implement

the video

co dec/sy stem co nt rol

and ADSP-2181 to

implement audio

co de c/ aco us ti c ec h o

cancellation.

The incom i ng

composite or S-VHS

c am e r a sig na l is

converted to 4:2:2

YUV format by the

frame grabber. Whe n

the ADSP-21061 is

ready to e ncode the

next frame, it sets up

DMA channel 7 to

t ran sfer data, eithe r in

QCIF (176x1 44) or

CIF (352x 288 pixels)

format from the frame

grabber into the

DRAM. The ADSP-

21061 receives an

interrupt at the end of

the fra m e tr an sf er .

Frame data is

tr ansf e rr ed on a

macroblock by

macroblock bas is

using DMA channel 9

from DRAM to

in ternal SRAM of the

ADSP-21061 for

motion estimation and

encoding.

Th e enco ded bitstream

is then multiplexed

with G.723.1 audio

bitsteam by the system

controller. H.223 data

framing, H.245 end-to-

e n d s ig nal in g and

co nt rol are al l

performed by the

system controller.

Video, audio and

system controller data

are the n se nt through

the modem

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PCI BUS

Windows Device

Driver/API

H.233 / H.245

Videophone

Application

Display Driver

Multimedia

Codec

AD1843

Audio I/O

Interface

H.263

Video Decoder

H.263

Video E ncoder

DMA

Interface

Module

DMA

Boot Control

Diags and

Kernel Routines

DMA

DRAM

Video Input

COMM Driver

Audio Codec

G.723

ADSP-21061

ADSP-2181

DMA

PRODUCT DESCRIPTION

Preliminary

HARDWARE SPECIFICA TIONS

Proc es sing Engines

ADSP-21061 @ 40 MHz for Video

Codec

ADSP-2181 @ 33 MHz for Audio

Codec & Acoustic Echo Cancellation

Pentium @60 MHz (minimum) for

System Control

Ext e rna l Mem o ry

256 k x 16 x 2-60 ns DRAM

4 Cycl es P age Miss

2 Cycl es P age Hit

Refresh: CAS before RAS

4 Cycles @12.5 µ s

ADSP-2181 Interface

16-Bit IDMA Port Access

Core Access o r DMA Acc ess

2 Cycle In dex Addre ss Write

2 Cycle Data Read/Wr ite

Synchronous Serial Interface

SPORT 1 (ADSP-218 1) to

SPORT 1 (ADSP-21061)

Hands hake Interrupts

ADSP-21061 to ADSP-2181

INTERRUPT

ADSP-2181 to ADSP-21061

INTERRUPT

FUN CTION AL SPECI FI CATIO NS

System Control

H.223 for Framing, Multiplex,

Error Cont rol

H.245 for End to End Signaling,

Capability Exchange

Video Codec

H.263

Source Format: SQCIF, QCIF, CIF

Motion Estimation

Half-Pixel Interpolation

PB Frames

Optiona l Error C orrection

Audio Codec

Narrow Band (8 KHz Sampling):

G.723.1 @ 5.3/6.3 Kbps

Dynamic Mo de Switching

Symmetrical and Asymmetrical

Audio Modes

Acousti c Echo Cancel lation

60-400 ms depe nding on Audio mode

Network Interface

28.8 Kbps (V.34)

Application Areas

Videoconferencing,

Security/Surveillance,

Distance learning, Video mail,

Set-Top Boxes, Tel emedicine

VIDEOCON H.324 SPECIFICATIONS

Audio I/O

Controll er: AD1843 SoundCom m

Inputs: Microphone - 1 Channel for

Dynamic or Condenser

Microphone

Outputs:

Speaker - 1 W @ 8 Ohms

Modem Support V.32 bis,

Sampling Rates: 4 kH z to 54 kHz

Gain: Programmable

Attenuation: Programmable

Mute: Programmable

Fil ters: On-Chip Digi tal

Interpolation Decimation and O/P

Low-Pas s Filter 3 On-Chip P LL’s

Host Interfa ce : TDM Serial Master

Mode to SPORT of ADSP-2181

Video Digitization

Digitizer: Bt 819

In pu t: PAL/NT SC Co mp osit e

Video 1

RCA Phono Input

Scaling - Horizontal: 6 TAP

Interpolation

Scaling - Vertical: 2 TAP

Interpolation

Picture Control: Programmable

Brightness, Contrast, Hue,

Saturation, Luma Decimation

Filter

Co n t r o l Inter face: I2C

Interrup t Generat ion: Frame Store

For More Information …

Analog D evices, Inc.

Soft ware & Systems Tech nology Division

USA

Phon e: 617-461-3060

Fax: 617-461-4 291

Email: systems.so luti ons@analog.com

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