Total-AceXtremeTM Ultra-Small, Ultra-Low Power MIL-STD-1553 Single Package Solution Model: BU-67301B Data Sheet World's smallest, ultra low power, fully integrated MIL-STD-1553 BGA package, complete with 1553 protocol, 2 Mb (64K x 36) RAM, transceivers, and isolation transformers inside a single package -- saves board space and simplifies 1553 design and layout. Available with development kit to ease integration. Features * Small, Fully Integrated 1553 Terminal with Transformers Inside: -- 16 x 16 x 4.7 mm (0.63 x 0.63 x 0.185 in.) -- Protocol, RAM, Transceivers and Transformers in a Single Package -- 324 Ball JEDEC Design Guide 4.5 Standard Size Fine Pitch Ball Grid Array with 0.8 mm Ball Pitch * Ultra Low Transceiver Power * Comprehensive Built-in Self Test * Versatile User Selectable High-Speed Backend for PCI or CPU Interface -- Access Time as low as 12.5ns -- DMA Engine with 264MB/sec Burst Transfer Rate * 1 Dual Redundant MIL-STD-1553 Channel -- BC or Multi-RT with Concurrent Bus Monitor -- Supports MIL-STD-1553 A/B and MIL-STD-1760 -- 2 Mb (64K x 36) RAM -- Tx Inhibit Ball for MT Only Applications -- BC Disable Ball for RT Only Applications -- 48-bit/100ns Time Stamp -- IRIG-106 Chapter 10 MT Support * * * * Supports JTAG Boundary Scan IRIG-B Input 8 Digital Discrete I/O Hardware/Software Development Kit with PCI Evaluation Board and Reference Design Artifacts For more information: www.ddc-web.com/BU-67301B (c) 2011 Data Device Corporation. All trademarks are the property of their respective owners. DDC's Data Networking Solutions MIL-STD-1553 | ARINC 429 | Fibre Channel As the leading global supplier of data bus components, cards, and software solutions for the military, commercial, and aerospace markets, DDC's data bus networking solutions encompass the full range of data interface protocols from MIL-STD-1553 and ARINC 429 to USB, and Fibre Channel, for applications utilizing a spectrum of form-factors including PMC, PCI, Compact PCI, PC/104, ISA, and VME/VXI. DDC has developed its line of high-speed Fibre Channel and Extended 1553 products to support the real-time processing of field-critical data networking netween sensors, compute notes, data storage displays, and weapons for air, sea, and ground military vehicles. Whether employed in increased bandwidth, high-speed serial communications, or traditional avionics and ground support applications, DDC's data solutions fufill the expanse of military requirements including reliability, determinism, low CPU utilization, real-time performance, and ruggedness within harsh environments. Out use of in-house intellectual property ensures superior mutli-generational support, independent of the life cycles of commercial devices. Moreover, we maintain software compatibility between product generations to protect our customers' investments in software development, system testing, and end-product qualification. MIL-STD-1553 DDC provides an assortment of quality MIL-STD-1553 commercial, military, and COTS grade cards and components to meet your data conversion and data interface needs. DDC supplies MIL-STD-1553 board level products in a variety of form factors including AMC, USB, PCI, cPCI, PCI-104, PCMCIA, PMC, PC/104, PC/104Plus, VME/VXI, and ISAbus cards. Our 1553 data bus board solutions are integral elements of military, aerospace, and industrial applications. Our extensive line of military and space grade components provide MIL-STD-1553 interface solutions for microprocessors, PCI buses, and simple systems. Our 1553 data bus solutions are designed into a global network of aircraft, helicopter, and missle programs. ARINC 429 DDC also has a wide assortment of quality ARINC-429 commercial, military, and COTS grade cards and components, which will meet your data conversion and data interface needs. DDC supplies ARINC-429 board level products in a variety of form factors including AMC, USB, PCI, PMC, PCI-104, PC/104 Plus, and PCMCIA boards. DDC's ARINC 429 components ensure the accurate and reliable transfer of flight-critical data. Our 429 interfaces support data bus development, validation, and the transfer of flight-critical data aboard commercial aerospace platforms. Fibre Channel DDC has developed its line of high-speed Fibre Channel network access controllers and switches to support the real-time processing demands of field-critical data networking between sensors, computer nodes, data storage, displays, and weapons, for air, sea, and ground military vehicles. Fibre Channel's architecture is optimized to meet the performance,reliability, and demanding environmental requirements of embedded, real time, military applications, and designed to endure the multi-decade life cycle demands of military/aerospace programs. DATA DEVICE CORPORATION ULTRA-SMALL, ULTRA-LOW POWER MIL-STD-1553 SINGLE PACKAGE SOLUTION BU-67301B DATA SHEET The information provided in this Data Sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise connection therewith. Specifications are subject to change without notice. Please visit our Web site at http://www.ddc-web.com/ for the latest information. All rights reserved. No part of this Data Sheet may be reproduced or transmitted in any form or by any mean, electronic, mechanical photocopying recording, or otherwise, without the prior written permission of Data Device Corporation. 105 Wilbur Place Bohemia, New York 11716-2426 Tel: (631) 567-5600, Fax: (631) 567-7358 World Wide Web - http://www.ddc-web.com For Technical Support - 1-800-DDC-5757 ext. 7771 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0)89-15 00 12-11, Fax: +49-(0)89-15 00 12-22 Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 Asia - Tel: +65-6489-4801 Data Device Corporation www.ddc-web.com i (c) 2010 Data Device Corp. DS-BU-67301B-E 2/12 RECORD OF CHANGE Revision Date Pages Pre Rev A Sept., 2010 All Preliminary release Rev. A Sept., 2011 All Initial Release Rev. B Rev. C Dec., 2011 Dec., 2011 6, 7, 9, 38, 113, 25-93, 95, 101115 Table 1: removed part numbers from Supply Voltage section, changed Storage Temperature Max. from: +150C to: +125C., added Ramp Rate specs, added Junction Temperature (TJ) Table 7: Changed Tah min from 2ns to 7ns. Table 25: removed redundant B1 listing in NC section. Section 6: changed heading to Host Interface. Added Section 7: Power Inputs Tables 15 - 22: Added Pullup/Pulldown column and values 10, 15, 96-97, 99, 100, 115 Table 1: Eliminated reference to "(Hottest Die)". Figure 5: Eliminated "MT 100 s Timer (16-bit)" block. Added Figure 56, Timing of CLK_IN, Logic_VDDIO, PLL_+1.8V, and Core_+1.8V. Figure 58: Made corrections Figure 59: Made corrections Table 22: Changed second column signal description for nSINGEND(I). Figure 2: Added nPOR and PLL_LOCKED Figures 7-10 and Figures 19-22: Added nPOR, supervisor circuit, and PLL_LOCKED, modifed use of nMSTCLR Figure 48: Added nPOR and PLL_LOCKED Paragraph 7.2: updated power-up sequence, modified Figure 56 Table 15: Added nPOR and PLL_LOCKED Table 18: Modified RST# Table 19: Modified nMSTCLR Table 26: Added nPOR and PLL_LOCKED Figure 61: Added nPOR and PLL_LOCKED Rev. D January, 2012 7, 36-39, 55-58, 89. 96-98, 104, 107-108, 110, 122, 125 Rev. E Feb., 2012 98 Data Device Corporation www.ddc-web.com Description Updated Figure 56 ii DS-BU-67301B-E 2/12 TABLE OF CONTENTS 1 PREFACE............................................................................................................. 1 1.1 Standard Definitions .................................................................................................... 1 1.2 Trademarks ................................................................................................................. 1 1.3 Technical Support ....................................................................................................... 2 2 OVERVIEW .......................................................................................................... 3 2.1 2.2 2.3 2.4 3 MIL-STD-1553 MODES AND ARCHITECTURE ................................................ 14 3.1 3.2 3.3 3.4 4 Bus Controller Mode.................................................................................................. 14 Remote Terminal Operation ...................................................................................... 15 Monitor Mode Operation ............................................................................................ 17 Advanced Data Handler (ADH) ................................................................................. 19 GLOBAL FEATURES ........................................................................................ 21 4.1 4.2 4.3 4.4 4.5 5 Features ...................................................................................................................... 3 Specifications .............................................................................................................. 8 Additional Support Documents .................................................................................. 12 Total-AceXtremeTM Development Kit ......................................................................... 13 Transceivers and Isolation Transformers................................................................... 21 Time Tags ................................................................................................................. 21 Local Timer ............................................................................................................... 21 DMA Controller.......................................................................................................... 22 Digital I/O .................................................................................................................. 23 BUILT-IN TEST .................................................................................................. 24 5.1 Total-AceXtremeTM Self-Test..................................................................................... 24 5.2 JTAG Boundary Scan................................................................................................ 24 6 HOST INTERFACE ............................................................................................ 26 6.1 6.2 6.3 6.4 6.5 7 Host Interface Configuration Options......................................................................... 26 Parallel CPU Interface ............................................................................................... 26 Asynchronous Interface Mode ................................................................................... 34 Synchronous Host Processor Interface ..................................................................... 50 PCI Interface ............................................................................................................. 87 POWER INPUTS ................................................................................................ 96 7.1 Decoupling Capacitors .............................................................................................. 96 7.2 Power Sequencing .................................................................................................... 96 8 MIL-STD-1553 TRANSCEIVER OPTIONS ........................................................ 99 8.1 Using the Internal Transceivers ................................................................................. 99 8.2 Connection to External Transceivers ....................................................................... 100 8.3 Using External Fiber Optic Transceivers ................................................................. 101 Data Device Corporation www.ddc-web.com iii DS-BU-67301B-E 2/12 TABLE OF CONTENTS 9 REGISTER AND MEMORY ADDRESSING ..................................................... 103 9.1 Memory Address Space .......................................................................................... 103 9.2 Register Address Space .......................................................................................... 103 10 TOTAL-ACEXTREMETM SIGNALS .................................................................. 104 10.1 10.2 10.3 10.4 Signal Descriptions and Pinout by Functional Groups ............................................. 104 Host Interface Signals ............................................................................................. 106 Pinout Table ............................................................................................................ 120 Total-AceXtremeTM Pin Diagram ............................................................................. 124 11 MECHANICAL OUTLINE ................................................................................. 125 12 ORDERING INFORMATION ............................................................................ 126 Data Device Corporation www.ddc-web.com iv DS-BU-67301B-E 2/12 LIST OF FIGURES Figure 1. BU-67301B Total-AceXtremeTM .................................................................................6 Figure 2. Total-AceXtremeTM Block Diagram .............................................................................7 Figure 3. Bus Controller Block Diagram ..................................................................................15 Figure 4. Remote Terminal Block Diagram ..............................................................................17 Figure 5. Monitor Block Diagram .............................................................................................18 Figure 6. PCI DMA Block Diagram ..........................................................................................22 Figure 7. 32-bit, Non-Multiplexed Address, Asynchronous Interface .......................................36 Figure 8. 32-bit, Multiplexed Address, Asynchronous Interface ...............................................37 Figure 9. 16-bit, Non-Multiplexed Address, Asynchronous Interface .......................................38 Figure 10. 16-bit, Multiplexed Address, Asynchronous Interface .............................................39 Figure 11. Asynchronous Non-Multiplexed Address 32-bit Read Timing .................................42 Figure 12. Asynchronous Non-Multiplexed Address 32-bit Write Timing .................................43 Figure 13. Asynchronous Non-Multiplexed Address 16-bit Read Timing .................................44 Figure 14. Asynchronous Non-Multiplexed Address 16-bit Write Timing .................................45 Figure 15. Asynchronous Multiplexed Address 32-bit Read Timing ........................................46 Figure 16. Asynchronous Multiplexed Address 32-bit Write Timing.........................................47 Figure 17. Asynchronous Multiplexed Address 16-bit Read Timing ........................................48 Figure 18. Asynchronous Multiplexed Address 16-bit Write Timing.........................................49 Figure 19. 32-bit, Non-Multiplexed Address, Synchronous Interface .......................................55 Figure 20. 32-bit, Multiplexed Address, Synchronous Interface ..............................................56 Figure 21. 16-bit, Non-Multiplexed Address, Synchronous Interface .......................................57 Figure 22. 16-bit, Multiplexed Address, Synchronous Interface ..............................................58 Figure 23. Synchronous, Non-Multiplexed Address.................................................................62 Figure 24. Synchronous, Non-Multiplexed Address.................................................................63 Figure 25. Synchronous, Non-Multiplexed Address.................................................................64 Figure 26. Synchronous, Non-Multiplexed Address 16-bit .......................................................65 Figure 27. Synchronous, Non-Multiplexed Address 16-bit .......................................................66 Figure 28. Synchronous, Non-Multiplexed Address.................................................................67 Figure 29. Synchronous, Non-Multiplexed Address.................................................................68 Figure 30. Synchronous, Multiplexed Address 32-bit ..............................................................69 Figure 31. Synchronous, Multiplexed Address 32-bit ..............................................................70 Figure 32. Synchronous, Multiplexed Address 32-bit Single-Word Write Timing .....................71 Figure 33. Synchronous, Multiplexed Address 16-bit ..............................................................72 Figure 34. Synchronous, Multiplexed Address 16-bit Single-Word Register Read Timing ......73 Figure 35. Synchronous, Multiplexed Address 16-bit Single-Word Memory Write Timing .......74 Figure 36. Synchronous, Multiplexed Address 16-bit Single-Word Register Write Timing ......75 Figure 37. Synchronous, Non-Multiplexed Address, 32-bit ......................................................76 Figure 38. Synchronous, Non-Multiplexed Address.................................................................77 Figure 39. Synchronous, Non-Multiplexed Address 32-bit .......................................................78 Figure 40. Synchronous, Non-Multiplexed Address.................................................................79 Figure 41. Synchronous, Non-Multiplexed Address.................................................................80 Figure 42. Synchronous, Non-Multiplexed Address.................................................................81 Figure 43. Synchronous, Multiplexed Address ........................................................................82 Figure 44. Synchronous, Multiplexed Address ........................................................................83 Figure 45. Synchronous, Multiplexed Address ........................................................................84 Data Device Corporation www.ddc-web.com v DS-BU-67301B-E 2/12 LIST OF FIGURES Figure 46. Synchronous, Multiplexed Address ........................................................................85 Figure 47. Timing for Assertion of CPU_nSTOP .....................................................................86 Figure 48. Interface Between Host PCI Bus and Total-AceXtremeTM ......................................89 Figure 49. PCI Parametric Timing ...........................................................................................92 Figure 50. PCI Slave Burst Write .............................................................................................92 Figure 51. PCI Slave Burst Read.............................................................................................93 Figure 52. PCI DMA Start Delay ..............................................................................................94 Figure 53. PCI DMA Burst Write ..............................................................................................94 Figure 54. PCI DMA Burst Read..............................................................................................95 Figure 55. Recommended +1.8V_PLL Filter Network .............................................................96 Figure 56. Power-Up Initialization Sequence Timing ...............................................................98 Figure 57. Total-AceXtremeTM Internal Transceiver and Isolation Transformer Connection to MIL-STD-1553 Bus ............................................................................................................99 Figure 58. Mandatory Connections for Integrated Transceivers ............................................100 Figure 59. Total-AceXtreme Interface to External McAir Transceiver ....................................101 Figure 60. Total-AceXtremeTM Interface to Fiber Optic Transceivers ....................................102 Figure 61. Total-AceXtremeTM Pin Diagram ..........................................................................124 Figure 62. Total-AceXtremeTM Mechanical Outline Drawing .................................................125 Data Device Corporation www.ddc-web.com vi DS-BU-67301B-E 2/12 LIST OF TABLES Table 1. Total-AceXtremeTM Series Specifications ....................................................................8 Table 2. Supported JTAG Functions .......................................................................................25 Table 3. Total-AceXtremeTM Host Interface Configuration Options .........................................27 Table 4. Summary of the Operation of the nDATA_RDY Output Signal for Synchronous Single-Word Memory and Register Accesses ...................................................................32 Table 5. Asynchronous 16-bit Mode Configuration Options ....................................................35 Table 6. Asynchronous Transfers ............................................................................................40 Table 7. Asynchronous Timing Information .............................................................................40 Table 8. Synchronous 16-bit Mode Configuration Options ......................................................54 Table 9. Single-Word Synchronous Transfers .........................................................................59 Table 10. Synchronous Burst Transfers ..................................................................................59 Table 11. Synchronous Timing Parameters.............................................................................60 Table 12. Total-AceXtremeTM PCI Interface Characteristics ....................................................87 Table 13. PCI Bus Interface Signals ........................................................................................90 Table 14. PCI Timing Information ............................................................................................91 Table 15. Protocol Configuration ...........................................................................................104 Table 16. JTAG Test .............................................................................................................105 Table 17. General Purpose Discrete I/O................................................................................105 Table 18. PCI Signals ............................................................................................................106 Table 19. CPU Data Bus .......................................................................................................108 Table 20. RT Address Signals ...............................................................................................113 Table 21. Miscellaneous Signals ...........................................................................................113 Table 22. Additional Connections & Interface to External Transceiver ..................................116 Table 23. MIL-STD-1553 Interface ........................................................................................118 Table 24. Power and Ground Connections ............................................................................118 Table 25. No User Connections.............................................................................................119 Table 26. Signal Pinout by Ball Location ...............................................................................120 Data Device Corporation www.ddc-web.com vii DS-BU-67301B-E 2/12 1 PREFACE This section will define the acronyms used in the rest of the document. 1.1 1.2 Standard Definitions E2MA Extended Enhanced Mini-ACE(R) EMACE Enhanced Mini-ACE(R) BC MIL-STD-1553 Bus Controller MT MIL-STD-1553 Monitor Terminal RT MIL-STD-1553 Remote Terminal Multi-RT MIL-STD-1553 Multiple Remote Terminals ADH DDC Advanced Data Handler Host Controller connected to the Host Interface PCI Peripheral Component Interconnect Rx Receive by RT Tx Transmit by RT Bcst Broadcast MC Mode Code BIT Built-In Test PCB Printed Circuit Board FGPI Flexible Generic Processor Interface Trademarks All trademarks are the property of their respective owners. Data Device Corporation www.ddc-web.com 1 DS-BU-67301B-E 2/12 PREFACE 1.3 Technical Support In the event that problems arise beyond the scope of this manual, you can contact In the event that problems arise beyond the scope of this manual, you can contact DDC by the following: US Toll Free Technical Support: 1-800-DDC-5757, ext. 7771 Outside of the US Technical Support: 1-631-567-5600, ext. 7771 Fax: 1-631-567-5758, to the attention of DATA BUS Applications DDC Website: www.ddc-web.com/ContactUs/TechSupport.aspx Please note that the latest revisions of Software and Documentation are available for download at DDC's Web Site, www.ddc-web.com. Data Device Corporation www.ddc-web.com 2 DS-BU-67301B-E 2/12 2 OVERVIEW The Total-AceXtremeTM provides a complete, compact solution for providing MILSTD-1553 interfaces for embedded systems. It provides the required isolation transformers, MIL-STD-1553 transceivers, protocol, and 64K x 36 of internal memory within a single BGA device. It is ideal for extended temperature range applications where PCB space is at a premium, due to its very small size of just 16 mm x 16 mm, and its low power dissipation. The Host interface can be configured as either a flexible generic processor interface (FGPI), or as a PCI initiator/target interface. The FGPI allows direct connection with little or no glue logic to a variety of 16-, and 32-bit processors. The PCI interface allows for a direct connection to a 32-bit PCI bus and supports PCI clock speeds up to 66 MHz. The PCI Initiator interface provides DMA, allowing host software to initialize arbitrary sized read or write bursts between the Total-AceXtreme's shared memory and PCI host space. The device provides a dual redundant MIL-STD-1553 channel with very low power, less than 1 W maximum dissipation. It includes an IEEE 1149.1 compliant JTAG test interface to support boundary scan testing of circuit assemblies, a digital IRIG-B input, and 8 digital discrete I/O lines. The IRIG-B input can be used to create a common time tag reference for the 1553 messages. The Total-AceXtreme can be used as a MIL-STD-1553 Bus Controller (BC), single Remote Terminals (RT), multiple (up to 32) Remote Terminals, a Bus Monitor (MT), combined BC/Monitor, or combined single RT/Monitor, or Multi-RT/Monitor. 2.1 Features * Small Integrated BGA with Transformers Inside: - 324 Ball BGA 16 mm x 16 mm x 4.7 mm (0.63 in. x 0.63 in. x 0.185 in.) - Protocol, RAM, Transceivers and Transformers in a single package * Ultra Low Power, under 1 Watt dissipation at 100% duty cycle * Configurable Host Interface - 16-bit and 32-bit Options for Parallel CPU Interface Data Device Corporation www.ddc-web.com Synchronous and Asynchronous Options * Asynchronous Access Time 70 ns to read, 40 ns to write * Synchronous Access Time for first word as low as 125 ns to read, 50 ns to write * Synchronous Word Bursts at Host Clock Rate, up to 80 MHz 3 DS-BU-67301B-E 2/12 OVERVIEW - * * * * * 32-bit PCI Target/Initiator Interface Operates at up to 66 MHz Target single-word reads as low as 125 ns for reads, and 60 ns for writes Target Word Bursts at PCI Clock Rate PCI Initiator with built-in DMA Engine with 264MB/sec Burst Transfer Rate for reduced host resources. 1 Dual Redundant MIL-STD-1553 Channel - BC or Multi-RT with Concurrent Bus Monitor - Support of MIL-STD-1553 A/B, STANAG-3838, and MIL-STD-1760 - 2 Mb (64K x 36) RAM - Transmit Inhibit Ball for Monitor-only Applications - BC Disable Ball for RT-only Applications - 48-bit/100ns Time Stamp - IRIG-106 Chapter 10 Monitor 1553 Bus Controller (BC) - Highly Autonomous Controller, with 32-Instruction Set - Streaming and Minor/Major Frame Scheduling of Messages - High and Low Priority Asynchronous Message Insertion - Modify Messages or Data while BC is running 1553 Remote Terminal (RT) - Emulate up to 31 RT Addresses Simultaneously - Multiple Buffering Techniques - Programmable Command Illegalization - Programmable Busy by Sub-address - RT Auto-Boot Option for MIL-STD-1760 1553 Bus Monitor (MT) - IRIG-106 Chapter 10 Compatibility - Filter Based on RT Address, T/R bit, Sub-Address - Advanced Bit Level Error Detection to Isolate Bus Failures Advanced Data Handler (ADH) - For BC, RT, and Multi-RT modes, Option to Combine Control/Status and Data Structures into Consolidated Structures for each Message. Data Device Corporation www.ddc-web.com 4 DS-BU-67301B-E 2/12 OVERVIEW * Options for Transferring based on transmit and/or received messages. Transfer control/status structures and/or data words. For RT, can Filter based on RT Address/T-R bit/Subaddress. Filter on Valid and/or Invalid Messages. Host Interrupts Based on Time, Number of Messages, or Number of Words. Can work in Conjunction with DMA Controller and PCI Initiator Interface. Autonomous Built-In Self-Test - Host Initiated Protocol & RAM Self-Test - Automatic Power On Self-Test - Online Loopback Test - Capability for Channel A-to-B Wraparound Test - Capability to Test Transmitter Timeout Function * Provides JTAG Boundary Scan * IRIG-B Input * 8 Digital Discrete I/O * High-Level C Software Development Kits with Drivers for Windows(R), Linux(R), and VxWorks(R) * Optional Hardware/Software Development Kit with PCI Evaluation Board and Design Artifacts (see section 2.4) - PCI Evaluation Board with Cable - 1 Total-AceXtremeTM Component - BusTrACErTM with Application Code Generation for Software Development - Drivers for Windows(R), Linux(R), and VxWorks(R) - Thermal Model, IBIS Model and Schematic Symbols - PCI Card Reference Design Schematic * Extended Industrial Temperature Range, -40C to +100C * Thermal Balls for Improved Heatsinking * Leaded and RoHS Versions Available Total-AceXtreme Architectural Reference Guide. This document, which DDC can provide under an NDA, includes detailed information about the Total-AceXtreme architecture. This includes register bit maps and definitions, and detailed information about the AceXtreme's data structures and operations for BC, Multi-RT, and Monitor modes. Data Device Corporation www.ddc-web.com 5 DS-BU-67301B-E 2/12 OVERVIEW Figure 1. BU-67301B Total-AceXtremeTM Data Device Corporation www.ddc-web.com 6 DS-BU-67301B-E 2/12 OVERVIEW Figure 2. Total-AceXtremeTM Block Diagram Data Device Corporation www.ddc-web.com 7 DS-BU-67301B-E 2/12 OVERVIEW 2.2 Specifications Table 1. Total-AceXtremeTM Series Specifications PARAMETER MIN TYP MAX UNITS Logic +3.3V (VDDIO) -0.3 -- 4.0 V Core +1.8V -0.3 -- 2.0 V PLL +1.8V -0.3 -- 2.0 V -0.3 -0.3 -- -- 4.5 VDDIO +0.3, or 4.0 (which ever is less) V V -0.3 -- VDDIO +0.3, or 4.0 (which ever is less) V ABSOLUTE MAXIMUM RATINGS Supply Voltage (Note 11) * Transceivers +3.3V (during transmit) * DC Input or Output Logic Voltage Logic 3.3V Logic Input or Output Range RECEIVER Differential Input Impedance (Notes 1 - 6) * +3.3V Transformer Coupled 1.0 Input Voltage Range Threshold Voltage (Transformer Coupled) 0.86 0.200 K 14.0 0.860 VPK-PK VPK-PK 10 Vpeak 27 VPK-PK 14 mVRMS 250 mVPK 300 ns 0.5*VDDIO VDDIO + 0.3 V 2.0 VDDIO + 0.3 V All signals except for HOST_CLK/PCI_CLK and CLK_IN -0.3 0.3*VDDIO V CLK_IN -0.3 0.8 V -- Common Mode Voltage TRANSMITTER Differential Output Voltage Transformer Coupled Across 70 , Measured on Bus (Note 9) 20 21.5 Output Noise, Differential Output Offset Voltage, Transformer Coupled Across 70 -250 Rise/Fall Time 100 150 LOGIC VIH All signals except for CLK/PCI_CLK and CLK_IN HOST_CLK/PCI_CLK and CLK_IN VIL Data Device Corporation www.ddc-web.com 8 DS-BU-67301B-E 2/122 OVERVIEW Table 1. Total-AceXtremeTM Series Specifications PARAMETER MIN TYP MAX UNITS 0.4 0.7 V IIH (Vcc = TBDV, VIN = TBDV) -10 +10 A IIL (Vcc = TBDV, VIN = TBDV) -10 +10 A IIH 37 114 A IIL 38 97 A LOGIC (Con't) Schmidt Hysteresis HOST_CLK/PCI_CLK and CLK_IN IIH, IIL All signals except CLK_IN CLK_IN VOH (Vcc = TBDV, VIH = TBDV, VIL = TBDV, IOH = max) 0.9*VDDIO V VOL (Vcc = TBDV, VIH = TBDV, VIL = 0.2V, IOH = max) 0.1*VDDIO IOL (Vcc = TBDV) 500 A mA IOH (Vcc = TBDV) CI (Input Capacitance) All signals except for HOST_CLK/PCI_CLK, CLK_IN, and IDSEL CCLK (HOST_CLK and CLK_IN pin capacitance) Pin inductance V 5 -1.5 mA mA 10 pF 12 20 pF nH 10 pF 12 pF 20 pF PCI LOGIC (see PCI spec 3.3V signaling environment) CI (Input Capacitance) all PCI except PCI_CLK/HOST_CLK & IDSEL CI (Input Capacitance) PCI_CLK/HOST_CLK 5 CI (Input Capacitance) IDSEL POWER SUPPLY REQUIREMENTS Voltages/Tolerances * Logic +3.3V (VDDIO) * Logic +3.3V (VDDIO) Ramp Rate 3.0 3.3 3.6 1.85 V V/s * Core and PLL +1.8V (VCORE and VPLL) * Core and PLL +1.8V (VCORE and VPLL) Ramp Rate 1.65 1.8 1.95 1.85 V V/s * Transceivers +3.3V 3.135 3.3 3.465 V 3.3V (I/O and transceiver) (Note 10): * Idle -- -- 40 mA * 25% Duty Transmitter Cycle -- -- 214 mA * 50% Duty Transmitter Cycle -- -- 344 mA -- -- -- -- 624 160 mA mA Current Drain (Total Hybrid) (Note 10) * 100% Duty Transmitter Cycle 1.8V (logic core) (Note 10) Data Device Corporation www.ddc-web.com 9 DS-BU-67301B-E 2/12 OVERVIEW Table 1. Total-AceXtremeTM Series Specifications PARAMETER MIN TYP MAX UNITS * Idle -- -- 0.42 W * 25% Duty Transmitter Cycle -- -- 0.58 W * 50% Duty Transmitter Cycle -- -- 0.70 W * 100% Duty Transmitter Cycle -- -- 0.90 W * Idle -- -- 0.09 W * 25% Duty Transmitter Cycle -- -- 0.23 W * 50% Duty Transmitter Cycle -- -- 0.33 W * 100% Duty Transmitter Cycle -- -- 0.50 W PCI CLOCK INPUT FREQUENCY 0 -- 66 MHz HOST_CLK (CPU) CLOCK INPUT FREQUENCY 0 -- 80 MHz -- 40 -- MHz * 1553A Compliance 0.01 -- -0.01 % * 1553B Compliance 0.10 -- -0.10 % * 1553A Compliance -0.001 0.001 % * 1553B Compliance -0.01 -- -- -- -- 0.001 % 60 % 100 Ps POWER DISSIPATION: TOTAL HYBRID (Note 10) POWER DISSIPATION: TRANSCEIVER CHIP (Note 10) CLOCK INPUTS CLOCK_IN (MIL-STD-1553) FREQUENCY * Nominal Value Long Term Tolerance Short Term Tolerance, 1 second Duty Cycle 40 Jitter Tolerance -- 1553 MESSAGE TIMING BC Intermessage Gap (Note 7) BC/RT/MT No-Response Timeout - mid-parity-to-mid-sync programmable range (Note 8) RT Response Time (mid-parity to mid-sync) 10 4 Transmitter Watchdog Timeout -- 4 s 511.5 s -- 7 s 660.5 -- s 150 C -- C/W THERMAL TOTAL-ACEXTREME BGA 324-BALL BGA PACKAGE (See Thermal Management Section) Active Transceiver * Junction Temperature (TJ) * Junction-to-Ambient (JA via simulation) - Per JESD 51-2 standard at 25C JA in Still Air Data Device Corporation www.ddc-web.com -- 10 68.8 DS-BU-67301B-E 2/12 OVERVIEW Table 1. Total-AceXtremeTM Series Specifications PARAMETER MIN TYP MAX UNITS JA @ 1M/S -- 52.9 -- C/W JA @ 2M/S -- 47.1 -- C/W JA @ 3M/S -- 43.6 -- C/W -- 24.5 -- C/W -- 46.9 -- C/W -40 -- +100 C -65 -- +125 C THERMAL (Con't) - Per JESD 51-6 standard at 25C * Junction-to-case (JC via simulation) - Per JESD 51-12 standard at 25C JC * Junction-to-board (JB via simulation) - Per JESD 51-8 JB ALL PACKAGES Operating Case Temperature - EXX Storage Temperature SOLDERING 324-BALL BGA PACKAGE The reflow profile detailed in IPC/JEDEC J-STD-020 is applicable for both the leaded and lead-free versions of TotalAceXtreme. PHYSICAL CHARACTERISTICS Package Body Size 324-ball BGA * BU-67301B0TXL-E02 0.630 x 0.630 x 0.185 in (16 x 16 x 4.7) (mm) PHYSICAL CHARACTERISTICS (con't) Moisture and ESD Sensitivity * Moisture Sensitivity Level MSL-3 * Electrostatic Discharge Sensitivity ESD Class 0 Weight 324-ball BGA Data Device Corporation www.ddc-web.com 11 0.105 oz (3) (g) DS-BU-67301B-E 2/12 OVERVIEW Table 1. Total-AceXtremeTM Series Specifications PARAMETER MIN TYP MAX UNITS Notes: Notes 1 through 6 are applicable to the Receiver Differential Input Impedance specifications: 1. Specifications include contributions from the transformer, transmitter, and receiver. 2. Impedance parameters are specified directly between pins CHA(B)_1553 and CHA(B)_1553_L of the TotalAceXtreme hybrid. 3. It is assumed that all power and ground inputs to the package are connected. 4. The specifications are applicable for both unpowered and powered conditions. 5. The specifications assume a 2 volt rms balanced, differential, sinusoidal input. The applicable frequency range is 75 KHz to 1 MHz. 6. Minimum resistance and maximum capacitance parameters are guaranteed over the operating range, but are not tested. 7. Typical value for minimum Intermessage gap time. Under software control, this may be lengthened (to 65,535 s message time) in increments of 1 s. 8. In 0.5 S increments with a resolution of 12 S.9. Measured from mid-parity crossing of Command Word to midsync crossing of RT's Status Word. 9. MIL-STD-1760 requires a 20 VPK-PK minimum output on the stub connection. 10. Power supply currents and power dissipation assume nominal supply voltages, 1.8V and 3.3V. Power Dissipation is the input power consumption minus the power delivered to the 1553 fault isolation resistors, bus termination resistors, and the copper losses in the bus coupling transformer. This power is assumed to be approximately 1.5 Watts when the Total-AceXtreme is transmitting. 2.3 Additional Support Documents This data sheet has been written to address the implementation of the TotalAceXtreme device on a PC board and specify the device operational and functional modes. Additional information about MIL-STD-1553, the MIL-STD-1553 core (AceXtreme), and/or internal register/memory information is available, including the following: * The DDC MIL-STD-1553 Designer's Guide * MIL-STD-1553B Specification * MIL-STD-1553 Handbook * IRIG 106 Chapter 10 Specification * DDC BGA User's Guide * BU-69092SX AceXtreme C SDK Software Reference Manual * BU-69092SX AceXtreme C SDK Software User's Manual * Total-AceXtremeTM IBIS Model * Total-AceXtreme JTAG/BSDL File * Total-AceXtreme OrCad Schematic Symbol * Total-AceXtreme CAD Drawing/Layout Footprint for PADS * Total-AceXtreme CAD Drawing/Layout Footprint for Allegro * MTBF Prediction Report Data Device Corporation www.ddc-web.com 12 DS-BU-67301B-E 2/12 OVERVIEW 2.4 * BC Validation Test Report * RT Validation Test Report * AceXtreme Architectural Manual (Contact Factory) Total-AceXtremeTM Development Kit DDC offers a Development Kit for the BU-67301 Total-AceXtreme component. This kit contains a PCI Evaluation Card to allow easy integration of the BU-67301 component into a standard desktop personal computer. The Evaluation Card brings the various configuration, control, and other I/O signals of the Total-AceXtreme to switches, headers, and LEDs, as appropriate to allow the user to experiment with the various features that the component offers. The Development Kit also includes various reference data to aid in designing systems around the Total-AceXtreme component. Contents: * Total-AceXtreme PCI evaluation card. * BU-69092S Software Development Kit (SDK) * BU-69066S0 BusTrACEr Software * Searchable PDF Schematic Reference and Layout Information * FloTherm Thermal Model * IBIS Model * JTAG/BSDL File * OrCad Schematic Symbol * CAD Drawing/Layout Footprint for PADS * CAD Drawing/Layout Footprint for Allegro * MTBF Prediction Report * BC Validation Test Report * RT Validation Test Report * Product Brief * Data Sheet * SDK Usage Document * SDK Manual * Evaluation Card Quick Start Guide * Evaluation Card Hardware Manual Data Device Corporation www.ddc-web.com 13 DS-BU-67301B-E 2/12 3 MIL-STD-1553 MODES AND ARCHITECTURE 3.1 Bus Controller Mode The Total-AceXtreme's MIL-STD-1553 Bus Controller (BC) is based on the 32-bit architecture of DDC's AceXtreme 1553 Bus Controller. Total-AceXtreme's BC architecture retains much of the previous generation (Enhanced Mini-ACE, Mini-ACE Mark 3, Micro-ACE (TE), and Total-ACE) 1553 Bus Controller architecture. However, it expands upon it in specific areas to provide improved capabilities. The top-level BC design, shown in Figure 3, includes the Command Interpreter, Low and High Priority Queues (LPQ and HPQ respectively), 1553 Protocol engine, and General Purpose Queue (GPQ). The Total-AceXtremeTM BC architecture is based on a built-in command interpreter with a set of 32 instructions. The command interpreter is a message sequence control engine that provides a high degree of flexibility for implementing 1553 Message lists, including major and minor frame scheduling. It separates 1553 message data from control/status data for the purposes of implementing different data block handling schemes, performing bulk data transfers, and implementing automatic message retries. It also includes the capability for automatic bus switchover for failed messages and reporting of various error and status conditions to the host processor by means of five user-defined interrupts and a general-purpose queue. Two Asynchronous queues are also included, to improve the Bus Controller's efficiency and flexibility. The High Priority Queue (HPQ) enables the user to easily insert asynchronous messages into a running Message list, causing it to operate on the new message immediately. The Low Priority Queue (LPQ) enables the user to insert asynchronous messages which will only be processed when there's sufficient "dead-time" available on the bus at the end of a minor frame. The Total-AceXtreme's BC Engine implements all MIL-STD-1553B message formats. Message format is programmable on a message-by-message basis. Automatic retries and interrupt requests may be enabled or disabled for each individual messages. The BC performs all error checking required by MIL-STD1553B. This includes validation of response time, sync type and sync encoding, Manchester II encoding, parity, bit count, word count, Status Word RT Address field, and various RT-to-RT transfer errors. The BC No-Response timeout value is also programmable to enable operation over long buses or through repeaters. Data Device Corporation www.ddc-web.com 14 DS-BU-67301B-E 2/122 MIL-STD-1553 MODES AND ARCHITECTURE BC Block LP Queue Controller REG Interface 1553_IN_A 1553_IN_B BC Registers HP Queue Controller 1553 BC Protocol Engine 1553_OUT_A General Purpose Flags (GPF) LPQ 1553_OUT_B HPQ EXT_TRIG Delay Timer (16 bits) 1us GPQ Controller MB/DB Command Interpreter GPQ ICL Message Timer (16 bits) 1us MEM Interface Memory Bus (32-Bit) Instruction List (ICL) General Purpose Queue (GPQ) HP Queue (HPQ) LP Queue (LPQ) Message Blocks (MB) Data Blocks (DB) Shared RAM (Applicable Logical Areas Highlighted) Figure 3. Bus Controller Block Diagram 3.2 Remote Terminal Operation The Total-AceXtremeTM RT architecture builds upon the single-RT architecture of Enhanced Mini-ACE, Mini-ACE Mark 3, Micro-ACE(TE), and Total-ACE. One of the major new features of Total-AceXtreme is its Multi-RT capability. That is, the Total-AceXtreme provides the capability to implement up to 31 independent Remote Terminals (up to 32 RTs if Broadcast is disabled). The Total-AceXtreme -RT engine can also be configured to operate in a Single-RT legacy mode of operation. Single-RT operation supports hardware control of the RT address and automatic boot, allowing the Total-AceXtreme to respond to commands with Status with its Busy bit set immediately following power turn-on without requiring configuration by the host. For RT (and/or Monitor) applications, where the possibility of BC operation must be absolutely prohibited, the Total-AceXtreme includes a DISABLE_BC input signal. In Data Device Corporation www.ddc-web.com 15 DS-BU-67301B-E 2/12 MIL-STD-1553 MODES AND ARCHITECTURE addition to single-RT and Multi-RT operation, the Total-AceXtremeTM includes the following capabilities: * Meets MIL-STD-1553A, MIL-STD-1553B, MIL-STD-1760, and STANAG 3838 standards. * Multiple Data Handling Modes: - Single Buffer Mode - Double Buffer Mode - Circular Buffer Mode - Global Circular Buffer * Command Illegalization by Subaddress/Word Count, and Mode Codes * Programmable Busy by Subaddress * Flexible Interrupt Conditions, Including 50% and 100% Rollover Interrupts for Circular Buffers * Interrupt Status Queue with Programmable Filtering * Time Tagging Options for Synchronize Mode Codes * Option for RT Auto-Boot with Busy bit Set Data Device Corporation www.ddc-web.com 16 DS-BU-67301B-E 2/12 MIL-STD-1553 MODES AND ARCHITECTURE RT Block 1553_IN_A REG Interface 1553_IN_B RT Registers 1553 RT Protocol Engine RT Message Interpreter 1553_OUT_A 1553_OUT_B nEXT_SSF EXT_SRT RTBOOT EXT_RTA (4:0, P) DB GCD ISQ nMCRST / nINCMD MDS MRT RT_AD_LAT MEM Interface Memory Bus (32-Bit) Multi-RT Configuration Slots (MCS) Message Descriptor Stack (MDS) Global Circular DB (GCD) Data Blocks (DB) Interrupt Status Queue (ISQ Shared RAM (Applicable Logical Areas Highlighted) Figure 4. Remote Terminal Block Diagram 3.3 Monitor Mode Operation The Total-AceXtremeTM Monitor engine provides the next generation DDC MIL-STD1553 Monitor (MT) architecture. This new Monitor autonomously stores individual messages into a contiguous memory stack formatted as IRIG 106 Chapter 10 Data Packets. The legacy Monitor modes of operation traditionally implemented in previous generations of DDC MIL-STD-1553 engines can be emulated easily through host software. All information and functionality supported on the legacy Monitor engines is supported on the AceXtreme Monitor engine, or may be extracted from the stored messages. IRIG 106 Chapter 10 provides interoperability for such applications as test range telemetry, flight test instrumentation, mission recorders, video/data servers; surveillance and reconnaissance; health and usage monitoring; mission planning, Data Device Corporation www.ddc-web.com 17 DS-BU-67301B-E 2/12 MIL-STD-1553 MODES AND ARCHITECTURE debriefing, and training; and flight operations. IRIG 106 Chapter 10 defines a standardized file format, and within that specific representations for several types of flight data, including MIL-STD-1553 buses, PCM, analog, computer-generated data, images, discretes, UARTs, IEEE 1394, parallel, IRIG time, video, and voice. In addition, Chapter 106 provides standardization of time bases. For MIL-STD-1553, IRIG 106 Chapter 10 defines packets that can encapsulate one of more 1553 messages. Within these packets, all messages are tagged with either a 48-bit relative or 64-bit absolute time stamp. For each message, there is also a block status word, which includes indications of bus channel and message validity, and identifies specific errors. The 1553 format also defines indications of response time, plus storage of all 1553 Command, Status, and Data Words, in the order received. For supporting IRIG 106 Chapter 10, the Total-AceXtremeTM includes DMA capability, which operates in conjunction with the PCI Initiator interface to transfer monitored data from the 1553 monitor to PCI host space. Figure 5. Monitor Block Diagram Data Device Corporation www.ddc-web.com 18 DS-BU-67301B-E 2/12 MIL-STD-1553 MODES AND ARCHITECTURE 3.4 Advanced Data Handler (ADH) For its BC and RT modes, the Total-AceXtremeTM includes an Advanced Data Handler (ADH) feature. The ADH reduces host overhead for the transferring of message control and status information, and data word structures between the TotalAceXtreme's internal shared memory and CPU or PCI host address space. For each message processed by the Total-AceXtreme's BC, there are separate data structures for the BC instruction list; message control and status information; and transmitted or received data words. Similarly, for each message processed by the Total-AceXtreme's RT (or one of its multiple RTs), there are separate data structures for message status information; and for transmitted or received data. In a typical BC application, the Control/Status blocks and data blocks can be scattered in different areas of Total-AceXtremeTM memory. Similarly, in RT mode, the message status information is stored in entries in the RT's descriptor stack, while data is stored in individual data blocks, in RT/Subaddress-specific circular buffers, or in the global circular buffer. The ADH provides an optional mechanism for moving data from the TotalAceXtreme's native data structures, and a separate area of Total-AceXtreme memory dedicated to the ADH. The ADH offers an number of options, including: * Transferring data words only, or both message control/status and data words. * In the case where both message control/status information and data words are transferred, they will be combined into single, consolidated data structures for each message. This reduces the burden on the host processor from having to parse through multiple data structures for each message processed. * A filter option such that only valid messages are transferred to ADH memory, or for all messages, regardless of validity, to be transferred to ADH memory. * Transferring either received messages only, transmitted messages only, or both. * For RT mode, messages that are transferred into the ADH area of memory can be filtered on a T/R-bit/Subaddress basis. For the case of Multi-RT, messages can be filtered on an RT Address/T/R-bit/Subaddress basis. The ADH offers a number of interrupt options. These include following the transfer of a specified number of message, the transfer of a specified number of words, Data Device Corporation www.ddc-web.com 19 DS-BU-67301B-E 2/12 MIL-STD-1553 MODES AND ARCHITECTURE timeouts, or a software-initiated interrupt. The ADH also provides the host with indications when its command FIFO (list of messages to transfer) is full or empty. Following the issuance of ADH interrupts, the host can then transfer data from its ADH memory to designated areas in host space or PCI space memory. These transfers may be performed over either the parallel CPU or PCI Target interfaces, or by means of the Total-AceXtreme's DMA engine and PCI Initiator interface. Data Device Corporation www.ddc-web.com 20 DS-BU-67301B-E 2/12 4 GLOBAL FEATURES 4.1 Transceivers and Isolation Transformers The transceivers in Total-AceXtremeTM series terminals require only +3.3 power. The transmitter sections satisfy the MIL-STD-1760 requirement for a minimum of 20 volts peak-to-peak, transformer coupled output. The transceivers are very low power, and dissipate less than 0.5 Watts Max when transmitting. The receiver sections of the Total-AceXtreme are fully compliant with MIL-STD1553B Notice 2 in terms of front end overvoltage protection, threshold, commonmode rejection, and word error rate. The Total-AceXtreme integrates two isolation transformers from Beta Transformer Technology Corporation. As an alternative to using the internal transceivers and transformers, it is possible to operate the Total-AceXtreme with external electrical or fiber optic transceivers. For information about this, refer to section 8.3. 4.2 Time Tags In BC, Multi-RT, and MT modes, the Total-AceXtreme stores time tags associated with all processed MIL-STD-1553 messages. The Total-AceXtreme provides two sources for the relative time tags: a local timer with hardware support for the 1553 Synchronize mode codes, along with a digital IRIG-B input. The IRIG-B input supports applications where accurate synchronization with other devices is required. 4.3 Local Timer The Local Timer is a free-running 48-bit binary counter that is maintained locally by the Total-AceXtreme. It can optionally be modified under full host control or be set up to automatically update in response to "Synchronize" and "Synchronize with data" messages received from the 1553 bus. In BC mode, "Synchronize with data" messages can be configured to send the lower 16 bits of the current value of the time tag as the data word. Timer resolution and overflow frequency can also be programmed. Refer to the AceXtreme Architectural Manual for a full description on how to use the Local Timer. 4.3.1 IRIG-B Timer The Total-AceXtreme includes a digital IRIG-B input that can be used to synchronize the time tags used by the 1553 interface with external devices. The IRIG-B input will receive and synchronize to a new time-code once per second. Data Device Corporation www.ddc-web.com 21 DS-BU-67301B-E 2/122 GLOBAL FEATURES 4.4 DMA Controller The Total-AceXtremeTM includes a programmable DMA controller. The DMA controller, which operates in conjunction with the Total-AceXtreme's PCI Initiator interface, can be used to transfer data from the Total-AceXtreme's internal Shared RAM to PCI Host Memory space (Upstream) or from PCI Host Memory to Shared RAM (Downstream). This DMA controller can be configured to transfer the data using two different modes. In both the Block Mode and the Scatter/Gather Mode, DMA transfers are always host-initiated. They are never initiated autonomously by the Total-AceXtreme. These two modes are described below: * Block Mode: Each transfer is initiated by the System Host and is a contiguous block of memory transferred Upstream or Downstream. * Scatter/Gather Mode: The DMA Controller performs a series of independent transfers, which can include a mix of Upstream and Downstream transfers, using a descriptor table created by the host with no further host intervention. Clear Count Mode is an option within Scatter/Gather Mode. When enabled, the Transfer Size field of each descriptor will be cleared after the corresponding transfer has been completed so that the host can check how much of the transfer has been completed while in progress or following an abort or retry timeout. CPU Total-AceXtreme System Memory Controller PCI/DMA Controller PCI Bus Local Bus Shared RAM Upstream Downstream Host Memory Figure 6. PCI DMA Block Diagram Data Device Corporation www.ddc-web.com 22 DS-BU-67301B-E 2/12 GLOBAL FEATURES 4.5 Digital I/O The Total-AceXtremeTM provides 8 user-programmable I/O signals, DISCRETE_IO_7:0. These signals are independently programmable as inputs or outputs and are independently controllable. The direction and state (for outputs) of the Digital I/O signals are controllable by means of the Total-AceXtreme's Digital I/O Register. This register also allows the host processor to poll the values of Digital I/O signals designated as inputs and verify the values of signals designated as outputs. The power-on default state for DISCRETE_IO_7:0 is as input signals. In addition to DISCRETE_IO_7:0, The Total-AceXtreme includes two userprogrammable output-only signals, USER_OUTPUT_2:1. The power-on default state for USER_OUTPUT_2:1 is for logic `0'. Data Device Corporation www.ddc-web.com 23 DS-BU-67301B-E 2/12 5 BUILT-IN TEST 5.1 Total-AceXtremeTM Self-Test The Total-AceXtremeTM provides both on-line and off-line tests that can be used to verify correct operation. On-Line tests include a continuous loopback test which verifies that the waveform that is received from the bus matches what was intended to be transmitted on the bus, as well as verification that received commands and data are correctly formatted. Off-line tests include a modification of the loopback test that disconnects the transmitters and is received internally (before the transceiver) in order to test the BC logic without disrupting the 1553 bus, along with an RT protocol test. There is also a Bus A to Bus B loopback test, which requires that the two buses be connected together externally to verify the entire transmission and reception path, including the transceivers, transformers, and the rest of the signal path. The TotalAceXtreme BC mode also includes a memory self-test. In addition to the self-test features built into the Total-AceXtreme 1553 core, the Total-AceXtreme offers low-level Built-in-Test (BIST) functions that cover the internal memory blocks, 1553 core, and IRIG module. The shared RAM, scratchpad RAM, and microcode ROM can be tested simultaneously or independently, but once a test is started, it must either be allowed to complete or canceled before starting another test. There is also a full internal scan test of the 1553 and IRIG modules which provides 90% coverage against faults. Beyond all of the included hardware test options, the internal registers and shared RAM are fully accessible by the host processor and, therefore, may be tested by software routines that implement checkerboard, walking zero, walking one and counting patterns. 5.2 JTAG Boundary Scan The Total-AceXtreme contains an IEEE 1149.1 compliant JTAG port that supports Boundary Scan for board-level verification of assemblies. When used in a board assembly with other compliant chips, this allows an automatic tester to determine that all signal paths between those chips are bonded correctly with no shorts or opens by running a series of test vectors. All logic input signals can be sampled and all logic outputs can be selectively driven high, low, or tri-stated as desired by shifting the data through the JTAG port. The Data Device Corporation www.ddc-web.com 24 DS-BU-67301B-E 2/122 BUILT-IN TEST ordering of the signals in the scan chain is defined in the BSDL file that is included in the Total-AceXtremeTM Development Kit. Table 2. Supported JTAG Functions JTAG Instruction Instruction Register Value Description BYPASS 0b111 The BYPASS Instruction is used to allow data to connect directly from JTAG_TDI pin to the JTAG_TDO pin. Reserved 0b110 Reserved Reserved 0b101 Reserved USERCODE 0b100 The USERCODE specifies which version of the Total-AceXtreme is present. 0x000000FF denotes the BU-67301B0T0L-E02 Other values are reserved. IDCODE 0b011 The IDCODE for the Total-AceXtreme is 0x0590003F HIGHZ 0b010 Sets all the Outputs and Bidirectional Outputs to a high impedance state. The HIGHZ can be used to determine excessive leakage current during the TotalAceXtreme's manufacturing phase. SAMPLE/PRELOAD 0b001 The SAMPLE function provides the ability to capture the current state of the I/O pins. The Preload allows for JTAG to preload the JTAG cells with values which will not actually be loaded until the appropriate instruction (such as EXTEST) is entered. EXTEST 0b000 The EXTEST Instruction allows for a test vector to be applied from the Boundary Scan Register to the external pins of the Total-AceXtreme. Please contact DDC for further information on using the Boundary Scan feature. Data Device Corporation www.ddc-web.com 25 DS-BU-67301B-E 2/12 6 HOST INTERFACE 6.1 Host Interface Configuration Options The Total-AceXtremeTM device has a highly flexible host interface. At top-level, the Total-AceXtreme provides nine options for its host interface. Overall, the nine options include: 6.2 * Asynchronous 32-bit with separate address and data buses * Asynchronous 32-bit with multiplexed address and data bus * Asynchronous 16-bit with separate address and data buses * Asynchronous 16-bit with multiplexed address and data bus * Synchronous 32-bit with separate address and data buses * Synchronous 32-bit with multiplexed address and data bus * Synchronous 16-bit with separate address and data buses * Synchronous 16-bit with multiplexed address and data bus * 32-bit Target/Initiator PCI interface Parallel CPU Interface The first eight options listed above are the modes for the Total-AceXtreme's parallel CPU interface. As shown, the options for the parallel CPU interface are based on three parameters: Asynchronous vs. Synchronous, 32-bit vs. 16-bit, and nonmulticast vs. multicast address and data buses. In Asynchronous mode, the host processor does not provide a data transfer clock as an input to the Total-AceXtreme. In this mode, all transfer timing is controlled by the Total-AceXtreme's internal 160 MHz clock, which is derived from the TotalAceXtreme's 40 MHz CLK_IN input. In Synchronous mode, the timing of transfers between the host CPU and the Total-AceXtreme is controlled by a clock provided by the host, and connected to the Total-AceXtreme's HOST_CLK input. The TotalAceXtreme can operate with HOST_CLK speeds of up to 80 MHz. In addition for Synchronous mode, certain aspects of the data transfers are controlled by the TotalAceXtreme's internally derived 160 MHz clock. In 32-bit mode, data is transferred over CPU_DATA(31:0). In 16-bit mode, data is transferred over CPU_DATA(15:0), while CPU_DATA(31:16) aren't used. In non-multiplexed mode, the host processor presents its address over the TotalAceXtreme's address bus input, CPU_ADDR(15:0); that is on a separate path from the data, which is transferred over CPU_DATA(31:0) or CPU_DATA(15:0). In Data Device Corporation www.ddc-web.com 26 DS-BU-67301B-E 2/122 HOST INTERFACE multiplexed mode, the host's address is presented over CPU_DATA(15:0), prior to the data phase of the transfer. For applications demanding the fastest data throughput performance, use of either the Synchronous CPU interface or the Total-AceXtreme's PCI interface is recommended. This is because both of these interfaces support burst transfers. Bursting for the Synchronous CPU interface can be for either 32-bit or 16-bit words, at rates up to 80 Mwords/s. 6.2.1 Static Configuration Signals The Total-AceXtremeTM includes four static input signals for establishing the configuration for the host interface: PCI_nCPU, DATA32_n16, CPU_ASYNC_nSYNC, and ADMULTI. The operation of these signals is shown in Table 3. Note that DATA32_n16, CPU_ASYNC_nSYNC, and ADMULTI have no affect on the operation of the Total-AceXtreme's PCI interface. Table 3. Total-AceXtremeTM Host Interface Configuration Options Input Signal Name Operation if Logic `1' Operation if Logic `0' PCI_nCPU 32-bit Target/Initiator PCI Interface Parallel CPU Interface DATA32_n16 32-bit Parallel CPU Interface 16 Bit Parallel CPU Interface CPU_ASYNC_nSYNC Asynchronous Parallel CPU Interface Synchronous Parallel CPU Interface ADMULTI Multiplex Address/Data Mode for Parallel CPU Interface Separate Address and Data Buses for Parallel CPU Interface 6.2.2 Parallel CPU Interface Signals The following input and outputs signals are common to all or most of the parallel CPU interface modes: 6.2.2.1 * I/O Signals CPU_DATA(31:0): Bi-directional 32-bit host bit data bus. In 16-bit mode, only CPU_DATA(15:0) is used, while CPU_DATA(31:16) is not used. The operation of CPU_DATA(31:0) varies as a function of which host CPU interface configuration is used. For the multiplexed address/data modes, the host presents its memory or register address to the Total-AceXtreme on CPU_DATA(15:0) and must assert ADDR_LAT high during this time. Data Device Corporation www.ddc-web.com 27 DS-BU-67301B-E 2/12 HOST INTERFACE For 32-bit mode, individual data transfers may be performed over either CPU_DATA(31:0), CPU_DATA(31:16), or CPU_DATA(15:0). For each transfer, the host must designate whether or not data will be transferred over the upper and/or lower 16 bits. This is done by means of the two CPU_WORD_EN(1:0) inputs to the Total-AceXtremeTM. For read transfers, the Total-AceXtreme indicates when valid data appears on CPU_DATA(31:0) or CPU_DATA(15:0) by asserting its nDATA_RDY output low. For the case of Synchronous burst memory read transfers, the first data word will be driven on to CPU_DATA(31:0) or CPU_DATA(15:0) during the first host clock cycle when nDATA_RDY is initially asserted low. On each successive host clock cycle until the end of the burst transfer, a new data word will be driven on to CPU_DATA(31:0) or CPU_DATA(15:0), while nDATA_RDY remains low. For Asynchronous write transfers, CPU_DATA(31:0), CPU_DATA(31:16), or CPU_DATA(15:0) must be presented valid by the host prior to the falling edge of nDATA_STRB and remain asserted through the full transfer cycle. For single-word Synchronous write transfers, CPU_DATA(31:0), CPU_DATA(31:16), or CPU_DATA(15:0) must be presented valid during the same host clock cycle that nDATA_STRB is asserted low. For Synchronous burst write transfers, the first data word must be presented on CPU_DATA(31:0), CPU_DATA(31:16), or CPU_DATA(15:0) during the same host clock cycle that nDATA_STRB is asserted low (or, for the case of a random write burst, first asserted low). After the Total-AceXtreme asserts its nDATA_RDY output low, the host must present a new data word on CPU_DATA(31:0), CPU_DATA(31:16), or CPU_DATA(15:0) for each successive host clock cycle through the end of the burst transfer. 6.2.2.2 * Input Signals CPU_ADDR(15:0): 16-bit host address bus input. For non-multiplexed Asynchronous transfers, CPU_ADDR(15:0) must be presented valid by the host prior to the falling edge of nSELECT and nDATA_STRB and remain asserted through the full transfer cycle. For non-multiplexed single-word Synchronous transfers, CPU_ADDR(15:0) must first be presented valid during the same host clock cycle that nDATA_STRB is asserted low and remain low through the full transfer cycle. For non-multiplexed sequential Synchronous burst transfers, CPU_ADDR(15:0) must be presented valid during the same host clock cycle when nDATA_STRB is asserted low. Data Device Corporation www.ddc-web.com 28 DS-BU-67301B-E 2/12 HOST INTERFACE For non-multiplexed random Synchronous burst write transfers, the value of the first address to be written must be presented on CPU_ADDR(15:0) during the same host clock cycle that nDATA_STRB is initially asserted low, and driven until nDATA_RDY is asserted low. After the Total-AceXtremeTM asserts its nDATA_RDY output low, the host must then present a new address on CPU_ADDR(15:0) for each successive host clock cycle through the end of the burst transfer. In 16-bit mode, the host address must be driven on to CPU_ADDR(15:0) during both the first and second 16-bit transfers. In the multiplexed address/data mode, CPU_ADDR(15:0) is not used and may be left unconnected. * nSELECT: When asserted low, nSELECT is the "chip select" input to the Total-AceXtreme. nSELECT must remain asserted through the end of each transfer cycle. For Asynchronous mode, if the Total-AceXtreme is the only node on the bus, then nSELECT may be tied to logic `0'. In Synchronous mode, nSELECT must de-assert high and remain high for one host clock cycle to end the current transaction, and prior to re-asserting low to initiate the next transaction. * MEM_nREG: This signal selects between accesses to Total-AceXtreme internal memory (when high) and Total-AceXtreme registers (when low). It must be presented valid during the same time window as CPU_ADDR(15:0). In the multiplexed address/data modes, the value of MEM_nREG is latched when the ADDR_LAT input is asserted high. * nDATA_STRB: This active low input signal is the main control signal for the Total-AceXtreme's CPU interface. Its specific operation varies as a function of Asynchronous vs. Synchronous mode; and for Synchronous mode, for single-word transfers, sequential burst transfers, and random burst write transfers. The TotalAceXtreme does not support Synchronous random burst read transfers. In Asynchronous mode, nDATA_STRB must be asserted low through the full data portion of each 32-bit or 16-bit transfer cycle. In Synchronous mode, Data Device Corporation www.ddc-web.com 29 DS-BU-67301B-E 2/12 HOST INTERFACE nDATA_STRB must be asserted for exactly one host clock cycle for single-word accesses, and to initiate sequential Synchronous burst transfers. For random Synchronous burst write transfers, nDATA_STRB must be asserted low through the entire time of the transfer. * RD_nWR: This signal selects between read and write transfers. In 32-bit mode with POL_SEL = `1', RD_nWR = `0' to read and `1' to write. For all other parallel CPU interface configurations, RD_nWR = `1' to read and `0' to write. * ADDR_LAT: In the Multiplexed mode for the address and data buses (ADMULTI = `1'), the Total-AceXtremeTM will latch the host address from CPU_DATA(15:0), along with MEM_nREG, and (in 16-bit mode only) MSW_nLSW during a positive pulse on the ADDR_LAT input. For Asynchronous mode, ADDR_LAT must be at least 40 ns wide. For Synchronous mode, ADDR_LAT must meet the setup and hold times relative to HOST_CLK. In 16-bit multiplexed mode, ADDR_LAT must pulse high to latch in the address, MEM_nREG, and MSW_nLSW for both the first and second 16-bit word transfers. In the non-Multiplexed mode for the address and data buses (ADMULTI = `0'), ADDR_LAT must be connected to logic `1'. * CPU_nLAST: This input signal is used for Synchronous mode only. For single-word Synchronous transfers, CPU_nLAST must be asserted low through the full transfer cycle. For Synchronous burst transfers, CPU_nLAST must be asserted high until the last 32-bit or 16-bit word is written or read over the CPU data bus. During this last word transfer, CPU_nLAST must be asserted low. CPU_nLAST is not used in the Asynchronous CPU mode and may be left unconnected. * MSW_nLSW: For 16-bit mode, MSW_nLSW is the LSB of the CPU address bus and is used to select between the upper (bits 31:16) and lower (bits 15:0) 16-bit words. The polarity of MSW_nLSW is determined by the value of the POL_SEL static input. In the multiplexed address/data modes, the value of MSW_nLSW is latched when the ADDR_LAT input is asserted high. In 32-bit mode, MSW_nLSW is not used and be left unconnected. * CPU_WORD_EN(1:0): These two signals should be active throughout the entire transfer cycle, and operate as follows: Data Device Corporation www.ddc-web.com 30 DS-BU-67301B-E 2/12 HOST INTERFACE * * In 32-bit mode, CPU_WORD_EN(1) is used to activate memory transfers for data bits 31 through 16, while CPU_WORD_EN(0) is used to activate memory transfers for data bits 15 through 0. In 32-bit mode, these two inputs are used to specify which 16-bit data memory word(s) are valid for a memory transfer. * For a 32-bit memory write transfer, if either or both of the CPU_WORD_EN(1:0) inputs is `0', then the respective 16-bit word(s) will not be written to Total-AceXtremeTM memory. * For a 32-bit memory read transfer, if either or both of the CPU_WORD_EN(1:0) inputs is `0', then the value of the respective 16-bit word(s) returned that will be `0000'. * For all register transfers, the value of CPU_WORD_EN(1:0) must always be `11'. * For 16-bit mode, CPU_WORD_EN(1:0) are not used and must be connected to `11'. * CPU_WORD_EN(1:0) should be tied to `11' if not used. HOST_CLK: For the Synchronous interface mode, HOST_CLK is used for clocking address, data, and control issues, and for generating the nDATA_RDY, nINT, and CPU_nSTOP outputs. The maximum frequency for HOST_CLK is 80 MHz. HOST_CLK is not used in the Asynchronous CPU mode, and may be left unconnected. 6.2.2.3 * Output Signals nDATA_RDY: This active low signal is the main output control signal for the Total-AceXtreme's CPU interface. Its specific operation varies as a function of Asynchronous vs. Synchronous mode. In addition, for Synchronous mode, its function varies as a function of single-word transfers vs. burst transfers. For Asynchronous read transfers, nDATA_RDY asserts low when the TotalAceXtreme drives valid data on to CPU_DATA(31:0) or CPU_DATA(15:0). For Asynchronous write transfers, nDATA_RDY asserts low when the TotalAceXtreme has latched data driven by the host over CPU_DATA(31:0), CPU_DATA(31:16), or CPU_DATA(15:0). In either case, nDATA_RDY will continue to assert low until the host de-asserts nSELECT high. Data Device Corporation www.ddc-web.com 31 DS-BU-67301B-E 2/12 HOST INTERFACE The operation of the nDATA_RDY signal for single-word Synchronous memory and register accesses is summarized in Table 4 and described in the paragraphs that follow. Table 4. Summary of the Operation of the nDATA_RDY Output Signal for Synchronous Single-Word Memory and Register Accesses Transfer Type Operation of nDATA_RDY for Memory Access Operation of nDATA_RDY for Register Access 32-bit Read Asserts low until host clock following nSELECT going high Asserts low for single clock cycle 32-bit Write Asserts low for single clock cycle Asserts low for single clock cycle 16-bit Read: First Word Asserts low until host clock following nSELECT going high Asserts low for single clock cycle 16-bit Read: Second Word Asserts low until host clock following nSELECT going high Asserts low for single clock cycle 16-bit Write: First Word Asserts low for single clock cycle Asserts low until host clock following nSELECT going high. 16-bit Write: Second Word Asserts low for single clock cycle Asserts low for single clock cycle For 32-bit Synchronous single-word memory read accesses, nDATA_RDY asserts low when the Total-AceXtremeTM drives valid data to be read on CPU_DATA(31:0), and de-asserts high on the HOST_CLK rising edge after nSELECT is sampled high. For Synchronous 32-bit single-word memory or register write accesses, nDATA_RDY asserts low for a single host clock cycle when the data from CPU_DATA(31:0) has been internally latched. For Synchronous single-word register read accesses, nDATA_RDY asserts low for a single host clock cycle beginning when the Total-AceXtremeTM drives valid data to be read on CPU_DATA(31:0) for a 32-bit transfer, or CPU_DATA(15:0) for each of the two 16-bit transfers. For each of the two transfers for 16-bit Synchronous single-word memory read accesses, nDATA_RDY asserts low starting when the Total-AceXtremeTM drives valid data to be read on CPU_DATA(15:0) and de-asserts high on the HOST_CLK rising edge after nSELECT is sampled high. For each of the two transfers for 16-bit Synchronous single-word memory write accesses, nDATA_RDY asserts low for a single host clock cycle when the TotalAceXtremeTM internally latches the data transferred over CPU_DATA(15:0). Data Device Corporation www.ddc-web.com 32 DS-BU-67301B-E 2/12 HOST INTERFACE For the first word transfer for 16-bit Synchronous single-word register write accesses, nDATA_RDY will assert low when the Total-AceXtreme internally latches the data transferred over CPU_DATA(15:0) and de-asserts high on the HOST_CLK rising edge after nSELECT is sampled high. For the second word transfer, nDATA_RDY asserts low for a single host clock cycle when the TotalAceXtremeTM internally latches the data transferred over CPU_DATA(15:0). For Synchronous burst memory read transfers, nDATA_RDY is initially asserted low on the same host clock cycle that the Total-AceXtreme drives the first data word on to CPU_DATA(31:0) or CPU_DATA(15:0). For the case of Synchronous burst memory write transfers, nDATA_RDY is initially asserted low on the same host clock cycle that the Total-AceXtreme latches data driven by the host over CPU_DATA(31:0), CPU_DATA(31:16), or CPU_DATA(15:0). In either case, nDATA_RDY will continue to assert low through the end of the host clock cycle for the last word read by the host for a read burst transfer, or latched by the Total-AceXtreme for a write burst transfer. That is, nDATA_RDY will assert low until one host clock cycle after the host CPU has asserted CPU_nLAST low. * nINT: This is the interrupt request output for the Total-AceXtreme's parallel CPU interface. The operation of nINT is software-programmable for active high or active low, two-state or open drain, and level or pulse. For the case of a pulse interrupt, the pulse width is also programmable. The nINT pulse width may be programmed for a value between 3 and 65,537 clock cycles. The clock used for formulating the nINT pulse width will be the Total-AceXtreme's internal 160 MHz clock for the Asynchronous CPU interface mode, and the HOST_CLK input for the Synchronous CPU interface mode. * CPU_nSTOP: In Synchronous mode, this active low signal is used to indicate the occurrence of a "FIFO-full" condition, thereby terminating the current transfer. This condition will only occur following the occurrence of a "full" condition for the TotalAceXtreme's command (input) FIFO. For more information on this operation, refer to paragraph 6.4.2 and Figure 47. CPU_nSTOP will also be asserted low along with nDATA_RDY at the completion of a single-word Synchronous register (but not memory) read transfer. In either case, CPU_nSTOP will remain low until nSELECT is de-asserted high. For all other correctly completed Synchronous transfers, CPU_nSTOP will remain high. In Asynchronous mode, CPU_nSTOP is not used and will remain high. Data Device Corporation www.ddc-web.com 33 DS-BU-67301B-E 2/12 HOST INTERFACE 6.2.3 Additional CPU Interface Configuration Options In addition to the signals listed in Table 3, the Total-AceXtreme includes two additional static configuration signals, POL_SEL and TRIG_SEL. These signals operate differently in Asynchronous and Synchronous modes. In 32-bit mode, POL_SEL is used for selecting the polarity of the RD_nWR input signal, as follows: * If POL_SEL = `0', then RD_nWR = `1' to read and `0' to write. * If POL_SEL = `1', then RD_nWR = `0' to read and `1' to write. In 16-bit mode, POL_SEL indicates which word is the most significant word, as follows: * If POL_SEL is `1' then the value of MSW_nLSW for the least significant word (15:0) is `1', and the value of MSW_nLSW for the most significant word (31:16) is `0'. * If POL_SEL is `0' then the value of MSW_nLSW for the least significant word (15:0) is `0', and the value of MSW_nLSW for the most significant word (31:16) is `1'. In 16-bit Asynchronous mode, TRIG_SEL is used to select which word is transferred first. If TRIG_SEL = `1', then the upper data word (bits 31:16) is transferred first, and the lower data word (bits 15:0) is transferred second. If TRIG_SEL = `0', then the lower data word (bits 15:0) is transferred first, and the upper data word (bits 31:16) is transferred second. In 32-bit mode and Synchronous 16-bit mode, TRIG_SEL is not used and must be connected to logic `1'. 6.3 Asynchronous Interface Mode In Asynchronous mode, the host processor does not provide a data transfer clock as an input to the Total-AceXtremeTM. In this mode, all transfer timing is controlled by the Total-AceXtreme's 160 MHz internal clock. This clock is derived from the TotalAceXtreme's 40 MHz CLK_IN input. 6.3.1.1 Asynchronous 16-bit Mode Options In Asynchronous 16-bit mode, the order of data transfers for the upper and lower 16bit words, along with the polarity of the MSW_nLSW input signal, may be configured by means of the TRIG_SEL and POL_SEL static input signals, as shown in Table 5. Data Device Corporation www.ddc-web.com 34 DS-BU-67301B-E 2/12 HOST INTERFACE Table 5. Asynchronous 16-bit Mode Configuration Options FIRST WORD TRANSFER SECOND WORD TRANSFER TRIG_SEL POL_SEL RD_nWR 1 1 1 MSW_nLSW = 0 CPU RAM 31:16 MSW_nLSW = 1 CPU RAM 15:0 1 1 0 MSW_nLSW = 0 CPU RAM 31:16 MSW_nLSW = 1 CPU RAM 15:0 1 0 1 MSW_nLSW = 1 CPU RAM 31:16 MSW_nLSW = 0 CPU RAM 15:0 1 0 0 MSW_nLSW = 1 CPU RAM 31:16 MSW_nLSW = 0 CPU RAM 15:0 0 1 1 MSW_nLSW = 1 CPU RAM 15:0 MSW_nLSW = 0 CPU Buffer 31:16 0 1 0 MSW_nLSW = 1 CPU RAM 15:0 MSW_nLSW = 0 CPU RAM 31:16 0 0 1 MSW_nLSW = 0 CPU RAM 15:0 MSW_nLSW = 1 CPU RAM 31:16 0 0 0 MSW_nLSW = 0 CPU RAM 15:0 MSW_nLSW = 1 CPU RAM 31:16 6.3.1.2 Asynchronous Mode Connection Diagrams Figure 7 through Figure 10 show the four possible Asynchronous mode interface configurations, including the four combinations of 32-bit, 16-bit, non-multiplexed, and multiplexed. Data Device Corporation www.ddc-web.com 35 DS-BU-67301B-E 2/12 HOST INTERFACE Figure 7. 32-bit, Non-Multiplexed Address, Asynchronous Interface Data Device Corporation www.ddc-web.com 36 DS-BU-67301B-E 2/12 HOST INTERFACE Figure 8. 32-bit, Multiplexed Address, Asynchronous Interface Data Device Corporation www.ddc-web.com 37 DS-BU-67301B-E 2/12 HOST INTERFACE Figure 9. 16-bit, Non-Multiplexed Address, Asynchronous Interface Data Device Corporation www.ddc-web.com 38 DS-BU-67301B-E 2/12 HOST INTERFACE Figure 10. 16-bit, Multiplexed Address, Asynchronous Interface Data Device Corporation www.ddc-web.com 39 DS-BU-67301B-E 2/12 HOST INTERFACE 6.3.2 Asynchronous Timing Information Table 6 lists the eight Asynchronous mode timing diagrams, Figure 11 through Figure 18, while Table 7 lists the timing parameters that are applicable for these diagrams. Table 6. Asynchronous Transfers Non-Multiplexed or Multiplexed Address/Data 32-bit or 16-bit Read or Write Timing Diagram Non-Multiplexed 32 Read Figure 11 Non-Multiplexed 32 Write Figure 12 Non-Multiplexed 16 Read Figure 13 Non-Multiplexed 16 Write Figure 14 Multiplexed 32 Read Figure 15 Multiplexed 32 Write Figure 16 Multiplexed 16 Read Figure 17 Multiplexed 16 Write Figure 18 Table 7. Asynchronous Timing Information REF DESCRIPTION NOTES Timing Characteristics MIN TYP UNITS MAX tSS nSELECT setup time prior to nDATA_STRB low (for nonmultiplexed address) or ADDR_LAT high (for multiplexed address) 0 ns tSH nSELECT hold time following nDATA_STRB high 0 ns tAS CPU_ADDR, MEM_nREG, RD_nWR, and CPU_WORD_EN valid setup time prior to nDATA_STRB low (for non-multiplexed address) or ADDR_LAT high (for multiplexed address) 10 ns tAH CPU_ADDR, MEM_nREG, RD_nWR, and CPU_WORD_EN valid hold time following nDATA_STRB high (for non-multiplexed address) or ADDR_LAT low (for multiplexed address) 7 ns tWait Maximum delay from nDATA_STRB falling edge to nDATA_RDY falling edge 70 ns Maximum delay from nDATA_STRB falling edge to nDATA_RDY falling edge 40 ns Maximum delay from nDATA_STRB falling edge to nDATA_RDY falling edge 40 ns (32-bit read or first 16-bit read) tWait (second 16-bit read) tWait (write) Data Device Corporation www.ddc-web.com 40 DS-BU-67301B-E 2/12 HOST INTERFACE Table 7. Asynchronous Timing Information REF DESCRIPTION NOTES Timing Characteristics MIN TYP UNITS MAX tDD During READ operations: CPU_DATA valid delay following falling edge of nDATA_RDY 10pF load 5 ns tRDD nDATA_STRB high delay to nDATA_RDY high 10pF load 2 17 ns tOH CPU_DATA output valid hold time following nDATA_STRB high 10pF load 2 tOHZ nDATA_STRB high delay to CPU_DATA high-z 10pF load tDS CPU_DATA valid setup time prior to nDATA_STRB low 10 ns tDH CPU_DATA valid hold time following nDATA_STRB high 0 ns tALP ADDR_LAT pulse width 40 ns ns 17 ns For the 32-bit Asynchronous timing diagrams, POL_SEL is assumed to be connected to logic `0'. That is, RD_nWR = `1' to read and `0' to write. For the 16-bit Asynchronous timing diagrams, POL_SEL is assumed to be connected to logic `0' and TRIG_SEL is assumed to be connected to logic `1'. For these diagrams, the data indicated as "Data A" is bits 31:16, and is always transferred prior to the data indicated as "Data B", which is bits 15:0. For the 16-bit Asynchronous timing diagrams, RD_nWR = `1' to read and `0' to write. Data Device Corporation www.ddc-web.com 41 DS-BU-67301B-E 2/12 HOST INTERFACE nSELECT tSS tSH nDATA_STRB tAH tAS Address CPU_ADDR tAS tAH tAS tAH tAS tAH MEM_nREG RD_nWR CPU_WORD_EN[1:0] tOH tOHZ Data CPU_DATA tDD tWait tRDD nDATA_RDY Figure 11. Asynchronous Non-Multiplexed Address 32-bit Read Timing Figure 11 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle. In Asynchronous mode, nSELECT may be kept low for consecutive transactions by the Total-AceXtreme. 2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data memory words are valid for this transfer. If either or both these bits is `0', then the corresponding 16-bit word(s) will return a value of `0000'. These inputs should be tied high if unused. 3. For register accesses, the value of CPU_WORD_EN[1:0] must be `11'. Data Device Corporation www.ddc-web.com 42 DS-BU-67301B-E 2/12 HOST INTERFACE nSELECT tSS tSH tAS tAH tAS tAH tAS tAH tAS tAH nDATA_STRB CPU_ADDR MEM_nREG RD_nWR CPU_WORD_EN[1:0] tDS tDH Data CPU_DATA tWait tRDD nDATA_RDY Figure 12. Asynchronous Non-Multiplexed Address 32-bit Write Timing Figure 12 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle. In Asynchronous mode, nSELECT may be kept low for consecutive transactions by the Total-AceXtreme. 2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data memory words are to be written. If either or both these bits is `0', then the corresponding 16-bit word(s) will not be written. These inputs should be tied high if unused. 3. For register accesses, the value of CPU_WORD_EN[1:0] must be `11'. Data Device Corporation www.ddc-web.com 43 DS-BU-67301B-E 2/12 HOST INTERFACE nSELECT tSH tSS nDATA_STRB tAH tAS Address CPU_ADDR tAS tAH tAS tAH MEM_nREG CPU_WORD_EN[1:0] tAS tAH tAS MSW_nLSW tAH tAS RD_nWR tOH tOHZ tOH tOHZ Data B Data A CPU_DATA tWait tDD tRDD tWait tDD tRDD nDATA_RDY Figure 13. Asynchronous Non-Multiplexed Address 16-bit Read Timing Figure 13 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle. In Asynchronous mode, nSELECT may be kept low for consecutive transactions by the Total-AceXtreme. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. For register accesses, the value of CPU_WORD_EN[1:0] must be `11'. Data Device Corporation www.ddc-web.com 44 DS-BU-67301B-E 2/12 HOST INTERFACE nSELECT tSS tSH nDATA_STRB tAS tAH Address CPU_ADDR tAS tAH tAS tAH MEM_nREG CPU_WORD_EN[1:0] tAS tAS tAH MSW_nLSW tAS tAH RD_nWR tDH tDS CPU_DATA Data A tDS tDH Data B tWait tRDD tWait tRDD nDATA_RDY Figure 14. Asynchronous Non-Multiplexed Address 16-bit Write Timing Figure 14 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle. In Asynchronous mode, nSELECT may be kept low for consecutive transactions by the Total-AceXtreme. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. Data Device Corporation www.ddc-web.com 45 DS-BU-67301B-E 2/12 HOST INTERFACE nSELECT tSS tSH tALP ADDR_LAT nDATA_STRB tAH tAS MEM_nREG tAS tAH tAS tAH CPU_WORD_EN[1:0] RD_nWR tAH tAS CPU_DATA tDD tOH tOHZ Data Address tWait tRDD nDATA_RDY Figure 15. Asynchronous Multiplexed Address 32-bit Read Timing Figure 15 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle. In Asynchronous mode, nSELECT may be kept low for consecutive transactions by the Total-AceXtreme. 2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data memory words are valid for this transfer. If either or both these bits is `0', then the corresponding 16-bit word(s) will return a value of `0000'. These inputs should be tied high if unused. 3. For register accesses, the value of CPU_WORD_EN[1:0] must be `11'. Data Device Corporation www.ddc-web.com 46 DS-BU-67301B-E 2/12 HOST INTERFACE nSELECT tSS tSH tALP ADDR_LAT nDATA_STRB tDS tAH tAS Address CPU_DATA tAS tDH Data tAH MEM_nREG tAS tAH tAS tAH CPU_WORD_EN[1:0] RD_nWR tWait tRDD nDATA_RDY Figure 16. Asynchronous Multiplexed Address 32-bit Write Timing Figure 16 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle. In Asynchronous mode, nSELECT may be kept low for consecutive transactions by the Total-AceXtreme. 2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data memory words are to be written. If either or both these bits is `0', then the corresponding 16-bit word(s) will not be written. These inputs should be tied high if unused. 3. For register accesses, the value of CPU_WORD_EN[1:0] must be `11'. Data Device Corporation www.ddc-web.com 47 DS-BU-67301B-E 2/12 HOST INTERFACE nSELECT tSS tSH nDATA_STRB tALP tALP ADDR_LAT tAH tAS MEM_nREG tAS tAH CPU_WORD_EN[1:0] tAS tAS tAH MSW_nLSW tAH tAS RD_nWR tAS CPU_DATA tOH tOHZ tAH Address tDD tOH tOHZ tAH Address Data A tWait tAS tRDD Data B tWait tDD tRDD nDATA_RDY Figure 17. Asynchronous Multiplexed Address 16-bit Read Timing Figure 17 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle. In Asynchronous mode, nSELECT may be kept low for consecutive transactions by the Total-AceXtreme. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. Data Device Corporation www.ddc-web.com 48 DS-BU-67301B-E 2/12 HOST INTERFACE nSELECT tSH tSS nDATA_STRB tALP tALP ADDR_LAT tAH tAS MEM_nREG tAH tAS CPU_WORD_EN[1:0] tAH tAS tAS MSW_nLSW tAH tAS RD_nWR tAH tAS CPU_DATA Address tDS tDH Address Data A tWait tAH tAS tRDD tDH tDS Data B tWait tRDD nDATA_RDY Figure 18. Asynchronous Multiplexed Address 16-bit Write Timing Figure 18 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle. In Asynchronous mode, nSELECT may be kept low for consecutive transactions by the Total-AceXtreme. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. Data Device Corporation www.ddc-web.com 49 DS-BU-67301B-E 2/12 HOST INTERFACE 6.4 Synchronous Host Processor Interface In Synchronous mode, the timing of transfers between the host CPU and the TotalAceXtremeTM is controlled by a clock provided by the host and connected to the Total-AceXtreme's HOST_CLK input. The Total-AceXtreme can operate with HOST_CLK speeds up to 80 MHz. 6.4.1 Types of Synchronous Mode Transfers Within the Total-AceXtreme's Synchronous mode, there are three types of data transfers that may be performed. These are: * Single-word transfers. * Sequential burst transfers. * Random burst transfers. Single-word transfers are limited to a single 32-bit transfer or a pair of 16-bit transfers. With both sequential and random Synchronous transfers, the host performs a series of word transfers. In each case, during the active portion of the transfer, a 32-bit or 16-bit word is transferred during each cycle of the Total-AceXtreme's HOST_CLK input. With sequential burst transfers, the host CPU presents its starting address once, at the beginning of the transfer. Following that, a transfer is performed between the host and the starting address in the Total-AceXtreme's internal shared RAM. After that, a series of transfers is performed between the host and successive address locations in the Total-AceXtreme's internal shared RAM. Random burst Synchronous transfers are not limited to transferring data to or from successive locations in the Total-AceXtreme's internal memory. During the active portion of a random Synchronous burst transfer, the host CPU presents a new memory address during each cycle of HOST_CLK. 6.4.2 Operation of Command FIFO and CPU_nSTOP Signal The Synchronous burst mode involves the use of a command FIFO within the TotalAceXtreme. The size of the command FIFO is software programmable, with options of 32, 16, or 8 words. The default size for the FIFO is 32 words. There is one entry posted in the command FIFO for each 32-bit or 16-bit word to be written to or read from the Total-AceXtreme. This includes the values of the Total- Data Device Corporation www.ddc-web.com 50 DS-BU-67301B-E 2/12 HOST INTERFACE AceXtreme memory address; the values of the RD_nWR, MEM_nREG, and MSW_nLSW (for 16-bit mode only) signals; and, for write transfers only, 32-bit or 16bit data. In Synchronous burst mode, the rate that the command FIFO will fill is equal to the frequency of HOST_CLK. The command FIFO is drained by internal logic within the Total-AceXtremeTM. For memory transfers, the normal FIFO drain rate is 160 MHz, however this rate can temporarily drop to a value between 120 to 160 MHz during internal memory accesses by the Total-AceXtreme's MIL-STD-1553 protocol logic. However, for register write transfers, the drain rate is 40 MHz. As a result, the only scenario that can result in a full or near-full command FIFO is during or immediately following a register burst write transfer (the Total-AceXtreme does not support register burst read transfers), when the frequency of HOST_CLK is higher than 40 MHz. Once the command FIFO fills to capacity, the Total-AceXtreme will assert its CPU_nSTOP output signal low, and de-assert its nDATA_RDY high. At this time, the host CPU must terminate its transfer. To illustrate by example, if the command FIFO size is 32 words, the HOST_CLK frequency is 80 MHz, and a 32-bit sequential register write burst is performed. In this example, the command FIFO will fill at 80 MHz and drain at 40 MHz, for a "net fill rate" of 40 MHz. That is, for every two register words written to the FIFO, only one is drained. Therefore, after 64 32-bit words have been written by the host to a previously empty command FIFO, the command FIFO will fill, and the TotalAceXtreme will assert its CPU_nSTOP output signal (and bring nDATA_RDY high), thereby terminating the sequential register write burst transfer. The timing for this scenario is shown in Figure 47. Once CPU_nSTOP has asserted, it is recommended for the host to delay before attempting to retry the current multi-word transfer. To ensure that the FIFO has drained sufficiently, the host should delay for sufficient time to allow at least half of the words in the FIFO to be drained. Assuming that the FIFO is fully populated with register write transfer commands, these require 25 ns each to drain. Therefore, the minimum delay times to prevent a subsequent "STOP" condition are 425 ns for a 32word command FIFO; 225 ns for a 16-word command FIFO; and 125 ns for an 8word command FIFO. Another possible scenario that could occur is if the host performs a sequential register write burst that terminates normally. That is, the command FIFO is not filled to capacity, and the Total-AceXtreme asserts nDATA_RDY low, while CPU_nSTOP remains high. In this case, assume a 32-word FIFO that is filled half-way by register write transfers, and a HOST_CLK frequency of 80 MHz. Data Device Corporation www.ddc-web.com 51 DS-BU-67301B-E 2/12 HOST INTERFACE If the host then initiates a memory write transfer, the last register write command will be drained from the FIFO at approximately the same time that the host writes its 32nd word. This is the marginal case. If the memory write burst began with 15 or fewer register write words in the command FIFO, then the FIFO will not fill, and the TotalAceXtremeTM will not assert its CPU_nSTOP output. In this case, the TotalAceXtreme will assert its nDATA_RDY output because the written word(s) has (have) been pushed on to the FIFO, even though the word(s) haven't yet been transferred to Total-AceXtreme memory. However, if the memory write burst began with 17 or more register write words already in the FIFO, then the FIFO will fill to capacity and the Total-AceXtreme's CPU_nSTOP output will be asserted (with nDATA_RDY de-asserted high), thereby terminating the memory write transfer. Another case is the host performing a read transfer (even a single word read) when the command FIFO is partially full. In this case, unless the host performs a multi-word burst read transfer that overflows the command FIFO, the Total-AceXtreme will not assert its CPU_nSTOP output. However, in this case, the read transfer will not complete until all of the register write requests are first drained from the FIFO. For example, if the FIFO size is 32 words, there are 16 register write words on the FIFO, and the host performs a single-word memory read transfer, then there will be a delay of slightly over 400 ns (16 * 25 ns) before the Total-AceXtreme asserts its nDATA_RDY output low. The worst case additional wait time prior to nDATA_RDY asserting low for a read transfer would occur for a situation where there are 31 register write operations already queued up in the command FIFO ahead of the read command. In this situation, the additional delay time would be = (31 * 25 ns) = 775 ns. 6.4.3 Rules for Synchronous Burst Mode Transfers The following rules must be adhered to when performing Synchronous burst mode transfers: * There is no Asynchronous burst mode, only a Synchronous burst mode. * To initiate a non-multiplexed burst transfer, both nSELECT and nDATA_STRB must be asserted low on the same host clock cycle. * The following rules are applicable specifically for the multiplexed Synchronous mode: - In multiplexed mode, the Total-AceXtreme supports only sequential bursts. In multiplexed mode, random busts are not supported. - nSELECT must be asserted during the same host clock cycle or prior to ADDR_LAT asserting high. Data Device Corporation www.ddc-web.com 52 DS-BU-67301B-E 2/12 HOST INTERFACE - ADDR_LAT must be assert for one host clock cycle to cause the TotalAceXtremeTM to latch the host address bus from CPU_DATA(15:0). - The falling edge of nDATA_STRB must occur at least one cycle after ADDR_LAT pulses high. * A burst write transfer may be either sequential or random. If CPU_STROBE_L is high during the Data Phase, this will cause the burst to be sequential. In this case, the host does not need to continue to present its address on to CPU_ADDR(15:0). If nDATA_STRB remains asserted low during the full data phase, then this will result in a random burst transfer. For a random burst, the host must provide a new value of its address on to CPU_ADDR(15:0) for each word to be transferred. * The Total-AceXtreme does not support either sequential or random Synchronous register burst read operations. * A burst read is always a sequential burst read, and is therefore read from consecutive addresses. The address sampled during the address phase is used as the first address read. The Total-AceXtreme does not support random burst reads. * When the CPU_nLAST input signal is asserted low, this indicates to the Total-AceXtreme that the last word is being read or written on the upcoming host clock cycle. * The actual burst data transfer from or to the Total-AceXtreme begins on the first host clock when nDATA_RDY is initially asserted low. Data is transferred on every subsequent cycle until and including the cycle when the host CPU asserts CPU_nLAST low. In the case of a random burst transfer, the host must also present a new address on CPU_ADDR(15:0) for each word to be written. 6.4.4 Synchronous 16-bit Mode Options In the Synchronous 16-bit mode, the polarity of the MSW_nLSW input is determined by the value of the POL_SEL static input signal, as shown in Table 8. Note that in the 16-bit Synchronous mode, the low word is always transferred first. Note that TRIG_SEL has no effect in Synchronous mode and should be tied to logic `1'. Data Device Corporation www.ddc-web.com 53 DS-BU-67301B-E 2/12 HOST INTERFACE Table 8. Synchronous 16-bit Mode Configuration Options RD_nWR 1 1 MSW_nLSW = 1 CPU RAM 15:0 MSW_nLSW = 0 CPU RAM 31:16 1 0 MSW_nLSW = 1 CPU RAM 15:0 MSW_nLSW = 0 CPU RAM 31:16 0 1 MSW_nLSW = 0 CPU RAM 15:0 MSW_nLSW = 1 CPU RAM 31:16 0 0 MSW_nLSW = 0 CPU RAM 15:0 MSW_nLSW = 1 CPU RAM 31:16 6.4.4.1 FIRST WORD TRANSFER SECOND WORD TRANSFER POL_SEL Synchronous Mode Connection Diagrams Figure 19 through Figure 22 show the four possible Synchronous mode interface configurations, including the four combinations of 32-bit, 16-bit, non-multiplexed, and multiplexed. Data Device Corporation www.ddc-web.com 54 DS-BU-67301B-E 2/12 HOST INTERFACE Figure 19. 32-bit, Non-Multiplexed Address, Synchronous Interface Data Device Corporation www.ddc-web.com 55 DS-BU-67301B-E 2/12 HOST INTERFACE Figure 20. 32-bit, Multiplexed Address, Synchronous Interface Data Device Corporation www.ddc-web.com 56 DS-BU-67301B-E 2/12 HOST INTERFACE Figure 21. 16-bit, Non-Multiplexed Address, Synchronous Interface Data Device Corporation www.ddc-web.com 57 DS-BU-67301B-E 2/12 HOST INTERFACE Figure 22. 16-bit, Multiplexed Address, Synchronous Interface Data Device Corporation www.ddc-web.com 58 DS-BU-67301B-E 2/12 HOST INTERFACE 6.4.5 Synchronous Timing Information Table 9 lists the 12 single-word Synchronous mode timing diagrams, Figure 23 through Figure 35. Table 10 lists the ten Synchronous burst timing diagrams, Figure 37 through Figure 46. Table 11 lists the timing parameters that are applicable for these diagrams. 6.4.5.1 Synchronous Timing Information Table 9. Single-Word Synchronous Transfers Non-Multiplexed or Multiplexed Address/Data 32-bit or 16-bit Read or Write Memory or Register Timing Diagram Non-Multiplexed 32 Read Memory Figure 23 Non-Multiplexed 32 Read Register Figure 24 Non-Multiplexed 32 Write Memory or Register Figure 25 Non-Multiplexed 16 Read Memory Figure 26 Non-Multiplexed 16 Read Register Figure 27 Non-Multiplexed 16 Write Memory Figure 28 Non-Multiplexed 16 Write Register Figure 29 Multiplexed 32 Read Memory Figure 30 Multiplexed 32 Read Register Figure 31 Multiplexed 32 Write Memory or Register Figure 32 Multiplexed 16 Read Memory Figure 33 Multiplexed 16 Read Register Figure 34 Multiplexed 16 Write Memory Figure 35 Multiplexed 16 Write Register Figure 36 Table 10. Synchronous Burst Transfers Non-Multiplexed or Multiplexed 32-bit or 16-bit Sequential or Random Register or Memory Read or Write Timing Diagram Non-Multiplexed 32 Sequential Memory Read Figure 37 Non-Multiplexed 32 Sequential Memory or Register Write Figure 38 Non-Multiplexed 32 Random Memory or Register Write Figure 39 Non-Multiplexed 16 Sequential Memory Read Figure 40 Non-Multiplexed 16 Sequential Memory or Register Write Figure 41 Data Device Corporation www.ddc-web.com 59 DS-BU-67301B-E 2/12 HOST INTERFACE Table 10. Synchronous Burst Transfers Non-Multiplexed or Multiplexed 32-bit or Register or Memory Read or 16-bit Sequential or Random Timing Diagram Non-Multiplexed 16 Random Memory or Register Write Figure 42 Multiplexed 32 Sequential Memory Read Figure 43 Multiplexed 32 Sequential Memory or Register Write Figure 44 Multiplexed 16 Sequential Memory Read Figure 45 Multiplexed 16 Sequential Memory or Register Write Figure 46 Multiplexed 32-bit or 16-bit Random Memory or Register Read or Write Not Supported Non-Multiplexed or Multiplexed 32-bit or 16-bit Sequential or Random Register Read Not Supported Non-Multiplexed or Multiplexed 32-bit or 16-bit Random Memory or Register Read Not Supported Write Table 11. Synchronous Timing Parameters Timing Characteristics REF DESCRIPTION NOTES MIN TYP MAX fCLK HOST_CLK frequency 0 tCLK HOST_CLK cycle time 12.5 tSS nDATA_STRB setup time (NOTE) 4 tSH nDATA_STRB hold time (NOTE) 0 tCS nSELECT setup time (NOTE) 4 ns tCH nSELECT hold time (NOTE) 0 ns tAS CPU_ADDR valid setup time (NOTE) 4 ns tAH CPU_ADDR valid hold time (NOTE) 0 ns tMS MSW_nLSW setup time (NOTE) 4 ns tMH MSW_nLSW hold time (NOTE) 0 ns tWAIT-READ Read cycle latency from nDATA_STRB falling edge to nDATA_RDY falling edge tWAIT- Write cycle latency from nDATA_STRB falling edge to nDATA_RDY falling edge WRITE (6*tCLK) + 50 tDD CPU_DATA valid delay (NOTE) 10pF load tRDD nDATA_RDY delay (NOTE) 10pF load 2 tOH CPU_DATA output valid hold time (NOTE) 10pF load 2 tOHZ CPU_DATA delay to high-Z (NOTE) 10pF load Data Device Corporation www.ddc-web.com 60 80 UNITS MHz ns (7*tCLK) + 75 ns 4*tCLK ns 8 ns 7 ns ns 8 ns DS-BU-67301B-E 2/12 HOST INTERFACE Table 11. Synchronous Timing Parameters Timing Characteristics REF DESCRIPTION NOTES UNITS MIN TYP MAX tDS CPU_DATA valid setup time (NOTE) 4 ns tDH CPU_DATA valid hold time (NOTE) 0 ns tALS ADDR_LAT setup time (NOTE) 4 ns tALH ADDR_LAT hold time (NOTE) 0 tSTPD CPU_nSTOP delay (Only applicable during Register Read operation. Low otherwise) (NOTE) 10pF load 2 6.8 ns tLS CPU_nLAST setup time (NOTE) 4 ns tLH CPU_nLAST hold time (NOTE) 0 ns tSHC nSELECT hold cycle time (NOTE) tCLK ns Note: Indicated times are relative to the rising edge of HOST_CLK. For the 32-bit Synchronous timing diagrams, POL_SEL is assumed to be connected to logic `0'. That is, RD_nWR = `1' to read and `0' to write. For the 16-bit Synchronous timing diagrams, POL_SEL is assumed to be connected to logic `0'. For these diagrams, the data indicated as "Data A" is bits 15:0, and is always transferred prior to the data indicated as "Data B", which is bits 31:16. For the 16-bit Synchronous timing diagrams, RD_nWR = `1' to read and `0' to write. Data Device Corporation www.ddc-web.com 61 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait HOST_CLK tCS tCH tSHC nSELECT tSS tSH nDATA_STRB tAH tAS Address CPU_ADDR tAS tAH tAS tAH MEM_nREG RD_nWR tAH tAS CPU_WORD_EN[1:0] tOH tDD tOHZ Data CPU_DATA tRDD tRDD nDATA_RDY CPU_nSTOP CPU_nLAST Figure 23. Synchronous, Non-Multiplexed Address 32-bit Single-Word Memory Read Timing Figure 23 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle, and de-asserted high at the end of the transfer. 2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data memory words are valid for this transfer. If either or both these bits is `0', then the corresponding 16-bit word(s) will return a value of `0000'. These inputs should be tied high if unused. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP will not be asserted for memory accesses, and will remain high. Data Device Corporation www.ddc-web.com 62 DS-BU-67301B-E 2/12 HOST INTERFACE tWait tCLK HOST_CLK tSHC tCH tCS nSELECT tSS tSH nDATA_STRB tAH tAS Address CPU_ADDR tAS tAH tAS tAH MEM_nREG RD_nWR tAH tAS CPU_WORD_EN[1:0] tOH tDD tOHZ Data CPU_DATA tRDD tRDD nDATA_RDY tSTPD tSTPD CPU_nSTOP CPU_nLAST Figure 24. Synchronous, Non-Multiplexed Address 32-bit Single-Word Register Read Timing Figure 24 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT should be asserted throughout the entire transfer cycle, and de-asserted high at the end of the transfer. 2. For register transfers, the value of the CPU_WORD_EN[1:0] inputs must be `11'. 3. For a single-word register read access, CPU_nSTOP asserts (low) simultaneous with nDATA_RDY, and de-asserts (high) on the host clock cycle following nSELECT returning high. Data Device Corporation www.ddc-web.com 63 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait HOST_CLK tCS tCH tSHC nSELECT tSS tSH nDATA_STRB tAH tAS Address CPU_ADDR tAS tAH tAS tAH MEM_nREG RD_nWR tAH tAS CPU_WORD_EN[1:0] tDS tDH Data CPU_DATA tRDD tRDD nDATA_RDY CPU_nSTOP CPU_nLAST Figure 25. Synchronous, Non-Multiplexed Address 32-bit Single-Word Write Timing Figure 25 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle, and de-asserted high at the end of the transfer. 2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data memory words are to be written. If either or both these bits is `0', then the corresponding 16-bit word(s) will not be written to Total-AceXtreme memory. These inputs should be tied high if unused. For register transfers, the value of CPU_WORD_EN[1:0] must be `11'. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for memory accesses, and will remain high. Data Device Corporation www.ddc-web.com 64 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait tWait HOST_CLK tCS tCS tCH tCH tSHC nSELECT tSH tSS tSH tSS nDATA_STRB tAS tAH Address CPU_ADDR tAS tAH tAS tAH CPU_WORD_EN[1:0] MEM_nREG tAS tAS tAH MSW_nLSW tAS tAH RD_nWR tDD tOH tOHZ tDD Data A CPU_DATA tRDD tOH tOHZ Data B tRDD tRDD tRDD nDATA_RDY CPU_nSTOP CPU_nLAST Figure 26. Synchronous, Non-Multiplexed Address 16-bit Single-Word Memory Read Timing Figure 26 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle, and de-asserted high at the end of the transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP will not be asserted for memory accesses, and will remain high. Data Device Corporation www.ddc-web.com 65 DS-BU-67301B-E 2/12 HOST INTERFACE tWait tCLK tWait HOST_CLK tCH tCS tCS tSHC tCH nSELECT tSH tSS tSH tSS nDATA_STRB tAH tAS Address CPU_ADDR tAS CPU_WORD_EN[1:0] tAH tAS MEM_nREG tAS tAS tAH MSW_nLSW tAH tAS RD_nWR tDD tOH tOHZ tDD tRDD tOH tOHZ Data B Data A CPU_DATA tRDD tRDD tRDD nDATA_RDY tSTPD tSTPD tSTPD tSTPD CPU_nSTOP CPU_nLAST Figure 27. Synchronous, Non-Multiplexed Address 16-bit Single-Word Register Read Timing Figure 27 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle , and de-asserted high at the end of the transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. For a register read access, CPU_nSTOP asserts (low) simultaneous with nDATA_RDY, and deasserts (high) on the host clock cycle following nSELECT returning high. Data Device Corporation www.ddc-web.com 66 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait tWait HOST_CLK tCS tCH tCS tCH tSHC nSELECT tSH tSS tSH tSS nDATA_STRB tAS tAH Address CPU_ADDR tAS tAH tAS tAH CPU_WORD_EN[1:0] MEM_nREG tAS tAS tAH MSW_nLSW tAS tAH RD_nWR tDS tDH tDS Data A CPU_DATA tDH Data B tRDD tRDD tRDD tRDD nDATA_RDY CPU_nSTOP Figure 28. Synchronous, Non-Multiplexed Address 16-bit Single-Word Memory Write Timing Figure 28 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle, and de-asserted high at the end of the transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for write accesses, and will remain high. Data Device Corporation www.ddc-web.com 67 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait tWait HOST_CLK tCS tCH tCS tCH tSHC nSELECT tSH tSS tSH tSS nDATA_STRB tAS tAH Address CPU_ADDR tAS tAH tAS tAH CPU_WORD_EN[1:0] MEM_nREG tAS tAH tAS MSW_nLSW tAH tAS RD_nWR tDS CPU_DATA tDS tDH Data A tDH Data B tRDD tRDD tRDD tRDD nDATA_RDY CPU_nSTOP Figure 29. Synchronous, Non-Multiplexed Address 16-bit Single-Word Register Write Timing Figure 29 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle, and de-asserted high at the end of the transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for write accesses, and will remain high. Data Device Corporation www.ddc-web.com 68 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait HOST_CLK tCS tCH tSHC nSELECT tSS tSH nDATA_STRB tALH tALS ADDR_LAT tAS tAH MEM_nREG tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tAS CPU_DATA tAH tOH tDD tOHZ Data Address tRDD tRDD nDATA_RDY CPU_nSTOP CPU_nLAST Figure 30. Synchronous, Multiplexed Address 32-bit Single-Word Memory Read Timing Figure 30 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle, and de-asserted high at the end of the transfer. 2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data memory words are to be read for this transfer. If either or both these bits is `0', then the corresponding 16-bit word(s) will return a value of `0000'. These inputs should be tied high if unused. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for memory accesses, and will remain high. Data Device Corporation www.ddc-web.com 69 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait HOST_CLK tCS tCH tSHC nSELECT tSS tSH nDATA_STRB tALH tALS ADDR_LAT tAS tAH MEM_nREG tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tAH tAS CPU_DATA tOH tDD Address tOHZ Data tRDD tRDD nDATA_RDY tSTPD tSTPD CPU_nSTOP CPU_nLAST Figure 31. Synchronous, Multiplexed Address 32-bit Single-Word Register Read Timing Figure 31 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle, and de-asserted high at the end of the transfer. 2. For register accesses, the value of the CPU_WORD_EN[1:0] inputs must be `11'. 3. For a register read access, CPU_nSTOP asserts (low) simultaneous with nDATA_RDY, and deasserts (high) on the host clock cycle following nSELECT returning high. Data Device Corporation www.ddc-web.com 70 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait HOST_CLK tCS tCH tSHC nSELECT tSH tSS nDATA_STRB tALH tALS ADDR_LAT tAS tAH MEM_nREG tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tAS tAH Address tDS tDS Data CPU_DATA tRDD tRDD nDATA_RDY CPU_nSTOP CPU_nLAST Figure 32. Synchronous, Multiplexed Address 32-bit Single-Word Write Timing Figure 32 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle, and de-asserted high at the end of the transfer. 2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data memory word(s) are to be written. If either or both these bits is `0', then the corresponding 16-bit word(s) will not be written. These inputs should be tied high if unused. For register transfers, the value of CPU_WORD_EN[1:0] must be `11'. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for write accesses, and will remain high. Data Device Corporation www.ddc-web.com 71 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait tWait HOST_CLK tCH tCS tSHC tCH tCS nSELECT tSS tSH tSS tSH nDATA_STRB tALH tALS tALH tALS ADDR_LAT tAS tAS tAH MSB_nLSW tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tAS tAH tAS tAH tAS tAH MEM_nREG tAS CPU_DATA tAH tDD Address tOH tOHZ Address Data A tSTPD tDD tRDD tSTPD tOH tOHZ Data B tRDD nDATA_RDY CPU_nSTOP CPU_nLAST Figure 33. Synchronous, Multiplexed Address 16-bit Single-Word Memory Read Timing Figure 33 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle, and de-asserted high at the end of the transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for memory accesses, and will remain high. Data Device Corporation www.ddc-web.com 72 DS-BU-67301B-E 2/12 HOST INTERFACE tWait tCLK tWait HOST_CLK tCS tCS tCH tCH tSHC nSELECT tSS tSH tSS tSH nDATA_STRB tALH tALS tALH tALS ADDR_LAT tAS tAH tAS MSW_nLSW tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tAS tAH tAS tAH tAS tAH tAS tAH MEM_nREG CPU_DATA Address tDD tOH tOHZ Data A tRDD Address tRDD tDD tOH tOHZ Data B tRDD tRDD nDATA_RDY tSTPD tSTPD tRDD tRDD CPU_nSTOP CPU_nLAST Figure 34. Synchronous, Multiplexed Address 16-bit Single-Word Register Read Timing Figure 34 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle, and de-asserted high at the end of the transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. For a register read access, CPU_nSTOP asserts (low) simultaneous with nDATA_RDY, and deasserts (high) on the host clock cycle following nSELECT returning high. Data Device Corporation www.ddc-web.com 73 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait tWait HOST_CLK tCS tCS tCH tCH tSHC nSELECT tSH tSS tSH tSS nDATA_STRB tALH tALS tALH tALS ADDR_LAT tAS tAH CPU_WORD_EN[1:0] tAS tAH tAS tAH MEM_nREG tAS tAS tAH MSW_nLSW tAS tAH RD_nWR tAS CPU_DATA tAH tDS Address tDH tAS Data A tAH Address tRDD tRDD tDS tDH Data B tRDD tRDD nDATA_RDY CPU_nSTOP Figure 35. Synchronous, Multiplexed Address 16-bit Single-Word Memory Write Timing Figure 35 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle, and de-asserted high at the end of the transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for write accesses, and will remain high. Data Device Corporation www.ddc-web.com 74 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait tWait HOST_CLK tCS tCH tCS tCH nSELECT tSH tSS tSH tSS nDATA_STRB tALH tALS tALH tALS ADDR_LAT tAS tAH CPU_WORD_EN[1:0] tAS tAH tAS tAH MEM_nREG tAS tAS tAH MSW_nLSW tAS tAH RD_nWR tAS CPU_DATA tAH tDS Address tDH tAS Data A tAH Address tRDD tRDD tDS tDH Data B tRDD tRDD nDATA_RDY CPU_nSTOP Figure 36. Synchronous, Multiplexed Address 16-bit Single-Word Register Write Timing Figure 36 Notes: 1. When nSELECT is asserted (low), the Total-AceXtremeTM is selected for this data transfer. nSELECT must be asserted through the full transfer cycle, and de-asserted high at the end of the transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted for write accesses, and will remain high. Data Device Corporation www.ddc-web.com 75 DS-BU-67301B-E 2/12 tSHC HOST INTERFACE tCLK tWait HOST_CLK tCS tCH tSHC nSELECT tSS tSH nDATA_STRB tAH tAS Address CPU_ADDR tAS tAH MEM_nREG tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tLS tLH tLS tLH CPU_nLAST tDD Data tDH Data Data Data Data Data Data Data CPU_DATA tRDD tRDD nDATA_RDY CPU_nSTOP Figure 37. Synchronous, Non-Multiplexed Address, 32-bit Sequential Burst Memory Read Transfer Timing Figure 37 Notes: 1. A one-clock-cycle wide pulse of nDATA_STRB (low) when nSELECT is asserted (low) initiates the sequential burst transfer. nSELECT must be asserted low through the full burst cycle. 2. The nDATA_RDY output is initially asserted low on the same clock cycle when the TotalAceXtremeTM drives the first valid data word on the data bus. CPU_nLAST must be asserted high until the last word is to be read. On the rising clock edge following CPU_nLAST asserting low, the last word is removed (tri-stated) from the data bus, and nDATA_RDY is de-asserted (high). At this time (or later) nSELECT must be de-asserted high, completing the burst read transfer. 3. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data memory word(s) are valid for this transfer. If either or both these bits is `0', then the corresponding 16-bit word(s) will return a value of `0000'. These inputs should be tied high if unused. 4. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation www.ddc-web.com 76 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait HOST_CLK tCH tCS tSHC nSELECT tSS tSH nDATA_STRB tAH tAS Address CPU_ADDR tAS tAH MEM_nREG tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tLS tLH tLS tLH CPU_nLAST tDS tDH tDH Data Data CPU_DATA Data Data Data Data Data Data Data tRDD tRDD nDATA_RDY CPU_nSTOP Figure 38. Synchronous, Non-Multiplexed Address 32-bit Sequential Burst Write Transfer Timing Figure 38 Notes: 1. A one-clock-cycle wide pulse of nDATA_STRB (low) when nSELECT is asserted (low) and valid address presented initiates the sequential burst transfer. nSELECT must be asserted low through the full burst cycle. The nDATA_RDY output is initially asserted low on the clock cycle prior to the cycle in which the Total-AceXtremeTM reads the first data word from the data bus. CPU_nLAST must be asserted high until the last word is to be written. On the rising clock edge following CPU_nLAST asserting low, the Total-AceXtreme reads the last word from the data bus, and nDATA_RDY is de-asserted (high). At this time (or later) nSELECT must be de-asserted high, completing the burst write transfer. 2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data memory word(s) are to be written. If either or both of these bits is `0', then the corresponding 16-bit word(s) will not be written. These inputs should be tied high if unused. For register transfers, the value of CPR_WORD_EN[1:0] must be `11'. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation www.ddc-web.com 77 DS-BU-67301B-E 2/12 HOST INTERFACE tWait tCLK HOST_CLK tCS tCH tSS tSH tSHC nSELECT nDATA_STRB tAS tAH tAH Address CPU_ADDR Address Address Address Address Address Address Address Address tAH MEM_nREG tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tLS tLH tLS tLH CPU_nLAST tDS tDH tDH Data Data CPU_DATA Data Data Data Data Data Data Data tRDD tRDD nDATA_RDY CPU_nSTOP Figure 39. Synchronous, Non-Multiplexed Address 32-bit Random Burst Write Transfer Timing Figure 39 Notes: 1. For a random burst write transfer, both nDATA_STRB and nSELECT must be asserted low through the entire time of the transfer. The nDATA_RDY output is initially asserted low on the clock cycle prior to the cycle in which the Total-AceXtremeTM reads the first data word from the data bus. CPU_nLAST must be asserted high until the last word is to be written. On the rising clock edge following CPU_nLAST asserting low, the Total-AceXtreme reads the last word from the data bus, and nDATA_RDY is de-asserted (high). At this time (or later) nDATA_STRB and nSELECT must be de-asserted high, completing the burst write transfer. 2. The CPU_WORD_EN[1:0] inputs are used to specify which bit data memory word(s) are to be written. If either or both of these bits is `0', then the corresponding 16-bit word(s) will not be written. These inputs should be tied high if unused. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation www.ddc-web.com 78 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait HOST_CLK tCS tCH tSHC nSELECT tSH tSS nDATA_STRB tAH tAS Address CPU_ADDR tAS tAH MEM_nREG tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tLS tLS tLH CPU_nLAST tAS tAH tAH MSW_nLSW tDD Data tDH Data Data Data Data Data Data Data CPU_DATA tRDD tRDD nDATA_RDY CPU_nSTOP Figure 40. Synchronous, Non-Multiplexed Address 16-bit Sequential Burst Memory Read Transfer Timing Figure 40 Notes: 1. A one-clock-cycle wide pulse of nDATA_STRB (low) when nSELECT is asserted (low) and valid address presented initiates the sequential burst read transfer. nSELECT must be asserted low through the full burst cycle. The nDATA_RDY output is initially asserted low on the same clock cycle when the Total-AceXtremeTM drives the first valid 16-bit data word on the data bus. CPU_nLAST must be asserted high until the last 16-bit word is to be read. On the rising clock edge following CPU_nLAST asserting low, the last 16-bit word is removed (tri-stated) from the data bus, and nDATA_RDY is de-asserted (high). At this time (or later) nSELECT must be deasserted high, completing the burst read transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation www.ddc-web.com 79 DS-BU-67301B-E 2/12 HOST INTERFACE tWait tCLK HOST_CLK tCH tCS tSHC nSELECT tSH tSS nDATA_STRB tAH tAS Address CPU_ADDR tAH tAS MEM_nREG tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tLH tLS tLS tLH CPU_nLAST tAH tAS tAH MSW_nLSW tDS tDH Data Data CPU_DATA tDH Data Data Data Data Data Data Data Data tRDD tRDD nDATA_RDY CPU_nSTOP Figure 41. Synchronous, Non-Multiplexed Address 16-bit Sequential Burst Write Transfer Timing Figure 41 Notes: 1. A one-clock-cycle wide pulse of nDATA_STRB (low) when nSELECT is asserted (low) and valid address presented initiates the sequential burst write transfer. nSELECT must be asserted low through the full burst cycle. The nDATA_RDY output is initially asserted low on the clock cycle prior to the cycle in which the Total-AceXtremeTM reads the first 16-bit data word from the data bus. CPU_nLAST must be asserted high until the last 16-bit word is to be written. On the rising clock edge following CPU_nLAST asserting low, the Total-AceXtreme reads the last 16-bit word from the data bus, and nDATA_RDY is de-asserted (high). At this time (or later) nSELECT must be de-asserted high, completing the burst write transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation www.ddc-web.com 80 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait HOST_CLK tCS tCH tSS tSH tSHC nSELECT nDATA_STRB tAS tAH Address CPU_ADDR tAH Address Address Address Address tAS tAH tAS tAH tAS tAH MEM_nREG RD_nWR CPU_WORD_EN[1:0] tLS tLS tLH CPU_nLAST tAH tAS MSW_nLSW tDS tDH Data Data CPU_DATA tDH Data Data Data Data Data Data Data Data tRDD tRDD nDATA_RDY CPU_nSTOP Figure 42. Synchronous, Non-Multiplexed Address 16-bit Random Burst Write Transfer Timing Figure 42 Notes: 1. For a random burst write transfer, both nDATA_STRB and nSELECT must be asserted low through the entire time of the transfer. The nDATA_RDY output is initially asserted low on the clock cycle prior to the cycle in which the Total-AceXtremeTM reads the first 16-bit data word from the data bus. CPU_nLAST must be asserted high until the last 16-bit word is to be written. On the rising clock edge following CPU_nLAST asserting low, the Total-AceXtreme reads the last 16-bit word from the data bus, and nDATA_RDY is de-asserted (high). At this time (or later) nDATA_STRB and nSELECT must be de-asserted high, completing the burst write transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation www.ddc-web.com 81 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait HOST_CLK tCS tCH tSHC nSELECT tSH tSS nDATA_STRB tALS tALH ADDR_LAT tAS tAH tAH MEM_nREG tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tLS tLH tLS tLH CPU_nLAST tAH tAS Address CPU_DATA tDD Data tDH Data Data Data Data Data Data Data tRDD tRDD nDATA_RDY CPU_nSTOP Figure 43. Synchronous, Multiplexed Address 32-bit Sequential Burst Memory Read Transfer Timing Figure 43 Notes: 1. With nSELECT asserted low and valid address presented on CPU_DATA, a positive pulse on the ADDR_LAT input satisfying tALS and TAHL will result in the Total-AceXtremeTM latching the starting address for the sequential burst. One host clock cycle later, a one-clock-cycle wide pulse of nDATA_STRB (low) while nSELECT remains asserted (low) initiates the sequential burst transfer. nSELECT must be asserted low through the remainder of the burst cycle. The nDATA_RDY output is initially asserted low on the same host clock cycle when the Total-AceXtreme drives the first valid data word on the data bus. CPU_nLAST must be asserted high until the last word is to be read. On the rising host clock edge following CPU_nLAST asserting low, the last word is removed (tri-stated) from the data bus, and nDATA_RDY is de-asserted (high). At this time (or later) nSELECT must be de-asserted high, completing the burst read transfer. 2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data memory word(s) are valid for this transfer. If either or both these bits is `0', then the corresponding 16-bit word(s) will return a value of `0000'. These inputs should be tied high if unused. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation www.ddc-web.com 82 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK tWait HOST_CLK tCS tCH tSHC nSELECT tSH tSS nDATA_STRB tALH tALS ADDR_LAT tAH tAS MEM_nREG tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tLS tLH tLS tLH CPU_nLAST tAH tAS CPU_DATA Address tDH tDS Data Data tDH Data Data Data Data Data Data Data tRDD tRDD nDATA_RDY CPU_nSTOP Figure 44. Synchronous, Multiplexed Address 32-bit Sequential Burst Write Transfer Timing Figure 44 Notes: 1. With nSELECT asserted low and valid address presented on CPU_DATA, a positive pulse on the ADDR_LAT input satisfying tALS and TAHL will result in the Total-AceXtremeTM latching the starting address for the sequential burst. One host clock cycle later, a one-clock-cycle wide pulse of nDATA_STRB (low) while nSELECT remains asserted (low) initiates the sequential burst transfer. nSELECT must be asserted low through the remainder of the burst cycle. The nDATA_RDY output is initially asserted low on the same host clock cycle when the Total-AceXtreme latches the first data word from the data bus. CPU_nLAST must be asserted high until the last word is to be written. On the rising host clock edge following CPU_nLAST asserting low, the last word latched from the data bus, and nDATA_RDY is de-asserted (high). At this time (or later) nSELECT must be de-asserted high, completing the burst read transfer. 2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data memory word(s) are valid for this transfer. If either or both these bits is `0', then the corresponding 16-bit word(s) will not be written to Total-AceXtreme memory. These inputs should be tied high if unused. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation www.ddc-web.com 83 DS-BU-67301B-E 2/12 HOST INTERFACE tWait tCLK HOST_CLK tCH tCS tSHC nSELECT tSH tSS nDATA_STRB tAH tAS Address CPU_ADDR tAS tAH MEM_nREG tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tLS tLS tLH CPU_nLAST tAH tAS tAH MSW_nLSW tDD Data tDH Data Data Data Data Data Data Data CPU_DATA tRDD tRDD Figure 45. Synchronous, Multiplexed Address 16-bit Sequential Burst Memory Read Transfer Timing Figure 45 Notes: 1. With nSELECT asserted low and valid address presented on CPU_DATA, a positive pulse on the ADDR_LAT input satisfying tALS and TAHL will result in the Total-AceXtremeTM latching the starting address for the sequential burst. One clock cycle later, a one-clock-cycle wide pulse of nDATA_STRB (low) while nSELECT remains asserted (low) initiates the sequential burst transfer. nSELECT must be asserted low through the remainder of the burst cycle. The nDATA_RDY output is initially asserted low on the clock cycle prior to the cycle in which the Total-AceXtreme reads the first data word from the data bus. CPU_nLAST must be asserted high until the last word is to be written. On the rising clock edge following CPU_nLAST asserting low, the TotalAceXtreme reads the last word from the data bus, and nDATA_RDY is de-asserted (high). At this time (or later) nSELECT must be de-asserted high, completing the burst write transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation www.ddc-web.com 84 DS-BU-67301B-E 2/12 HOST INTERFACE tWait tCLK HOST_CLK tCH tCS tSHC nSELECT tSH tSS nDATA_STRB tALH tALS ADDR_LAT tAH tAS MEM_nREG tAS tAH tAS tAH RD_nWR CPU_WORD_EN[1:0] tLS tLS tLH CPU_nLAST tAS tAH tAH MSW_nLSW tAH tAS CPU_DAT A tDH Data tDS Address Data tDH Data Data Data Data Data Data Data Data tRDD tRDD nDATA_RDY CPU_nSTOP Figure 46. Synchronous, Multiplexed Address 16-bit Sequential Burst Write Transfer Timing Figure 46 Notes: 1. With nSELECT asserted low and valid address presented on CPU_DATA, a positive pulse on the ADDR_LAT input satisfying tALS and TAHL will result in the Total-AceXtremeTM latching the starting address for the sequential burst. One clock cycle later, a one-clock-cycle wide pulse of nDATA_STRB (low) while nSELECT remains asserted (low) initiates the sequential burst transfer. nSELECT must be asserted low through the remainder of the burst cycle. The nDATA_RDY output is initially asserted low on the clock cycle prior to the cycle in which the Total-AceXtreme reads the first 16-bit data word from the data bus. CPU_nLAST must be asserted high until the last 16-bit word is to be written. On the rising clock edge following CPU_nLAST asserting low, the Total-AceXtreme reads the last 16-bit word from the data bus, and nDATA_RDY is de-asserted (high). At this time (or later) nSELECT must be de-asserted high, completing the burst write transfer. 2. For 16-bit accesses, CPU_WORD_EN[1:0] must be `11' through the full transfer cycle. 3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not asserted, and will remain high. Data Device Corporation www.ddc-web.com 85 DS-BU-67301B-E 2/12 HOST INTERFACE tWait tCLK HOST_CLK tCH tCS tSHC nSELECT tSS tSH nDATA_STRB tAH tAS Address CPU_ADDR tAS tAH MEM_nREG tAH tAS RD_nWR tAH tAS Data CPU_WORD_EN[1:0] tLS tLH CPU_nLAST Last Valid Data tDS CPU_DATA tDH tDH Data Data tRDD Data Data Data tRDD nDATA_RDY tSTPD tSTPD CPU_nSTOP Figure 47. Timing for Assertion of CPU_nSTOP Output During Synchronous Burst Write Transfer Figure 47 Note: In this example, the fourth word written by the host results in the filling of the Total-AceXtremeTM's command FIFO to its capacity. The capacity of the command FIFO is software programmable for either 32, 16, or 8 words. As a result, the Total-AceXtreme will not be able to accept any further additional word transfers until one or more commands are drained from the FIFO. At this time, the Total-AceXtreme will terminate the current transfer by asserting its CPU_nSTOP output low. If this occurs, it is recommended for the host to delay before attempting to retry the current multi-word transfer. To ensure that the FIFO has drained sufficiently, the host should delay for sufficient time to allow at least half of the words in the FIFO to be drained. Assuming that the FIFO is fully populated with register write transfer commands, these require 25 ns each to drain. Therefore, the minimum delay times to prevent a subsequent "STOP" condition are 425 ns for a 32-word command FIFO; 225 ns for a 16-word command FIFO; and 125 ns for an 8-word command FIFO. Data Device Corporation www.ddc-web.com 86 DS-BU-67301B-E 2/12 HOST INTERFACE 6.5 PCI Interface In addition to the flexible parallel CPU interface, the Total-AceXtremeTM also includes a PCI 2.3 compliant Target/Initiator interface. Table 12 lists the features and characteristics of the Total-AceXtreme's PCI interface. Table 12. Total-AceXtremeTM PCI Interface Characteristics PCI Characteristic/Feature Total-AceXtremeTM PCI Specification Compliance Revision 2.3 Maximum PCI clock frequency 66 MHz Support 32-bit PCI Bus YES Support 64-bit PCI Bus (AD[63::32]) NO 3.3V Signaling YES 5V Tolerant NO PCI Target Interface YES PCI Initiator Interface YES Single-Channel PCI Initiator/DMA Engine Memory only, not registers PCI Initiator/DMA Engine: Transfer Directions Supports transfers in both directions: host-to-TotalAceXtreme and Total-AceXtreme -to-host. PCI Initiator/DMA Engine: Data Transfer Modes * Block transfer mode (single descriptor execution via registers). * Scatter/gather mode (descriptors stored in host memory) PCI Initiator/DMA Engine: PCI burst lengths Programmable (including infinite) PCI Initiator/DMA Engine: PCI Retry timeout Programmable (including infinite) PCI Initiator/DMA Engine: Programmable Interrupts Memory and Register Addressability * DMA Complete * DMA Descriptor Done * DMA Abort Function via register control * DWord or Word write accesses to memory * DWord write accesses to registers * DWord or Word read accesses from registers * No 8-bit accesses Interrupts supported INTA# PCI Retries Supported Disconnect with Data Supported Target Abort Total-AceXtreme will never generate a target abort Delayed Transactions Supports up to two simultaneous BAR0/BAR1 Support BAR0 = Total-AceXtreme Memory BAR1 = Total-AceXtreme Registers Zero wait state bursts Supported, for both reads and writes as both Target and Initiator Data Device Corporation www.ddc-web.com 87 DS-BU-67301B-E 2/12 HOST INTERFACE Table 12. Total-AceXtremeTM PCI Interface Characteristics PCI Characteristic/Feature Total-AceXtremeTM Target Burst Writes Supported to memory and registers Target Burst Reads Supported only for Memory MSI Support NO PRSNT[1::2]# Signals N/A CLKRUN Signal NO PCI Power Management and PME# Signal NO M66EN Signal N/A 64-bit addressing NO C/BE[7:4] NO LOCK# Signal NO The following describes the byte/word lane behavior for Total-AceXtremeTM Memory accesses: 6.5.1 PCI Memory Interface * Writes to memory (BAR0) require either 2 high, 2 low, or all 4 byte lanes (C/BE[3:0]) active or the writes will not take place (terminated on PCI bus and discarded internally). This allows for either 16-bit or 32-bit writes to memory. 8-bit memory writes are not supported. * Reads from memory (BAR0) will ignore byte lanes because reads are nondestructive and cause no state change to the circuit. This allows for any combination of byte lane assertion to read a full 32-bit memory location. 6.5.2 PCI Register Interface * Writes to registers (BAR1) require all 4 byte lanes to be active or the write will not take place (terminated on PCI bus but discarded). * Reads from registers (BAR1) require either 2 high, 2 low, or all 4 byte lanes active and full 32-bit read will be returned over the PCI bus. * Reads from registers (BAR1) without either 2 high, 2 low, or all 4 byte lanes active will result in no read performed and 0's returned on the PCI bus. * The PCI interface acts as a standard 32-bit PCI device. It can operate at 33 or 66MHz clock rates and will act as a bus master for DMA operations. 6.5.3 PCI Interface Diagram Figure 48 shows the connection between a PCIbus and Total-AceXtremeTM. Data Device Corporation www.ddc-web.com 88 DS-BU-67301B-E 2/12 HOST INTERFACE Figure 48. Interface Between Host PCI Bus and Total-AceXtremeTM Data Device Corporation www.ddc-web.com 89 DS-BU-67301B-E 2/12 HOST INTERFACE 6.5.4 PCI Signal List Table 13. PCI Bus Interface Signals Signal Name DIR Description HOST_CLK I PCI Clock Input clock from the host. Can be up to 66MHz PCI_AD[31:0] I/O PCI Address / Data GNT# I Bus Master Grant Indicates to the Total-AceXtreme that access to the bus has been granted by the PCI Arbiter. This is only required for DMA/PCI Initiator transactions. REQ# O Bus Master Request Request to the bus Arbiter for control of the PCI bus. This is only required for DMA/PCI Initiator transactions. PERR# I/O Parity Error This pin is used for reporting parity errors. It does not indicate Parity errors during the Address phase. IDSEL I Initialization Device Select This signal is used as a chip select during configuration read or write operations. It should be connected to an upper PCI A/D line or an individual control signal from the PCI Bus Controller. The connection is system specific. DEVSEL# I/O Device Select This signal is sourced by the active target upon decoding that its address and bus commands are valid. STOP# I/O IRDY# I/O TRDY# I/O FRAME# I/O PAR I/O C/BE[3:0]# I/O SERR# I/O PCI Stop. This signal indicates the current target is requesting the master to stop the current transaction. Initiator Ready This signal indicates that the initiating agent is able to complete the current data phase of the transaction. PCI Target Ready This signal indicates the ability of the target agent's (selected device) ability to complete the current data phase of the transaction. PCI Frame This signal is driven by the current master to indicate the beginning and duration of an access. PCI Parity This signal represents even3 parity across AD[31::00] and C/BE[3::0]#. PCI Command and Byte Enables These signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3::0]# define the bus command. During the data phase, C/BE[3::0]# are used as Byte Enables. PCI System Error This signal is used for reporting address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. INTA# O Data Device Corporation www.ddc-web.com Interrupt This pin is a level sensitive, active low interrupt to the host. 90 DS-BU-67301B-E 2/12 HOST INTERFACE Table 13. PCI Bus Interface Signals Signal Name DIR RST# I Description PCI Reset Negative true Reset input, normally asserted low following power turn-on. This input conforms to PCI RST# convention. 6.5.5 PCI Target Interface The Total-AceXtreme's PCI Target interface supports a similar set of data transfer capabilities as the Synchronous parallel CPU interface. These include: * 32-bit read and write operations to registers and memory. * 16-bit memory write operations. * Sequential reads from registers are not supported. Table 14 lists the timing parameters for the Total-AceXtreme's PCI interface. Figure 49 through Figure 51 illustrate the timing for the Total-AceXtreme's PCI Target interface. 6.5.5.1 PCI Target STOP# Assertion Similar to the Synchronous parallel CPU interface, the Total-AceXtremeTM posts all requests to read or write individual words on to a command FIFO. As described in paragraph 6.4.2, it is possible to fill the FIFO by means of a burst write transfer to Total-AceXtreme registers. Since burst transfers can write to the command FIFO at up to 66 MHz and register writes are drained at only a 40 MHz rate, it is possible to incur a FIFO overflow condition. When this occurs, the Total-AceXtreme's PCI Target interface will terminate the current transaction by asserting its STOP# output low. Table 14. PCI Timing Information Timing Characteristics REF DESCRIPTION NOTES UNITS MIN TYP MAX fCLK HOST_CLK frequency tCLK HOST_CLK cycle time 15 ns tS Input setup time 3 ns tH input hold time 0 ns tD output valid delay 10pF load tHZ output high-z delay 10pF load Data Device Corporation www.ddc-web.com 66 91 2 MHz 6 ns 14 ns DS-BU-67301B-E 2/12 HOST INTERFACE Table 14. PCI Timing Information Timing Characteristics REF DESCRIPTION NOTES UNITS MIN tWRITE FRAME# to TRDY# delay for a slave write cycle tREAD FRAME# to TRDY# delay for a slave write cycle 66MHz or 33MHz Falling edge of TRDY# for the write to start the DMA to the falling edge of REQ# for the first DMA transfer 66MHz 33MHz tDMA_START TYP MAX 4*tCLK ns 5 tCLK + 50 6*tCLK + 75 ns 330 540 390 660 ns ns tCLK HOST_CLK tS INPUT tH Input Valid tHZ tD OUTPUT Output Valid tD Figure 49. PCI Parametric Timing tCLK HOST_CLK FRAME# tWrite AD[31:0] C/BE[3:0]# Address Data Data 0x7 Data Data 0x0 IRDY# DEVSEL# TRDY# Figure 50. PCI Slave Burst Write Data Device Corporation www.ddc-web.com 92 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK HOST_CLK FRAME# tRead AD[31:0] Address C/BE[3:0]# Data Data 0x7 Data Data 0x0 IRDY# DEVSEL# TRDY# Figure 51. PCI Slave Burst Read 6.5.6 PCI Initiator Timing Figure 52 through Figure 54 illustrate the operation of the Total-AceXtremeTM's PCI Initiator interface. The Total-AceXtreme's Initiator is activated by the host writing a logic `1' to the DMA Start bit of the DMA Command/Status Register. Figure 52 shows tDMA_START, the delay from the end of the host write to the Total-AceXtreme's PCI Target interface (falling edge of TRDY#) to the falling edge of the TotalAceXtreme's REQ# output. By asserting REQ#, the Total-AceXtreme is vying to the PCI arbiter to become the next bus master. Once the arbiter responds by asserting the Total-AceXtreme's GNT# input low, the Total-AceXtreme's PCI Initiator interface will begin its DMA burst write transfer, as shown in Figure 53; or its DMA burst read transfer, as shown in Figure 54. Data Device Corporation www.ddc-web.com 93 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK HOST_CLK REQ# tDMA_Start FRAME# AD[31:0] C/BE[3:0]# Address Data 0x7 0x0 IRDY# DEVSEL# TRDY# Figure 52. PCI DMA Start Delay tCLK HOST_CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# Address Data Data Data Data 0x0 0x7 IRDY# DEVSEL# TRDY# Figure 53. PCI DMA Burst Write Data Device Corporation www.ddc-web.com 94 DS-BU-67301B-E 2/12 HOST INTERFACE tCLK HOST_CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# Address Data Data Data Data 0x0 0xE IRDY# DEVSEL# TRDY# Figure 54. PCI DMA Burst Read Data Device Corporation www.ddc-web.com 95 DS-BU-67301B-E 2/12 7 POWER INPUTS 7.1 Decoupling Capacitors For the Total-AceXtreme's power supply input, DDC recommends the use of the following decoupling capacitors: * For +1.8V_CORE (7 balls): o 1 - 0.1uF Ceramic Chip o 1 - 0.01uF Ceramic Chip. * For +3.3V_LOGIC (12 balls): o 1 - 10uF Ceramic Chip or 10uF Low ESR/ESL Tantalum o 3 - 0.1uF Ceramic Chip o 8 - 0.01uF Ceramic Chip * For +3.3V_XCVR (11 balls): o 2 - 10uF Ceramic Chip or 10uF Low ESR/ESL Tantalum o 2 - 0.1uF Ceramic Chip o 6 - 0.01uF Ceramic Chip * For +1.8V_PLL (1 ball): o 1 - 0.1uF Ceramic Chip o 1 - 0.01uF Ceramic Chip In order to minimize power supply noise on the PLL supply pin, DDC recommends the use of a ferrite bead in series with decoupling capacitors as shown in Figure 55. Figure 55. Recommended +1.8V_PLL Filter Network 7.2 Power Sequencing In order to ensure proper initialization of the Total-AceXtreme under all conditions, it is necessary to perform the power-up initialization sequence described below. Figure 56 illustrates the required timing relationships for the Total-AceXtreme's power inputs, the CLK_IN and nPOR input signals, and the PLL_LOCKED output signal. Data Device Corporation www.ddc-web.com 96 DS-BU-67301B-E 2/122 POWER INPUTS 1. Provide 1.8V power to the Total-AceXtreme's 1.8V_PLL and 1.8V_CORE pins. Note that in order to ensure correct initialization, the PLL_+1.8V and 1.8V_CORE voltages must rise to 1.0 volts prior to or simultaneous with the +3.3V_LOGIC and +3.3V_XCVR voltage rising to 2.0 volts. 2. Provide 3.3V power to the Total-AceXtreme's 3.3V_LOGIC and +3.3V_XCVR pins. During the ramp-up of the +3.3V supply, external logic inputs must not be driven to voltages above that of the Total-AceXtreme's 3.3V supply voltage. It is acceptable to power external logic (including the oscillator for clock inputs) from the same +3.3V supply voltage as the TotalAceXtreme. 3. When (or following) the 3.3V_LOGIC and +3.3V_XCVR voltages rise to above 2.0V, it will be necessary for the 40 MHz CLK_IN clock to be stable and to assert the nPOR input to logic `0'. Asserting nPOR low is necessary to ensure the correct initialization of the TotalAceXtreme. 4. Following a minimum of 1 s after nPOR is low and CLK_IN is stable, the nPOR input signal should be transitioned from `0' to `1'. 5. If enabled (i.e., if DISABLE_BIST = `0') the Total-AceXtreme will initiate its internal built-in self-test (BIST) 100 s after the low-to-high transition of nPOR. 6. The host processor or external PCI Initiator should not attempt to access the TotalAceXtreme's memory and registers until at least 1 ms following the low-to-high transition of nPOR if DISABLE_BIST = `0', or until at least 500 s following the low-to-high transition of nPOR if DISABLE_BIST = `1'. The PLL_LOCKED output signal will assert high within 100 s after the low-to-high transition of nPOR, indicating that the internal 160 MHz clock (PLL output) is operational. If this signal does not rise, the internal chip reset will remain in place and the chip will be unresponsive. Data Device Corporation www.ddc-web.com 97 DS-BU-67301B-E 2/12 POWER INPUTS Figure 56. Power-Up Initialization Sequence Timing Data Device Corporation www.ddc-web.com 98 DS-BU-67301B-E 2/12 8 MIL-STD-1553 TRANSCEIVER OPTIONS 8.1 Using the Internal Transceivers Most Total-AceXtremeTM applications will involve use of the internal 1553 transceivers and transformers. For these applications, the connections shown in Figure 58 will be applicable. This includes making the indicated connections of the digital signals between the protocol logic chip and the transceivers. The MIL-STD-1553 Core interface signals and internal MIL-STD-1553 signals are implemented as external signals to specific pins. The user has the option of connecting them on the PC board as shown in Figure 58, or connecting the 1553 Core interface signals to an external Transceiver. If the internal transceiver is not used, this allows the Total-AceXtreme to be used with MIL-STD-1773 (fiber optic) transceivers. The decoders can also be configured to operate with single-ended input signals for interfacing to fiber optic transceivers. Z0 Total-AceXtreme Internal Isolation Transformer 1.0:2.038 Protocol Logic Bus Coupler 1.0:1.4 CHx_1553 0.75?Z0 Transceiver MIL-STD-1553 Bus CHx_1553_L 0.75?Z0 CHx = CH. A or CH. B CHx_1553-CT Z0 Figure 57. Total-AceXtremeTM Internal Transceiver and Isolation Transformer Connection to MIL-STD-1553 Bus Data Device Corporation www.ddc-web.com 99 DS-BU-67301B-E 2/122 MIL-STD-1553 TRANSCEIVER OPTIONS Figure 58. Mandatory Connections for Integrated Transceivers 8.2 Connection to External Transceivers Most MIL-STD-1553 and STANAG-3838 applications, including for MIL-STD-1760, require the use of a transceiver providing a trapezoidal waveform, with rise/fall times in the range of 100 to 300 ns. However, there are some applications that require compatibility with McAir standards such A3818, A5232, and A5690. For these applications, a transceiver providing an approximate sinusoidal waveform with reduced harmonic content, rather than a trapezoidal waveform, must be used. In addition, the McAir standards require both direct and transformer coupling, and require connections to the isolation transformer center taps on the stub side. Figure 59 shows the use of Total-AceXtreme for applications requiring compatibility with the McAir standards. For this, DDC's BU-67401-L0D0L-100 dual 3.3V transceiver includes a McAir-compatible transmitter, while Beta Transformer Technology Corporation's DSS-3300-1 dual transformer provides both direct and transformer coupled taps, and brings out the center tap connections on the stub (secondary) side. Data Device Corporation www.ddc-web.com 100 DS-BU-67301B-E 2/12 MIL-STD-1553 TRANSCEIVER OPTIONS Figure 59. Total-AceXtreme Interface to External McAir Transceiver 8.3 Using External Fiber Optic Transceivers As an alternative to using the internal transceivers and transformers, it is possible to use Total-AceXtremeTM with external (electrical) MIL-STD-1553 transceivers, or with fiber optic transceivers. Figure 60 illustrates the interface between Total-AceXtreme and a pair of external fiber optic transceivers. Note for this interface, it is necessary to configure the Total-AceXtreme's Manchester decoders to accept a single-ended input signal. This is done by connecting the nSINGEND to logic `0'. Data Device Corporation www.ddc-web.com 101 DS-BU-67301B-E 2/12 MIL-STD-1553 TRANSCEIVER OPTIONS Figure 60. Total-AceXtremeTM Interface to Fiber Optic Transceivers Data Device Corporation www.ddc-web.com 102 DS-BU-67301B-E 2/12 9 REGISTER AND MEMORY ADDRESSING 9.1 Memory Address Space The Total-AceXtreme's memory and registers are accessible from either the PCI Interface or the CPU Interface. When using the PCI Interface, the Total-AceXtremeTM memory is accessed from BAR0 via byte addresses on the PCI bus. On the BC/RT/MT versions, the BAR0 size is 256KByte. When using the CPU Interface, the Total-AceXtreme memory is accessed via 32-bit transactions addresses on the CPU bus. The entire memory range (256 KBytes) is accessible through the Host interface. 9.2 Register Address Space Total-AceXtremeTM registers are accessible from both the PCI Interface and CPU Interface. When using the PCI Interface, the Total-AceXtreme registers are accessed from BAR1 via byte addresses on the PCI bus. BAR1 is always 4Kbytes in size regardless of the Total-AceXtreme's mode of operation. When using the CPU interface, the Total-AceXtreme registers are accessed via 32bit addresses on the CPU bus. Any attempt to read/write a register location beyond address x"3FF" will result in a rollover back to the beginning of the 4Kbyte space. Data Device Corporation www.ddc-web.com 103 DS-BU-67301B-E 2/122 10 TOTAL-ACEXTREMETM SIGNALS 10.1 Signal Descriptions and Pinout by Functional Groups Table 15. Protocol Configuration Signal Name BAL L Pullup/ Pulldown DISABLE_BC (I) C14 50k Pulldown When `1', indicates that the Total-AceXtreme cannot operate in BC mode (i.e. BC operation is disabled). When `0', indicates that the Total-AceXtreme can operate in BC mode provided that it isn't an RT-ONLY device. DISABLE_MULTI_RT (I) D14 50k Pulldown When `1', indicates that the Total-AceXtreme cannot operate in Multi-RT mode (i.e. Limited to one RT-Address). When `0', indicates that the Total-AceXtreme can operate in Multi-RT mode. PCI_nCPU (I) C11 50k Pulldown When `1', indicates that the PCI interface is active. When `0', indicates that the CPU Interface is active. nRTBOOT (I) D13 50k Pullup If nRTBOOT is connected to logic "0", the Total-AceXtreme will initialize in RT mode with the Busy status word bit set following power turn-on. If nRTBOOT is hardwired to logic "1", the Total-AceXtreme will initialize in either Idle mode (for an RT-only part), or BC mode (for a BC/RT/MT part). nPOR C10 None Power-on Reset. Asserting nPOR low resets all Total-AceXtreme logic, along with the PLL that generates the internal 160 MHz clock. Following the low-tohigh transition of nPOR, if enabled (by DISABLE_BIST = `0'), the TotalAceXtreme will initiate its internal built-in self-test (BIST). The host processor should not attempt to access the Total-AceXtreme registers or memory until at least 1 ms after the low-to-high transition of nPOR. Following nPOR being asserted high, the host processor must wait a minimum of 1 ms if DISABLE_BIST = `0', or 500 s if DISABLE_BIST ='1' before accessing memory or registers. PLL_LOCKED A13 None PLL Locked output. Indicates that the output from the PLL providing the internal 160 MHz clock is operational. Immediately following power turn-on, PLL_LOCKED will assert low, and will remain low while nPOR is asserted low. Assuming correct operation of the PLL, PLL_LOCKED will transition from `0' to `1' following a maximum of 100 s after nPOR goes high. Data Device Corporation www.ddc-web.com Description 104 DS-BU-67301B-E 2/122 TOTAL-ACEXTREMETM SIGNALS Table 16. JTAG Test Signal Name BAL L Pullup/ Pulldown Description JTAG_TCK (I) A7 50k Pullup This ball is the JTAG test clock. The Test Clock is used to load the test mode data from the JTAG TMS pin, and the test data on the TDI pin [on the rising edge]. On the falling edge test clock outputs the test data on the TDO pin. JTAG_TMS (I) A10 50k Pullup This ball is the test mode select input signal. Controls the operation of the test logic, by receiving the incoming data. JTAG_TDI (I) B10 50k Pullup This ball is the serial test data input. Receives serial input data which is either fed to the test data registers or instruction register. JTAG_TDO (O) B8 N/A This ball is the serial test data output. Outputs serial data which comes from either the test data registers or instruction register. JTAG_nTRST (I) B9 50k Pullup This ball is test reset and will asynchronously reset the JTAG test logic. Table 17. General Purpose Discrete I/O Signal Name BAL L Pullup/ Pulldown DISCRETE_IO_7 (I/O) H12 50k Pullup DISCRETE_IO_6 (I/O) L14 50k Pullup DISCRETE_IO_5 (I/O) J12 50k Pullup DISCRETE_IO_4 (I/O) J13 50k Pullup DISCRETE_IO_3 (I/O) L13 50k Pullup DISCRETE_IO_2 (I/O) K12 50k Pullup DISCRETE_IO_1 (I/O) K13 50k Pullup DISCRETE_IO_0 (I/O) M14 50k Pullup Data Device Corporation www.ddc-web.com Description Discrete I/O (Digital Logic levels) Following power-up, each register is reset to zero, and all outputs are reset to high impedance state (input mode). All registers are read/write. Each Discrete IO bit is independently programmable for input vs. output, and each bit has independent 3-state control. 105 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS 10.2 Host Interface Signals 10.2.1 Operation for PCI Mode. Note that most of these signals are dual use. That is, they take on different function, depending on whether the Total-AceXtremeTM is configured for PCI mode or for FGPI mode. Table 18. PCI Signals Signal Name BALL Pullup/ Pulldown PCI_AD(31) (I/O) MSB A5 None PCI_AD(30) (I/O) A4 None PCI_AD(29) (I/O) B5 None PCI_AD(28) (I/O) B4 None PCI_AD(27) (I/O) B3 None PCI_AD(26) (I/O) D1 None PCI_AD(25) (I/O) C2 None PCI_AD(24) (I/O) D3 None PCI_AD(23) (I/O) F1 None PCI_AD(22) (I/O) E2 None PCI_AD(21) (I/O) E3 None PCI_AD(20) (I/O) F3 None PCI_AD(19) (I/O) G1 None PCI_AD(18) (I/O) G3 None PCI_AD(17) (I/O) J5 None PCI_AD(16) (I/O) H1 None PCI_AD(15) (I/O) K1 None PCI_AD(14) (I/O) M2 None PCI_AD(13) (I/O) L1 None PCI_AD(12) (I/O) N1 None PCI_AD(11) (I/O) L3 None PCI_AD(10) (I/O) K2 None PCI_AD(09) (I/O) M1 None PCI_AD(08) (I/O) N2 None PCI_AD(07) (I/O) N3 None PCI_AD(06) (I/O) N4 None PCI_AD(05) (I/O) M4 None Data Device Corporation www.ddc-web.com Description 32-Bit PCI Bus Address / Data lines. Address and Data are multiplexed on the same pins. Each bus operation consists of an address phase followed by one or more data phases. Address phases are identified when the control signal FRAME# is asserted. Data transfers occur during those clock cycles in which the control signals IRDY# and TRDY# are both asserted. 106 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 18. PCI Signals Signal Name BALL Pullup/ Pulldown Description PCI_AD(04) (I/O) K3 None PCI_AD(03) (I/O) M5 None PCI_AD(02) (I/O) L4 None PCI_AD(01) (I/O) K4 None PCI_AD(00) (I/O) LSB L5 None GNT# (I) A6 None Grant indicates to the agent that access to the bus has been granted. This is a point-to-point signal. Every master has its own GNT# which must be ignored while RST# is asserted. REQ# (O) B7 None Request indicates to the arbiter that the Total-AceXtreme desires use of the bus. This is a point-to-point signal. Every master has its own REQ# output which must be tri-stated while RST# is asserted. PERR# (I/O) G2 None Parity Error. This pin is used for reporting parity errors during the data portion of the bus transaction for all cycles except a Special Cycle. It is sourced by the agent receiving data and driven active two clocks following the detection of an error. This signal is driven inactive (high) two clocks prior to returning to the tri-state condition. IDSEL (I) D2 None Initialization Device Select. This pin is used as a chip select during configuration read or write operations. DEVSEL# (I/O) J1 None Device Select. This signal is sourced by an active target upon decoding that its address and bus commands are valid. For bus masters, it indicates whether any device has decoded the current bus cycle. STOP# (I/O) H2 None Stop. The Stop signal is sourced by the selected target and conveys a request to the bus master to stop the current transaction. IRDY# (I/O) C3 None Initiator Ready. This signal is sourced by the bus master and indicates that the bus master is able to complete the current data phase of a bus transaction. For write operations, it indicates that valid data is on the PCI_AD[31:0] pins. Wait states occur until both TRDY# and IRDY# are asserted together. TRDY# (I/O) J3 None Target Ready. This signal is sourced by the selected target and indicates that the target is able to complete the current data phase of a bus transaction. For read operations, it indicates that the target is providing valid data on the PCI_AD[31:0] pins. Wait states occur until both TRDY# and IRDY# are asserted together. FRAME# (I/O) H3 None Frame. This signal is driven by the current bus master and identifies both the beginning and duration of a bus operation. When FRAME# is first asserted, it indicates that a bus transaction is beginning and that valid addresses and a corresponding bus command are present on the PCI_AD[31:0] and C/BE[3:0]# lines, qualified by HOST_CLOCK. When FRAME# is de-asserted the transaction is in the final data phase or has been completed. PAR (I/O) L2 None Parity. This signal is even parity across the entire PCI_AD[31:0] field along with the C/BE[3:0]# field. The parity is stable in the clock following the address phase and is sourced by the Bus Master. During the data phase for write operations, the Bus Master sources this signal on the clock following IRDY# active. During the data phase for read operations, this signal is sourced by the Target and is valid on the clock following TRDY# active. The PAR signal therefore has the same timing as PCI_AD[31:0], delayed by one clock. Data Device Corporation www.ddc-web.com 107 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 18. PCI Signals Signal Name BALL Pullup/ Pulldown Description C/BE[3]# (I/O) E1 None Bus Command and Byte Enables. These signals are multiplexed on the same pins. During the address phase of a bus operation, these pins identify the bus command, as shown in the table below. During the data phase of a bus operation, these pins are used as Byte Enables, with C/BE[0]# enabling byte 0 (LSB) and C/BE[3]# enabling byte 3 (MSB). The Total-AceXtreme responds to the following PCI commands C/BE[3:0]# Description (during address phase) 0 1 1 0 - Memory Read 0 1 1 1 - Memory Write 1 0 1 0 - Configuration Read 1 0 1 1 - Configuration Write 1 1 0 0 - Memory Read Multiple 1 1 1 0 - Memory Read Line 1 1 1 1 - Memory Write and Invalidate Note that the last three memory commands are aliased to the basic memory commands: Memory Read and Memory Write. C/BE[2]# (I/O) J4 None C/BE[1]# (I/O) K5 None C/BE[0]# (I/O) M3 None SERR# (I/O) J2 None System Error. This pin is used for reporting address parity errors, data parity errors on Special Cycle commands, or any other condition having a catastrophic system impact. INTA# (O) A9 None Interrupt A. This pin is a level sensitive, active low interrupt to the host RST# (I) B6 None PCI Reset. Negative true Reset input, normally asserted low following power turn-on. This input conforms to PCI RST# convention. Asserting RST# low resets all internal logic, including the PCI interface. However, this signal does not reset the PLL that generates the internal 160 MHz clock. 10.2.2 PCI Signals Table 19. CPU Data Bus Signal Name BAL L CPU_DATA(31) (I/O) MSB A5 None CPU_DATA(30) (I/O) A4 None CPU_DATA(29) (I/O) B5 None CPU_DATA(28) (I/O) B4 None CPU_DATA(27) (I/O) B3 None CPU_DATA(26) (I/O) D1 None CPU_DATA(25) (I/O) C2 None Data Device Corporation www.ddc-web.com Pullup/ Pulldown Description 32-Bit bi-directional CPU Data Bus. This bus interfaces the host processor to the Total-AceXtreme internal registers and internal RAM. Most of the time, the outputs for DATA31 through DATA00 are in the high impedance state. They drive outward when the host CPU reads the internal RAM or registers. CPU_DATA[31:16] are only used when the 32-bit mode is enabled. For the multiplexed address/data mode, CPU_DATA(15:0) operate as the address bus inputs during the first (address) portion of a transfer cycle. 108 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 19. CPU Data Bus Signal Name BAL L Pullup/ Pulldown CPU_DATA(24) (I/O) D3 None CPU_DATA(23) (I/O) F1 None CPU_DATA(22) (I/O) E2 None CPU_DATA(21) (I/O) E3 None CPU_DATA(20) (I/O) F3 None CPU_DATA(19) (I/O) G1 None CPU_DATA(18) (I/O) G3 None CPU_DATA(17) (I/O) J5 None CPU_DATA(16) (I/O) H1 None CPU_DATA(15) (I/O) K1 None CPU_DATA(14) (I/O) M2 None CPU_DATA(13) (I/O) L1 None CPU_DATA(12) (I/O) N1 None CPU_DATA(11) (I/O) L3 None CPU_DATA(10) (I/O) K2 None CPU_DATA(09) (I/O) M1 None CPU_DATA(08) (I/O) N2 None CPU_DATA(07) (I/O) N3 None CPU_DATA(06) (I/O) N4 None CPU_DATA(05) (I/O) M4 None CPU_DATA(04) (I/O) K3 None CPU_DATA(03) (I/O) M5 None CPU_DATA(02) (I/O) L4 None CPU_DATA(01) (I/O) K4 None CPU_DATA(00) (I/O) L5 None CPU_ADDR(15) (I) MSB T4 50k Pullup CPU_ADDR(14) (I) T3 50k Pullup CPU_ADDR(13) (I) A6 None CPU_ADDR(12) (I) B7 None CPU_ADDR(11) (I) G2 None CPU_ADDR(10) (I) D2 None CPU_ADDR(09) (I) J1 None CPU_ADDR(08) (I) H2 None CPU_ADDR(07) (I) C3 None Data Device Corporation www.ddc-web.com Description 16-bit CPU address bus. The host CPU accesses Total-AceXtreme registers and internal RAM by means of CPU_ADDR(15:0) In the multiplexed address/data mode for the parallel CPU interface, CPU_ADDR(15:0) may be left unconnected. 109 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 19. CPU Data Bus Signal Name BAL L Pullup/ Pulldown Description CPU_ADDR(06) (I) J3 None CPU_ADDR(05) (I) H3 None CPU_ADDR(04) (I) L2 None CPU_ADDR(03) (I) E1 None CPU_ADDR(02) (I) J4 None CPU_ADDR(01) (I) K5 None CPU_ADDR(00) (I) M3 None NC J2 None Not Used / No User Connection NC A9 None Not Used / No User Connection nMSTCLR (I) B6 None Master Clear. Negative true Reset input. Asserting this signal low resets all internal logic. However, this signal does not reset the PLL that generates the internal 160 MHz clock. nSELECT (I) T2 50k Pullup Device Select. Chip select to select this device. This signal should be asserted active low throughout the entire transfer cycle. It may be tied low if this device is the only device in the system. Generally connected to a CPU address signal or to a CPU address decoder output to select the Total-AceXtreme for a transfer to/from either RAM or register. nDATA_STRB (I) M6 50k Pullup Strobe Data. For non-multiplexed asynchronous mode, nDATA_STRB must be asserted throughout each 32-bit or 16-bit data transfer, until nDATA_RDY is asserted. For multiplexed asynchronous mode, nDATA_STRB must be asserted following the address portion of the transfer cycle, that is following the falling edge of the ADDR_LAT input signal, and maintained low throughout the data portion 32-bit or 16-bit data transfer, that is until nDATA_RDY is asserted. For synchronous non-multiplexed single or sequential burst transactions, nDATA_STRB must be asserted low for exactly one clock cycle and synchronous to the first active low chip select and valid address. For random burst transactions, nDATA_STRB should be synchronous to the first active low chip select and valid address, and remain low indicating a new address is present for each clock cycle. For synchronous multiplexed mode, nDATA_STRB should be asserted low for exactly one host clock cycle to initiate first data cycle of the CPU transfer, on the host clock cycle following the address transfer (ADDR_LAT). RD_nWR (I) Data Device Corporation www.ddc-web.com J6 50k Pullup Read/Write. Indicating the type of transfer: `1' to read or `0' to write. This signal should be active throughout the entire transfer cycle (See POL_SEL for active high/low options). 110 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 19. CPU Data Bus Signal Name ADDR_LAT (I) BAL L R3 Pullup/ Pulldown 50k Pulldown Description Address Latch. When CPU_ADDR_MULTI equals `1', this indicates that the address is presented on CPU_DATA(15:0). For the case of synchronous multiplexed mode, ADDR_LAT should be asserted high for one clock cycle of the host clock. For non-multiplexed mode, ADDR_LAT should be hardwired high . DATA32_n16 (I) K6 50k Pullup Data Bus Select. Indicates 32-bit mode when `1' and 16-bit mode when `0'. MSW_nLSW (I) L6 50k Pullup Most Significant Byte/Least Significant Byte. In 16-bit modes, indicates the high `1' or low `0' word that is being transferred (See POL_SEL). This signal should be active high or low throughout address phase of transfer. Not used in 32-bit mode. POL_SEL (I) K7 50k Pullup CPU Polarity Select. Input which determines which word is "high" or "low". In 32-Bit Mode: If `1', RD_nWR has normal polarity, i.e. read is `1' and write is `0'. If POL_SEL is `0' then RD_nWR* has inverted polarity, i.e. read is `0' and write is `1'. In 16-Bit Mode: POL_SEL indicates which word is the most significant word. If POL_SEL is `0' then the least significant word has an address LSB of `0' and the most significant word has an address LSB of `1'. If POL_SEL is `1' then the least significant word has an address LSB of `1' and the most significant word has an address LSB of `0'. Static signal. TRIG_SEL (I) L8 50k Pullup CPU Trigger Select input. In 16-bit modes, indicates which 16-bit transfer will trigger a read or write operation. When `1' then the "high" order word triggers the transfer and when `0' the low word triggers the transfer. This is used in conjunction with POL_SEL which determines which word is "high" or "low". TRIG_SEL is not used in 32-bit mode or in Synchronous Mode. MEM_nREG (I) R2 50k Pullup CPU Memory/Register. Indicates the selection of memory space if `1', or register space if `0'. This signal should be active high or low throughout the address phase of transfer. Total-AceXtreme registers are accessed by asserting MEM_nREG = `0'. Any attempt to access a register location beyond address x"3FF" will result in a rollover back to the beginning of the 8K register space. Data Device Corporation www.ddc-web.com 111 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 19. CPU Data Bus Signal Name nDATA_RDY (O) BAL L R1 Pullup/ Pulldown N/A Description Handshake output to host processor. Active low signal indicating that a write transfer has been accepted or a read transfer is ready on the data bus. In asynchronous mode, nDATA_RDY will assert low when data to be read is valid on the CPU_DATA bus, or when data to be written has been stored in memory. In asynchronous mode, nDATA_RDY will remain asserted until nDATA_STRB has been de-asserted. In synchronous mode, nDATA_RDY will assert for a single cycle of the host clock when data to be read is valid on the CPU_DATA bus, or when data to be written has been stored in memory. CPU_ASYNC_nSYNC (I) J7 50k Pullup Indicating ASYNCHRONOUS CPU mode when equal to `1' and SYNCHRONOUS CPU mode when equal to `0'. ADMULTI (I) L7 50k Pullup When `0' indicates non-multiplexed mode, when `1' indicates multiplexed address and data mode. CPU_nLAST (I) R4 50k Pullup In synchronous mode, when asserted to `1', CPU_nLAST enables a burst transfer. When de-asserted to `0', this indicates the last transfer of a burst or a single read or write transfer. CPU_nLAST should be active through the entire transfer cycle. Not used in asynchronous mode. CPU_WORD_EN(1) (I) P4 50k Pullup CPU_WORD_EN(0) (I) P3 50k Pullup CPU_nSTOP (O) P1 N/A Signal(s) should be active throughout the entire transfer cycle. 32-Bit Mode: Input to specify which input 16-bit data words are valid for this transfer. Should be tied high if unused. For valid register transfers the value should be `11' always. For memory accesses, these bits indicate which word(s) will be written/read. 16-Bit Mode: (only CPU_WORD_EN(0) used): In 16-bit mode, CPU_WORD_EN[1:0] must be connected to `11'. For synchronous mode, CPU_nSTOP is issued by the CPU Target Interface to direct the Host Interface to immediately terminate the current transaction. If CPU_nSTOP is coincident with nDATA_RDY, then the final transaction is acceptable. If CPU_nSTOP is not coincident with nDATA_RDY, then the transaction should be aborted. CPU_nSTOP will be asserted at the completion of a single register read cycle and is coincident with nDATA_RDY. CPU_nSTOP should not be expected at the completion of a valid single memory read cycle, or any valid single write cycle, because the Total-AceXtreme target interface is not yet certain whether this is a burst cycle or not. In addition, CPU_nSTOP will go active low when the target determines a transfer did not complete (i.e. a FIFO is full or an invalid transfer). When asserted, the next transfer shall not start until at least one clock after CPU_nSTOP has been de-asserted. CPU_nSTOP is not used in asynchronous mode. Data Device Corporation www.ddc-web.com 112 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 20. RT Address Signals Signal Name BALL Pullup/ Pulldown Description RTAD4 (MSB) (I) H14 50k Pullup RT Address input. If the RT ADDRESS SOURCE, of the RT_GCFG (RT Global Configuration) Register, is programmed to logic "0", then the Total-AceXtreme RT address is provided by means of these 5 input signals. RTAD3 (I) G12 50k Pullup RTAD2 (I) G10 50k Pullup RTAD1 (I) G13 50k Pullup RTAD0 (LSB) (I) G14 50k Pullup RTADP (I) H13 50k Pullup Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4-RTAD0 in order for the RT to respond to non-broadcast commands. That is, there must be an odd number of logic "1"s from among RTAD4-RTAD0 and RTADP. RT_AD_LAT (I) G11 50k Pullup RT Address Latch. Input signal used to control the Total-AceXtreme's internal RT address latch. If RT_AD_LAT is logic "0," then the Total-AceXtreme internal RT Address will continuously track inputs RTAD4-RTAD0 and RTADP. In addition, if RT ADDRESS SOURCE is logic "0", the source of RT address parity is RTADP. When a logic "1" level is applied to the RT_AD_LAT input, the TotalAceXtreme internal RT address may be optionally latched under software control. If RT_AD_LAT transitions from logic `0' to logic "1" while nMSTCLR is high, the Total-AceXtreme RT address will be latched from inputs RTAD4-RTAD0 and RTADP on this rising edge. For single RT mode, to enable the Total-AceXtreme's RT address to be software programmable, RT_AD_LAT must be connected to logic `1'. Table 21. Miscellaneous Signals Signal Name TAG_CLK (I) BALL M13 Pullup/ Pulldown 50k Pullup Description Time Tag Clock. External clock that may be used to increment the Time Tag Register. This option is selected when input ball TAG_ENABLE is logic `1'. TAG_LOAD (I) M12 50k Pullup External Time Tag Load Pulse. Loads 48-bit, Time Tag Counter with value from an internal register TAG_ENABLE (I) N13 50k Pullup Time Tag Enable. If this input is set to logic `1', the 48-bit, internal Time Tag counter will be enabled. A logic `0' input disables the internal Time Tag counter. Data Device Corporation www.ddc-web.com 113 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 21. Miscellaneous Signals Signal Name nMCRST/nINCMD (O) BALL L12 Pullup/ Pulldown N/A Description Mode Code Reset or In-command. The function of this pin is controlled by bit 19 of "RT_GCFG" (RT Global Configuration) register. When RT_GCFG = `0', nMCRST / nINCMD functions as nINCMD. nINCMD is asserted low to frame the time that a message is being processed by the Total-AceXtreme. When RT_GCFG = `1', - nMCRST / nINCMD functions as nMCRST. In RT mode, nMCRST is asserted low for two CLOCK_IN clock cycles (50 ns) following receipt of a Reset remote terminal mode command. In BC-only or Monitor-only modes, this signal is inoperative; i.e., in this case, it will always output a value of logic `1'. In addition, nMCRST/nINCMD will also assert low during the time that the Total-AceXtreme is performing its logic self-test. Therefore, nMCRST/nINCMD can be monitored to determine when this self-test has been completed. DISABLE_BIST (I) C13 50k Pulldown If this input is set to logic `0', the Built-In-Self-Test (BIST) will be enabled after hardware reset (for example, following the low-to-high transition of nPOR following power-up). A logic `1' input disables both the power-up and userinitiated automatic BIST. TX_INH_A (I) P13 50k Pullup TX_INH_B (I) P14 50k Pullup Transmitter inhibit inputs for Channel A and Channel B, MIL-STD-1553 transmitters. For normal operation, these inputs should be connected to logic `0'. To force a shutdown of Channel A and/or Channel B, a value of logic `1' should be applied to the respective TX_INH input. IRIG_DIG_IN (I) N14 50k Pullup Digital IRIG-B time code input supporting 48-bit time-tags. Digital IRIG data is read once per second. IRIG Time can be used as the Time-Tag instead of the local timer. nINT (O) P2 50k Pullup Interrupt Request output. The operation of nINT is programmable by means of the CPU Interrupt Pin Control Register. This register is only accessible via the CPU Interface, not the PCI interface. The user-programmable parameters for nINT include: (1) (2) (3) (4) CLOCK_IN (I) A8 Data Device Corporation www.ddc-web.com None Open-drain or TTL output Active high or low Pulse or level For the case of a pulse interrupt, the pulse width is programmable. The pulse width may be programmed for a value between 3 and 65,537 clock cycles. The clock used for formulating the nINT pulse width will be the Total-AceXtreme's internal 160 MHz clock for the Asynchronous CPU interface mode, and the HOST_CLK for the Synchronous CPU interface mode. 40 MHz clock input (MIL-STD-1553 bus clock) 114 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 21. Miscellaneous Signals Signal Name HOST_CLK/PCI_CLK (I) BALL F2 Pullup/ Pulldown None USER_OUTPUT_1 (O) T13 N/A USER_OUTPUT_2 (O) U13 N/A Description HOST/PCI Clock. Input clock from the PCI Bus or host processor. All input signals: address, data and control must meet the setup and hold time requirements relative to this clock signal. All output data and control propagation delay (8 ns max) will be referenced to this input clock. The input clock is designed to run up to 80-MHz (12.5 ns period) in CPU mode and up to 66-MHz (15.0 ns period) in PCI mode. Represents the status of bits 18 & 17 of "GBL_CFG" (Global Configuration) Register. When bit 18 is set to `1', USER_OUTPUT_1 is driven to a logic high. When `0', USER_OUTPUT_1 will be driven to a logic low. When bit 17 is set to `1', USER_OUTPUT_2 is driven to a logic high. When `0', USER_OUTPUT_2 will be driven to a logic low. TEMP_DIODE E13 N/A This signal must be pulled up to +3.3V in order to measure the temperature of the Total-AceXtreme digital protocol chip. The protocol chip temperature may be measured and digitized using a Maxim MAX6642 temperature sensor chip (http://pdfserv.maximic.com/en/ds/MAX6642.pdf). EXT_TRIG (I) T11 50k Pullup BC External Trigger. EXT_TRIG may be used to synchronize BC operation to an external source. Can be used to start the operation of the BC Command Interpreter, or can be used to have the BC wait at specific points in the Instruction List for an external synchronization. In BC mode, during the execution of a Wait for External Trigger (WTG) instruction, the Total-AceXtreme BC will wait for a low-to-high transition on EXT_TRIG before proceeding to the next instruction. EXT_TRIG is a rising edge sensitive signal that must not violate a minimum pulse width of 100ns to ensure proper sampling. nSSFLAG (I) R14 50k Pullup Subsystem Flag (RT Mode only) In Single-RT mode, if this input is asserted low, the Subsystem Flag bit will be set in the Total-AceXtreme's RT Status Word. If the nSSFLAG input is logic `0' while bit 7 of the "RT Status Input Control" register has been programmed to logic `1' (cleared), the Subsystem Flag RT Status Word bit will become logic "1," but bit 7 of the "RT Status Input Control" register, will return logic `1' when read. That is, the logic sense provided to the nSSFLAG input has no effect on the value of the SUBSYSTEM FLAG register bit. In BC, Multi-RT, and Monitor (only) modes, the nSSFLAG input is not used and should be connected to logic `1'. Data Device Corporation www.ddc-web.com 115 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 22. Additional Connections & Interface to External Transceiver Signal Name nSINGEND(I) Utilizing Internal "Built-In" Transceivers Connect to +3.3V_LOGIC or leave floating if using built-in transceivers. BALL Pullup/ Pulldown R13 50k Pullup For Use With External Transceivers "Transceiverless Mode" If nSINGEND is connected to logic '0`, the Manchester decoder inputs will be configured to accept singleended input signals (e.g., MIL-STD-1773 fiber optic receiver outputs). Refer to paragraph 8.3 for use of the single-ended input mode to interface with a fiber optic transceiver. If nSINGEND is connected to logic '1`, the decoder inputs will be configured to accept standard doubleended Manchester bi-phase input signals; i.e., MILSTD-1553 receiver outputs. TXDATA_OUT_A (O) TXDATA_IN_A (I) TXDATA_OUT_A_L (O) TXDATA_IN_A_L (I) TXDATA_OUT_B (O) TXDATA_IN_B (I) TXDATA_OUT_B_L (O) TXDATA_IN_B_L (I) TXINH_OUT_A (O) TXINH_IN_A (I) These two signals MUST be directly connected for normal "Built-In" transceiver operation. These two signals MUST be directly connected for normal "Built-In" transceiver operation. These two signals MUST be directly connected for normal "Built-In" transceiver operation. These two signals MUST be directly connected for normal "Built-In" transceiver operation. These two signals MUST be directly connected for normal "Built-In" transceiver operation. J10 N/A K10 50k Pulldown J11 N/A K11 50k Pulldown Digital Manchester bi-phase transmit data outputs. Connect directly to corresponding inputs of a MILSTD-1553 or MIL-STD-1773 (fiber optic) transceiver. L10 N/A These two signals MUST be separated for "Transceiverless" operation. M10 50k Pulldown Digital Manchester bi-phase transmit data outputs. Connect directly to corresponding inputs of a MILSTD-1553 or MIL-STD-1773 (fiber optic) transceiver. L9 N/A These two signals MUST be separated for "Transceiverless" operation. M9 50k Pulldown Digital Manchester bi-phase transmit data outputs. Connect directly to corresponding inputs of a MILSTD-1553 or MIL-STD-1773 (fiber optic) transceiver. H10 N/A These two signals MUST be separated for "Transceiverless" operation. H11 These two signals MUST be separated for "Transceiverless" operation. Digital Manchester bi-phase transmit data outputs. Connect directly to corresponding inputs of a MILSTD-1553 or MIL-STD-1773 (fiber optic) transceiver. These two signals MUST be separated for "Transceiverless" operation. 50k Pulldown Transmitter inhibit inputs for Channel A of external MIL-STD-1553 transmitters. To enable transmission on Channel A, this input must be connected to logic "0". To force a shutdown of Channel A, a value of logic "1" should be applied to the respective TX_INH input. Digital transmit inhibit outputs. Connect to TXINH_OUT_A inputs of an external MIL-STD-1553 transceiver. Asserted high to inhibit when not transmitting on the respective bus. Data Device Corporation www.ddc-web.com 116 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 22. Additional Connections & Interface to External Transceiver Signal Name TXINH_OUT_B (O) TXINH_IN_B (I) RXDATA_IN_A (I) RXDATA_OUT_A (O) RXDATA_IN_A_L (I) RXDATA_OUT_A_L (O) RXDATA_IN_B (I) RXDATA_OUT_B (O) RXDATA_IN_B_L (I) RXDATA_OUT_B_L (O) Utilizing Internal "Built-In" Transceivers These two signals MUST be directly connected for normal "Built-In" transceiver operation. These two signals MUST be directly connected for normal "Built-In" transceiver operation. These two signals MUST be directly connected for normal "Built-In" transceiver operation. These two signals MUST be directly connected for normal "Built-In" transceiver operation. These two signals MUST be directly connected for normal "Built-In" transceiver operation. BALL L11 M11 Pullup/ Pulldown N/A For Use With External Transceivers "Transceiverless Mode" These two signals MUST be separated for "Transceiverless" operation. 50k Pulldown J8 50k Pullup K8 N/A Transmitter inhibit inputs for Channel B of external MIL-STD-1553 transmitters. To enable transmission on Channel B, this input must be connected to logic "0". To force a shutdown of Channel B, a value of logic "1" should be applied to the respective TX_INH input. Digital transmit inhibit outputs. Connect to TX_INH_OUT inputs of an external MIL-STD-1553 transceiver. Asserted high to inhibit when not transmitting on the respective bus. RXDATA_IN_A is an output from the TotalAceXtreme's internal MIL-STD-1553 Channel A receiver. These two signals MUST be separated for "Transceiverless" operation. J9 50k Pullup K9 N/A Digital Manchester bi-phase receive data inputs. Connect directly to corresponding outputs of a MILSTD-1553 or MIL-STD-1773 (fiber optic) transceiver. RXDATA_IN_L_A is an output from the TotalAceXtreme's internal MIL-STD-1553 Channel A receiver. These two signals MUST be separated for "Transceiverless" operation. U6 50k Pullup V6 N/A Digital Manchester bi-phase receive data inputs. Connect directly to corresponding outputs of a MILSTD-1553 or MIL-STD-1773 (fiber optic) transceiver. RXDATA_IN_B is an output from the TotalAceXtreme's internal MIL-STD-1553 Channel B receiver. These two signals MUST be separated for "Transceiverless" operation. U7 50k Pullup V7 N/A Digital Manchester bi-phase receive data inputs. Connect directly to corresponding outputs of a MILSTD-1553 or MIL-STD-1773 (fiber optic) transceiver. RXDATA_IN_B_L is an output from the TotalAceXtreme's internal MIL-STD-1553 Channel B receiver. These two signals MUST be separated for "Transceiverless" operation. Digital Manchester bi-phase receive data inputs. Connect directly to corresponding outputs of a MILSTD-1553 or MIL-STD-1773 (fiber optic) transceiver. Data Device Corporation www.ddc-web.com 117 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 23. MIL-STD-1553 Interface Signal Name BALL CHA_1553 (I/O) F17, F18, G17, G18 CHA_1553_L (I/O) D17, D18, E17, E18 CHB_1553 (I/O) N17, N18, P17, P18 CHB_1553_L (I/O) R17, R18, T17, T18 Description Transmit/Receive Input/Outputs. Connect directly to MIL-STD-1553 long (transformer-coupled) stub. Table 24. Power and Ground Connections Signal Name BALL Description +3.3V_LOGIC C4, C5, C6, C7, C8, C9, H4, H5, H6, H7, H8, H9, C12, D10, M7 +3.3V Protocol (VDD) I/O Supply Voltage +1.8V_CORE E5, E6, E7, F5, F6, F7, F8 +1.8V Protocol Core (VDD) Supply Voltage +1.8V_PLL E8 +1.8V PLL (VDD) Supply Voltage +3.3V_XCVR N5, N6, N7, N8, N9, T5, T6, T7, T8, T9, U10 +3.3V Transceiver (VDD) Supply Voltage GND_LOGIC A14, A15, B14, D4, D5, D6, D7, D8, D9, E4, E9, F4, F9, G4, G5, G6, G7, G8, G9, J14, K14, U14, V14, V15, A11, A12, B11, B12, B13, D11, E10, E14, F10, F13, F14 Logic Ground (VSS) GND_XCVR P5, P6, P7, P8, P9, R5, R6, R7, R8, R9, , V10, E11, E12, F11, F12, P11, P12, R11, R12 Transceiver Ground (VSS) Data Device Corporation www.ddc-web.com 118 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 25. No User Connections Signal Name NC BALL A1, A2, A3, A16, A17, A18, B1, B2, B15, B16, B17, B18, C1, C15, C16, C17, C18, D15, D16, E15, E16, F15, F16, G15, G16, H15, H16, H17, H18, J15, J16, J17, J18, K15, K16, K17, K18, L15, L16, L17, L18, M15, M16, M17, M18, N11, N12, N15, N16, P15, P16, , R15, R16, T1, T12, T14, T15, T16, U1, U2, U9, U11, U12, U15, U16, U17, U18, V1, V2, V3, V9, V11, V12, V13, V16, V17, V18, D12, , U3, U4, V4, M8, V5, U5, U8, V8, N10, P10, T10, R10 Data Device Corporation www.ddc-web.com Description No User Connections to these balls allowed. 119 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS 10.3 Pinout Table Table 26. Signal Pinout by Ball Location BALL Signal Name BALL Signal Name BALL Signal Name A1 NC G1 PCI_AD(19)/CPU_DATA(19) N1 PCI_AD(12)/CPU_DATA(12) A2 NC G2 PERR#/CPU_ADDR(11) N2 PCI_AD(08)/CPU_DATA(08) A3 NC G3 PCI_AD(18)/CPU_DATA(18) N3 PCI_AD(07)/CPU_DATA(07) A4 PCI_AD(30)/CPU_DATA( 30) G4 GND_LOGIC N4 PCI_AD(06)/CPU_DATA(06) A5 PCI_AD(31)/CPU_DATA( 31) G5 GND_LOGIC N5 +3.3V_XCVR A6 PCI_GNT#/CPU_ADDR(1 3) G6 GND_LOGIC N6 +3.3V_XCVR A7 JTAG_TCK G7 GND_LOGIC N7 +3.3V_XCVR A8 CLOCK_IN G8 GND_LOGIC N8 +3.3V_XCVR A9 INTA# G9 GND_LOGIC N9 +3.3V_XCVR A10 JTAG_TMS G10 RTAD2 N10 NC A11 GND_LOGIC G11 RT_AD_LAT N11 NC A12 GND_LOGIC G12 RTAD3 N12 NC A13 PLL_LOCKED G13 RTAD1 N13 TAG_ENABLE A14 GND_LOGIC G14 RTAD0 N14 IRIG_DIG_IN A15 GND_LOGIC G15 NC N15 NC A16 NC G16 NC N16 NC A17 NC G17 CHA_1553 N17 CHB_1553 (I/O) A18 NC G18 CHA_1553 N18 CHB_1553 (I/O) B1 NC H1 PCI_AD(16)/CPU_DATA(16) P1 CPU_nSTOP B2 NC H2 STOP#/CPU_ADDR(08) P2 nINT B3 PCI_AD(27)/CPU_DATA( 27) H3 FRAME#/CPU_ADDR(05) P3 CPU_WORD_EN(0) B4 PCI_AD(28)/CPU_DATA( 28) H4 +3.3V_LOGIC P4 CPU_WORD_EN(1) B5 PCI_AD(29)/CPU_DATA( 29) H5 +3.3V_LOGIC P5 GND_XCVR B6 RST#/nMSTCLR H6 +3.3V_LOGIC P6 GND_XCVR B7 REQ#/CPU_ADDR(12) H7 +3.3V_LOGIC P7 GND_XCVR B8 JTAG_TDO H8 +3.3V_LOGIC P8 GND_XCVR B9 JTAG_nTRST H9 +3.3V_LOGIC P9 GND_XCVR B10 JTAG_TDI H10 TXINH_OUT_A P10 NC Data Device Corporation www.ddc-web.com 120 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 26. Signal Pinout by Ball Location BALL Signal Name BALL Signal Name BALL Signal Name B11 GND_LOGIC H11 TXINH_IN_A P11 GND_XCVR B12 GND_LOGIC H12 DISCRETE_IO_7 P12 GND_XCVR B13 GND_LOGIC H13 RTADP P13 TX_INH_A B14 GND_LOGIC H14 RTAD4 P14 TX_INH_B B15 NC H15 NC P15 NC B16 NC H16 NC P16 NC B17 NC H17 NC P17 CHB_1553 (I/O) B18 NC H18 NC P18 CHB_1553 (I/O) C1 NC J1 DEVSEL#/CPU_ADDR(09) R1 nDATA_RDY C2 PCI_AD(25)/CPU_DATA( 25) J2 SERR# R2 MEM_nREG C3 IRDY#/CPU_ADDR(07) J3 TRDY#/CPU_ADDR(06) R3 ADDR_LAT C4 +3.3V_LOGIC J4 C/BE[2]#/CPU_ADDR(02) R4 CPU_nLAST C5 +3.3V_LOGIC J5 PCI_AD(17)/CPU_DATA(17) R5 GND_XCVR C6 +3.3V_LOGIC J6 RD_nWR R6 GND_XCVR C7 +3.3V_LOGIC J7 CPU_ASYNC_nSYNC R7 GND_XCVR C8 +3.3V_LOGIC J8 RXDATA_IN_A R8 GND_XCVR C9 +3.3V_LOGIC J9 RXDATA_IN_A_L R9 GND_XCVR C10 nPOR J10 TXDATA_OUT_A R10 NC C11 PCI_nCPU J11 TXDATA_OUT_A_L R11 GND_XCVR C12 +3.3V_LOGIC J12 DISCRETE_IO_5 R12 GND_XCVR C13 DISABLE_BIST J13 DISCRETE_IO_4 R13 nSINGEND C14 DISABLE_BC J14 GND_LOGIC R14 nSSFLAG C15 NC J15 NC R15 NC C16 NC J16 NC R16 NC C17 NC J17 NC R17 CHB_1553_L C18 NC J18 NC R18 CHB_1553_L D1 PCI_AD(26)/CPU_DATA( 26) K1 PCI_AD(15)/CPU_DATA(15) T1 NC D2 IDSEL/CPU_ADDR(10) K2 PCI_AD(10)/CPU_DATA(10) T2 nSELECT D3 PCI_AD(24)/CPU_DATA( 24) K3 PCI_AD(04)/CPU_DATA(04) T3 CPU_ADDR(14) D4 GND_LOGIC K4 PCI_AD(01)/CPU_DATA(01) T4 CPU_ADDR(15) D5 GND_LOGIC K5 C/BE[1]#/CPU_ADDR(01) T5 +3.3V_XCVR D6 GND_LOGIC K6 DATA32_n16 T6 +3.3V_XCVR Data Device Corporation www.ddc-web.com 121 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 26. Signal Pinout by Ball Location BALL Signal Name BALL Signal Name BALL Signal Name D7 GND_LOGIC K7 POL_SEL T7 +3.3V_XCVR D8 GND_LOGIC K8 RXDATA_OUT_A T8 +3.3V_XCVR D9 GND_LOGIC K9 RXDATA_OUT_A_L T9 +3.3V_XCVR D10 +3.3V_LOGIC K10 TXDATA_IN_A T10 NC D11 GND_LOGIC K11 TXDATA_IN_A_L T11 EXT_TRIG D12 NC K12 DISCRETE_IO_2 T12 NC D13 nRTBOOT K13 DISCRETE_IO_1 T13 USER_OUTPUT_1 D14 DISABLE_MULTI_RT K14 GND_LOGIC T14 NC D15 NC K15 NC T15 NC D16 NC K16 NC T16 NC D17 CHA_1553_L K17 NC T17 CHB_1553_L D18 CHA_1553_L K18 NC T18 CHB_1553_L E1 C/BE[3]#/CPU_ADDR(03) L1 PCI_AD(13)/CPU_DATA(13) U1 NC E2 PCI_AD(22)/CPU_DATA( 22) L2 PAR/CPU_ADDR(04) U2 NC E3 PCI_AD(21)/CPU_DATA( 21) L3 PCI_AD(11)/CPU_DATA(11) U3 NC E4 GND_LOGIC L4 PCI_AD(02)/CPU_DATA(02) U4 NC E5 +1.8V_CORE L5 PCI_AD(00)/CPU_DATA(00) U5 NC E6 +1.8V_CORE L6 MSW_nLSW U6 RXDATA_IN_B E7 +1.8V_CORE L7 ADMULTI U7 RXDATA_IN_B_L E8 +1.8V_PLL L8 TRIG_SEL U8 NC E9 GND_LOGIC L9 TXDATA_OUT_B_L U9 NC E10 GND_LOGIC L10 TXDATA_OUT_B U10 +3.3V_XCVR E11 GND_XCVR L11 TXINH_OUT_B U11 NC E12 GND_XCVR L12 nMCRST/nINCMD U12 NC E13 TEMP_DIODE L13 DISCRETE_IO_3 U13 USER_OUTPUT_2 E14 GND_LOGIC L14 DISCRETE_IO_6 U14 GND_LOGIC E15 NC L15 NC U15 NC E16 NC L16 NC U16 NC E17 CHA_1553_L L17 NC U17 NC E18 CHA_1553_L L18 NC U18 NC F1 PCI_AD(23)/CPU_DATA( 23) M1 PCI_AD(09)/CPU_DATA(09) V1 NC F2 HOST_CLK/PCI CLK M2 PCI_AD(14)/CPU_DATA(14) V2 NC Data Device Corporation www.ddc-web.com 122 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS Table 26. Signal Pinout by Ball Location BALL Signal Name BALL Signal Name BALL Signal Name F3 PCI_AD(20)/CPU_DATA( 20) M3 C/BE[0]#/CPU_ADDR(00) V3 NC F4 GND_LOGIC M4 PCI_AD(05)/CPU_DATA(05) V4 NC F5 +1.8V_CORE M5 PCI_AD(03)/CPU_DATA(03) V5 NC F6 +1.8V_CORE M6 nDATA_STRB V6 RXDATA_OUT_B F7 +1.8V_CORE M7 +3.3V_LOGIC V7 RXDATA_OUT_B_L F8 +1.8V_CORE M8 NC V8 NC F9 GND_LOGIC M9 TXDATA_IN_B_L V9 NC F10 GND_LOGIC M10 TXDATA_IN_B V10 GND_XCVR F11 GND_XCVR M11 TXINH_IN_B V11 NC F12 GND_XCVR M12 TAG_LOAD V12 NC F13 GND_LOGIC M13 TAG_CLK V13 NC F14 GND_LOGIC M14 DISCRETE_IO_0 V14 GND_LOGIC F15 NC M15 NC V15 GND_LOGIC F16 NC M16 NC V16 NC F17 CHA_1553 M17 NC V17 NC F18 CHA_1553 M18 NC V18 NC Data Device Corporation www.ddc-web.com 123 DS-BU-67301B-E 2/12 TOTAL-ACEXTREMETM SIGNALS 10.4 Total-AceXtremeTM Pin Diagram A B C D E F G H J K U V NC CHB_15 CHB_15 CHB_15 CHB_15 53_L 53_L 53 53 NC NC 18 NC NC CHB_15 CHB_15 CHB_15 CHB_15 53_L 53_L 53 53 NC NC 17 NC 16 L M P N R T 18 NC NC NC CHA_15 CHA_15 CHA_15 CHA_15 53_L 53 53_L 53 17 NC NC NC CHA_15 CHA_15 CHA_15 CHA_15 53_L 53 53_L 53 16 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 15 GND_ LOGIC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND_ 15 LOGIC 14 GND_ LOGIC GND_ LOGIC DISAB _BC DISAB _MULT _RT GND_ LOGIC GND_ LOGIC RTAD 0 RTAD 4 GND_ LOGIC GND_ LOGIC DISC IO (6) DISC IO (0) IRIG_ TX_INH nSSFLA DIG_IN _B G NC GND_ LOGIC GND_ 14 LOGIC 13 PLL_LOC KED GND_ LOGIC DISAB_B IST nRT BOOT TEMP_ DIODE GND_ LOGIC RTAD 1 RTAD P DISC IO (4) DISC IO (1) DISC IO (3) TAG_ CLK TAG_ TX_INH nSNGE ENABLE _A ND USER_ OUT_1 USER_ OUT_2 NC 13 12 GND_ LOGIC GND_ LOGIC +3.3V LOGIC NC GND_ XCVR GND_ XCVR RTAD 3 DISC IO (7) DISC IO (5) DISC IO (2) nMCRST/ nINCMD TAG_LO AD NC GND_ XCVR GND_ XCVR NC NC NC 12 11 GND_ LOGIC GND_ LOGIC PCI_nC PU GND_ LOGIC GND_ XCVR GND_ XCVR RT_AD _LAT TXINH_ OUT_B TXINH _IN_B NC GND_ XCVR GND_ XCVR EXT_ TRIG NC NC 11 10 JTAG TMS JTAG TDI nPOR +3.3V LOGIC GND_ LOGIC GND_ LOGIC RTAD 2 TXINH_ OUT_A TXDATA TXDATA TXDATA TXDATA _OUT_A _IN_A _OUT_B _IN_B NC NC NC NC +3.3V XCVR GND_ XCVR 10 +3.3V GND_LO GND_ LOGIC GIC LOGIC GND_ LOGIC GND_ LOGIC +3.3V LOGIC TXDATA RXDATA RXDATA_ TXDATA _OUT_B_ _IN_A_L OUT_A_L _IN_B_L L +3.3V XCVR GND_ XCVR GND_ XCVR +3.3V XCVR NC NC 9 RXDATA RXDATA _IN_A _OUT_A NC NC NC NC NC NC NC TXDATA TXINH_ TXDATA _OUT_A_ IN_A _IN_A_L L 9 PCI_INT JTAG A# nTRST 8 CLOCK_I N JTAG TDO +3.3V LOGIC GND_ LOGIC 1.8V PLL 1.8V CORE GND_ LOGIC +3.3V LOGIC 7 JTAG TCK PCIREQ#/ CPU_ADD R(12) +3.3V LOGIC GND_ LOGIC 1.8V CORE 1.8V CORE GND_ LOGIC +3.3V CPU_AS YNC_nS LOGIC YNC 6 /CPU_AD nMSTCLR RST#/ +3.3V LOGIC GND_ LOGIC 1.8V CORE 1.8V CORE GND_ LOGIC +3.3V LOGIC 5 PCI_AD31/ PCI_AD29/ DATA31 DATA29 +3.3V LOGIC GND_ LOGIC 1.8V CORE 1.8V CORE GND_ LOGIC +3.3V LOGIC C/BE1#/C PCI_AD17/ PCI_AD0/ PU_ADDR DATA17 DATA0 (1) 4 PCI_AD30/ PCI_AD28/ DATA30 DATA28 +3.3V LOGIC GND_ LOGIC GND_ LOGIC GND_ LOGIC GND_ LOGIC +3.3V LOGIC C/BE2#/C PCI_AD1/ PU_ADDR DATA1 (2) PCI_GNT# DR (13) RD_ nWR POL_ SEL TRIG_ SEL NC +3.3V XCVR GND_ XCVR GND_ XCVR +3.3V XCVR NC NC 8 CPU_ AD_ MULTI +3.3V LOGIC +3.3V XCVR GND_ XCVR GND_ XCVR +3.3V XCVR RXDATA _IN_B_L RXDATA_ OUT_B_L 7 +3.3V XCVR GND_ XCVR GND_ XCVR +3.3V XCVR RXDATA RXDATA _IN_B _OUT_B 6 PCI_AD3/ DATA3 +3.3V XCVR GND_ XCVR GND_ XCVR +3.3V XCVR PCI_AD5/ DATA5 PCI_AD6/ DATA6 DATA32 MSW_ nDATA_ _n16 nLSW STRB PCI_AD2/ DATA2 PCI_IRDY PCI_FRA PCI_TRDY PCI_AD27/ PCI_AD4/ PCI_AD11/ PCI_AD24/ PCI_AD21/ PCI_AD20/ PCI_AD18/ #/CPU_AD ME#/CPU_ #/CPU_AD DATA27 DATA20 DATA18 DATA4 DATA11 DATA24 DATA21 DR(7) ADDR(5) DR(6) 3 NC 2 NC NC 1 NC NC NC A B C PCI_IDSE PCI_AD25/ PCI_AD22/ L/CPU_AD DATA25 DATA22 DR(10) NC NC 5 CPU_W CPU_ CPU_A DEN1 nBLAST DDR15 NC NC 4 C/BE0#/ PCI_AD7/ CPU_W ADDR_L CPU_A CPU_A DATA7 AT DDR14 DEN0 DDR(0) NC NC 3 nSELEC T NC NC 2 NC NC NC 1 T U V HOST_ PCI_PERR PCI_STOP PCI_SE PCI_AD10/ PCI_PAR/ PCI_AD14/ PCI_AD8/ #/CPU_AD #/CPU_AD CPU_ADD DATA10 DATA14 DATA8 CLK RR# DR(11) DR(8) R(4) C/BE3#/C DEVSEL#/ PCI_AD26/ PCI_AD23/ PCI_AD19/ PCI_AD16/ PCI_AD15/ PCI_AD13/ PCI_AD9/ PCI_AD12/ PU_ADDR CPU_ADD DATA26 DATA23 DATA19 DATA16 DATA15 DATA13 DATA9 DATA12 (3) R(9) D E F G H J K L M nINT MEM_ nREG CPU_ nDATA_ nSTOP RDY N P R MCM BALL LAYOUT LOOKING TOP DOWN THRU MCM PCI BUS CPU BUS 1553 MISC MISC TEST / PROGRAM PAD CONFIG PAD (STATIC) XCVR MISC Figure 61. Total-AceXtremeTM Pin Diagram Data Device Corporation www.ddc-web.com 124 DS-BU-67301B-E 2/12 11 MECHANICAL OUTLINE Figure 62. Total-AceXtremeTM Mechanical Outline Drawing Data Device Corporation www.ddc-web.com 125 DS-BU-67301B-E 2/122 12 ORDERING INFORMATION BU-67301B0T0X-E02 - Total-AceXtreme Component L = Contains Lead R = RoHS Compliant BU-67301E0T0R-JL0 - Hardware / Software Development Kit (Optional) - PCI Evaluation Board with Cable - Thermal Model, IBIS Model and Schematic Symbols - PCI Card Reference Design Schematic - JTAG/BSDL File - CAD Drawing footprints for PADS and Allegro - MTBF Report, BC Validation Report and RT Validation Report TM - BusTrACEr with Application Code Generation for Software Development (R) (R) (R) - Drivers for Windows , Linux , and VxWorks Data Device Corporation www.ddc-web.com 126 DS-BU-67301B-E 2/122 Data Device Corporation Leadership Built on Over 45 Years of Innovation Military | Commercial Aerospace | Space | Industrial Data Device Corporation (DDC) is the world leader in the design and manufacture of high-reliability data bus products, motion control, and solid-state power controllers for aerospace, defense, and industrial automation applications. For more than 45 years, DDC has continuously advanced the state of high-reliability data communications and control technology for MIL-STD-1553, ARINC 429, Synchro/Resolver interface, and Solid-State Power Controllers with innovations that have minimized component size and weight while increasing performance. DDC offers a broad product line consisting of advanced data bus technology for Fibre Channel networks; MIL-STD-1553 and ARINC 429 Data Networking cards, components, and software; Synchro/Resolver interface components; and Solid-State Power Controllers and Motor Drives. Product Families Data Bus | Synchro/Resolver | Power Controllers | Motor Drives DDC is a leader in the development, design, and manufacture of highly reliable and innovative military data bus solutions. DDC's Data Networking Solutions include MIL-STD-1553, ARINC 429, and Fibre Channel. Each Interface is supported by a complete line of quality MIL-STD-1553 and ARINC 429 commercial, military, and COTS grade cards and components, as well as software that maintain compatibility between product generations. The Data Bus product line has been field proven for the military, commercial and aerospace markets. DDC is also a global leader in Synchro/Resolver Solutions. We offer a broad line of Synchro/Resolver instrumentgrade cards, including angle position indicators and simulators. Our Synchro/Resolver-to-Digital and Digital-toSynchro/Resolver microelectronic components are the smallest, most accurate converters, and also serve as the building block for our card-level products. All of our Synchro/Resolver line is supported by software, designed to meet today's COTS/MOTS needs. The Synchro/Resolver line has been field proven for military and industrial applications, including radar, IR, and navigation systems, fire control, flight instrumentation/simulators, motor/ motion feedback controls and drivers, and robotic systems. As the world's largest supplier of Solid-State Power Controllers (SSPCs) and Remote Power Controllers (RPCs), DDC was the first to offer commercial and fully-qualified MIL-PRF-38534 and Class K Space-level screening for these products. DDC's complete line of SSPC and RPC boards and components support real-time digital status reporting and computer control, and are equipped with instant trip, and true IT wire protection. The SSPC and RPC product line has been field proven for military markets, and are used in the Bradley fighting vehicles and M1A2 tank. DDC is the premier manufacturer of hybrid motor drives and controllers for brush, 3-phase brushless, and induction motors operating from 28 Vdc to 270 Vdc requiring up to 18 kilowatts of power. Applications range from aircraft actuators for primary and secondary flight controls, jet or rocket engine thrust vector control, missile flight controls, to pumps, fans, solar arrays and momentum wheel control for space and satellite systems. Certifications Data Device Corporation is ISO 9001: 2008 and AS 9100, Rev. C certified. DDC has also been granted certification by the Defense Supply Center Columbus (DSCC) for manufacturing Class D, G, H, and K hybrid products in accordance with MIL-PRF-38534, as well as ESA and NASA approved. Industry documents used to support DDC's certifications and Quality system are: AS9001 OEM Certification, MIL-STD-883, ANSI/NCSL Z540-1, IPC-A-610, MIL-STD-202, JESD-22, and J-STD-020. (R) IR M RE G U IST E Outside the U.S. - Call 1-631-567-5700 RED F DATA DEVICE CORPORATION REGISTERED TO ISO 9001:2008 REGISTERED TO AS9100:2004-01 FILE NO. A5976 The first choice for more than 45 years--DDC DDC is the world leader in the design and manufacture of high reliability data interface products, motion control, and solid-state power controllers for aerospace, defense, and industrial automation. Inside the U.S. - Call Toll-Free 1-800-DDC-5757 Headquarters and Main Plant 105 Wilbur Place, Bohemia, NY 11716-2426 Tel: (631) 567-5600 Fax: (631) 567-7358 Toll-Free, Customer Service: 1-800-DDC-5757 Web site: www.ddc-web.com United Kingdom: DDC U.K., LTD Mill Reef House, 9-14 Cheap Street, Newbury, Berkshire RG14 5DD, England Tel: +44 1635 811140 Fax: +44 1635 32264 France: DDC Electronique 10 Rue Carle-Herbert 92400 Courbevoie France Tel: +33-1-41-16-3424 Fax: +33-1-41-16-3425 Germany: DDC Elektronik GmbH Triebstrasse 3, D-80993 Munchen, Germany Tel: +49 (0) 89-15 00 12-11 Fax: +49 (0) 89-15 00 12-22 Japan: DDC Electronics K.K. Dai-ichi Magami Bldg, 8F, 1-5, Koraku 1-chome, Bunkyo-ku, Tokyo 112-0004, Japan Tel: 81-3-3814-7688 Fax: 81-3-3814-7689 Web site: www.ddcjapan.co.jp Asia: Data Device Corporation - RO Registered in Singapore Blk-327 Hougang Ave 5 #05-164 Singapore 530327 Tel: +65 6489 4801 The information in this Data Sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice.