PIC18F45K22-E/PT - Microchip Technology

 2010-2011 Microchip Technology Inc. DS80498D-page 1

PIC18(L)F25/45K22

The PIC18(L)F25/45K22 family devices that you have

received conform functionally to the current Device Data

Sheet (DS41412D), except for the anomalies described

in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC18(L)F25/45K22 silicon.

Data Sheet clarifications and corrections start on page 6,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB® IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2 programmer/

debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Select Tool).

4. Perform a “Connect” operation to the device

(Debugger>Connect). Depending on the

development tool used, the part number and

Device Revision ID value appear in the Output

window.

The DEVREV values for the various PIC18(L)F25/

45K22 silicon revisions are shown in Tabl e 1 .

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A5).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID(1) Revision ID for Silicon Revision(2)

A2 A3 A4 A5

PIC18F25K22 0101 0101 010x xxxx 0 0010 0 0011 0 0100 0 0101

PIC18LF25K22 0101 0101 011x xxxx 0 0010 0 0011 0 0100 0 0101

PIC18F45K22 0101 0101 000x xxxx 0 0010 0 0011 0 0100 0 0101

PIC18LF45K22 0101 0101 001x xxxx 0 0010 0 0011 0 0100 0 0101

Note 1: The Device ID is located in the last configuration memory space.

2: Refer to the “PIC18(L)F2XK22/4XK22 Flash Memory Programming Specification” (DS41398) for detailed

information on Device and Revision IDs for your specific device.

PIC18(L)F25/45K22 Rev. A2/A3/A4/A5

Silicon Errata and Data Sheet Clarification

PIC18(L)F25/45K22

DS80498D-page 2  2010-2011 Microchip Technology Inc.

TABLE 2: SILICON ISSUE SUMMARY

Module Feature Item

Number Issue Summary

Affected

Revisions(1)

A2 A3 A4 A5

Voltage Reference Default Value 1.1 VREFCON0 = 0X00 at Reset. X X

Voltage Reference Internal Reference 1.2 Reference may be unstable at low

temperatures.

HLVD HLVD module 2. The HLVD module does not function. X X

Comparators CxSYNC Control 3. The comparator output to the device pin

(Cx) always bypasses the Timer1

synchronization latch.

HS Oscillator HS Oscillator Start-up 4. HS oscillator may not start at low voltage/

high temperature.

Clock Switching Fail-Safe mode 5.1 Execution is delayed when waking from

Sleep.

Clock Switching Fail-Safe Clock

Monitor

5.2 When the FCMEN Configuration bit is set

and the IESO Configuration bit is not set,

then a clock failure during Sleep will not

be detected.

CTMU Current Source 6.1 Current source is noisy. X X

CTMU Control Register 6.2 Control registers are not cleared by

Resets.

CCP3, CCP4 and

CCP5

PWM mode 7. Clock selection by CCP2 only. X X

ADC GO/DONE bit 8. GO/DONE bit gets stuck. X X

Power-on Reset

(POR)

Power-on Reset 9.1 Transient current spikes on some parts

during power-up may cause the part to

become stuck in Reset.

XXX

Power-on Reset

(POR)

Power-on Reset 9.2 Min VDD for PIC18F2X/4XK22 parts is

limited to 2.3V.

Min VDD for PIC18LF2X/4XK22 parts is

1.8V.

XXXX

Timer1/3/5 Gate Timer1/3/5 Gate 10. The Timer1/3/5 gate times cannot be

resolved to the two Least Significant bits,

when using FOSC as the Timer1/3/5

source.

XXXX

EUSART EUSART

Asynchronous

Operation

11. The EUSART asynchronous operation

may miss the Start bit edge.

XXX

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

 2010-2011 Microchip Technology Inc. DS80498D-page 3

PIC18(L)F25/45K22

Silicon Errata Issues

1. Module: Voltage Reference

1.1 The default value of VREFCON0 after Reset

is 0x00 instead of 0x10.

Work around

Select the desired fixed voltage reference buffer

as part of initialization.

Affected Silicon Revisions

1.2 Internal voltage reference may become

unstable at cold temperature.

Work around

None.

Affected Silicon Revisions

2. Module: HLVD

Although the HLVDIF flag will be set immediately

after enabling the HLVD circuit, the HLVD module

is not functional and should not be used.

Work around

None.

Affected Silicon Revisions

3. Module: Comparators

The CxSYNC controls are inoperative. The

comparator output (Cx) always bypasses the

Timer1 synchronization latch.

Work around

None.

Affected Silicon Revisions

4. Module: HS Oscillator

The HS oscillator may not start when VDD is less

than 3V, especially at high temperatures.

Work around

None.

Affected Silicon Revisions

5. Module: Clock Switching

5.1 When Clock Fail-Safe mode or Clock

Switchover mode is selected, then code

execution will be delayed after waking from

Sleep by the start-up time of the HFINTOSC.

Work around

Disable HFINTOSC stabilization time by setting

the HFOFST bit of the Configuration register 3H.

Affected Silicon Revisions

5.2 When the FCMEN Configuration bit is set

and the IESO Configuration bit is not set,

then a clock failure during Sleep will not be

detected.

Work around

The IESO Configuration bit must also be set when

the FCMEN Configuration bit is set.

Affected Silicon Revisions

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated by the shaded column in

the following tables apply to the current

silicon revision (A5).

A2 A3 A4 A5

PIC18(L)F25/45K22

DS80498D-page 4  2010-2011 Microchip Technology Inc.

6. Module: CTMU

6.1 Current source may be noisy to the CTMU

module.

Work around

None.

Affected Silicon Revisions

6.2 CTMU control registers are not cleared by

the RESET instruction or MCLR Reset.

Work around

Clear the CTMU control registers as part of device

initialization.

Affected Silicon Revisions

7. Module: CCP3, CCP4 and CCP5

PWM mode does not work independently of

CCP2. Clock selection is cross-wired with that of

CCP2.

Work around

Use CCP1 and/or CCP2 for PWM applications.

Reserve CCP3, CCP4 and CCP5 for capture and

compare applications.

Affected Silicon Revisions

8. Module: ADC

GO/DONE bit may become stuck in GO mode.

Work around

Use the ADC FRC clock selection to reduce the

probability of the GO bit becoming stuck. To

capture the events when the GO bit does become

stuck, use one of the timers to determine if the GO

bit stays set longer than expected. When this

occurs, restart the ADC conversion by clearing the

GO/DONE bit and then setting the GO/DONE bit.

Affected Silicon Revisions

9. Module: Power-on Reset (POR)

9.1 There may be transient current spikes on

some parts during power-up. If the

application cannot supply enough current to

get past these transients, then the part may

become stuck in Reset.

Work around

Ensure that the application is capable of supplying

at least 30 mA of transient current during power-

up.

Affected Silicon Revisions

9.2 Min VDD for PIC18F2X/4XK22 parts is

limited to 2.3V. Min VDD for PIC18LF2X/

4XK22 parts is 1.8V.

Work around

None.

Affected Silicon Revisions

10. Module: Timer1/3/5 Gate

The Timer gate times cannot be resolved to the

two Least Significant timer bits when the source

frequency is FOSC (TMRxCS[1:0]=01). This is

because the gate edges are synchronized with the

FOSC/4 clock.

Work around

None.

Affected Silicon Revisions

A2 A3 A4 A5

XXX

A2 A3 A4 A5

XXXX

A2 A3 A4 A5

XXXX

 2010-2011 Microchip Technology Inc. DS80498D-page 5

PIC18(L)F25/45K22

11. Module: EUSART

The EUSART asynchronous operation has a

probability of 1 in 256 of missing the Start bit edge

for all combinations of BRGH and BRG16 values,

other than BRGH = 1, BRG16 = 1.

Work around

Set BRGH = 1, and BRG16 = 1 and use this

baud rate formula:

Affected Silicon Revisions

A2 A3 A4 A5

XXX

Baud_Rate Fosc/4 SPBRGH:SPBRGL+1=

PIC18(L)F25/45K22

DS80498D-page 6  2010-2011 Microchip Technology Inc.

Data Sheet Clarifications

The following typographic corrections and clarifications

are to be noted for the latest version of the device data

sheet (DS41412D):

1. Module: I/O Ports

In Table 10-5, the Buffer Type column listed ST

(Schmitt Trigger) for functions RB1-RB7, when

the Pin Type was I (Input), should be TTL. The

Table below reflects the correction.

Note: Corrections are shown in bold. Where

possible, the original bold text formatting

has been removed for clarity.

TABLE 10-5: PORTB I/O SUMMARY

Pin Function TRIS

Setting

ANSEL

Setting

Type

Buffer

Type Description

RB0/INT0/CCP4/

FLT0/SRI/SS2/

AN12

RB0 01O DIG LATB<0> data output; not affected by analog input.

10 I TTL PORTB<0> data input; disabled when analog input

enabled.

INT0 1 0 I ST External interrupt 0.

CCP4(3) 01O DIG Compare 4 output/PWM 4 output.

10 I ST Capture 4 input.

FLT0 10 I ST PWM Fault input for ECCP auto-shutdown.

SRI 10 I ST SR Latch input.

SS2(3) 10 I TTL SPI slave select input (MSSP2).

AN12 11 I AN Analog input 12.

RB1/INT1/P1C/

SCK2/SCL2/

C12IN3-/AN10

RB1 01O DIG LATB<1> data output; not affected by analog input.

10 ITTL PORTB<1> data input; disabled when analog input

enabled.

INT1 10 I ST External Interrupt 1.

P1C(3) 01O DIG Enhanced CCP1 PWM output 3.

SCK2(3) 01O DIG MSSP2 SPI Clock output.

10 I ST MSSP2 SPI Clock input.

SCL2(3) 01ODIGMSSP2 I

2CTM Clock output.

10 II

2C MSSP2 I2CTM Clock input.

C12IN3- 11 I AN Comparators C1 and C2 inverting input.

AN10 11 I AN Analog input 10.

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =

CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.

 2010-2011 Microchip Technology Inc. DS80498D-page 7

PIC18(L)F25/45K22

RB2/INT2/CTED1/

P1B/SDI2/SDA2/

AN8

RB2 01O DIG LATB<2> data output; not affected by analog input.

10 ITTL PORTB<2> data input; disabled when analog input

enabled.

INT2 10 I ST External interrupt 2.

CTED1 10 I ST CTMU Edge 1 input.

P1B(3) 01O DIG Enhanced CCP1 PWM output 2.

SDI2(3) 10 I ST MSSP2 SPI data input.

SDA2(3) 00ODIGMSSP2 I

2CTM data output.

10 II

2C MSSP2 I2CTM data input.

AN8 11 I AN Analog input 8.

RB3/CTED2/P2A/

CCP2/SDO2/

C12IN2-/AN9

RB3 01O DIG LATB<3> data output; not affected by analog input.

10 ITTL PORTB<3> data input; disabled when analog input

enabled.

CTED2 10 IST CTMU Edge 2 input.

P2A 01O DIG Enhanced CCP1 PWM output 1.

CCP2(2) 01O DIG Compare 2 output/PWM 2 output.

10 I ST Capture 2 input.

SDO2(2) 01O DIG MSSP2 SPI data output.

C12IN2- 11 I AN Comparators C1 and C2 inverting input.

AN9 11 I AN Analog input 9.

RB4/IOC0/P1D/

T5G/AN11

RB4 01O DIG LATB<4> data output; not affected by analog input.

10 ITTL PORTB<4> data input; disabled when analog input

enabled.

IOC0 10 I TTL Interrupt-on-change pin.

P1D 01O DIG Enhanced CCP1 PWM output 4.

T5G 10 I ST Timer5 external clock gate input.

AN11 11 I AN Analog input 11.

RB5/IOC1/P2B/

P3A/CCP3/T3CKI/

T1G/AN13

RB5 01O DIG LATB<5> data output; not affected by analog input.

10 ITTL PORTB<5> data input; disabled when analog input

enabled.

IOC1 10 I TTL Interrupt-on-change pin 1.

P2B(1)(3) 01O DIG Enhanced CCP2 PWM output 2.

P3A(1) 01O DIG Enhanced CCP3 PWM output 1.

CCP3(1) 01O DIG Compare 3 output/PWM 3 output.

10 I ST Capture 3 input.

T3CKI(2) 10 I ST Timer3 clock input.

T1G 10 I ST Timer1 external clock gate input.

AN13 11 I AN Analog input 13.

TABLE 10-5: PORTB I/O SUMMARY (CONTINUED)

Pin Function TRIS

Setting

ANSEL

Setting

Type

Buffer

Type Description

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =

CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.

PIC18(L)F25/45K22

DS80498D-page 8  2010-2011 Microchip Technology Inc.

RB6/KBI2/PGC RB6 01O DIG LATB<6> data output; not affected by analog input.

10 ITTL PORTB<6> data input; disabled when analog input

enabled.

IOC2 10 I TTL Interrupt-on-change pin.

TX2(3) 01O DIG EUSART 2 asynchronous transmit data output.

CK2(3) 01O DIG EUSART 2 synchronous serial clock output.

10 I ST EUSART 2 synchronous serial clock input.

PGC xx I ST In-Circuit Debugger and ICSPTM programming clock input.

RB7/KBI3/PGD RB7 01O DIG LATB<7> data output; not affected by analog input.

10 ITTL PORTB<7> data input; disabled when analog input

enabled.

IOC3 10 I TTL Interrupt-on-change pin.

RX2(2), (3) 10 I ST EUSART 2 asynchronous receive data input.

DT2(2), (3) 01O DIG EUSART 2 synchronous serial data output.

10 I ST EUSART 2 synchronous serial data input.

PGD xxO DIG In-Circuit Debugger and ICSPTM programming data output.

xx I ST In-Circuit Debugger and ICSPTM programming data input.

TABLE 10-5: PORTB I/O SUMMARY (CONTINUED)

Pin Function TRIS

Setting

ANSEL

Setting

Type

Buffer

Type Description

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =

CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.

 2010-2011 Microchip Technology Inc. DS80498D-page 9

PIC18(L)F25/45K22

APPENDIX A: DOCUMENT

REVISION HISTORY

Rev A Document (5/2010)

Initial release of this document.

Rev B Document (8/2010)

Updated errata to the new format; Updated for Revision

A4 silicon release; Added Modules 5.2, 9.1, 9.2 and 10.

Data Sheet Clarifications: Added Module 1.

Rev C Document (7/2011)

Updated for Revision A5 silicon release; Module 9.1

errata fixed.

Data Sheet Clarifications: No changes.

Rev D Document (8/2011)

Added Module 11, EUSART; Module 11 errata fixed on

Silicon revision A5.

Data Sheet Clarifications: No changes.

PIC18(L)F25/45K22

DS80498D-page 10  2010-2011 Microchip Technology Inc.

NOTES:

 2010-2011 Microchip Technology Inc. DS80498D-page 11

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Printed on recycled paper.

ISBN: 978-1-61341-508-5

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS80498D-page 12  2010-2011 Microchip Technology Inc.

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Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Worldwide Sales and Service

08/02/11