ACNT-H61L-500E - Avago Technologies

ACNT-H61L

Low Power 10 MBd Digital CMOS Optocoupler

in 14.2 mm Creepage/Clearance Stretched SO8 Package

Data Sheet

Description

The ACNT-H61L is a stretched wide optically coupled op-

tocoupler that combines a light-emitting diode and an in-

tegrated high gain photo detector to address low power

need for isolated interface. The optocoupler consumes

extremely low power, at maximum 2 mA across tempera-

ture. The LED forward current operates from 4.5 mA.

This optocoupler supports both 3.3 V and 5 V supply volt-

age with guaranteed AC and DC operational parameters

from temperature range -40 °C to +105 °C. The output

of the detector IC is a CMOS output. The internal Faraday

shield provides a guaranteed common mode transient

immunity specication of 20 kV/µs.

ACNT-H61L of 14.2 mm creepage/clearance and high volt-

age insulation capability suit for isolated communicate

logic interface and control in high-voltage power sys-

tems such as 690 VAC drives, renewable inverters, medical

equipment.

Functional Diagram

TRUTH TABLE

(POSITIVE LOGIC)

LED OUTPUT Vo

ON L

OFF H

Features

• Low IDD power supply consumption: 2 mA max.

• Input current capability: 4.5 mA min.

• Package: Stretched SO-8

• 20 kV/µs minimum Common Mode Rejection (CMR) at

VCM = 1000 V

• High Speed: 10 MBd min.

• Guaranteed AC and DC performance over wide

temperature: -40 °C to +105 °C

• Safety Approval (Pending)

- UL 1577 recognized - 7500 Vrms for 1 minute

- CSA Approval

- IEC/EN 60747-5-5 VIORM = 2262 Vpeak for Reinforced

Insulation

Applications

• Communication Interface: RS-485, CAN Bus

• Digital isolation for A/D, D/A conversion

• High-voltage power systems, e.g., 690 V drives

• Renewable energy inverters

• Medical imaging and patient monitoring

A 0.1 µF bypass capacitor must be connected between pins VDD and GND

Anode

VDD

GND

Shield

Cathode

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this

component to prevent damage and/or degradation which may be induced by ESD. The components

featured in this datasheet are not to be used in military or aerospace applications or environments.

6.248 ±0.127

0.246 ±0.005

0.457 ±0.100

0.018 ±0.004

1.270

0.05

BSC

16.61 ±0.25

0.654 ±0.010

0.254 ±0.050

0.010 ±0.002

15.01

0.591

0.20 ±0.10

0.008 ± 0.004

7°

7° 8° Nom

13.600 ± 0.127

0.535 ± 0.005

0.635

0.025

Min

3.607 ± 0.127

0.142 ± 0.005 7°

7°

17.857

0.703

Ref

0.630

0.025

1.905

0.075

Ref

14.047

0.553

Land Pattern Recommendation

Dimensions in mm [inch]

Maximum Mold Flash on each side is 0.127 mm [0.005 inch]

Note: Floating Lead Protusion is 0.15 mm [0.006 inch] Max if applicable

Package Outline Drawing

ACNT-H61L Stretched SO-8 Package

NNNN

● YYWW

EEE

Device Part Number

Date Code

Lead Free

Lot ID

Ordering Information

ACNT-H61L is UL Recognized with 7500 Vrms for 1 minute per UL 1577.

Part Number

Option

Package

Surface

Mount

Tape

& Reel UL 1577

IEC/EN

60747-5-5 QuantityRoHS Compliant

ACNT-H61L -000E 14.2 mm

Stretched S08

X X X 80 per tube

-500E X X X X 1000 per reel

To order, choose a part number from the Part Number column and combine with the desired option from the Option

column to form an order entry.

Solder Reow Prole

Recommended reow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.

Regulatory Information

The ACNT-H61L is pending approval by the following organizations:

IEC/EN 60747-5-5

UL Approval under UL 1577, component recognition program up to VISO = 7500 VRMS File E55361.

CSA Approval under CSA Component Acceptance Notice #5, File CA 88324.

IEC/EN 60747-5-5 Insulation Characteristics*

Description Symbol Characteristic Unit

Installation classication per DIN VDE 0110/39, Table 1

for rated mains voltage ≤ 600 Vrms

for rated mains voltage ≤ 1000 Vrms

I – IV

Climatic Classication 40/105/21

Pollution Degree (DIN VDE 0110/39) 2

Maximum Working Insulation Voltage VIORM 2262 Vpeak

Input to Output Test Voltage, Method b*

VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 4241 Vpeak

Input to Output Test Voltage, Method a*

VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC VPR 3619 Vpeak

Highest Allowable Overvoltage

(Transient Overvoltage tini = 60 sec)

VIOTM 12000 Vpeak

Safety-limiting values – maximum values allowed in the event of a failure.

Case Temperature

Input Current

Output Power

IS, INPUT

PS, OUTPUT

150

400

1000

°C

Insulation Resistance at TS, VIO = 500 V RS >109W

* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN

60747-5-5) for a detailed description of Method a and Method b partial discharge test proles.

Insulation and Safety Related Specications

Parameter Symbol ACNT-H61L Unit Conditions

Minimum External Air Gap

(External Clearance)

L(101) 14.2 mm Measured from input terminals to output terminals,

shortest distance through air.

Minimum External Tracking

(External Creepage)

L(102) 14.2 mm Measured from input terminals to output terminals,

shortest distance path along body.

Minimum Internal Plastic Gap

(Internal Clearance)

0.5 mm Through insulation distance conductor to conductor,

usually the straight line distance thickness between the

emitter and detector.

Tracking Resistance

(Comparative Tracking Index)

CTI >300 V DIN IEC 112/VDE 0303 Part 1

Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1

Absolute Maximum Ratings

Parameter Symbol Min Max Units Condition

Storage Temperature TS-55 125 °C

Operating Temperature TA-40 105 °C

Reverse Input Voltage VR5 V

Supply Voltage VDD 6.5 V

Average Forward Input Current IF- 10 mA

Peak Forward Input Current IF(TRAN) - 1 A <1µs Pulse Width, <300 pulses per second

80 mA <1µs Pulse Width, <10% Duty Cycle

Output Current IO10 mA

Output Voltage VO–0.5 VDD+0.5 V

Input Power Dissipation PI20 mW

Output Power Dissipation PO22 mW

Lead Solder Temperature TLS 260°C for 10 sec., 1.6 mm below seating plane

Solder Reow Temperature Prole Refer to Solder Reow Prole section

Recommended Operating Conditions

Parameter Symbol Min Max Units

Operating Temperature TA-40 105 °C

Input Current, Low Level IFL 0 250 µA

Input Current, High Level IFH 4.5 8 mA

Power Supply Voltage VDD 2.7 5.5 V

Forward Input Voltage VF (OFF) 0.8 V

Electrical Specications (DC)

Over recommended temperature (TA = –40 °C to +105 °C), supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical specications

are at VDD = 5 V, TA = 25 °C

Parameter Symbol Min Typ Max Units Test Conditions Figure

Input Forward Voltage VF1.20 1.38 1.85 V IF = 7 mA 1, 2

Input Reverse Breakdown Voltage BVR7 V IR = 10 µA

Logic High Output Voltage VOH VDD - 0.1 VDD V IF = 0 mA, VI = 0 V,

IO = -20 µA

VDD - 1.0 VDD V IF = 0 mA, VI = 0 V,

IO = -3.2mA

Logic Low Output Voltage VOL 0.02 0.1 V IF = 7 mA, VI = 5 V / 3.3 V,

IO = 20 µA

0.2 0.4 V IF = 7 mA, VI = 5 V / 3.3 V,

IO = 3.2 mA

Input Threshold Current ITH 0.7 3.8 mA 3

Logic Low Output Supply Current IDDL 1 2 mA 4

Logic High Output Supply Current IDDH 1 2 mA 5

Input Capacitance CIN 20 pF f = 1 MHz, VF = 0 V

Input Diode Temperature Coecient ΔVF/ΔTA-1.5 mV/°C IF = 7 mA

Switching Specications (AC)

Over recommended temperature (TA = –40 °C to +105 °C), supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical specications

are at VDD = 5 V, TA = 25 °C

Parameter Symbol Min Typ Max Units Test Conditions

Propagation Delay Time to

Logic Low Output [1]

tPHL 40 100 ns IF = 7 mA, VI = 3.3 / 5 V,

CL= 15 pF, CMOS Signal Levels.

Figure 6, 7, 8, 9

Propagation Delay Time to

Logic High Output [1]

tPLH 40 100 ns

Pulse Width tPW 100 ns

Pulse Width Distortion [2] PWD 5 40 ns

Propagation Delay Skew [3] tPSK 40 ns

Output Rise Time

(10% – 90%)

tR10 ns

Output Fall Time

(90% - 10%)

tF10 ns

Static Common Mode Transient

Immunity at Logic High Output [4]

| CMH | 20 35 kV/µs VCM = 1000 V, TA = 25°C,

IF = 0 mA, VI = 0 V, CL= 15 pF,

CMOS Signal Levels.

Static Common Mode Transient

Immunity at Logic Low Output [5]

| CML | 20 35 kV/µs VCM = 1000 V, TA = 25°C,

IF = 7 mA, VI = 5 V / 3.3 V, CL= 15pF,

CMOS Signal Levels.

Dynamic Common Mode Transient

Immunity [6]

CMRD 35 kV/µs VCM = 1000 V, TA = 25°C,

IF = 7 mA, VI = 5 V / 3.3 V,

10MBd datarate,

the absolute increase of PWD <10ns

Package Characteristics

All typical at TA = 25 °C.

Parameter Symbol Min Typ Max Units Test Conditions

Input-Output Insulation VISO 7500 Vrms RH < 50% for 1 min. TA = 25 °C

Input-Output Resistance RI-O 1012 WVI-O = 500 V

Input-Output Capacitance CI-O 0.6 pF f=1 MHz, TA = 25 °C

Notes:

1. tPHL propagation delay is measured from the 50% (Vin or IF) on the rising edge of the input pulse to the 50% VDD of the falling edge of the VO signal.

tPLH propagation delay is measured from the 50% (Vin or IF) on the falling edge of the input pulse to the 50% level of the rising edge of the VO

signal.

2. PWD is dened as |tPHL - tPLH|.

3. tPSK is equal to the magnitude of the worst case dierence in tPHL and/or tPLH that will be seen between units at any given temperature within the

recommended operating conditions.

4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.

5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.

6. CMD is the maximum tolerable rate of the common mode voltage during data transmission to assure that the absolute increase of the PWD is less

than 10ns.

1.1 1.2 1.3 1.4 1.5

IF - FORWARD CURRENT - mA

VF - FORWARD VOLTAGE - V

TA = 25°C

1.28

1.30

1.32

1.34

1.36

1.38

1.40

1.42

1.44

1.46

1.48

1.50

-40 -20 0 20 40 60 80 100

VF - FORWARD VOLTAGE - V

TA - TEMPERATURE - °C

0.2

0.4

0.6

0.8

-40 -20 0 20 40 60 80 100

ITH - INPUT THRESHOLD CURRENT - mA

TA - TEMPERATURE - °C

3.3V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-40 -20 0 20 40 60 80 100

DDL

- LOGIC LOW OUTPUT SUPPLY CURRENT - mA

TA - TEMPERATURE - °C

3.3V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-40 -20 0 20 40 60 80 100

IDDH - LOGIC HIGH OUTPUT SUPPLY CURRENT - mA

TA - TEMPERATURE - °C

3.3V

Figure 1. Typical input diode forward characteristic Figure 2. Typical VF versus temperature

Figure 3. Typical input threshold current ITH versus temperature

Figure 4. Typical logic low output supply current IDDL versus temperature Figure 5. Typical logic high output supply current IDDH versus temperature

-40 -20 0 20 40 60 80 100

TP - PROPOGATION DELAY;

PWD - PULSE WIDTH DISTORTION - ns

TA - TEMPERATURE - °C

TpHL_5V

TpLH_5V

PWD_5V

-40 -20 0 20 40 60 80 100

TP - PROPOGATION DELAY;

PWD - PULSE WIDTH DISTORTION - ns

TA - TEMPERATURE - °C

TpHL_3.3V

TpLH_3.3V

PWD_3.3V

4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0

TP - PROPOGATION DELAY;

PWD - PULSE WIDTH DISTORTION - ns

IF - PULSE INPUT CURRENT- mA

TpHL_5V

TpLH_5V

PWD_5V

4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0

TP - PROPOGATION DELAY;

PWD - PULSE WIDTH DISTORTION - ns

IF - PULSE INPUT CURRENT- mA

TpHL_3.3V

TpLH_3.3V

PWD_3.3V

Figure 8. Typical switching speed versus temperature at 5V supply voltage Figure 9. Typical switching speed versus temperature at 3.3V supply voltage

Figure 7. Typical switching speed versus pulse input current at 3.3V supply

voltage

Figure 6. Typical switching speed versus pulse input current at 5V supply

voltage

Figure 10. Recommended printed circuit board layout

Figure 11. Propagation delay skew waveform

50%

tPSK

2.5 V,

CMOS

2.5 V,

CMOS

DATA

INPUTS

CLOCK

DATA

OUTPUTS

CLOCK

tPSK

Figure 12. Parallel data transmission example

Bypassing and PC Board Layout

The external components required for proper operation

are the input limiting resistors and the output bypass ca-

pacitor. Capacitor values should be 0.1 µF.

For each capacitor, the total lead length between both

ends of the capacitor and the power-supply pins should

not exceed 20 mm.

Propagation Delay, Pulse-Width Distortion and

Propagation Delay Skew

Propagation delay is a gure of merit which describes how

quickly a logic signal propagates through a system. The

propagation delay from low to high (tPLH) is the amount

of time required for an input signal to propagate to the

output, causing the output to change from low to high.

Similarly, the propagation delay from high to low (tPHL) is

the amount of time required for the input signal to propa-

gate to the output, causing the output to change from

high to low (see Figure 10).

Pulse-width distortion (PWD) results when tPLH and tPHL

dier in value. PWD is dened as the dierence between

tPLH and tPHL and often PWD is dened as the dierence

between tPLH and tPHL. This parameter determines the

maximum data rate capability of a transmission system.

PWD can be expressed in percent by dividing the PWD

(in ns) by the minimum pulse width (in ns) being trans-

mitted. Typically, PWD in the order of 20-30% of the mini-

mum pulse width is tolerable; the exact gure depends

on the particular application (RS232, RS422, T-1, etc.).

Propagation delay skew, tPSK, is an important parameter to

consider in parallel data applications where synchroniza-

tion of signals on parallel data lines is a concern. If the par-

allel data is being sent through a group of optocouplers,

dierences in propagation delays will cause the data to ar-

rive at the outputs of the optocouplers at dierent times.

If this dierence in propagation delays is large enough, it

will determine the maximum rate at which parallel data

can be sent through the optocouplers.

Propagation delay skew is dened as the dierence be-

tween the minimum and maximum propagation delays,

either tPLH or tPHL, for any given group of optocouplers

which are operating under the same conditions (i.e., the

same supply voltage, output load, and operating temper-

ature). As illustrated in Figure 10, if the inputs of a group of

optocouplers are switched either ON or OFF at the same

time, tPSK is the dierence between the shortest propaga-

tion delay, either tPLH or tPHL, and the longest propagation

delay, either tPLH or tPHL. As mentioned earlier, tPSK can de-

termine the maximum parallel data transmission rate.

Anode

Cathode

Pulse Gen

C = 0.1µF

Output

Monitoring

node

VOGND

V (min.)

VDD

0 V SWITCH AT A: I = 0 mA

SWITCH AT B: I = 7 mA

CM L

V (max.)

V (PEAK)

XXX

YWW

GND1

VDD

C = 0.1 µF

GND2

RT = R1 + R2, R1/R2 ≈ 1.5

3.3V / 5V

VDD

GND

Shield

−

Figure 11 is the timing diagram of a typical parallel data

application with both the clock and the data lines being

sent through optocouplers. The gure shows data and

clock signals at the inputs and outputs of the optocou-

plers. To obtain the maximum data transmission rate, both

edges of the clock signal are being used to clock the data;

if only one edge were used, the clock signal would need

to be twice as fast.

Propagation delay skew represents the uncertainty of

where an edge might be after being sent through an

optocoupler. Figure 11 shows that there will be uncer-

tainty in both the data and the clock lines. It is important

that these two areas of uncertainty not overlap, otherwise

the clock signal might arrive before all of the data outputs

have settled, or some of the data outputs may start to

change before the clock signal has arrived.

From these considerations, the absolute minimum pulse

width that can be sent through optocouplers in a paral-

lel application is twice tPSK. A cautious design should use

a slightly longer pulse width to ensure that any additional

uncertainty in the rest of the circuit does not cause a prob-

lem.

The tPSK specied optocouplers oer the advantages of

guaranteed specications for propagation delays, pulse-

width distortion and propagation delay skew over the

recommended temperature, and power supply ranges.

Optocoupler CMR performance

The principal protection against common mode noise

comes down to the fundamental isolation properties of

the optocoupler, this in turn is directly related to the input-

output leakage capacitance of the optocoupler.

To provide maximum protection to circuitry connected to

the input or output of the optocoupler the leakage capac-

itance is minimized by having large separation distances

at all points in the optocoupler construction, including

the LED/photodiode interface.

In addition to the constructional design, additional circuit

design steps are taking to further mitigate the eects of

common mode noise. The most important of these is the

use of a Faraday shield on the photodetector stage. This

faraday shield is eective in optocouplers because the in-

ternal modulation frequency (light) is many orders of mag-

nitude higher than the common mode noise frequency.

Application level CMR Performance

In application, it desirable that the optocoupler’s common

mode isolation perform as close as possible to that indi-

cated in the data sheets specications.

The rst step in meeting this goal is to ensure maintain-

ing maximum separation between PCB interconnects on

either side of the optocoupler and avoid routing tracks

beneath the optocoupler. Nonetheless, it is inevitable that

a certain amount of CMR noise will be coupled into the

inputs which can potentially result in false-triggering of

the input.

This problem is frequently observed in devices with in-

put high input impedence such as CMOS buered inputs

in either optocoupler or alternate isolator technologies.

In some cases, this not only causes momentary missing

pulses but in some technologies may even cause input

circuitry to latch-up.

The ACNT-H61L does not face input latch up issue even

at very high CMR levels, such as those experienced in end

equipment level tests (for example IEC 61000-4-4) due to

the simple diode structure of the LED.

In some cases achieving the rated data sheet CMR perfor-

mance levels is not possible in the intended application,

often because of the practical need to actually connect

the isolator input to the output of a dynamically chang-

ing signal rather than tying the input statically to VDD1

or GND1.

This specsmanship issue is often observable with alterna-

tive isolators utilizing AC encoding techniques.

To address this requirement for clear transparency

on the achievable end application performance, the

ACNT-H61L optocoupler includes an additional typi-

cal performance indication of the dynamic CMR in the

electrical parameter table. What this information indi-

cates is the achievable CMR performance whilst the in-

put is being toggled on or o during the occurrence of

a CMR transient. The logic output of the optocoupler

is mainly controlled by the level of the LED current due

to the short transition rise/fall time of the LED current

(approximately 10ns), the dynamic noise immunity is

essentially the same as the static noise immunity.

To achieve this goal of meeting the maximum inherent

CMR capabilities some simple consideration needs to be

given to the operation of the LED at the application level.

In particular ensuring that the LED stays either on or o

during a CMR transient.

Some common design techniques which are sometimes

used to meet this goal:

Keeping LED On:

i) Overdrive the LED with a higher than required forward

current.

Keeping LED O:

i) Reverse bias the LED during the o state.

ii) Minimize the o state impedance across the anode and

cathode of the LED during the o state.

All these methods are fully capability of enabling the full

CMR capabilities o the ACNT-H61L to be achieved. But

they do come at the cost of practical implementation is-

sues or a compromise on power consumption.

An eective method to meet the goal of maintaining the

LED status during a CMR event with no other design com-

promises other the addition of a single low cost compo-

nent (resistor).

Figure 13. Recommended drive circuit for high-CMR

Figure 14. AC equivalent of ACNT-H61L

This CMR optimization method fundamentally makes use

of the dierential input capability of the LED input. By en-

suring the common mode impedance on both the cath-

ode and anode of the LED are balanced, it eectively nul-

lies the eect of a CMR transient on the LED. This is most

easily achieved by splitting the input bias resistor into two

(as shown in Figure 10).

Split resistor conguration

Figure 13 shows the recommended drive circuit for the

ACNT-H61L for optimal common-mode rejection per-

formance. Two LED-current setting resistors are used to

balance the common mode impe-dance at LED anode

and cathode. Common-mode transients can capacitively

couple from the LED anode (or cathode) to the output-

side ground causing current to be shunted away from

the LED (which can be bad if the LED is on) or conversely

cause current to be injected into the LED (bad if the LED is

meant to be o). Figure14 shows the parasitic capacitanc-

es which exists between LED anode/cathode and output

ground (CLA and CLC).

Table 1 indicates the directions of ILP and ILN ow depend-

ing on the direction of the common-mode transient. For

transients occurring when the LED is on, common-mode

rejection (CML, since the output is in the “low” state) de-

pends upon the amount of LED current drive (IF). For con-

ditions where IF is close to the switching threshold (ITH),

CML also depends on the extent which ILP and ILN balance

each other. In other words, any condition where common-

mode transients cause a momentary decrease in IF (i.e.

when dVCM/dt>0 and |IFP| > |IFN|, referring to Table 1) will

cause common-mode failure for transients which are fast

enough.

Likewise for common-mode transients which occur when

the LED is o (i.e. CMH, since the output is “high”), if an im-

balance between ILP and ILN results in a transient IF equal

to or greater than the switching threshold of the optocou-

pler, the transient “signal” may cause the output to spike

below 2 V (which constitutes a CMH failure).

The balanced ILED-setting resistors help equalize the com-

mon mode voltage change at anode and cathode to re-

duce the amount by which ILED is modulated from tran-

sient coupling through CLA and CLC.

Shield

0.1 µF

GND2

RT = R1 + R2, R1/R2 ≈ 1.5

Anode

Cathode

GND1

VDD

Anode

VDD

Shield

Cathode

0.1 µF

CLA

CLC

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AV02-4677EN - December 16, 2014

Table 1. Eects of Common Mode Pulse Direction on Transient ILED

If dVCM/dt Is: then ILP Flows: and ILN Flows:

If |ILP| < |ILN|,

LED IF Current

Is Momentarily:

If |ILP| > |ILN|,

LED IF Current

Is Momentarily:

positive (>0) away from LED

anode through CLA

away from LED

cathode through CLC

increased decreased

negative (<0) toward LED

anode through CLA

toward LED

cathode through CLC

decreased increased

Mouser Electronics

Authorized Distributor

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